Variable gain amplifier control circuit

Abstract

The invention relates to the field of electronic circuits, in particular to a variable gain amplifier control circuit which comprises 10 resistors R1 to R10, 6 PNP transistors QP1 to QP6, 13 NPN transistors QN1 to QN13 and two current sources I1 and I2. Different control schemes are implemented according to the size of input signals, adjustable threshold voltage is introduced, gain control current is dynamically adjusted, signal gain is adjusted in a segmented mode, so that the gain scheme is more flexible, and the problem that weak signals are single in amplification capacity is solved; fewer feedback loops are adopted, the structure is simple, and the circuit reliability is higher.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and particularly to a variable gain amplifier control circuit. Background Art

[0002] Variable Gain Amplifiers (VGA) are widely used in the fields of communication, radar, and audio processing. Its core function is to dynamically adjust the gain according to the size of the input signal to achieve stable output or linear control of the signal amplitude.

[0003] The VGA control circuits in the prior art usually use fixed resistor networks or simple voltage control circuits, and still have deficiencies in aspects such as gain adjustment accuracy, temperature stability, and design complexity. For this reason, some literatures and patents have proposed improvement schemes to achieve higher performance through dynamic feedback and current source regulation, but there are still problems such as slow response speed, poor matching, and high power consumption.

[0004] The prior art, such as a variable gain amplifier circuit, a main amplifier controller, and related control methods disclosed in CN107947748B, mainly realizes dynamic gain adjustment through a current sensing circuit and a variable load, controls the output power through a feedback mechanism, and solves the problem of gain instability caused by temperature changes, and has significant advantages in linear adjustment of input signals and multi-stage current mirror design. There are problems such as single control function, poor weak signal processing ability, and circuit reliability caused by multiple feedback loops.

[0005] Therefore, there is an urgent need for a variable gain amplifier control circuit at present. Summary of the Invention

[0006] In view of this, the present invention discloses a variable gain amplifier control circuit to solve the above problems; it includes components: 10 resistors, 6 PNP transistors, 13 NPN transistors, 2 current sources I1 and I2;

[0007] Further, the emitter of QP1 is connected to the emitter of QP2, the base of QP1 is respectively connected to the base of QP2, the collector of QP2, and one end of R1, and the collector of QP1 is respectively connected to the base of QN6, the collector of QN6, the collector of QP5, the collector of QP6, and the base of QN7;

[0008] The other end of R1 is respectively connected to one end of R2, one end of R3, and one end of R4;

[0009] The other end of R2 is connected to the emitter of QN3;

[0010] The other end of R3 is respectively connected to the emitter of QN4 and the emitter of QP5;

[0011] The other end of R4 is connected to the emitter of QP6;

[0012] The base of QN3 is respectively connected to the base of QN4, the base of QN5, and the collector of QN5. The collector of QN3 is respectively connected to the collector of QN4, the emitter of QN1, and the emitter of QN2;

[0013] The base of QN1 is respectively connected to one end of R7 and one end of R9. The collector of QN1 is respectively connected to the emitter of QP3 and the emitter of QP4;

[0014] The base of QN2 is respectively connected to one end of R8 and one end of R10. The collector of QN2 is respectively connected to the collector of QP3, the base of QP3, and the base of QP4;

[0015] The collector of QP4 is respectively connected to the collector of QN7 and the collector of QN8;

[0016] The emitter of QN5 is respectively connected to the base of QP5, the base of QP6, and the input end of I1;

[0017] The output end of I1 is respectively connected to the emitter of QN6, the emitter of QN7, one end of R5, the emitter of QN11, the emitter of QN12 and is grounded;

[0018] The other end of R5 is connected to the emitter of QN8;

[0019] The base of QN8 is respectively connected to the emitter of QN9 and the collector of QN11;

[0020] The collector of QN9 is connected to the input end of I2;

[0021] The output end of I2 is respectively connected to the base of QN9, the base of QN10, and the collector of QN10;

[0022] The emitter of QN10 is connected to one end of R6;

[0023] The other end of R6 is respectively connected to the base of QN11, the base of QN12, and the collector of QN12;

[0024] The other end of R7 is respectively connected to the emitter of QN13 and the other end of R8;

[0025] The other end of R9 is grounded;

[0026] The other end of R10 is grounded.

[0027] The present invention implements different control schemes according to the magnitude of the input signal, introduces an adjustable threshold voltage, dynamically adjusts the gain control current, and adjusts the signal gain in segments to make the gain scheme more flexible, solving the problem of single weak signal amplification ability; it uses fewer feedback loops, has a simple structure, and higher circuit reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a circuit structure diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] In order to make the purpose, technical solutions, features and advantages of the present invention clearer, the present invention will be further described below in conjunction with the drawings and embodiments.

[0030] The variable gain amplifier control circuit disclosed by the present invention includes components: 10 resistors R1 to R10, 6 PNP transistors QP1 to QP6, 13 NPN transistors QN1 to QN13, and 2 current sources I1 and I2. Their connection method is as follows: The emitter of QP1 is connected to the emitter of QP2. The base of QP1 is respectively connected to the base of QP2, the collector of QP2, and one end of R1. The collector of QP1 is respectively connected to the base of QN6, the collector of QN6, the collector of QP5, the collector of QP6, and the base of QN7. The other end of R1 is respectively connected to one end of R2, one end of R3, and one end of R4. The other end of R2 is connected to the emitter of QN3. The other end of R3 is respectively connected to the emitter of QN4 and the emitter of QP5. The other end of R4 is connected to the emitter of QP6. The base of QN3 is respectively connected to the base of QN4, the base of QN5, and the collector of QN5. The collector of QN3 is respectively connected to the collector of QN4, the emitter of QN1, and the emitter of QN2. The base of QN1 is respectively connected to one end of R7 and one end of R9. The collector of QN1 is respectively connected to the emitter of QP3 and the emitter of QP4. The base of QN2 is respectively connected to one end of R8 and one end of R10. The collector of QN2 is respectively connected to the collector of QP3, the base of QP3, and the base of QP4. The collector of QP4 is respectively connected to the collector of QN7 and the collector of QN8. The emitter of QN5 is respectively connected to the base of QP5, the base of QP6, and the input end of I1. The output end of I1 is respectively connected to the emitter of QN6, the emitter of QN7, one end of R5, the emitter of QN11, and the emitter of QN12 and grounded. The other end of R5 is connected to the emitter of QN8. The base of QN8 is respectively connected to the emitter of QN9 and the collector of QN11. The collector of QN9 is connected to the input end of I2. The output end of I2 is respectively connected to the base of QN9, the base of QN10, and the collector of QN10. The emitter of QN10 is connected to one end of R6. The other end of R6 is respectively connected to the base of QN11, the base of QN12, and the collector of QN12. The other end of R7 is respectively connected to the emitter of QN13 and the other end of R8. The other end of R9 is grounded. The other end of R10 is grounded.

[0031] Among them, the end where R3 and R4 are connected is used as the input end of the circuit. The collector of QP4 is used as the output end of the circuit. The collector of QP2 is used as the comparison end 1 of the circuit. The emitter of QN4 is used as the comparison end 2 of the circuit. The emitters of QP2, the collector of QN13, the collector of QN5, and the collector of QN9 are used as the power supply ends of the circuit. The base of QN13 is used as the reference voltage end.

[0032] Further, the resistance values of R7 and R8 are the same; R9 >> R7, R10 >> R7, R2 >> R3, R4 >> R3; the resistance value range of R10 is 22.5 kΩ to 422 kΩ, the resistance value range of R5 is 1 kΩ to 20 kΩ, the voltage of the power supply terminal is 5V, the voltage of the reference voltage terminal is 3.7V, the current of I1 is 25 μA, the current of I2 is 30 μA, the voltages of comparison terminal 1 and comparison terminal 2, and the resistance values of R5 and R10 are adjusted by the user customarily.

[0033] Further, the circuit introduces a threshold voltage through comparison terminal 1 and comparison terminal 2. The voltage of comparison terminal 1 is the upper threshold voltage V TH_RP , and the voltage of comparison terminal 2 is the lower threshold voltage V TH_NG . By comparing the input signal V LDSF with the threshold voltage, the gain control current is dynamically adjusted to achieve segmented control of the output current signal I ctrl .

[0034] Specifically, there are three working states when the circuit is working:

[0035] Working state 1: When the signal satisfies V LDSF > V TH_RP , the current flow direction is as shown by the Figure 1 blue arrow. The current flows through QP4 and QP5 and converges, and then is mirrored by the current mirror composed of QN11 and QN12 into I NGO in the figure. The output signal I ctrl is composed of the current I NGO passing through the collector of QN7 and the current I RPG passing through the collector of QN8. The magnitude of I RPG is controlled by R5. The symbol with a subscript is used to replace the resistance value of the resistor, such as R5 replacing the resistance value of resistor R5.

[0036] Further, the calculation formula of the output signal is:

[0037]

[0038] Among them, V EB5 is the voltage from the emitter to the base of QP5, and V EB6 is the voltage from the emitter to the base of QP6.

[0039] Further, by combining, we get:

[0040]

[0041] Further, in the present invention, R4 >> R3, and I ctrl is approximately:

[0042]

[0043] Among them, I2 represents Figure 1 the current of the PTAT (proportional to absolute temperature) current source in it is 30 μA, V B_RPG is the base voltage of QN8, V BE8 is the base-to-emitter voltage of QN8, V T is the thermal voltage of the transistor, and the calculation formula is V T = kT / q, where k represents the Boltzmann constant, T represents the temperature, q represents the electron charge, and the thermal voltage V T is about 26 mV at room temperature of 300 K.

[0044] Furthermore, since I RPG can be further simplified to:

[0045]

[0046] Furthermore, I RPG is proportional to the temperature and inversely proportional to the R5 resistor. The obtained signal V LDSF is greater than V TH_RP when the output current is:

[0047]

[0048] Operating state 2: When the signal satisfies V TH_NG < V LDSF < V TH_RP <, the current flows as shown by the purple arrow, and the current path converges at the collectors of QN3 and QN4. The current is controlled and distributed by the base voltage difference of QN1 and QN2, and the voltage distribution is controlled through the external resistor R Figure 1 10 to control the magnitude of V BCMPR - V CCMPR CCMPR . The current in the branch where QN2 is located is mirrored by the current mirrors QP3 and QP4 to I CMRP , and I ctrl is composed of I CMRP and I RPG . Among them, R 10 10 , R5 are set by the user.

[0049]

[0049] Furthermore, I TCMP represents the converging current I TCMP at the collectors of QN3 and QN4, and the calculation formula is as follows:

[0050]

[0051] Among them, V BEQN4 is the base-to-emitter voltage of QN4, VBEQN3 is the base-to-emitter voltage of QN4, L CQN1 is the collector current of QN1, L CQN2 is the collector current of QN2, L CQN3 is the collector current of QN3, I CQN4 is the collector current of QN4.

[0052]

[0053] I CQN7 + I CQN8 = I TCMP

[0054]

[0055] Among them, V B3V represents the emitter voltage of QN13.

[0056] Furthermore, in the present invention, R 10 >> R7, R9 >> R7, R2 >> R3, so there is:

[0057]

[0058] Furthermore, it is obtained that:

[0059]

[0060] Operating state 3: When the signal is less than the lowest threshold V LDSF < V TH_NG At this time, in addition to the current path shown in case 2, there is also a current flow direction as shown by the red arrow in Figure 1 . The current passes through the current mirrors of QP7 and QP8, and then through the current mirrors of QN11 and QN12 to I NGO , I ctrl is composed of I CMPR , I RPG , I NGO . I RPG is controlled by the external resistor R5, and R 10 , R5 are set by the user.

[0061] Furthermore, when the input signal is less than V TH_NG , there will be an additional item I NGO pull-down current in the gain control current. At this time, the formula for I ctrl is:

[0062] I ctrl = I NGO + I RPG - I CMPR

[0063]

[0064] Furthermore, the total input control current is:

[0065]

[0066] Finally, it should be noted that the above description only depicts some embodiments of the present invention. For those skilled in the art, various changes, modifications, substitutions, and variations can be conceived without departing from the principles and spirit of the present invention. The protection scope of the present invention is defined by the appended claims and their equivalents, and the above actions should all be covered within the protection scope of the present invention.

Claims

1. A variable gain amplifier control circuit, characterized in that: include: 10 resistors R1 to R10, 6 PNP transistors QP1 to QP6, 13 NPN transistors QN1 to QN13, 2 current sources I1 and I2; The connection method is as follows: the emitter of QP1 is connected to the emitter of QP2, the base of QP1 is connected to the base of QP2, the collector of QP2, and one end of R1 respectively, and the collector of QP1 is connected to the base of QN6, the collector of QN6, the collector of QP5, the collector of QP6, and the base of QN7 respectively; The other end of R1 is connected to one end of R2, one end of R3, and one end of R4 respectively; The other end of R2 is connected to the emitter of QN3; The other end of R3 is connected to the emitter of QN4 and the emitter of QP5 respectively; The other end of R4 is connected to the emitter of QP6; The base of QN3 is connected to the base of QN4, the base of QN5, and the collector of QN5, respectively. The collector of QN3 is connected to the collector of QN4, the emitter of QN1, and the emitter of QN2, respectively. The base of QN1 is connected to one end of R7 and one end of R9 respectively, and the collector of QN1 is connected to the emitter of QP3 and the emitter of QP4 respectively; The base of QN2 is connected to one end of R8 and one end of R10 respectively, and the collector of QN2 is connected to the collector of QP3, the base of QP3 and the base of QP4 respectively; The collector of QP4 is connected to the collector of QN7 and the collector of QN8 respectively; The emitter of QN5 is connected to the base of QP5, the base of QP6, and the input terminal of I1 respectively; The output end of I1 is respectively connected to the emitter of QN6, the emitter of QN7, one end of R5, the emitter of QN11, the emitter of QN12 and grounded; The other end of R5 is connected to the emitter of QN8; The base of QN8 is connected to the emitter of QN9 and the collector of QN11 respectively; The collector of QN9 is connected to the input of I2; The output end of I2 is connected to the base of QN9, the base of QN10, and the collector of QN10 respectively; The emitter of QN10 is connected to one end of R6; The other end of R6 is connected to the base of QN11, the base of QN12, and the collector of QN12 respectively; The other end of R7 is connected to the emitter of QN13 and the other end of R8 respectively; The other end of R9 is grounded; The other end of R10 is grounded.

2. The variable gain amplifier control circuit according to claim 1, characterized in that: The end where R3 and R4 are connected serves as the input end of the circuit, the collector of QP4 serves as the output end of the circuit, the collector of QP2 serves as the comparison end 1 of the circuit, the emitter of QN4 serves as the comparison end 2 of the circuit, the emitter of QP2, the collector of QN13, the collector of QN5, and the collector of QN9 serve as the power supply end of the circuit, and the base of QN13 serves as the reference voltage end.

3. The variable gain amplifier control circuit according to claim 2, characterized in that: The voltage at comparison terminal 1 is higher than the voltage at comparison terminal 2. According to the relationship between the input voltage and comparison terminals 1 and 2, the circuit has three states: the input voltage is less than the voltage at comparison terminal 2; the input voltage is between the voltage at comparison terminal 1 and the voltage at comparison terminal 2; the input voltage is greater than the voltage at comparison terminal 1; by comparing the voltage of the input signal with the voltage at the comparison terminal, the gain control current is dynamically adjusted to achieve segmented signal gain adjustment.

4. The variable gain amplifier control circuit according to claim 3, characterized in that: By adjusting the resistance values ​​of R10 and R5, the signal gain in the state can be adjusted. The resistance adjustment range of R10 is 22.5kΩ~422kΩ, and the resistance adjustment range of R5 is 1kΩ~20kΩ.

5. The variable gain amplifier control circuit according to claim 1, characterized in that: R7 and R8 have the same resistance value; R9>>R7, R10>>R7, R2>>R3, R4>>R3.

6. The variable gain amplifier control circuit according to claim 1, characterized in that: The power supply terminal voltage is 5V, and the reference voltage terminal voltage is 3.7V.

7. The variable gain amplifier control circuit according to claim 1, characterized in that: The current of I1 is 25μA, and I2 is a PTAT (proportional to absolute temperature) current source, and the current of I2 is 30μA.

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