Special voltage early-out and late-off time sequence control circuit and application method
By designing a special voltage early out-night off timing control circuit including preset logic lines, RC delay lines and logic inverter lines, the problem of early out-night off timing control of CPU voltage supply is solved, and the accuracy and cost-effectiveness of voltage control are achieved.
Patent Information
- Application Number
- CN202510276621.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2025-06-27
AI Technical Summary
The prior art is difficult to effectively control the early exit and late shutdown timing of CPU voltage power supply, especially in the absence of clear time requirements, which leads to complex hardware design, high cost and high programming difficulties.
A special voltage early exit and late closing timing control circuit is designed, including preset logic lines, RC delay lines and logic inverter lines. Through the combination of these lines, precise control of voltage output is achieved.
This control circuit can easily, practically and cost-effectively realize the timing control of voltage out and late shutdown, solving the problem of no specific time requirements for voltage getting up and late falling, and improving the feasibility and efficiency of hardware design.
Smart Images
Figure CN120223025A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of CPU voltage power supply control, and more specifically, to a special voltage early-on and late-off timing control circuit and an application method thereof. Background Art
[0002] In the application of X86 PC computers, due to different power supply groups for the CPU voltage power supply in domestic platforms, there are special requirements for the power-on / off timing of the power supply. The requirement is that one voltage obtains the control enable to turn on the voltage latest, and it is the last one to turn off when the voltage output is turned off; the reason is that the CPU has its own considerations for the voltage design. Mainly, it turns off first under the condition of a large power consumption current and heavy load to avoid sudden power-off of the power of other secondary functional modules and related settings, which may cause instability during the next startup.
[0003] In addition, there is no clear time requirement for this special power-on and power-off, that is, it is not necessary to accurately control the time interval between each level of voltage. In hardware design, it is difficult to implement with ordinary control logic. It is often implemented by programmable methods such as CPLD / MCU / EC, which has relatively high requirements for component selection, requires multiple independent control IO ports, and has a relatively high cost. At the same time, it requires additional professional human support in programming;
[0004] To solve the above industry problems, a special voltage early-on and late-off timing control circuit and an application method thereof are needed. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a special voltage early-on and late-off timing control circuit in view of the above defects of the prior art, and also provide an application method of the special voltage early-on and late-off timing control circuit.
[0006] The technical solution adopted by the present invention to solve its technical problems is as follows:
[0007] Construct a special voltage early-on and late-off timing control circuit, which includes a preset logic circuit, an RC delay circuit, and a logic inverter circuit;
[0008] The preset logic circuit is connected to two input control terminals, and is used to output a low level through NAND when the two input control terminals are at a high level, and output a high level through NAND when the two input control terminals are at a low level;
[0009] The RC delay circuit includes a first delay circuit and a second delay circuit. Both the first delay circuit and the second delay circuit are connected to the output terminal of the preset logic circuit, and are used to output two low levels one after another when the output terminal of the preset logic circuit is at a low level, and output two high levels one after another when the output terminal of the preset logic circuit is at a high level;
[0010] The logic inverter circuit receives the outputs of the first delay circuit and the second delay circuit, and when the outputs of the first delay circuit and the second delay circuit are two low levels in sequence, obtains the first control signal and the second control signal with driving ability correspondingly, and when the outputs of the first delay circuit and the second delay circuit are two high levels in sequence, obtains the second control signal and the first control signal with driving ability correspondingly.
[0011] In the special voltage early output and late turn-off timing control circuit of the present invention, the preset logic circuit includes: a NAND gate with two inputs, the two inputs of the NAND gate are respectively connected to two input control terminals, and the output terminal of the NAND gate is connected to an RC delay circuit.
[0012] In the special voltage early output and late turn-off timing control circuit of the present invention, one input terminal of the NAND gate is further connected with a first resistor and a second resistor, the other end of the first resistor is connected to a 3.3V power supply terminal, and the other end of the second resistor is grounded; the other input terminal of the NAND gate is further connected with a third resistor, the other end of the third resistor is connected to the corresponding input control terminal and a fourth resistor, and the other end of the fourth resistor is grounded; the positive pin of the NAND gate is connected to the 3.3V power supply terminal and a first capacitor, and the other end of the first capacitor is grounded; the negative pin of the NAND gate is grounded.
[0013] In the special voltage early output and late turn-off timing control circuit of the present invention, the first delay circuit includes: a fifth resistor, a sixth resistor and a first diode, one end of the fifth resistor and the negative electrode of the first diode are both connected to the output terminal of the preset logic circuit, and the other end of the fifth resistor is connected to the positive electrode of the first diode and the sixth resistor; the other end of the sixth resistor is connected with a second capacitor, and the other end of the second capacitor is connected to the 3.3V power supply terminal.
[0014] In the special voltage early output and late turn-off timing control circuit of the present invention, the second delay circuit includes: a seventh resistor, an eighth resistor and a second diode, one end of the seventh resistor and the positive electrode of the second diode are both connected to the output terminal of the preset logic circuit, and the other end of the seventh resistor is connected to the negative electrode of the second diode and the eighth resistor; the other end of the eighth resistor is connected with a third capacitor, and the other end of the third capacitor is connected to the 3.3V power supply terminal.
[0015] In the special voltage early output and late turn-off timing control circuit of the present invention, the logic inverter circuit includes a first branch and a second branch;
[0016] The first branch includes: a first Schmitt inverter, a ninth resistor, a tenth resistor, and a fourth capacitor; the input terminal of the first Schmitt inverter is connected to the other end of the sixth resistor, the output terminal of the first Schmitt inverter is connected to the ninth resistor and the tenth resistor, the positive electrode of the first Schmitt inverter is connected to the 3.3V power supply terminal and the fourth capacitor, the other end of the fourth capacitor is grounded, and the negative electrode of the first Schmitt inverter is grounded; the other end of the ninth resistor is grounded, and the other end of the tenth resistor is the output terminal of the first branch;
[0017] The second branch includes: a second Schmitt inverter, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor; the input terminal of the second Schmitt inverter is connected to the other end of the eighth resistor, the output terminal of the second Schmitt inverter is connected to the eleventh resistor, the twelfth resistor, the thirteenth resistor, and the fourteenth resistor, the other end of the eleventh resistor is grounded, and the other ends of the twelfth resistor, the thirteenth resistor, and the fourteenth resistor are all output terminals of the second branch.
[0018] In the special voltage early-on and late-off timing control circuit of the present invention, the first control signal and the second control signal are EN1 and VDDCPU_EN respectively.
[0019] A method for applying a special voltage early-on and late-off timing control circuit, which applies the special voltage early-on and late-off timing control circuit as described above, wherein the method includes the steps of:
[0020] Adopt a preset logic circuit connected to the two input control terminals, and output a low level through NAND when the two input control terminals are at a high level, and output a high level through NAND when the two input control terminals are at a low level;
[0021] Connect both the first delay circuit and the second delay circuit to the output terminal of the preset logic circuit, output two low levels one after another when the output terminal of the preset logic circuit is at a low level, and output two high levels one after another when the output terminal of the preset logic circuit is at a high level;
[0022] Through a logic inverter circuit, receive the outputs of the first delay circuit and the second delay circuit. When the outputs of the first delay circuit and the second delay circuit are two low levels one after another, correspondingly obtain the first control signal and the second control signal with driving ability. When the outputs of the first delay circuit and the second delay circuit are two high levels one after another, correspondingly obtain the second control signal and the first control signal with driving ability.
[0023] The beneficial effect of the present invention is that a preset logic circuit connected to the two input control terminals is adopted,
[0024] When the two input control terminals are at high level, the output is low level after NAND operation, and when the two input control terminals are at low level, the output is high level after NAND operation; both the first delay line and the second delay line are connected to the output terminal of the preset logic line. When the output terminal of the preset logic line is at low level, two low levels are output one after the other, and when the output terminal of the preset logic line is at high level, two high levels are output one after the other; through the logic inverter line, receiving the outputs of the first delay line and the second delay line, when the outputs of the first delay line and the second delay line are two low levels one after the other, the first control signal and the second control signal with driving ability are correspondingly obtained, and when the outputs of the first delay line and the second delay line are two high levels one after the other, the second control signal and the first control signal with driving ability are correspondingly obtained;
[0025] Applying the method of the present application, using the secondary unidirectionality and RC delay lines, the front-end preset level control line and the rear-end logic signal processing to ensure the driving ability line form an application line of control RC delay control for the appearance of opening and closing. The circuit design of the control line is simple, practical and low-cost, and can well solve the industry problem of early voltage rise and late voltage drop without specific time requirements. Brief Description of the Drawings
[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will further illustrate the present invention in conjunction with the drawings and embodiments. The drawings in the following description are only partial embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts:
[0027] Figure 1 is the circuit diagram of the special voltage early appearance and late turn-off timing control circuit of the preferred embodiment of the present invention;
[0028] Figure 2 is the timing control flowchart of the special voltage early appearance and late turn-off timing control circuit of the preferred embodiment of the present invention;
[0029] Figure 3 is the application method flowchart of the special voltage early appearance and late turn-off timing control circuit of the preferred embodiment of the present invention. Detailed Embodiments
[0030] In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are partial embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
[0031] The special voltage early-on and late-off timing control circuit of the preferred embodiment of the present invention, as Figure 1 shown, also referring to Figure 2 , includes a preset logic circuit 1, an RC delay circuit 2, and a logic inverter circuit 3;
[0032] The preset logic circuit 1 is connected to two input control terminals, and is used to output a low level after NAND operation when the two input control terminals are at high levels, and output a high level after NAND operation when the two input control terminals are at low levels;
[0033] The RC delay circuit 2 includes a first delay circuit 20 and a second delay circuit 20. Both the first delay circuit and the second delay circuit are connected to the output terminal of the preset logic circuit, and are used to output two low levels one after another when the output terminal of the preset logic circuit is at a low level, and output two high levels one after another when the output terminal of the preset logic circuit is at a high level;
[0034] The logic inverter circuit 3 receives the outputs of the first delay circuit and the second delay circuit, and correspondingly obtains a first control signal and a second control signal with driving ability when the outputs of the first delay circuit and the second delay circuit are two low levels one after another, and correspondingly obtains two second control signals and a first control signal with driving ability when the outputs of the first delay circuit and the second delay circuit are two high levels one after another;
[0035] Adopt a preset logic circuit connected to two input control terminals, output a low level after NAND operation when the two input control terminals are at high
[0036] levels, and output a high level after NAND operation when the two input control terminals are at low levels; both the first delay circuit and the second delay circuit are connected to the output terminal of the preset logic circuit, output two low levels one after another when the output terminal of the preset logic circuit is at a low level, and output two high levels one after another when the output terminal of the preset logic circuit is at a high level; through the logic inverter circuit, receive the outputs of the first delay circuit and the second delay circuit, and correspondingly obtain a first control signal and a second control signal with driving ability when the outputs of the first delay circuit and the second delay circuit are two low levels one after another, and correspondingly obtain two second control signals and a first control signal with driving ability when the outputs of the first delay circuit and the second delay circuit are two high levels one after another;
[0037] Preferably, the first control signal and the second control signal are EN1 and VDDCPU_EN respectively.
[0038] By applying the method of the present application, using the second-order unidirectionality and RC delay circuit, the pre-set level control circuit, the post-logic signal processing, and the post-end drive capability circuit are combined to form an application circuit for controlling the RC delay of the on and off occurrences. The circuit design of the control circuit is simple, practical, and low-cost, and can well solve the industry problem of early voltage rise and late voltage drop without specific time requirements.
[0039] A specific implementation circuit, as Figure 1 shown, can adopt:
[0040] The preset logic circuit includes: a NAND gate U38 with two inputs. The two inputs of the NAND gate U38 are respectively connected to two input control terminals, and the output terminal of the NAND gate U38 is connected to the RC delay circuit; one input terminal of the NAND gate U38 is also connected to a first resistor R606 and a second resistor R609. The other end of the first resistor R606 is connected to a 3.3V power supply terminal, and the other end of the second resistor R609 is grounded; the other input terminal of the NAND gate U38 is also connected to a third resistor R611. The other end of the third resistor R611 is connected to the corresponding input control terminal and a fourth resistor R613, and the other end of the fourth resistor R603 is grounded; the positive pin of the NAND gate U38 is connected to the 3.3V power supply terminal and a first capacitor C224, and the other end of the first capacitor C224 is grounded; the negative pin of the NAND gate U38 is grounded.
[0041] Preferably, the first delay circuit includes: a fifth resistor R614, a sixth resistor R615, and a first diode D39. One end of the fifth resistor R614 and the cathode of the first diode D39 are both connected to the output terminal of the preset logic circuit. The other end of the fifth resistor R614 is connected to the anode of the first diode D39 and the sixth resistor; the other end of the sixth resistor R615 is connected to a second capacitor C227, and the other end of the second capacitor C227 is connected to the 3.3V power supply terminal;
[0042] The second delay circuit includes: a seventh resistor R734, an eighth resistor R739, and a second diode D46. One end of the seventh resistor R734 and the anode of the second diode D46 are both connected to the output terminal of the preset logic circuit. The other end of the seventh resistor R734 is connected to the cathode of the second diode D46 and the eighth resistor R739; the other end of the eighth resistor R739 is connected to a third capacitor C223, and the other end of the third capacitor C223 is connected to the 3.3V power supply terminal;
[0043] The logic inverter circuit 3 includes a first branch and a second branch;
[0044] The first branch includes: the first Schmitt inverter U39A, the ninth resistor R617, the tenth resistor R616, and the fourth capacitor C227; the input terminal of the first Schmitt inverter U39A is connected to the other end of the sixth resistor R615, the output terminal of the first Schmitt inverter U39A is connected to the ninth resistor R617 and the tenth resistor R616, the positive terminal of the first Schmitt inverter U39A is connected to the 3.3V power supply terminal and the fourth capacitor, the other end of the fourth capacitor is grounded, and the negative terminal of the first Schmitt inverter U39A is grounded; the other end of the ninth resistor R617 is grounded, and the other end of the tenth resistor R616 is the output terminal of the first branch;
[0045] The second branch includes: the second Schmitt inverter U39B, the eleventh resistor R744, the twelfth resistor R727, the thirteenth resistor R605, and the fourteenth resistor R630; the input terminal of the second Schmitt inverter U39B is connected to the other end of the eighth resistor R739, the output terminal of the second Schmitt inverter U39B is connected to the eleventh resistor R744, the twelfth resistor R727, the thirteenth resistor R605, and the fourteenth resistor R630, the other end of the eleventh resistor R744 is grounded, and the other ends of the twelfth resistor R727, the thirteenth resistor R605, and the fourteenth resistor R630 are all the output terminals of the second branch;
[0046] Combined with Figure 1 and Figure 2 The description is as follows:
[0047] The pre - set logic circuit uses a two - input "NAND gate". Before power - on, the input terminals are at low level. After inversion, the pre - set default value is at high level; it keeps the voltage across CAP in the RC circuit at 3.3V level; when both input terminals are at high level, it outputs a low level through logical NAND, and then passes through RC delay circuits in different directions;
[0048] The RC delay circuit, when there is a valid high level in the front, obtains a low level. An RC delay circuit is composed of a resistor, a diode, and a capacitor. Then, according to different parameters, output enable signals with different time differences before and after are obtained;
[0049] The post - logic inverter circuit uses a Schmitt logic inverter to change the RC discharge / charge to a certain level into a stable output level value, and uses the driving ability of the inverter to control multiple voltage output enable terminals simultaneously;
[0050] The logic circuit for realizing timing control:
[0051] 1. Turn-on voltage control: When the two input control terminals are at high level, the output is low level after NAND operation, and then through the first RC1 (R614 / R615 / C228) delay line and the second RC2 (D46 / R739 / C223) delay line, two low levels with a time difference are generated, which are respectively sent to the Schmitt inverter to obtain two drivable EN1 and VDDCPU_EN;
[0052] 2. Turn-off voltage control: When shutting down, when the two inputs are at low level, the output is high level after NAND operation, and then through the first RC1 (D39 / R615 / C228) delay line and the second RC2 (R734 / R739 / C223) delay line, two inverted high levels with a time difference are generated, which are respectively sent to the Schmitt inverter to obtain two drivable VDDCPU_EN and EN1.
[0053] A method for applying a special voltage early-on and late-off timing control circuit, which applies the special voltage early-on and late-off timing control circuit as described above, as Figure 3 shown, the method includes the steps:
[0054] S01: Use a preset logic circuit connected to the two input control terminals to output a low level after NAND operation when the two input control terminals are at high level, and output a high level after NAND operation when the two input control terminals are at low level;
[0055] S02: Connect both the first delay line and the second delay line to the output terminal of the preset logic circuit, output two low levels with a time difference when the output terminal of the preset logic circuit is at low level, and output two high levels with a time difference when the output terminal of the preset logic circuit is at high level;
[0056] S03: Through the logic inverter circuit, receive the outputs of the first delay line and the second delay line. When the outputs of the first delay line and the second delay line are two low levels with a time difference, obtain the first control signal and the second control signal with driving ability correspondingly. When the outputs of the first delay line and the second delay line are two high levels with a time difference, obtain the second control signal and the first control signal with driving ability correspondingly;
[0057] Applying the method of the present application, using the second-level unidirectionality and RC delay lines, the pre-set preset level control circuit and the post-logic signal processing to ensure the driving ability of the backend form an application circuit for controlling the RC delay of the turn-on and turn-off, and the circuit design of the control circuit is simple, practical and low-cost, which can well solve the industry problem of the early rise and late drop of voltage without specific time requirements.
[0058] It should be understood that those of ordinary skill in the art can make improvements or modifications based on the above description, and all such improvements and modifications shall fall within the protection scope of the appended claims of the present invention.
Claims
1. A special voltage early-out late-off timing control circuit, characterized in that: including a preset logic circuit, an RC delay circuit, and a logic inverter circuit; The preset logic circuit is connected to the two input control terminals, and is used to output a low level after performing an AND operation when the two input control terminals are at a high level, and to output a high level after performing an AND operation when the two input control terminals are at a low level; The RC delay line includes a first delay line and a second delay line, both of which are connected to the output end of the preset logic line, and are used to output two low levels one after the other when the output end of the preset logic line is at a low level, and to output two high levels one after the other when the output end of the preset logic line is at a high level; The logic inverter circuit receives the outputs of the first delay line and the second delay line, and when the outputs of the first delay line and the second delay line are two low levels one after the other, the first control signal and the second control signal with driving capability are correspondingly obtained, and when the outputs of the first delay line and the second delay line are two high levels one after the other, the two second control signals and the first control signal with driving capability are correspondingly obtained.
2. The special voltage early-out late-off timing control circuit according to claim 1, characterized in that: The preset logic circuit includes: a NAND gate with two inputs, the two inputs of the NAND gate are respectively connected to two input control terminals, and the output terminal of the NAND gate is connected to an RC delay circuit.
3. The special voltage early-out late-off timing control circuit according to claim 2, characterized in that: One input end of the NAND gate is also connected to a first resistor and a second resistor, the other end of the first resistor is connected to a 3.3V power supply end, and the other end of the second resistor is grounded; another input end of the NAND gate is also connected to a third resistor, the other end of the third resistor is connected to a corresponding input control end and a fourth resistor, and the other end of the fourth resistor is grounded; the positive pin of the NAND gate is connected to a 3.3V power supply end and a first capacitor, and the other end of the first capacitor is grounded; the negative pin of the NAND gate is grounded.
4. The special voltage early-out late-off timing control circuit according to claim 1, characterized in that: The first delay line includes: a fifth resistor, a sixth resistor and a first diode, one end of the fifth resistor and the cathode of the first diode are connected to the output end of the preset logic circuit, the other end of the fifth resistor is connected to the anode of the first diode and the sixth resistor; the other end of the sixth resistor is connected to a second capacitor, and the other end of the second capacitor is connected to a 3.3V power supply terminal.
5. The special voltage early-out late-off timing control circuit according to claim 4, characterized in that: The second delay line includes: a seventh resistor, an eighth resistor and a second diode, one end of the seventh resistor and the positive electrode of the second diode are connected to the output end of the preset logic circuit, the other end of the seventh resistor is connected to the negative electrode of the second diode and the eighth resistor; the other end of the eighth resistor is connected to a third capacitor, and the other end of the third capacitor is connected to a 3.3V power supply terminal.
6. The special voltage early-out late-off timing control circuit according to claim 5, characterized in that: The logic inverter circuit includes a first branch and a second branch; The first branch includes: a first Schmidt inverter, a ninth resistor, a tenth resistor and a fourth capacitor; the input end of the first Schmidt inverter is connected to the other end of the sixth resistor, the output end of the first Schmidt inverter is connected to the ninth resistor and the tenth resistor, the positive electrode of the first Schmidt inverter is connected to the 3.3V power supply end and the fourth capacitor, the other end of the fourth capacitor is grounded, and the negative electrode of the first Schmidt inverter is grounded; the other end of the ninth resistor is grounded, and the other end of the tenth resistor is the output end of the first branch; The second branch includes: a second Schmitt inverter, an eleventh resistor, a twelfth resistor, a thirteenth resistor and a fourteenth resistor; the input end of the second Schmitt inverter is connected to the other end of the eighth resistor, the output end of the second Schmitt inverter is connected to the eleventh resistor, the twelfth resistor, the thirteenth resistor and the fourteenth resistor, the other end of the eleventh resistor is grounded, and the other end of the twelfth resistor, the other end of the thirteenth resistor and the other end of the fourteenth resistor are all output ends of the second branch.
7. The special voltage early-out late-off timing control circuit according to claim 1, characterized in that: The first control signal and the second control signal are EN1 and VDDCPU_EN respectively.
8. A method for applying a special voltage early-out late-off timing control circuit, using the special voltage early-out late-off timing control circuit as claimed in any one of claims 1 to 7, characterized in that: The method comprises the steps of: Using a preset logic circuit connected to the two input control terminals, when the two input control terminals are at a high level, a low level is output through a negative AND operation, and when the two input control terminals are at a low level, a high level is output through a negative AND operation; Connecting the first delay line and the second delay line to the output end of the preset logic line, outputting two low levels one after the other when the output end of the preset logic line is at a low level, and outputting two high levels one after the other when the output end of the preset logic line is at a high level; The outputs of the first delay line and the second delay line are received through a logic inverter circuit. When the outputs of the first delay line and the second delay line are two low levels one after the other, a first control signal and a second control signal with driving capability are correspondingly obtained. When the outputs of the first delay line and the second delay line are two high levels one after the other, two second control signals and a first control signal with driving capability are correspondingly obtained.