Phase adjusting circuit based on SYSREF signal
By designing a phase adjustment circuit based on SYSREF signal, the clock phase of multiple ADC chips is automatically adjusted, which solves the problem of manual phase adjustment in the prior art, and achieves efficient multi-chip synchronization and glitch filtering.
Patent Information
- Application Number
- CN202510377705.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-06-27
AI Technical Summary
In the prior art, the method of manually adjusting the phase has the disadvantages of cumbersome operation and low efficiency, making it difficult to efficiently realize the synchronization of multiple high-speed ADC chips.
A phase adjustment circuit based on SYSREF signal is designed, including a phase reading circuit and a phase adjustment circuit. By judging the phase relationship between the reference clock signal and the SYSREF signal, a phase adjustment control codeword is generated, and the phase of the clock signal is automatically adjusted to avoid glitch generation.
Automatic phase adjustment is realized, tedious operation of manual adjustment is avoided, efficiency is improved, and by filtering out glitches, the impact on the digital circuit feedback loop is reduced, and the clock signal after filtering out glitches is obtained that is aligned with the rising edge of the SYSREF signal.
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Figure CN120223028A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of phase adjustment, and particularly to a phase adjustment circuit based on a SYSREF signal. Background Art
[0002] With the rapid development of digital signal processing technology, in scientific research and engineering, high-speed ADC (Analog-to-Digital Converter) circuits are often used to collect multiplexed signal data at different times, which has a wide range of applications in radar communication, real-time monitoring, etc., thus posing higher requirements for the synchronization of multiple high-speed ADC chips.
[0003] In high-speed ADC circuits, an externally input low-speed SYSREF signal is often used as a reference signal. When the rising edge of the SYSREF signal arrives, reset operations are performed on circuits such as frequency dividers and counters of the circuits to be synchronized in the system. Since the SYSREF signals input by multiple ADC chips are the same, all ADC chips complete the reset operation at the same time, thereby achieving clock and data alignment operations.
[0004] Taking a frequency divider by two as an example, Figure 1 A commonly used method for resetting the frequency divider is given:
[0005] Among them, clk_div1 is the input clock signal, clk_div2 is the output clock signal divided by two, rst_n is the asynchronous reset terminal, and sysref_divder_rst is the reset signal (low-level reset) generated by detecting the rising edge of the SYSREF signal. However, in this method, the sysref_divder_rst generation circuit needs to add an additional feedback circuit to avoid generating glitches, which has a high cost. In addition, by manually adjusting the phase, there are defects such as cumbersome operation and low efficiency. Summary of the Invention
[0006] The technical problem to be solved by the present disclosure is to overcome the defects of cumbersome operation and low efficiency in the prior art by manually adjusting the phase, and to provide a phase adjustment circuit based on a SYSREF signal.
[0007] The present disclosure solves the above technical problem through the following technical solutions:
[0008] The first aspect of the present disclosure provides a phase adjustment circuit based on a SYSREF signal, including a phase reading circuit and a phase adjustment circuit;
[0009] The phase reading circuit is used to determine the phase relationship between at least one reference clock signal and the SYSREF signal, obtain a phase adjustment control codeword, and adjust the phase adjustment circuit based on the phase adjustment control codeword;
[0010] The phase adjustment circuit is used to select a corresponding phase delay time based on the phase adjustment control codeword, delay the target divided-frequency clock based on the phase delay time, and filter out glitches to obtain a glitch-free clock signal aligned with the rising edge of the SYSREF signal.
[0011] Preferably, it further includes a division ratio selection circuit;
[0012] The division ratio selection circuit is used to generate at least one reference clock signal, select the target divided-frequency clock based on the division ratio control word; and transmit the at least one reference clock signal to the phase reading circuit, and transmit the target divided-frequency clock to the phase adjustment circuit.
[0013] Preferably, it further includes an edge adjustment circuit;
[0014] The edge adjustment circuit is used to adjust the externally input SYSREF signal and transmit the adjusted SYSREF signal to the phase reading circuit.
[0015] Preferably, the phase adjustment circuit is specifically configured to input the clock phase according to the phase adjustment control codeword, with an adjustment step of half a device clock cycle, and use the falling edge of the phase pre-adjusted clock signal to beat a preset number of beats for the change edge of each phase adjustment control codeword, and take the target number of beats as the corresponding phase delay time. After XORing the signals of the first beat and the last beat in the preset number of beats, a negative pulse signal is generated to filter out the glitches generated during the phase adjustment.
[0016] Preferably, the phase adjustment circuit is specifically configured to perform an OR operation on the division ratio control word and determine the non-divided clock signal or the even-divided clock signal according to the output result.
[0017] Preferably, the phase adjustment circuit is further used to perform a gating operation through multiple gated inverters and output the clock signal of the corresponding phase.
[0018] Preferably, the edge adjustment circuit is used to detect the falling edge of the first pulse of the low-frequency SYSREF signal, pull the start signal from low to high, and AND the start signal with the low-frequency SYSREF signal to output a stable SYSREF signal.
[0019] Preferably, the division ratio selection circuit is used to beat the other reference clock signals except the first reference clock signal in the at least one reference clock signal through a gated inverter, and perform equivalent delay on the first reference clock signal to obtain at least one reference clock signal with aligned rising edges.
[0020] Preferably, it further includes an edge adjustment circuit; the edge adjustment circuit includes an enable terminal, and the enable terminal is active high.
[0021] Preferably, it further includes an edge adjustment circuit; the phase reading circuit is specifically configured to sample at least one reference clock signal through a reference SYSREF signal generated by the edge adjustment circuit.
[0022] Based on the common knowledge in the art, the above preferred conditions can be combined arbitrarily to obtain various preferred examples of the present disclosure.
[0023] The positive and progressive effects of the present disclosure are as follows:
[0024] Based on the divided clock, the present disclosure determines the phase relationship between at least one reference clock signal and the SYSREF signal through the phase reading circuit to obtain a phase adjustment control codeword, thereby adaptively adjusting the phase of the output clock signal, avoiding the cumbersome operation of manual adjustment and alignment, improving the efficiency, filtering out the glitches generated during the phase adjustment through the phase adjustment circuit, avoiding affecting the feedback loop of the digital circuit, and obtaining a glitch-free clock signal aligned with the rising edge of the SYSREF signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 FIG. 1 is a schematic structural diagram of a phase adjustment circuit based on the SYSREF signal provided in Embodiment 1 of the present disclosure.
[0026] Figure 2 FIG. 2 is a schematic circuit diagram of the phase reading circuit provided in Embodiment 1 of the present disclosure.
[0027] Figure 3 FIG. 3 is a schematic waveform diagram of the phase reading circuit provided in Embodiment 1 of the present disclosure.
[0028] Figure 4 FIG. 4 is a schematic circuit diagram of the edge adjustment circuit provided in Embodiment 1 of the present disclosure.
[0029] Figure 5 FIG. 5 is a schematic circuit diagram of the phase adjustment circuit provided in Embodiment 1 of the present disclosure.
[0030] FIG. 6(a) is a first schematic diagram of glitch elimination provided in Embodiment 1 of the present disclosure.
[0031] FIG. 6(b) is a second schematic diagram of glitch elimination provided in Embodiment 1 of the present disclosure.
[0032] Figure 7 FIG. 7 is a schematic overall waveform diagram of the phase adjustment circuit provided in Embodiment 1 of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0033] The present disclosure will be further described below by way of examples, but the present disclosure is not limited to the scope of the described examples.
[0034] In the embodiments of the present disclosure, prefix words such as "first" and "second" are only used to distinguish different described objects, and have no restrictive effect on the position, order, priority, quantity, content, etc. of the described objects. In the embodiments of the present disclosure, the use of prefix words such as ordinal numbers to distinguish described objects does not constitute a restriction on the described objects. For the statements of the described objects, refer to the description in the claims or the context of the embodiments, and no redundant restrictions should be formed due to the use of such prefix words. In addition, in the description of this embodiment, unless otherwise specified, the meaning of "a plurality of" is two or more.
[0035] In the embodiments of the present disclosure, the processing of the collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information involved all complies with the provisions of relevant laws and regulations and does not violate public order and good customs.
[0036] Embodiment 1
[0037] Figure 1 FIG. is a schematic structural diagram of a phase adjustment circuit based on a SYSREF signal provided for Embodiment 1 of the present disclosure, including a phase reading circuit and a phase adjustment circuit; specifically, as Figure 1 shown, clk_div1 is an externally input device clock, clk_div2 and clk_div4 are respectively divided-frequency clock signals generated by dividing clk_div1 by two and four, and can be selected for output by the control word div<1:0>; sysref_in is an externally input SYSREF signal, en is an enable signal, adj_clk_edge and adj_sysref_edge are respectively used to adjust the effective edge of clock sampling and the effective level of the sampled SYSREF signal; clk_out is the finally output clock signal, and sysref_out is the SYSREF signal aligned to the rising edge of clk_out.
[0038] The phase reading circuit is used to judge the phase relationship between at least one reference clock signal and the SYSREF signal, obtain a phase adjustment control codeword, and adjust the phase adjustment circuit based on the phase adjustment control codeword;
[0039] In this embodiment, as Figure 2It is the circuit schematic diagram of the phase reading circuit. For example, taking the number of at least one path of reference clock signals as 4 paths, where clk_div1, clk_div2, and clk_div4 are the non-divided, divided-by-two, and divided-by-four clocks generated by the frequency division ratio selection circuit respectively. On this basis, the divided-by-eight clock clk_div8 is further generated. The clk_div2, clk_div4, and clk_div8 are clocked by the device clock for one beat, and then added with the clk_div1 signal after equivalent delay, and four initial rising-edge-aligned reference clock signals ref_clk8, ref_clk4, ref_clk2, and ref_clk1 are obtained simultaneously.
[0040] The sysref_phase signal (reference SYSREF signal) generated by the edge adjustment circuit is used to sample the four reference clock signals respectively. After inversion, the phase control codeword required by the phase adjustment circuit can be obtained, and the rising edge of the adjustment clock signal is aligned to the SYSREF signal.
[0041] Taking the divided-by-two case as an example, the waveform schematic diagram of the implementation of this circuit function is as Figure 3 shown:
[0042] In the actual implementation process, to ensure that the rising edges of the four divided reference clock signals are aligned, it is necessary to clock them by the device clock for one beat to align. The corresponding SYSREF signal also needs to be clocked one more beat backward. Corresponding to the Figure 4 circuit, that is, the sysref_align1 is clocked for one beat to obtain the sysref_phase signal. Therefore, the ultimate goal is to align the rising edge of clk_out to the rising edge of sysref_align1.
[0043] At this time, the sysref_align1 signal is only aligned to one rising edge position of the device clock, and is not aligned with the divided clock clk_div2. At this time, it is necessary to adjust the phase of the output divided clock, that is, according to the read codeword 0010 ( Figure 3 the dotted arrow in), the clk_div2 is shifted to the right by 2 device clock (clk_div1) periods of T / 2 through the phase adjustment circuit to obtain the clk_out signal. The rising edge of this signal is less than half a device clock period away from the rising edge of the sysref_align1 signal, achieving the alignment effect.
[0044] The phase adjustment circuit is used to select the corresponding phase delay time based on the phase adjustment control codeword, delay the target divided clock based on the phase delay time, and filter out the glitches to obtain a glitch-filtered clock signal aligned with the rising edge of the SYSREF signal.
[0045] This embodiment is based on a divided-frequency clock. By means of a phase reading circuit, the phase relationship between at least one reference clock signal and the SYSREF signal is judged to obtain a phase adjustment control codeword, thereby adaptively adjusting the phase of the output clock signal, avoiding the cumbersome operation of manual adjustment alignment, improving efficiency, and filtering out the glitches generated during the phase adjustment through a phase adjustment circuit, avoiding affecting the feedback loop of the digital circuit, and obtaining a glitch-filtered clock signal aligned with the rising edge of the SYSREF signal.
[0046] In an optional embodiment, it further includes a division ratio selection circuit;
[0047] The division ratio selection circuit is used to generate at least one reference clock signal, select a target divided-frequency clock based on a division ratio control word; and transmit at least one reference clock signal to the phase reading circuit and transmit the target divided-frequency clock to the phase adjustment circuit.
[0048] In an optional embodiment, it further includes an edge adjustment circuit;
[0049] The edge adjustment circuit is used to adjust the externally input SYSREF signal and transmit the adjusted SYSREF signal to the phase reading circuit.
[0050] In an optional embodiment, the phase adjustment circuit is specifically configured to input the clock phase according to the phase adjustment control codeword, with an adjustment step of half a device clock cycle, and use the falling edge of the phase pre-adjustment clock signal to beat a preset number of beats for the change edge of each phase adjustment control codeword, take the target number of beats among them as the corresponding phase delay time, and generate a negative pulse signal after XORing the signals of the first beat and the last beat in the preset number of beats to filter out the glitches generated during the phase adjustment.
[0051] In this embodiment, Figure 4 is the circuit schematic diagram of the edge adjustment circuit, where en is the enable terminal, high level effective. In this circuit, sysref_in and clk_in each pass through the front logic circuit first. When adj_sysref_edge or adj_clk_edge is 0, sysref_buf or clk_buf outputs a signal in phase with the input signal. When adj_sysref_edge or adj_clk_edge is 1, sysref_buf or clk_buf outputs a signal with the opposite phase to the input signal.
[0052] The sysref_phase signal is output to the phase reading module. The phase adjustment control codeword generated by this phase reading module is used for the automatic phase adjustment circuit, so that the clock signal output by the automatic phase adjustment circuit is aligned with the SYSREF signal; the sysref_out signal is the SYSREF signal aligned with the rising edge of the final output clock clk_out, and this signal can be further passed backward to synchronize subsequent circuits.
[0053] In an optional embodiment, the phase adjustment circuit is specifically configured to perform an OR operation on the division ratio control word, and determine the non-divided clock signal or the even-divided clock signal according to the output result.
[0054] In this embodiment, as Figure 5 is the circuit schematic diagram of the phase adjustment circuit. This circuit first performs an OR operation on the division ratio control words div<0> and div<1>. When its output ratio_flag is 0, it is non-divided. At this time, the parity relationship is determined according to adj_phase<0> (the least significant bit). For even numbers, it remains unchanged, and for odd numbers, it is inverted, and the lower branch is added; when ratio_flag is 1, it is divided by 2 or 4, and then it is still output through the original path.
[0055] In an optional embodiment, the phase adjustment circuit is further configured to perform a gating operation through a plurality of gated inverters to output the clock signal corresponding to the phase.
[0056] In this embodiment, as Figure 5 shown, a plurality of gated inverters (for example, using the device clock) are used for the clk_mux to perform phase transformation, and a gating operation is performed through a plurality of gated inverters, so as to output the clock signal corresponding to the phase.
[0057] In addition, since glitches will be generated on the clock signal during the adjustment of the phase adjustment control codeword, which may affect the feedback loop of the digital circuit. Combining the principle of glitch-free clock switching, the falling edge of clk_ini (phase pre-adjustment clock signal) is used to beat the change edge of each phase adjustment control codeword by 4 beats, and the second beat is taken as the real phase adjustment moment, and a negative pulse signal is generated by the exclusive OR of the first beat and the fourth beat signals to filter out the glitches generated during the phase adjustment. Taking the case of division by 2 as an example, two adjustment examples are given (the clk_ini signal is adjusted from clk_ini_a to clk_ini_b). Finally, the clock signal clk_out after filtering out the glitches can be output, as shown in Figures 6(a) and 6(b).
[0058] In an optional embodiment, the edge adjustment circuit is configured to detect the first pulse falling edge of the low-frequency SYSREF signal, pull the start signal from low to high, and AND the start signal with the low-frequency SYSREF signal to output a stable SYSREF signal.
[0059] In this embodiment, as Figure 4 shown, the circuit shown in the dashed box is an edge adjustment circuit, which is used to detect the falling edge of the first pulse of the sysref_sub (low-frequency signal) signal, pull the start signal from low to high at this time, and then AND the start signal with the sysref_sub signal, so as to avoid the first unstable pulse in the sysref_sub signal and output a stable sysref_out signal.
[0060] In an alternative embodiment, a frequency division ratio selection circuit is used to delay the other reference clock signals except the first reference clock signal in at least one path of reference clock signals by one beat through a gated inverter, and after equivalently delaying the first reference clock signal, at least one path of reference clock signals with rising edges aligned is obtained.
[0061] In an alternative embodiment, an edge adjustment circuit is further included; the edge adjustment circuit includes an enable terminal, and the high level of the enable terminal is valid.
[0062] In an alternative embodiment, an edge adjustment circuit and a phase reading circuit are further included; specifically, the phase reading circuit is used to sample at least one path of reference clock signals through a reference SYSREF signal generated by the edge adjustment circuit.
[0063] In the specific implementation process, taking the case of frequency division by two as an example, Figure 7 gives Figure 1 the waveform schematic diagram of the automatic phase adjustment circuit shown.
[0064] Assume that the initial position of the SYSREF signal sysref_align0 after being delayed by one beat by clk_buf is located at the Figure 7 position in. To ensure that the subsequent clock signals can sample the SYSREF signal, the sysref_align0 is further delayed by one beat by clk_buf to obtain the sysref_align1 signal, and this signal is used as the SYSREF signal that the rising edge of the automatically phase-adjusted clock clk_out needs to align with.
[0065] Since the above-mentioned four paths of reference divided clocks are shifted one device clock cycle to the right relative to the divider output clock clk_div2, it is necessary to delay the sysref_align1 by one beat by clk_buf to obtain the sysref_phase signal. From this, the current phase codeword is read as 0110 ( Figure 7 the position shown by the dashed arrow in). Therefore, it is necessary to shift clk_div2 six T / 2 device clock cycles to the right, and theoretically, the clk_ideal signal will be obtained, and this signal is indeed aligned with the sysref_align1 signal.
[0066] In fact, the actual phase adjustment process is not ideal. The sysref_phase samples four reference clock signals to obtain adj_phase <n>, this moment is the adjustment moment. Combining the above content, the phase adjustment circuit incorporates the idea of a glitch-free clock switching circuit and adjusts adj_phase <n>The adjust obtained by clocking two beats on the falling edge of clk_ini <n>The signal serves as a new adjustment moment, and then by adj_phase <n>Use the falling edge of the clk_ini clock to generate a negative pulse signal mode_all_adj by XORing the signals after one - clock - cycle delay and four - clock - cycle delay. AND this signal with the original clk_ini clock to filter out the glitch signals generated during the adjustment moment, and obtain a glitch - free clk_out clock signal.
[0067] In order to obtain a SYSREF signal aligned with the rising edge of the clk_out clock signal, the clk_out clock signal is used to delay the sysref_align0 signal by one clock cycle, and thus the sysref_sub signal can be obtained. Due to the influence of the phase adjustment period, the first pulse period of this signal is incorrect, which may affect the subsequent synchronization. Therefore, it is necessary to use Figure 4 The start signal generated by the circuit in the dashed box is ANDed with it, and finally a stable SYSREF signal: sysref_out, which is aligned with the rising edge of the clk_out clock signal, can be obtained. This signal and the clk_out clock signal are transmitted to the subsequent circuits to synchronize the subsequent circuits in sequence.
[0068] In this embodiment, different from the traditional phase - adjustment circuit, the present disclosure combines the idea of a glitch - free clock - switching circuit, which can filter out the glitches generated during the phase adjustment period and avoid affecting the feedback loop of the digital circuit. Further, different from the traditional phase - adjustment circuit, the present disclosure can adaptively adjust the phase of the clock signal according to the relative phase relationship of the input SYSREF signal, avoiding the cumbersome operation of manual adjustment for alignment. Further, different from the traditional method of simultaneously resetting the frequency divider based on the rising edge of SYSREF to achieve synchronization, the present disclosure is based on the divided - clock, generates four reference clock signals, and then uses the SYSREF signal to sample the four reference clock signals to obtain the phase - adjustment control word, thereby adjusting the phase of the output clock. By shifting the clock phases of multiple chips, their rising edges are all aligned to the rising edge of the same SYSREF signal, so as to achieve the purpose of multi - chip synchronization. Specifically, by detecting the relative phase relationship between the SYSREF signal and the reference clock ref_clk, the phase - adjustment control word of SYSREF is obtained, and this is used as a control signal to feedback - adjust the phase relationship of the sampling clock. The adjustment accuracy is half of the clock period of a device clock (the non - divided input clock signal), so as to achieve the purpose of aligning the sampling clocks of multiple chips to the same SYSREF signal.
[0069] Although the specific embodiments of the present disclosure have been described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Without departing from the principles and essence of the present disclosure, those skilled in the art can make various changes or modifications to these embodiments, but these changes and modifications all fall within the protection scope of the present disclosure.< / n> < / n> < / n> < / n>
Claims
1. A phase adjustment circuit based on a SYSREF signal, characterized in that: It includes a phase reading circuit and a phase adjustment circuit; The phase reading circuit is used to determine the phase relationship between at least one reference clock signal and the SYSREF signal, obtain a phase adjustment control codeword, and adjust the phase adjustment circuit based on the phase adjustment control codeword; The phase adjustment circuit is used to select a corresponding phase delay time based on the phase adjustment control codeword, delay and filter out glitch processing on the target frequency-divided clock based on the phase delay time, and obtain a glitch-filtered clock signal aligned with the rising edge of the SYSREF signal.
2. The phase adjustment circuit based on the SYSREF signal according to claim 1, characterized in that: Also included is a frequency division ratio selection circuit; The frequency division ratio selection circuit is used to generate at least one reference clock signal and select a target frequency division clock based on the frequency division ratio control word; and transmit the at least one reference clock signal to the phase reading circuit and transmit the target frequency division clock to the phase adjustment circuit.
3. The phase adjustment circuit based on the SYSREF signal according to claim 1, characterized in that: Also included is an edge conditioning circuit; The edge adjustment circuit is used to adjust the externally input SYSREF signal and transmit the adjusted SYSREF signal to the phase reading circuit.
4. The phase adjustment circuit based on the SYSREF signal according to claim 1, characterized in that: The phase adjustment circuit is specifically used to input the clock phase according to the phase adjustment control codeword, with the adjustment step length being half a device clock cycle, and use the falling edge of the phase pre-adjustment clock signal to beat the changing edge of each phase adjustment control codeword for a preset number of times, take the target number of beats as the corresponding phase delay time, and generate a negative pulse signal after performing XOR on the signal of the first beat and the last beat in the preset number of beats to filter the burrs generated during the phase adjustment.
5. The phase adjustment circuit based on the SYSREF signal according to claim 1, characterized in that: The phase adjustment circuit is specifically used to perform an OR operation on the frequency division ratio control word, and determine a non-frequency division clock signal or an even-number frequency division clock signal according to the output result.
6. The phase adjustment circuit based on the SYSREF signal according to claim 1, characterized in that: The phase adjustment circuit is also used to perform gating operations through multiple gated inverters to output clock signals of corresponding phases.
7. The phase adjustment circuit based on the SYSREF signal as claimed in claim 3, characterized in that: The edge adjustment circuit is used to detect the first pulse falling edge of the low-frequency SYSREF signal, pull the start signal from low to high, and AND the start signal with the low-frequency SYSREF signal to output a stable SYSREF signal.
8. The phase adjustment circuit based on the SYSREF signal as claimed in claim 2, characterized in that: The frequency division ratio selection circuit is used to beat the other reference clock signals except the first reference clock signal in at least one reference clock signal through a gated inverter, and obtain at least one reference clock signal with rising edge alignment after equivalently delaying the first reference clock signal.
9. The phase adjustment circuit based on the SYSREF signal according to claim 1, characterized in that: It also includes an edge regulation circuit; the edge regulation circuit includes an enable terminal, and the enable terminal is valid when the high level is high.
10. The phase adjustment circuit based on the SYSREF signal according to claim 1, characterized in that: It also includes an edge adjustment circuit; the phase reading circuit is specifically used to sample at least one reference clock signal through the reference SYSREF signal generated by the edge adjustment circuit.