Universal input / output interface
By designing a general-purpose input/output interface, using the TX module, RX module and voltage protection circuit, the selectivity of the level signal range is achieved, the problem of fixed level output range of the traditional GPIO is solved, and protocol compatibility and application scenarios are enhanced.
Patent Information
- Application Number
- CN202510284494.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-11
- Publication Date
- 2025-06-27
AI Technical Summary
The fixed analog level output range of traditional GPIOs limits its application scenarios and cannot be compatible with more protocols, especially when data transmission speeds are not fast.
A general-purpose input/output interface is designed, and the selectivity of the level signal range is achieved through the TX module, the RX module and the voltage protection circuit, which enhances the application scenarios and protocol compatibility of the circuit.
It has achieved optimization of traditional GPIO structure, can select the output voltage range, is compatible with more protocols and is suitable for more application scenarios.
Smart Images
Figure CN120223058A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of transmission interfaces for digital circuits and analog circuits, and particularly relates to a general-purpose input / output interface. Background Art
[0002] GPIO (General-Purpose IO ports) is a general-purpose input / output interface, which can be configured into an output mode to control external devices or an input mode to read external signals.
[0003] Generally, GPIO is used as a transmission interface for digital circuits and analog circuits, converting the input low-voltage digital level signal into a high-voltage analog level signal for output, or converting the input high-voltage analog level signal into a low-voltage digital level for output.
[0004] However, with the increase in application protocols, in the case where the data transmission speed is not very fast, the applicable scenarios of traditional GPIO are limited by the range of interface voltages it can withstand.
[0005] The analog level range output by common GPIO is fixed, which cannot increase the application scenarios of the circuit and thus cannot be compatible with more protocols. Summary of the Invention
[0006] In view of the deficiencies of the prior art, the present invention provides a general-purpose input / output interface, the range of the output level signal of which can be selected, which can increase the application scenarios of the circuit to be compatible with more protocols.
[0007] The technical solution of the present invention is as follows:
[0008] A general-purpose input / output interface includes a TX module, an RX module, and a withstand voltage protection circuit. The TX module includes:
[0009] A first inverter, with a first control signal input to its input terminal;
[0010] A second inverter, with a second control signal input to its input terminal;
[0011] A first AND gate, its first input terminal electrically connected to the output terminal of the first inverter, and its second input terminal electrically connected to the output terminal of the second inverter;
[0012] A second AND gate, its first input terminal receiving a first control signal, and its second input terminal electrically connected to the output terminal of the second inverter;
[0013] A first NAND gate, its first input terminal serving as the input pin of the general-purpose input / output interface, and its second input terminal electrically connected to the output terminal of the first AND gate;
[0014] A second NAND gate, whose first input terminal is electrically connected to the first input terminal of the first NAND gate, and whose second input terminal is electrically connected to the output terminal of the second AND gate;
[0015] A third NAND gate, whose first input terminal is electrically connected to the first input terminal of the first NAND gate, and whose second input terminal is electrically connected to the output terminal of the second inverter;
[0016] A third AND gate, whose first input terminal is electrically connected to the output terminal of the third NAND gate, and whose second input terminal is electrically connected to the output terminal of the second inverter;
[0017] A bias circuit, whose first input terminal receives a first control signal, and whose second input terminal is electrically connected to the output terminal of the second inverter;
[0018] A level conversion circuit, whose input terminal is electrically connected to the output terminal of the first NAND gate;
[0019] A buffer, whose input terminal is electrically connected to the output terminal of the second NAND gate;
[0020] A first PMOS transistor, whose source terminal receives a first interface voltage, and whose gate terminal is electrically connected to the output terminal of the level conversion circuit;
[0021] A second PMOS transistor, whose source terminal is electrically connected to the drain terminal of the first PMOS transistor, and whose gate terminal is electrically connected to the first output terminal of the bias circuit;
[0022] A first NMOS transistor, whose drain terminal is electrically connected to the drain terminal of the second PMOS transistor, and whose gate terminal is electrically connected to the first output terminal of the bias circuit;
[0023] A second NMOS transistor, whose drain terminal is electrically connected to the source terminal of the first NMOS transistor, whose gate terminal is electrically connected to the output terminal of the third AND gate, and whose source terminal is grounded;
[0024] A third PMOS transistor, whose source terminal receives a second interface voltage, and whose gate terminal is electrically connected to the output terminal of the buffer;
[0025] A fourth PMOS transistor, whose source terminal is electrically connected to the drain terminal of the third PMOS transistor, whose gate terminal is electrically connected to the second output terminal of the bias circuit, and whose drain terminal is electrically connected to the drain terminal of the second PMOS transistor and serves as the input / output pin of the general-purpose input / output interface;
[0026] The RX module includes:
[0027] A Schmitt trigger, whose output terminal serves as the output pin of the general-purpose input / output interface, and is controlled to be turned on or off by a third control signal IE;
[0028] A first switch, having its first end receiving a second interface voltage, and being controlled to be closed or opened by a first switch control signal;
[0029] A pull-up resistor, having its first end electrically connected to the second end of the first switch and its second end electrically connected to the input end of a Schmitt trigger;
[0030] A pull-down resistor, having its first end electrically connected to the input end of the Schmitt trigger;
[0031] A second switch, having its first end electrically connected to the second end of the pull-down resistor and its second end grounded, and being controlled to be closed or opened by a second switch control signal;
[0032] The withstand voltage protection circuit includes:
[0033] A third NMOS transistor, having its gate electrically connected to the drain of a fourth PMOS transistor, its source electrically connected to the input end of the Schmitt trigger, and its drain electrically connected to the first output end of a bias circuit;
[0034] A fourth NMOS transistor, having its gate electrically connected to the drain of the third NMOS transistor and its drain electrically connected to the drain of the fourth PMOS transistor;
[0035] A fifth NMOS transistor, having its gate electrically connected to the drain of the third NMOS transistor, its drain electrically connected to the source of the fourth NMOS transistor, and its source electrically connected to the input end of the Schmitt trigger;
[0036] A fifth PMOS transistor, having its source electrically connected to the drain of the fourth PMOS transistor;
[0037] A sixth PMOS transistor, having its source electrically connected to the drain of the fifth PMOS transistor and its drain electrically connected to the input end of the Schmitt trigger;
[0038] A tenth PMOS transistor, having its gate electrically connected to the output end of a first inverter and its source receiving the second interface voltage;
[0039] A seventh PMOS transistor, having its source electrically connected to the drain of the tenth PMOS transistor and its drain electrically connected to the drain of the fourth PMOS transistor;
[0040] An eighth PMOS transistor, having its source electrically connected to the drain of the tenth PMOS transistor, its drain electrically connected to the gate of the seventh PMOS transistor, and its gate electrically connected to the drain of the seventh PMOS transistor;
[0041] A ninth PMOS transistor, having its source electrically connected to the drain of the seventh PMOS transistor, its drain electrically connected to the gates of the fifth PMOS transistor and the sixth PMOS transistor respectively, and its gate electrically connected to the drain of the eighth PMOS transistor and the first output end of a bias circuit Biase respectively;
[0042] A sixth NMOS transistor, whose gate is electrically connected to the drain of an eighth PMOS transistor, and whose drain is electrically connected to the drain of a ninth PMOS transistor;
[0043] A seventh NMOS transistor, whose gate receives a first control signal, whose drain is electrically connected to the source of the sixth NMOS transistor, and whose source is electrically connected to ground.
[0044] It further includes:
[0045] An electrostatic discharge protection circuit, which includes a p-type diode and an n-type diode; wherein, the anode of the p-type diode is electrically connected to the drain of a fourth PMOS transistor, the cathode of the p-type diode receives a first interface voltage, the cathode of the n-type diode is electrically connected to the drain of the fourth PMOS transistor, and the anode of the n-type diode is electrically connected to ground.
[0046] The level conversion circuit includes:
[0047] A nineteenth PMOS transistor, whose source receives a first interface voltage and whose gate receives a second interface voltage;
[0048] An eighteenth PMOS transistor, whose source is electrically connected to the drain of the nineteenth PMOS transistor;
[0049] A seventeenth PMOS transistor, whose source is electrically connected to the drain of the nineteenth PMOS transistor, whose drain is electrically connected to the gate of the eighteenth PMOS transistor and serves as the output terminal of the level conversion circuit, and whose gate is electrically connected to the drain of the eighteenth PMOS transistor;
[0050] An eleventh PMOS transistor, whose source receives a second interface voltage;
[0051] An eighth NMOS transistor, whose gate is electrically connected to the gate of the eleventh PMOS transistor and serves as the input terminal of the level conversion circuit, whose drain is electrically connected to the drain of the eleventh PMOS transistor, and whose source is electrically connected to ground;
[0052] A ninth NMOS transistor, whose gate is electrically connected to the source of the eleventh PMOS transistor, and whose source is electrically connected to the drain of the eleventh PMOS transistor;
[0053] A twelfth PMOS transistor, whose source is electrically connected to the drain of the eighteenth PMOS transistor, and whose gate is electrically connected to the source of the eleventh PMOS transistor;
[0054] A tenth NMOS transistor, whose gate is electrically connected to the gate of the twelfth PMOS transistor, whose drain is electrically connected to the drain of the twelfth PMOS transistor, and whose source is electrically connected to ground;
[0055] The thirteenth PMOS transistor, whose source is electrically connected to the drain of the eighteenth PMOS transistor, whose gate is electrically connected to the drain of the twelfth PMOS transistor, and whose drain is electrically connected to the gate of the twelfth PMOS transistor;
[0056] The fourteenth PMOS transistor, whose source is electrically connected to the drain of the seventeenth PMOS transistor, and whose drain is electrically connected to the source of the eleventh PMOS transistor;
[0057] The fifteenth PMOS transistor, whose source is electrically connected to the drain of the seventeenth PMOS transistor, whose gate is electrically connected to the source of the eleventh PMOS transistor, and whose drain is electrically connected to the gate of the fourteenth PMOS transistor;
[0058] The eleventh NMOS transistor, whose gate is electrically connected to the drain of the fourteenth PMOS transistor, whose drain is electrically connected to the drain of the fifteenth PMOS transistor, and whose source is electrically connected to the ground;
[0059] The twelfth NMOS transistor, whose gate is electrically connected to the source of the eleventh PMOS transistor, and whose drain is electrically connected to the drain of the fifteenth PMOS transistor;
[0060] The sixteenth PMOS transistor, whose source is electrically connected to the source of the eleventh PMOS transistor, whose gate is electrically connected to the drain of the eleventh PMOS transistor, and whose drain is electrically connected to the source of the twelfth NMOS transistor;
[0061] The thirteenth NMOS transistor, whose gate is electrically connected to the drain of the eleventh PMOS transistor, whose drain is electrically connected to the drain of the sixteenth PMOS transistor, and whose source is electrically connected to the ground.
[0062] The bias circuit includes:
[0063] The third inverter, whose input terminal serves as the second input terminal of the bias circuit;
[0064] The fourth AND gate, whose first input terminal is electrically connected to the input terminal of the third inverter, and whose second input terminal serves as the first input terminal of the bias circuit;
[0065] The twentieth PMOS transistor, whose source inputs the second interface voltage, and whose gate is electrically connected to the output terminal of the third inverter;
[0066] The twenty-first PMOS transistor, whose source inputs the second interface voltage, whose gate is electrically connected to the input terminal of the third inverter, and whose drain is electrically connected to the drain of the twentieth PMOS transistor and then serves as the first output terminal of the bias circuit;
[0067] The twenty-second PMOS transistor, whose source is electrically connected to the drain of the twentieth PMOS transistor, and whose gate is electrically connected to the output terminal of the fourth AND gate;
[0068] The fourteenth NMOS transistor has its gate electrically connected to the output terminal of the fourth AND gate, its drain electrically connected to the drain of the twenty-second PMOS transistor and serves as the second output terminal of the bias circuit, and its source electrically connected to the ground.
[0069] The beneficial technical effects of the present invention are as follows:
[0070] The present invention optimizes the traditional GPIO structure to select the output voltage range, and the present invention can be compatible with more protocols and applicable to more application scenarios. Description of the Drawings
[0071] Figure 1 It is a schematic circuit diagram of the general-purpose input / output interface of the present invention;
[0072] Figure 2 It is a schematic circuit diagram of the present invention when the signal voltage amplitude range on the input / output pins is 0 to VDDIOH, mode_sel = 0, OEN = 0, and IE = VDDIOL;
[0073] Figure 3 It is a schematic circuit diagram of the present invention when the signal voltage amplitude range on the input / output pins is 0 to VDDIOL, mode_sel = VDDIOL, OEN = 0, and IE = VDDIOL;
[0074] Figure 4 It is a schematic diagram of the level conversion circuit of the present invention;
[0075] Figure 5 It is a schematic diagram of the bias circuit of the present invention. Detailed Embodiments
[0076] The present invention will be further described below through specific embodiments, but not limited thereto.
[0077] Refer to Figure 1 , a general-purpose input / output interface in one of the numerous embodiments of the present invention, includes a TX module, an RX module, and a withstand voltage protection circuit. The TX module includes a first inverter inv1, a second inverter inv2, a first AND gate and1, a second AND gate and2, a third AND gate and3, a first NAND gate nand1, a second NAND gate nand2, a third NAND gate nand3, a bias circuit Biase, a level conversion circuit level_shifter, a buffer buffer, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a first NMOS transistor MN1, a second NMOS transistor MN2.
[0078] The first control signal mode_sel is input to the input terminal of the first inverter inv1, and the fourth control signal mode_selb is output from the output terminal of the first inverter inv1.
[0079] The second control signal OEN is input to the input terminal of the second inverter inv2.
[0080] The first input terminal of the first AND gate and1 is electrically connected to the output terminal of the first inverter inv1, and the second input terminal of the first AND gate and1 is electrically connected to the output terminal of the second inverter inv2.
[0081] The first control signal mode_sel is input to the first input terminal of the second AND gate and2, and the second input terminal of the second AND gate and2 is electrically connected to the output terminal of the second inverter inv2.
[0082] The first input terminal of the first NAND gate nand1 serves as the input pin I of the general-purpose input / output interface, and the second input terminal of the first NAND gate nand1 is electrically connected to the output terminal of the first AND gate and1.
[0083] The first input terminal of the second NAND gate nand2 is electrically connected to the first input terminal of the first NAND gate nand1, and the second input terminal of the second NAND gate nand2 is electrically connected to the output terminal of the second AND gate and2.
[0084] The first input terminal of the third NAND gate nand3 is electrically connected to the first input terminal of the first NAND gate nand1, and the second input terminal of the third NAND gate nand3 is electrically connected to the output terminal of the second inverter inv2.
[0085] The first input terminal of the third AND gate and3 is electrically connected to the output terminal of the third NAND gate nand3, and the second input terminal of the third AND gate and3 is electrically connected to the output terminal of the second inverter inv2.
[0086] The first control signal mode_sel is input to the first input terminal of the bias circuit Biase, and the second input terminal of the bias circuit Biase is electrically connected to the output terminal of the second inverter inv2.
[0087] The input terminal of the level shifter circuit level_shifter is electrically connected to the output terminal of the first NAND gate nand1.
[0088] The input terminal of the buffer buffer is electrically connected to the output terminal of the second NAND gate nand2.
[0089] The source of the first PMOS transistor MP1 inputs the first interface voltage VDDIOH, and the gate of the first PMOS transistor MP1 is electrically connected to the output terminal of the level shifter circuit level_shifter.
[0090] The source of the second PMOS transistor MP2 is electrically connected to the drain of the first PMOS transistor MP1, and the gate of the second PMOS transistor MP2 is electrically connected to the first output terminal of the bias circuit Biase. The first output terminal of the bias circuit Biase outputs a first bias voltage biaseh.
[0091] The drain of the first NMOS transistor MN1 is electrically connected to the drain of the second PMOS transistor MP2, and the gate of the first NMOS transistor MN1 is electrically connected to the first output terminal of the bias circuit Biase.
[0092] The drain of the second NMOS transistor MN2 is electrically connected to the source of the first NMOS transistor MN1, the gate of the second NMOS transistor MN2 is electrically connected to the output terminal of the third AND gate and3, and the source of the second NMOS transistor MN2 is electrically connected to the ground GND.
[0093] The source of the third PMOS transistor MP3 inputs a second interface voltage VDDIOL, and the gate of the third PMOS transistor MP3 is electrically connected to the output terminal of the buffer buffer.
[0094] The source of the fourth PMOS transistor MP4 is electrically connected to the drain of the third PMOS transistor MP3, the gate of the fourth PMOS transistor MP4 is electrically connected to the second output terminal of the bias circuit Biase, and the drain of the fourth PMOS transistor MP4 is electrically connected to the drain of the second PMOS transistor MP2 and serves as the input / output pin PAD of the general-purpose input / output interface. The second output terminal of the bias circuit Biase outputs a second bias voltage biasel.
[0095] The RX module includes a Schmitt trigger Schmitt_trigger, a first switch S1, a pull-up resistor R1, a pull-down resistor R2, and a second switch S2.
[0096] The output terminal of the Schmitt trigger Schmitt_trigger serves as the output pin C of the general-purpose input / output interface, and outputs a second digital signal C. The third control signal IE controls the turning on or off of the Schmitt trigger Schmitt_trigger.
[0097] The first terminal of the first switch S1 inputs a second interface voltage VDDIOL, and the first switch S1 is controlled to be closed or opened by a first switch control signal PU.
[0098] The first end of the pull-up resistor R1 is electrically connected to the second end of the first switch S1, and the second end of the pull-up resistor R1 is electrically connected to the input end of the Schmitt trigger Schmitt_trigger. The signal input to the input end of the Schmitt trigger Schmitt_trigger is the trigger input signal RX_in.
[0099] The first end of the pull-down resistor R2 is electrically connected to the input end of the Schmitt trigger Schmitt_trigger.
[0100] The first end of the second switch S2 is electrically connected to the second end of the pull-down resistor R2, and the second end of the second switch S2 is electrically connected to the ground GND. The second switch S2 is controlled to be closed or opened by the second switch control signal PD.
[0101] The voltage withstand protection circuit includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, and a tenth PMOS transistor MP10.
[0102] The gate of the third NMOS transistor MN3 is electrically connected to the drain of the fourth PMOS transistor MP4, the source of the third NMOS transistor MN3 is electrically connected to the input end of the Schmitt trigger Schmitt_trigger, and the drain of the third NMOS transistor MN3 is electrically connected to the first output end of the bias circuit Biase.
[0103] The gate of the fourth NMOS transistor MN4 is electrically connected to the drain of the third NMOS transistor MN3, and the drain of the fourth NMOS transistor MN4 is electrically connected to the drain of the fourth PMOS transistor MP4.
[0104] The gate of the fifth NMOS transistor MN5 is electrically connected to the drain of the third NMOS transistor MN3, the drain of the fifth NMOS transistor MN5 is electrically connected to the source of the fourth NMOS transistor MN4, and the source of the fifth NMOS transistor MN5 is electrically connected to the input end of the Schmitt trigger Schmitt_trigger.
[0105] The source of the fifth PMOS transistor MP5 is electrically connected to the drain of the fourth PMOS transistor MP4.
[0106] The source of the sixth PMOS transistor MP6 is electrically connected to the drain of the fifth PMOS transistor MP5, and the drain of the sixth PMOS transistor MP6 is electrically connected to the input end of the Schmitt trigger Schmitt_trigger.
[0107] The gate of the tenth PMOS transistor MP10 is electrically connected to the output terminal of the first inverter inv1, and the source of the tenth PMOS transistor MP10 inputs the second interface voltage VDDIOL.
[0108] The source of the seventh PMOS transistor MP7 is electrically connected to the drain of the tenth PMOS transistor MP10, and the drain of the seventh PMOS transistor MP7 is electrically connected to the drain of the fourth PMOS transistor MP4.
[0109] The source of the eighth PMOS transistor MP8 is electrically connected to the drain of the tenth PMOS transistor, the drain of the eighth PMOS transistor MP8 is electrically connected to the gate of the seventh PMOS transistor MP7, and the gate of the eighth PMOS transistor MP8 is electrically connected to the drain of the seventh PMOS transistor.
[0110] The source of the ninth PMOS transistor MP9 is electrically connected to the drain of the seventh PMOS transistor. The drain of the ninth PMOS transistor MP9 is electrically connected to the gates of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 respectively. The gate of the ninth PMOS transistor MP9 is electrically connected to the drain of the eighth PMOS transistor and the first output terminal of the bias circuit Biase respectively.
[0111] The gate of the sixth NMOS transistor MN6 is electrically connected to the drain of the eighth PMOS transistor, and the drain of the sixth NMOS transistor MN6 is electrically connected to the drain of the ninth PMOS transistor.
[0112] The gate of the seventh NMOS transistor MN7 inputs the first control signal mode_sel. The drain of the seventh NMOS transistor MN7 is electrically connected to the source of the sixth NMOS transistor, and the source of the seventh NMOS transistor MN7 is electrically connected to the ground GND.
[0113] In some embodiments, the present invention further includes an electrostatic discharge protection circuit. The electrostatic discharge protection circuit includes a p-type diode p_diode and an n-type diode n_diode. The positive electrode of the p-type diode p_diode is electrically connected to the drain of the fourth PMOS transistor MP4, the negative electrode of the p-type diode p_diode inputs the first interface voltage, the negative electrode of the n-type diode n_diode is electrically connected to the drain of the fourth PMOS transistor MP4, and the positive electrode of the n-type diode n_diode is electrically connected to the ground.
[0114] Whether the bias circuit Biase generates an output voltage through resistor voltage division or through a bandgap reference source (Badgap), as long as it can provide a suitable bias for the subsequent circuit, it is applicable to the present invention. A circuit structure of a bias circuit Biase will be exemplarily given later. For the level shifter circuit level_shifter, as long as the input voltage range is 0 to VDDIOL and the output voltage range is VDDIOL to VDDIOH, the level shifter circuit is applicable to the present invention. A circuit structure of a level shifter circuit level_shifter will be exemplarily given later.
[0115] See Figure 4 , an exemplary level shifter circuit level_shifter of the present invention includes an eleventh pmos transistor MP11, a twelfth pmos transistor MP12, a thirteenth pmos transistor MP13, a fourteenth pmos transistor MP14, a fifteenth pmos transistor MP15, a sixteenth pmos transistor MP16, a seventeenth pmos transistor MP17, an eighteenth pmos transistor MP18, a nineteenth pmos transistor MP19, an eighth nmos transistor MN8, a ninth nmos transistor MN9, a tenth nmos transistor MN10, an eleventh nmos transistor MN11, a twelfth nmos transistor MN12, and a thirteenth nmos transistor MN13.
[0116] The source of the nineteenth pmos transistor MP19 inputs the first interface voltage VDDIOH, and the gate of the nineteenth pmos transistor MP19 inputs the second interface voltage VDDIOL.
[0117] The source of the eighteenth pmos transistor MP18 is electrically connected to the drain of the nineteenth pmos transistor MP19.
[0118] The source of the seventeenth pmos transistor MP17 is electrically connected to the drain of the nineteenth pmos transistor MP19. The drain of the seventeenth pmos transistor MP17 is electrically connected to the gate of the eighteenth pmos transistor MP18 and serves as the output terminal Outp of the level shifter circuit level_shifter. The gate of the seventeenth pmos transistor MP17 is electrically connected to the drain of the eighteenth pmos transistor MP18.
[0119] The source of the eleventh pmos transistor MP11 inputs the second interface voltage VDDIOL.
[0120] The gate of the eighth nmos transistor MN8 is electrically connected to the gate of the eleventh pmos transistor MP11 and serves as the input terminal In1 of the level shifter circuit level_shifter. The drain of the eighth nmos transistor MN8 is electrically connected to the drain of the eleventh pmos transistor MP11. The source of the eighth nmos transistor MN8 is electrically connected to the ground GND.
[0121] The gate of the ninth NMOS transistor MN9 is electrically connected to the source of the eleventh PMOS transistor MP11, and the source of the ninth NMOS transistor MN9 is electrically connected to the drain of the eleventh PMOS transistor MP11.
[0122] The source of the twelfth PMOS transistor MP12 is electrically connected to the drain of the eighteenth PMOS transistor MP18, and the gate of the twelfth PMOS transistor MP12 is electrically connected to the source of the eleventh PMOS transistor MP11.
[0123] The gate of the tenth NMOS transistor MN10 is electrically connected to the gate of the twelfth PMOS transistor MP12, the drain of the tenth NMOS transistor MN10 is electrically connected to the drain of the twelfth PMOS transistor MP12, and the source of the tenth NMOS transistor MN10 is electrically connected to the ground GND.
[0124] The source of the thirteenth PMOS transistor MP13 is electrically connected to the drain of the eighteenth PMOS transistor MP18, the gate of the thirteenth PMOS transistor MP13 is electrically connected to the drain of the twelfth PMOS transistor MP12, and the drain of the thirteenth PMOS transistor MP13 is electrically connected to the gate of the twelfth PMOS transistor MP12.
[0125] The source of the fourteenth PMOS transistor MP14 is electrically connected to the drain of the seventeenth PMOS transistor MP17, and the drain of the fourteenth PMOS transistor MP14 is electrically connected to the source of the eleventh PMOS transistor MP11.
[0126] The source of the fifteenth PMOS transistor MP15 is electrically connected to the drain of the seventeenth PMOS transistor MP17, the gate of the fifteenth PMOS transistor MP15 is electrically connected to the source of the eleventh PMOS transistor MP11, and the drain of the fifteenth PMOS transistor MP15 is electrically connected to the gate of the fourteenth PMOS transistor MP14.
[0127] The gate of the eleventh NMOS transistor MN11 is electrically connected to the drain of the fourteenth PMOS transistor MP14, the drain of the eleventh NMOS transistor MN11 is electrically connected to the drain of the fifteenth PMOS transistor MP15, and the source of the eleventh NMOS transistor MN11 is electrically connected to the ground GND.
[0128] The gate of the twelfth NMOS transistor MN12 is electrically connected to the source of the eleventh PMOS transistor MP11, and the drain of the twelfth NMOS transistor MN12 is electrically connected to the drain of the fifteenth PMOS transistor MP15.
[0129] The source of the sixteenth PMOS transistor MP16 is electrically connected to the source of the eleventh PMOS transistor MP11, the gate of the sixteenth PMOS transistor MP16 is electrically connected to the drain of the eleventh PMOS transistor MP11, and the drain of the sixteenth PMOS transistor MP16 is electrically connected to the source of the twelfth NMOS transistor MN12.
[0130] The gate of the thirteenth NMOS transistor MN13 is electrically connected to the drain of the eleventh PMOS transistor MP11, the drain of the thirteenth NMOS transistor MN13 is electrically connected to the drain of the sixteenth PMOS transistor MP16, and the source of the thirteenth NMOS transistor MN13 is electrically connected to the ground GND.
[0131] The ninth NMOS transistor MN9 is to protect the eighth NMOS transistor MN8 from being in a breakdown voltage state when the drain voltage of the twelfth PMOS transistor MP12 is VDDIOH. Similarly, the twelfth NMOS transistor MN12 is to protect the thirteenth NMOS transistor MN13 from being in a breakdown voltage state when the drain voltage of the fifteenth PMOS transistor MP15 is VDDIOH.
[0132] The level signal range input to the input terminal of the level shifter circuit level_shifter is 0 to VDDIOL. After passing through the inverter composed of the eleventh PMOS transistor MP11 and the eighth NMOS transistor MN8 and reaching the drain of the ninth NMOS transistor MN9 from the source of the ninth NMOS transistor MN9, its level signal range becomes 0 to VDDIOH. Similarly, the drain level signal range of the twelfth NMOS transistor MN12 is also 0 to VDDIOH.
[0133] At the same time, because the gates of the twelfth PMOS transistor MP12 and the fifteenth PMOS transistor MP15 are both connected to the input second interface voltage VDDIOL, the level signal ranges on the sources of the thirteenth PMOS transistor MP13 and the fourteenth PMOS transistor MP4 both become VDDIOL to VDDIOH, and the polarities are opposite.
[0134] In summary, the level shifter circuit level_shifter has completed the conversion of the level signal range from 0 to VDDIOL input to its input terminal to the level signal range from VDDIOL to VDDIOH at its output terminal Outp. The input terminal of the level shifter circuit level_shifter and its output terminal Outp have the same polarity.
[0135] See Figure 5 , an exemplary bias circuit Biase of the present invention includes a third inverter inv3, a fourth AND gate and4, a twentieth PMOS transistor MP20, a twenty-first PMOS transistor MP21, a twenty-second PMOS transistor MP22, and a fourteenth NMOS transistor MN14.
[0136] The input terminal of the third inverter inv3 serves as the second input terminal of the bias circuit Biase.
[0137] The first input terminal of the fourth AND gate and4 is electrically connected to the input terminal of the third inverter inv3, and the second input terminal of the fourth AND gate and4 serves as the first input terminal of the bias circuit (Biase).
[0138] The source of the twentieth PMOS transistor MP20 inputs the second interface voltage VDDIOL, and the gate of the twentieth PMOS transistor MP20 is electrically connected to the output terminal of the third inverter inv3.
[0139] The source of the twenty-first PMOS transistor MP21 inputs the second interface voltage VDDIOL, the gate of the twenty-first PMOS transistor MP21 is electrically connected to the input terminal of the third inverter inv3, and the drain of the twenty-first PMOS transistor MP21 is electrically connected to the drain of the twentieth PMOS transistor MP20 and serves as the first output terminal of the bias circuit Biase.
[0140] The source of the twenty-second PMOS transistor MP22 is electrically connected to the drain of the twentieth PMOS transistor MP20, and the gate of the twenty-second PMOS transistor MP22 is electrically connected to the output terminal of the fourth AND gate and4.
[0141] The gate of the fourteenth NMOS transistor MN14 is electrically connected to the output terminal of the fourth AND gate and4, the drain of the fourteenth NMOS transistor MN14 is electrically connected to the drain of the twenty-second PMOS transistor MP22 and serves as the second output terminal of the bias circuit Biase, and the source of the fourteenth NMOS transistor MN14 is electrically connected to the ground.
[0142] When the enable signal OE input to the second input terminal of the bias circuit Biase is VDDIOL, regardless of whether the first control signal model_sel input to the first input terminal of the bias circuit Biase is equal to 0 or VDDIOL, the first bias voltage biaseh output by the first output terminal of the bias circuit Biase is equal to VDDIOL. When the enable signal OE input to the second input terminal of the bias circuit Biase is 0, the first bias voltage biaseh is also equal to VDDIOL.
[0143] When the enable signal OE input to the second input terminal of the bias circuit Biase is VDDIOL, the first control signal mode_sel input to the first input terminal of the bias circuit Biase is 0, and the second bias voltage biasel is equal to VDDIOL; when the first control signal mode_sel input to the first input terminal of the bias circuit Biase is VDDIOL, the second bias voltage biasel output from the second output terminal of the bias circuit Biase is equal to 0. When the enable signal OE input to the second input terminal of the bias circuit Biase is 0, the second bias voltage biasel output from the second output terminal of the bias circuit Biase is equal to VDDIOL.
[0144] The aforementioned enable signal OE is the signal sent from the output terminal of the second inverter inv2 to the bias circuit.
[0145] The working principle of the present invention will be specifically described later.
[0146] The entire circuit design of the present invention is as Figure 1 shown, MP* represents a pmos transistor, MN* represents an nmos transistor, both MP* and MN* are high-voltage transistors, and the voltage difference between the drain and the source that a single transistor can withstand is VDDIOL. The bias circuit Biase outputs a first bias voltage biaseh and a second bias voltage biasel. VDDIOH represents the higher interface voltage, i.e., the first interface voltage, and VDDIOL represents the lower interface voltage, i.e., the second interface voltage. Theoretically, the maximum voltage value of VDDIOH cannot exceed twice that of VDDIOL.
[0147] The level conversion circuit level_shifter is to enable the driving circuit to work properly when the voltage signal range on the input / output pin PAD of the general-purpose input / output interface is within 0 to VDDIOH, and convert the input level signal in the range of 0 to VDDIOL into a level signal in the range of VDDIOL to VDDIOH and output it to the gate of the first pmos transistor MP1.
[0148] The input signal voltage range on the input pin I is within 0 to VDDIOL, and the output signal voltage range on the output pin C is within 0 to VDDIOL; the input / output signal voltage range on the input / output pin PAD can be selected as 0 to VDDIOH (mode_sel = 0) and 0 to VDDIOL (mode_sel = VDDIOL). Among them, the input signal on the input pin I and the output signal on the output pin C are both digital signals, and the input / output signals on the input / output pin PAD are analog signals.
[0149] The second control signal OEN controls the enabling or disabling of the TX module. It is effective when OEN = 0. When the TX module is enabled, data is transmitted from the input pin I to the input / output pin PAD. When OEN = VDDIOL, it is ineffective, the TX module is disabled, and there is no signal transmission from the input pin I to the input / output pin PAD.
[0150] The third control signal IE controls the enabling or disabling of the Schmitt trigger in the RX module. It is effective when IE = VDDIOL. When the Schmitt trigger is enabled, the input / output pin PAD transmits a signal to the output pin C. When IE = 0, it is ineffective, the Schmitt trigger is disabled, and there is no signal transmission from the input / output pin PAD to the output pin C.
[0151] The third control signal IE and the second control signal OEN can be enabled separately or simultaneously.
[0152] The first switch control signal PU controls the closing and opening of the first switch S1. It is effective when PU = VDDIOL, and the first switch S1 closes. It is ineffective when PU = 0, and the first switch S1 closes. The second switch control signal PD controls the closing or opening of the second switch S2. It is effective when PD = VDDIOL, and the second switch S2 closes. It is ineffective when PD = 0, and the second switch S2 opens.
[0153] The first control signal mode_sel controls the voltage amplitude range of the input / output signal output from the TX to the input / output pin PAD. When mode_sel = 0, the amplitude range of the output signal on the input / output pin PAD is 0 to VDDIOH. When mode_sel = VDDIOL, the amplitude range of the output signal on the input / output pin PAD is 0 to VDDIOL. The fourth control signal mode_selb is the signal after inverting the first control signal mode_sel.
[0154] The pull-up resistor R1, the pull-down resistor R2, the first switch S1, and the second switch S2 together form a pull-up / down circuit. When the first switch S1 closes, the trigger input signal RX_in is pulled up to VDDIOL (this pull-up path is a weak pull-up). When the first switch S1 opens, the pull-up path is turned off. When the second switch S2 closes, the trigger input signal RX_in is pulled down to ground (this pull-down path is a weak pull-down). When the second switch S2 opens, the pull-down path is closed. During normal operation, both the pull-up and pull-down paths should be closed. When neither the TX module nor the RX module is working, either a pull-up path or a pull-down path can be opened separately to prevent the Schmitt trigger from having a high-impedance input, which could lead to a large leakage current.
[0155] Weak pull-up and weak pull-down mean that they are turned on during normal operation and do not affect the transmission of normal data.
[0156] As Figure 2 shown, the signal voltage amplitude range on the input / output pin PAD is 0 to VDDIOH (mode_sel = 0. When OEN = 0 and IE = VDDIOL, the red line indicates the circuit usage in this mode):
[0157] When mode_sel = 0, the output of the second AND gate and2 is 0, the output of the second NAND gate nand2 is VDDIOL, and the output voltage signal of the buffer buffer is VDDIOL. Therefore, the voltage on the gate of the third PMOS transistor MP3 is the second interface voltage VDDIOL. Figure 2 This path has been omitted.
[0158] When mode_sel = 0, the first output voltage biaseh generated by the bias circuit Biase is equal to the second output voltage biasel and equal to the second interface voltage VDDIOL; the voltages on the gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both equal to the second interface voltage VDDIOL. At this time, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both turned off, and the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2 together form a driving circuit, so that the signal output voltage range on the input / output pin PAD is 0 to VDDIOH.
[0159] When the voltage on the input / output pin PAD is VDDIOH, the voltages on the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both VDDIOL, approximately one transistor conducts to the first interface voltage VDDIOH; at the same time, the voltage on the gate of the first NMOS transistor MN1 is VDDIOL, ensuring that the voltages on the source and drain of the second NMOS transistor MN2 are not in the breakdown voltage state.
[0160] When the voltage on the input / output pin PAD is 0, the voltages on the gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both VDDIOL, approximately one transistor conducts to the ground GND; at the same time, the voltage on the gate of the first PMOS transistor MP1 is VDDIOH, and the first PMOS transistor MP1 is cut off. At this time, the voltage on the gate of the second PMOS transistor MP2 is VDDIOL, ensuring that the voltages on the source and drain of the first PMOS transistor MP1 are not in the breakdown voltage state.
[0161] Since mode_sel = 0, mode_selb = VDDIOL, so the tenth PMOS transistor MP10 and the seventh NMOS transistor MN7 are turned off; also, since the gate of the ninth PMOS transistor MP9 is controlled by the first bias voltage biaseh, and at this time biaseh = VDDIOL, the source of the ninth PMOS transistor MP9 is electrically connected to the input / output pin PAD, so the polarity of the signal biasep output from the drain of the ninth PMOS transistor MP9 is the same as the polarity of the signal on the input / output pin PAD, but the output amplitude range becomes VDDIOL~VDDIOH; when the signal on the input / output pin PAD is equal to 0, biasep = VDDIOL; when the signal on the input / output pin PAD is equal to VDDIOH, biasep = VDDIOH.
[0162] When the signal on the input / output pin PAD is equal to 0, the third NMOS transistor MN3 is turned off, and the voltages on the gates of the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are all equal to VDDIOL. The 0-level signal is sent from the input / output pin PAD through the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 to the input of the Schmitt trigger, and at this time RX_in = 0.
[0163] When the signal on the input / output pin PAD is equal to VDDIOH, the voltages on the gates of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are both equal to VDDIOH, and the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are both turned off; the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 are all turned on, and the second interface voltage VDDIOL is sent to the input of the Schmitt trigger through the drain of the third NMOS transistor MN3, RX_in = VDDIOL. At this time, since the voltages on the gates of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are both VDDIOL, the signal transmitted from the input / output pin PAD to the input of the Schmitt trigger is limited to VDDIOL; so the signal on the input / output pin PAD is equal to 0, RX_in = 0; the signal on the input / output pin PAD is equal to VDDIOH, RX_in = VDDIOL; thus, it is ensured that when the output voltage range of the input / output pin PAD is 0~VDDIOH, the input of the Schmitt trigger can sample the signal normally.
[0164] As Figure 3As shown, the signal voltage amplitude range on the input / output pin PAD is 0 to VDDIOL, mode_sel = VDDIOL. When OEN = 0 and IE = VDDIOL, the red line indicates the circuit usage in this mode:
[0165] When mode_sel = VDDIOL, the output of the first inverter INV1 is 0, the output of the first AND gate and1 is also 0, the output of the first NAND gate nand1 is VDDIOL, and the output of the level shifter is VDDIOH. So the voltage on the gate of the first PMOS transistor MP1 is VDDIOH. Figure 3 This path has been omitted.
[0166] When mode_sel = VDDIOL, the first bias voltage biaseh output by the bias circuit Biase is equal to VDDIOL, and the first bias voltage biasel = 0; at the same time, the voltage on the gate of the first PMOS transistor MP1 is VDDIOH, and the first PMOS transistor MP1 is turned off. At this time, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the first NMOS transistor MN1, and the second NMOS transistor MN2 together form a driving circuit, and the signal voltage range on the input / output pin PAD is 0 to VDDIOL.
[0167] When the voltage on the input / output pin PAD is VDDIOL, the voltages on the gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both 0, approximately one transistor conducts to the power supply VDDIOL, and the voltage on the gate of the second NMOS transistor MN2 is 0, so the second NMOS transistor MN2 is turned off.
[0168] When the voltage on the input / output pin PAD is 0, the voltages on the gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both VDDIOL, approximately one transistor conducts to the ground GND, and the voltage on the gate of the third PMOS transistor MP3 is VDDIOL, so the third PMOS transistor MP3 is turned off.
[0169] Because mode_sel = VDDIOL, the seventh NMOS transistor MN7 is turned on, and mode_selb = 0, so the tenth PMOS transistor MP10 is also turned on. At the same time, the voltage on the gate of the sixth NMOS transistor MN6 is VDDIOL, so the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 conduct to the ground GND, and biasep = 0.
[0170] When PAD = VDDIOL, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are all turned on, and RX_in = VDDIOL; when PAD = 0, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are conducting, the third NMOS transistor MN3, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are turned off, and the signal on the input / output pin PAD is transmitted to the input terminal of the Schmitt trigger through the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5, and RX_in = 0.
[0171] Therefore, when mode_sel = VDDIOL, if PAD = 0, then RX_in = 0; if PAD = VDDIOL, then RX_in = VDDIOL.
[0172] Through the above description, the present invention realizes the function of selecting two output voltage ranges, where the output voltage range of the signal transmitted from the input pin I to the input / output pin PAD is from 0 to VDDIOH (mode_sel = 0) and from 0 to VDDIOL (mode_sel = VDDIOL). At the same time, when transmitting data from the input / output pin PAD to the output pin C, regardless of whether the signal voltage range on the input / output pin PAD is from 0 to VDDIOH (mode_sel = 0) or from 0 to VDDIOL (mode_sel = VDDIOL), the Schmitt trigger can receive data normally.
[0173] The electrostatic discharge protection circuit ESD functions to protect the internal circuit from electrostatic discharge. Generally, a pair of back-to-back diodes (as shown in Figure 1 ) are added at the position corresponding to the input / output pin to protect the internal circuit.
[0174] The present invention makes certain optimizations to the traditional GPIO structure. The operating level range of the signal output by the traditional GPIO structure cannot be selected, which limits its application range. Nowadays, many protocols often require different output voltage ranges of the signal. For example, a multimedia interface chip requires the output voltage range of the circuit to be selectable between 0 - 3.3V / 0 - 1.8V. At this time, the transmission rate of the traditional GPIO is sufficient, but it cannot be compatible with two output voltages. This is where the advantage of the present invention of selectable output voltage range is reflected. The present invention can be compatible with more protocols and is applicable to more application scenarios.
Claims
1. A universal input / output interface, comprising a TX module, an RX module and a voltage protection circuit, characterized in that: The TX module includes: A first inverter (inv1), an input terminal of which inputs a first control signal (mode_sel); A second inverter (inv2), an input terminal of which is input with a second control signal (OEN); A first AND gate (and1), a first input terminal of which is electrically connected to the output terminal of the first inverter (inv1), and a second input terminal of which is electrically connected to the output terminal of the second inverter (inv2); A second AND gate (and2), a first input terminal of which inputs the first control signal (mode_sel), and a second input terminal of which is electrically connected to the output terminal of the second inverter (inv2); A first NAND gate (nand1), whose first input end serves as an input pin (I) of a universal input / output interface, and whose second input end is electrically connected to an output end of the first AND gate (and1); A second NAND gate (nand2), a first input terminal of which is electrically connected to the first input terminal of the first NAND gate (nand1), and a second input terminal of which is electrically connected to the output terminal of the second AND gate (and2); a third NAND gate (nand3), a first input end of which is electrically connected to the first input end of the first NAND gate (nand1), and a second input end of which is electrically connected to the output end of the second inverter (inv2); a third AND gate (and3), a first input end of which is electrically connected to the output end of the third NAND gate (nand3), and a second input end of which is electrically connected to the output end of the second inverter (inv2); A bias circuit (Biase), wherein a first input terminal thereof inputs a first control signal (mode_sel), and a second input terminal thereof is electrically connected to an output terminal of a second inverter (inv2); a level shifting circuit (level_shifter), an input end of which is electrically connected to an output end of the first NAND gate (nand1); a buffer (buffer), having an input end electrically connected to an output end of the second NAND gate (nand2); A first pmos transistor (MP1), a source of which inputs a first interface voltage (VDDIOH), and a gate of which is electrically connected to an output end of a level conversion circuit (level_shifter); A second pmos transistor (MP2), a source of which is electrically connected to the drain of the first pmos transistor (MP1), and a gate of which is electrically connected to the first output end of the bias circuit (Biase); A first nmos transistor (MN1), a drain of which is electrically connected to a drain of a second pmos transistor (MP2), and a gate of which is electrically connected to a first output end of a bias circuit (Biase); A second nmos transistor (MN2), a drain of which is electrically connected to the source of the first nmos transistor (MN1), a gate of which is electrically connected to the output end of the third AND gate (and3), and a source of which is electrically connected to the ground (GND); The third pmos transistor (MP3) has a source electrode inputting the second interface voltage (VDDIOL) and a gate electrode electrically connected to an output terminal of a buffer; A fourth pmos tube (MP4), whose source is electrically connected to the drain of the third pmos tube (MP3), whose gate is electrically connected to the second output end of the bias circuit (Biase), whose drain is electrically connected to the drain of the second pmos tube (MP2) and serves as an input / output pin (PAD) of a general input / output interface; The RX module includes: A Schmitt trigger (Schmitt_trigger), whose output end is used as an output pin (C) of a general-purpose input / output interface, which is turned on or off by a third control signal (IE); A first switch (S1), a first end of which inputs a second interface voltage (VDDIOL), and is controlled to be closed or opened by a first switch control signal (PU); A pull-up resistor (R1), a first end of which is electrically connected to the second end of the first switch (S1), and a second end of which is electrically connected to the input end of a Schmitt trigger (Schmitt_trigger); A pull-down resistor (R2) having a first end electrically connected to an input end of a Schmitt trigger (Schmitt_trigger); A second switch (S2), a first end of which is electrically connected to the second end of the pull-down resistor (R2), a second end of which is electrically connected to the ground (GND), and a second switch (S2) is controlled to be closed or opened by a second switch control signal (PD); The withstand voltage protection circuit comprises: A third nmos transistor (MN3), a gate of which is electrically connected to the drain of the fourth pmos transistor (MP4), a source of which is electrically connected to the input end of a Schmitt trigger (Schmitt_trigger), and a drain of which is electrically connected to the first output end of a bias circuit (Biase); a fourth nmos tube (MN4), a gate of which is electrically connected to the drain of the third nmos tube (MN3), and a drain of which is electrically connected to the drain of the fourth pmos tube (MP4); A fifth nmos transistor (MN5), whose gate is electrically connected to the drain of the third nmos transistor (MN3), whose drain is electrically connected to the source of the fourth nmos transistor (MN4), and whose source is electrically connected to the input end of a Schmitt trigger (Schmitt_trigger); A fifth pmos tube (MP5), a source of which is electrically connected to a drain of the fourth pmos tube (MP4); A sixth pmos transistor (MP6), whose source is electrically connected to the drain of the fifth pmos transistor (MP5), and whose drain is electrically connected to the input end of a Schmitt trigger (Schmitt_trigger); A tenth pmos transistor (MP10), a gate of which is electrically connected to the output end of the first inverter (inv1), and a source of which inputs the second interface voltage (VDDIOL); A seventh pmos tube (MP7), a source of which is electrically connected to the drain of the tenth pmos tube (MP10), and a drain of which is electrically connected to the drain of the fourth pmos tube (MP4); an eighth pmos tube (MP8), whose source is electrically connected to the drain of the tenth pmos tube (MP10), whose drain is electrically connected to the gate of the seventh pmos tube (MP7), and whose gate is electrically connected to the drain of the seventh pmos tube (MP7); a ninth pmos tube (MP9), whose source is electrically connected to the drain of the seventh pmos tube (MP7), whose drain is electrically connected to the gate of the fifth pmos tube (MP5) and the gate of the sixth pmos tube (MP6), and whose gate is electrically connected to the drain of the eighth pmos tube (MP8) and the first output end of the bias circuit (Biase); A sixth nmos transistor (MN6), a gate of which is electrically connected to the drain of the eighth pmos transistor (MP8), and a drain of which is electrically connected to the drain of the ninth pmos transistor (MP9); The seventh nmos tube (MN7) has a gate that inputs a first control signal (mode_sel), a drain that is electrically connected to the source of the sixth nmos tube (MN6), and a source that is electrically connected to the ground (GND).
2. The universal input / output interface according to claim 1, characterized in that: Also includes: An electrostatic discharge protection circuit comprises a p-type diode (p_diode) and an n-type diode (n_diode); wherein the anode of the p-type diode (p_diode) is electrically connected to the drain of a fourth pmos tube (MP4), the cathode of the p-type diode (p_diode) inputs a first interface voltage (VDDIOH), the cathode of the n-type diode (n_diode) is electrically connected to the drain of the fourth pmos tube (MP4), and the anode of the n-type diode (n_diode) is electrically connected to ground (GND).
3. The universal input / output interface according to claim 1, characterized in that: The level conversion circuit (level_shifter) comprises: The nineteenth pmos transistor (MP19), the source of which inputs the first interface voltage (VDDIOH), and the gate of which inputs the second interface voltage (VDDIOL); An eighteenth pmos tube (MP18), a source of which is electrically connected to a drain of a nineteenth pmos tube (MP19); The seventeenth pmos tube (MP17), whose source is electrically connected to the drain of the nineteenth pmos tube (MP19), whose drain is electrically connected to the gate of the eighteenth pmos tube (MP18) and serves as the output end (Outp) of the level conversion circuit (level_shifter), and whose gate is electrically connected to the drain of the eighteenth pmos tube (MP18); The eleventh pmos tube (MP11), the source of which inputs the second interface voltage (VDDIOL); an eighth nmos transistor (MN8), whose gate is electrically connected to the gate of the eleventh pmos transistor (MP11) and serves as an input terminal (In1) of a level conversion circuit (level_shifter), whose drain is electrically connected to the drain of the eleventh pmos transistor (MP11), and whose source is electrically connected to ground (GND); A ninth nmos tube (MN9), a gate of which is electrically connected to the source of the eleventh pmos tube (MP11), and a source of which is electrically connected to the drain of the eleventh pmos tube (MP11); A twelfth pmos tube (MP12), a source of which is electrically connected to the drain of the eighteenth pmos tube (MP18), and a gate of which is electrically connected to the source of the eleventh pmos tube (MP11); A tenth nmos tube (MN10), a gate of which is electrically connected to the gate of the twelfth pmos tube (MP12), a drain of which is electrically connected to the drain of the twelfth pmos tube (MP12), and a source of which is electrically connected to the ground; a thirteenth pmos tube (MP13), whose source is electrically connected to the drain of the eighteenth pmos tube (MP18), whose gate is electrically connected to the drain of the twelfth pmos tube (MP12), and whose drain is electrically connected to the gate of the twelfth pmos tube (MP12); A fourteenth pmos tube (MP14), a source of which is electrically connected to a drain of a seventeenth pmos tube (MP17), and a drain of which is electrically connected to a source of an eleventh pmos tube (MP11); A fifteenth pmos tube (MP15), whose source is electrically connected to the drain of the seventeenth pmos tube (MP17), whose gate is electrically connected to the source of the eleventh pmos tube (MP11), and whose drain is electrically connected to the gate of the fourteenth pmos tube (MP14); An eleventh nmos tube (MN11), a gate of which is electrically connected to a drain of a fourteenth pmos tube (MP14), a drain of which is electrically connected to a drain of a fifteenth pmos tube (MP15), and a source of which is electrically connected to ground (GND); A twelfth nmos tube (MN12), a gate of which is electrically connected to the source of the eleventh pmos tube (MP11), and a drain of which is electrically connected to the drain of the fifteenth pmos tube (MP15); A sixteenth pmos tube (MP16), whose source is electrically connected to the source of the eleventh pmos tube (MP11), whose gate is electrically connected to the drain of the eleventh pmos tube (MP11), and whose drain is electrically connected to the source of the twelfth nmos tube (MN12); The gate of the thirteenth nmos tube (MN13) is electrically connected to the drain of the eleventh pmos tube (MP11), the drain of the thirteenth pmos tube (MP16) is electrically connected, and the source of the thirteenth nmos tube (MN13) is electrically connected to the ground (GND).
4. The universal input / output interface according to claim 1, characterized in that: The bias circuit (Biase) includes: A third inverter (inv3), an input terminal of which serves as a second input terminal of a bias circuit (Biase); a fourth AND gate (and4), a first input terminal of which is electrically connected to the input terminal of the third inverter (inv3), and a second input terminal of which serves as a first input terminal of a bias circuit (Biase); A twentieth pmos transistor (MP20), a source of which inputs the second interface voltage (VDDIOL), and a gate of which is electrically connected to the output end of the third inverter (inv3); The twenty-first pmos transistor (MP21) has a source electrode inputting the second interface voltage (VDDIOL), a gate electrode electrically connected to the input end of the third inverter (inv3), and a drain electrode electrically connected to the drain electrode of the twentieth pmos transistor (MP20) to serve as the first output end of the bias circuit (Biase); A twenty-second pmos transistor (MP22), a source of which is electrically connected to the drain of the twentieth pmos transistor (MP20), and a gate of which is electrically connected to the output end of the fourth AND gate (and4); A fourteenth nmos tube (MN14) has a gate electrically connected to the output end of the fourth AND gate (AND4), a drain electrically connected to the drain of the twenty-second pmos tube (MP22) and serving as the second output end of the bias circuit (Biase), and a source electrically connected to the ground (GND).