Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes a first terminal; an oscillation circuit that generates a first clock signal and a second clock signal; an AD conversion circuit; a correction circuit that corrects the digital signal obtained by the AD conversion circuit on the basis of the correction data stored in the storage circuit, and outputs the digital signal; an averaging circuit; a sampling circuit; a current generation circuit; and a superimposing circuit generating correction data based on an output of the sampling circuit when the dispersed current is superimposed on the detection current, and storing the correction data in the storage circuit.

Description

[0001] Cross - reference to related applications

[0002] The disclosure of Japanese Patent Application No. 2023-217779, filed on December 25, 2023, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method of manufacturing the same, for example, a semiconductor device including an analog-to-digital (hereinafter also referred to as AD) conversion circuit and a method of manufacturing the same. Background Art

[0004] The disclosed technologies are listed below.

[0005] [Non-Patent Document 1] AN118: Improving ADC Resolution through Oversampling and Averaging, [online], 2013 7 / 13, version 1.3, Silicon Laboratories, pp. 1-20, [retrieved on November 9, 2023], Internet <URL:https: / / WWW.silabs.com / documents / public / application-note / an118.pdf>

[0006] For example, Non-Patent Document 1 discloses a technique for improving the resolution of an AD conversion circuit. In Non-Patent Document 1, it is shown that by sampling an analog signal at a frequency higher than the frequency determined by the sampling theorem, performing AD conversion, and averaging through a digital filter, the apparent resolution is improved. This allows high-resolution measurements to be performed using a low-resolution AD conversion circuit, thereby reducing costs. In the following description, sampling at a frequency higher than the frequency determined by the sampling theorem (i.e., a frequency twice the maximum frequency of the analog signal) is referred to as oversampling. Summary of the Invention

[0007] As a semiconductor device including an AD conversion circuit, for example, there is a semiconductor device that uses the AD conversion circuit to convert an output signal output from the semiconductor device and adjusts the value of the output signal based on the pulse width corresponding to the difference between the digital signal obtained by the AD conversion circuit and the target value data. By using the AD conversion circuit and digital filter according to the technique disclosed in Non-Patent Document 1 as the AD conversion circuit incorporated in such a semiconductor device, the cost of the semiconductor device can be reduced while improving the resolution.

[0008] On the other hand, errors occur in an analog block including an AD conversion circuit. To reduce such errors, it is conceivable to mount a digital correction circuit (hereinafter also simply referred to as a correction circuit) on a semiconductor device and a storage circuit that supplies correction data to the correction circuit. In this case, it is conceivable that during a test step of manufacturing the semiconductor device, a predetermined value is input to the AD conversion circuit, correction data is generated based on a digital signal (a digital signal corresponding to the predetermined value) obtained by the AD conversion circuit to correct the error occurring in the analog block, and the correction data is written into the memory circuit. When the semiconductor device is actually used, the correction circuit uses the correction data to reduce the error included in the digital signal output from the AD conversion circuit.

[0009] In the technique disclosed in Non-Patent Document 1, in order to achieve the effect of averaging by a digital filter, it is assumed that the signal input to the AD conversion circuit includes a certain amount of noise. Therefore, during the test step, it is required that the predetermined value input to the AD conversion circuit also includes a certain amount of noise. Therefore, the inventors considered generating an AC signal using a tester or the like during the test step and inputting the AC signal as the predetermined value to the AD conversion circuit. However, this method causes a problem of increased test cost.

[0010] A brief overview of the representative embodiments disclosed in the present application is as follows.

[0011] That is, a semiconductor device according to an embodiment includes a first terminal; an oscillation circuit that generates a first clock signal and a second clock signal, the second clock signal having a frequency that is an integer fraction of the first clock signal; an AD conversion circuit that oversamples a detection current corresponding to a current flowing through the first terminal according to the first clock signal and converts the detection current into a digital signal; a correction circuit that corrects the digital signal obtained by the AD conversion circuit based on correction data stored in a memory circuit and outputs the digital signal; an averaging circuit that operates according to the first clock signal and averages the digital signal output from the correction circuit; a sampling circuit that downsamples the digital signal averaged by the averaging circuit according to the second clock signal; a current generation circuit that generates a current based on the output of the sampling circuit and target current data and supplies the current to the first terminal; and a superimposing circuit that superimposes a dispersion current on the detection current when generating the correction data. Here, when the dispersion current is superimposed on the detection current, the correction data is generated based on the output of the sampling circuit and the correction data is stored in the storage circuit.

[0012] According to the description of the present specification and the drawings, other objects and novel features will be apparent.

[0013] According to one embodiment, it is possible to provide a semiconductor device including an AD conversion circuit capable of improving resolution while suppressing an increase in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram illustrating the configuration of a semiconductor device according to a first embodiment.

[0015] Figure 2 is a set of waveform diagrams for illustrating the operation of a semiconductor device according to a first embodiment.

[0016] Figure 3 is a block diagram for illustrating the superposition of dispersed currents according to a first embodiment.

[0017] Figure 4 is a circuit diagram illustrating an example of a DA conversion circuit according to a first embodiment.

[0018] Figure 5 is a schematic waveform diagram for illustrating the operation during the test of a semiconductor device according to a first embodiment.

[0019] Figure 6 is a schematic waveform diagram for illustrating the operation during the test of a semiconductor device according to a first embodiment.

[0020] Figure 7 is a waveform diagram illustrating a comparative example according to a first embodiment.

[0021] Figure 8A is a waveform diagram illustrating the operation during the test of a semiconductor device according to a first embodiment.

[0022] Figure 8B is a waveform diagram illustrating the operation during the test of a semiconductor device according to a first embodiment.

[0023] Figure 8C is a waveform diagram illustrating the operation during the test of a semiconductor device according to a first embodiment.

[0024] Figure 8D is a waveform diagram illustrating the operation during the test of a semiconductor device according to a first embodiment.

[0025] Figure 9 is a block diagram illustrating a semiconductor device according to a second embodiment.

[0026] Figure 10 is a waveform diagram illustrating the operation of a semiconductor device according to a second embodiment.

[0027] Figure 11 is a block diagram illustrating a semiconductor device according to a third embodiment.

[0028] Figure 12A and Figure 12B is a flowchart for illustrating a method of manufacturing a semiconductor device according to a first embodiment.

[0029] Figure 13 is a schematic block diagram illustrating an example of a test board according to the first embodiment.

[0030] Figure 14 is a block diagram illustrating reducing errors and accompanying problems occurring in an analog block. Detailed Description

[0031] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the present disclosure is merely an example, and any modifications that can be easily conceived by those skilled in the art without departing from the spirit of the present invention are properly included within the scope of the present invention.

[0032] In addition, in this specification and the drawings, the same reference numerals are assigned to elements similar to those described in the previous drawings, and detailed descriptions may be appropriately omitted.

[0033] (First Embodiment)

[0034] <Configuration of Semiconductor Device>

[0035] Figure 1 is a block diagram illustrating the configuration of a semiconductor device according to the first embodiment, and Figure 2 is a set of waveform diagrams for illustrating the operation of a semiconductor device according to the first embodiment. The semiconductor device 1 according to the first embodiment includes a single semiconductor substrate on which a plurality of circuit blocks are formed using known semiconductor manufacturing techniques, and a plurality of external terminals (hereinafter also referred to as terminals) to which the circuit blocks formed on the semiconductor substrate are connected. Although not particularly limited, the semiconductor substrate is sealed with a single package, and the plurality of external terminals protrude from the package.

[0036] In Figure 1 CHP surrounded by a dotted line indicates the semiconductor substrate on which a plurality of circuit blocks are formed. Although various circuit blocks are formed as a plurality of circuit blocks on the semiconductor substrate CHP, only the circuit blocks necessary for illustration are shown in Figure 1 In addition, in Figure 1 T1 to T4 indicate the external terminals connected to the circuit blocks. Regarding the external terminals, similar to the circuit blocks, only those necessary for illustration are shown in Figure 1 In

[0037] In the first embodiment, a semiconductor device including a current regulator will be described as an example of the semiconductor device 1. The current regulator outputs a current corresponding to a target current value (target value data) specified by a user via an external terminal. However, it is naturally not limited to this example.

[0038] In Figure 1 , reference numeral 2 denotes a target data output circuit that outputs a target current value (numerical value) Iset specified by the user. The target current value Iset is supplied to a current generation circuit IGC.

[0039] The current generation circuit IGC includes an arithmetic circuit 3, a PID control circuit 4, a PWM generation circuit 5, an inverter circuit 6, and N-channel field effect transistors N1 and N2. Hereinafter, the field effect transistor will be referred to as a MOS transistor, the N-channel MOS transistor will be referred to as an NMOS transistor, and the P-channel MOS transistor will be referred to as a PMOS transistor.

[0040] The arithmetic circuit 3 calculates the difference between a detected current (numerical value) Idet, which will be described later, and the target current value Iset, and supplies the calculated difference as a control current (numerical value) Icnt to the PID control circuit 4.

[0041] The PID control circuit 4 operates according to a clock signal CLK_FS supplied to a clock terminal ck, generates a control signal (numerical value) PI_D corresponding to the input control current Icnt, and outputs it to the PWM generation circuit 5. The PWM generation circuit 5 also operates according to the clock signal CLK_FS supplied to the clock terminal ck, generates a PWM control signal PW_D, and outputs it to the inverter circuit 6 and the gate of the NMOS transistor N1. The frequency of the clock signal CLK_FS is, for example, 16 MHz. The PWM control signal PW_D output by the PWM generation circuit 5 is a periodic signal having a predetermined frequency Fpwm, and the period of the PWM control signal PW_D is 1 / Fpwm, as Figure 2 shown. By means of the PID control circuit 4 and the PWM generation circuit 5, a PWM control signal PW_D is generated, in which the ratio of the high-level period to the low-level period within the period 1 / Fpwm varies according to the value of the control current Icnt.

[0042] The drain of the CMOS transistor N1 is connected to the power supply voltage Vdd, the source of the NMOS transistor N2 is connected to the ground voltage Vss, and the source of the NMOS transistor N1 is connected to the drain of the NMOS transistor N2 and an external terminal (first terminal) T1. In addition, the output of the inverter circuit 6 is supplied to the gate of the NMOS transistor N2.

[0043] Therefore, during the high level period of the PWM control signal PW_D, the NMOS transistor N1 is in the on state, and the NMOS transistor N2 is in the off state, allowing the current I_out to flow between the power supply voltage Vdd and the external terminal T1 via the NMOS transistor N1. On the other hand, during the low level period of the PWM control signal PW_D, the NMOS transistor N2 is in the on state, and the NMOS transistor N1 is in the off state, allowing the current I_out to flow between the external terminal T1 and the ground voltage Vss via the NMOS transistor N2. As a result, the current generation circuit IGC generates a current (output current) I_out based on the target current value Iset and the detected current Idet, and supplies it to the external terminal T1.

[0044] In the semiconductor device 1 according to the first embodiment, a correlation current (analog value) Il related to the current flowing through the external terminal T1 is used to generate the detected current Idet. The correlation current Il is detected by the current detection circuit 7, and is output as a detected current (analog value) Isig from the current detection circuit 7 to the AD conversion circuit 8.

[0045] The clock signal CLK_AD is supplied to the clock terminal ck of the AD conversion circuit 8. The AD conversion circuit 8 samples the detected current Isig supplied to its input terminal using the clock signal CLK_AD supplied to the clock terminal ck, converts the sampled signal into a digital detection signal, and outputs the detection signal from the output terminal d. In the first embodiment, although not particularly limited, the AD conversion circuit 8 is an AD conversion circuit with a 10-bit resolution.

[0046] The sampling frequency of the AD conversion circuit 8 determined by the sampling theorem, that is, the frequency of the clock signal CLK_AD supplied to the clock terminal ck, is 125 kHz with respect to the frequency of the detected current supplied to the input terminal of the AD conversion circuit 8. However, in the first embodiment, the frequency of the clock signal CLK_AD is set to 1 MHz. That is, the AD conversion circuit 8 converts the analog detected current into a digital signal by oversampling.

[0047] The detection signal output from the output terminal d of the AD conversion circuit 8 is supplied to the arithmetic circuit 18. The output signal of the arithmetic circuit 18 (the digital signal at the output terminal e of the arithmetic circuit 18) is supplied to the correction circuit (hereinafter also referred to as the calibration circuit) 9. As will be referred to later Figure 14 In the example illustrated in the figure, errors occur in the analog block including the AD conversion circuit 8. To reduce such errors, a correction circuit 9 and a storage circuit 10 for storing correction data C_data are provided. As will be referred to later with reference to Fig. 12 and Figure 13As described, the calibration data C_data is obtained during a test step in the manufacture of the semiconductor device 1 and is written into the memory circuit 10.

[0048] When the current generation circuit IGC generates a current corresponding to the target current value Iset and supplies this current as the output current I_out to the external terminal T1, that is, when the semiconductor device 1 actually operates as a current regulator, the calibration circuit 9 uses the calibration data C_data supplied from the memory circuit 10 to calibrate the output signal supplied from the arithmetic circuit 18. The output signal (digital value) of the calibration result obtained by the calibration of the calibration circuit 9 is supplied from the output terminal f of the calibration circuit 9 to the averaging circuit 11.

[0049] The averaging circuit 11 includes a digital filter (averaging filter) that operates according to the clock signal supplied to the clock terminal ck. The clock signal supplied to the clock terminal ck of the averaging circuit 11 is the same clock signal CLK_AD as the clock signal supplied to the clock terminal ck of the AD conversion circuit 8. The averaging circuit 11 averages the supplied output signal of the calibration circuit 9 and outputs the average signal as an analog output signal from the output terminal g.

[0050] The analog output signal output from the averaging circuit 11 is supplied to the downsampling (sampling) circuit 12. The downsampling (downsampler) 12 downsamples the analog output signal supplied from the averaging circuit 11 according to the clock signal CLK_DS supplied to the clock terminal ck and outputs the downsampled signal as a digital output signal from the output terminal h. The digital output signal output from the output terminal h is supplied to the arithmetic circuit 3 as the detected current Idet.

[0051] In the first embodiment, the frequency of the clock signal CLK_DS is 125 kHz. That is, the frequency of the clock signal CLK_DS is 1 / 8 of the frequency of the clock signal CLK_AD, and this frequency is the sampling frequency determined by the sampling theorem.

[0052] In addition to the schematic waveform of the described PWM control signal PW_D, Figure 2 the schematic waveforms at the output terminal d of the AD conversion circuit 8 and at the output terminal h of the downsampling circuit 12 are also illustrated in Figure 2The waveforms at output terminals d and h. AL indicates the waveform (triangular waveform) of the analog signal input to the AD conversion circuit 8 and the downsampling circuit 12. In addition, for the waveform at output terminal d, the black circles (●) SP indicate the timing of sampling (sampling timing) performed in the AD conversion circuit 8 and the value of the code (output code) output from the AD conversion circuit 8. Further, regarding the waveform at output terminal h, the black circles (●) SD indicate the sampling timing of sampling performed in the downsampling circuit 12 and the value of the output code output from the downsampling circuit 12.

[0053] In the AD conversion circuit 8, oversampling is performed; thus, the number of times of sampling (average region) performed within one period of the analog signal AL is as large as, for example, six times (the number of black circles SP). However, in the downsampling circuit 12, the number of times of sampling performed within one period of the analog signal AL is as small as, for example, once (black circles SD). From a different perspective, the output codes obtained from the sampling of the AD conversion circuit 8 can be considered to be thinned out to fewer output codes by the downsampling circuit 12.

[0054] In addition, regarding the waveform at output terminal d, the dashed line AVL indicates the average value of the six output codes (black circles SP) included in the average region AVA. The six output codes (black circles SP) obtained by AD conversion by the AD conversion circuit 8 are averaged by the averaging circuit 11. As a result, the output signal of the averaging circuit 11 schematically has Figure 2 the waveform shown by the dashed line AVL in Figure 2 As shown at output terminal d of Figure 2 , even if the resolution is low and there is no black circle SP at the sampling timing for sampling the dashed line AVL, sampling of the dashed line AVL obtained by averaging can be performed at the black circle SD, as shown at output terminal h of

[0055] The above clock signals CLK_FS, CLK_AD, and CLK_DS are generated by a clock generation circuit (oscillation circuit) CLK_GN. The clock generation circuit CLK_GN according to the first embodiment includes a frequency generator 13, a counter 14, and a PWM frequency generation circuit 15. The frequency generator 13 generates clock signals CLK_FS and CLK_AD having a predetermined frequency. As described above, the clock signal (first clock signal) CLK_AD is supplied to the clock terminals ck of the AD conversion circuit 8 and the averaging circuit 11, and is also supplied to the counter 14. The counter 14 counts the pulses of the clock signal CLK_AD, and supplies the count value to the PWM frequency generation circuit 15. As described above, based on the supplied count value, the PWM frequency generation circuit 15 generates a signal (second clock signal having an integer fraction of the first clock signal frequency) CLK_DS, and supplies the generated signal to the clock terminal ck of the downsampling circuit 12.

[0056] The semiconductor device 1 further includes a control circuit 22, which includes a control register (not shown), a switch 21 controlled by a test enable signal (hereinafter also simply referred to as a test signal) Test_en output from the control circuit 22, an external terminal (fourth terminal) T4 connected to the control circuit 22, an external terminal (second terminal) T2 connected to the output terminal h of the downsampling circuit 12 via the switch 21, and an external terminal (third terminal) T3 connected to the memory circuit 10.

[0057] In addition, the semiconductor device 1 includes logic circuits 19 and 20, a decoder 16 connected to the output terminal ca of the counter 14 via the logic circuit 20, and a digital-to-analog (hereinafter also referred to as DA) conversion circuit 17 that converts the output signal (digital value) din of the decoder 16 into an analog value.

[0058] The control circuit 22, the switch 21, the external terminals T2 to T4, the logic circuits 19 and 20, the decoder 16, and the DA conversion circuit 17 will be described later, and their descriptions are omitted here.

[0059] In Figure 1 the symbol LL indicates a schematic load connected between the external terminal T1 and the ground voltage Vss.

[0060] <<Overview of Current Regulator Operation>>

[0061] When the semiconductor device 1 operates, the current generation circuit IGC generates an output current I_out and supplies the output current I_out from the external terminal T1 to the load LL. The current detection circuit 7 detects a relevant current Il related to the output current I_out, and the current detection circuit 7 outputs a detection current Isig corresponding to the relevant current Il. The AD conversion circuit 8 samples the detection current Isig by oversampling and converts it into a digital detection signal. Then, the digital detection signal is corrected by the correction circuit 9 and averaged by the averaging circuit 11. The analog output signal obtained by averaging is downsampled by the downsampling circuit 12 to generate a detection current Idet. In the current generation circuit IGC, the period during which the NMOS transistors N1 and N2 are controlled to be in the on state is adjusted such that the detection current Idet coincides with the target current value Iset. This process is repeated, and the output current I_out corresponding to the target current value Iset is supplied from the external terminal T1 to the load LL.

[0062] <Manufacture of semiconductor device>

[0063] Before being provided to the user, the semiconductor device 1 according to the first embodiment undergoes testing during the manufacturing process. Based on the detection current measured through the testing, correction data is generated and written into the storage circuit 10 of the semiconductor device 1.

[0064] Figure 12A and Figure 12B are flowcharts for illustrating the method of manufacturing the semiconductor device according to the first embodiment. Here, Figure 12A is a flowchart illustrating the entire manufacturing method, and Figure 12B is a flowchart illustrating Figure 12A the details of step S3 in

[0065] In Figure 12A the step S0 shown, the manufacture of the semiconductor device 1 starts. Step S1 is a preparation step for preparing a semiconductor substrate. In step S2 as a formation step, a plurality of circuit blocks including Figure 1 circuit blocks such as those shown are formed on the semiconductor substrate prepared in the preparation step S1 by a known semiconductor manufacturing method. In step S2, Figure 1 external terminals T1 to T4 etc. shown are connected to the circuit blocks and sealed by a package to complete the semiconductor device 1.

[0066] Next, in step S3, the semiconductor device 1 is tested. The test steps in step S3 will be described with reference to Figure 12B and thus its description is omitted here. In step S4 after step S3, the semiconductor device 1 is provided to the user, and in step S5, the manufacture of the semiconductor device is completed.

[0067] <<Test Steps>>

[0068] In the test step of step S3, the semiconductor device 1 according to the first embodiment is mounted on a test board, tests are performed on the test board, and correction data is written.

[0069] Figure 13 is a schematic block diagram showing an example of a test board according to the first embodiment. In Figure 13 , the dashed line TTB indicates a schematic diagram of the test board. A plurality of semiconductor devices 1_0 to 1_n (each corresponding to the semiconductor device 1 in Figure 1 ) completed in step S2 are mounted on the test board TTB, and the tester TST performs testing, generation of correction data, and writing of correction data. Although Figure 13 illustrates a state in which one semiconductor device 1_0 is connected to the tester TST, the other semiconductor devices (1_n, etc.) are similarly connected.

[0070] The tester TST also includes a plurality of circuit blocks, but in Figure 13 , only the circuit blocks required for illustration are shown. In Figure 13 , CNT indicates a control circuit, WRC indicates a writing circuit, and TS_T1 to TS_T4 indicate external terminals of the tester TST.

[0071] During testing, the control circuit CNT generates a test current I_tst and supplies this current to the external terminal T1 of the semiconductor device 1_0 via the external terminal TS_T1. The test current I_tst is a predetermined fixed current. Further, during testing, the control circuit CNT supplies test setting data TT_en for generating a test signal Test_en and an offset value Offset to the external terminal T4 of the semiconductor device 1_0 via the external terminal ST_T4, which will be described later. Further, during testing, a detection current Idet is supplied to the control circuit CNT via the external terminal TS_T2 connected to the external terminal T2 of the semiconductor device 1_0. The control circuit CNT generates correction data C_data based on the test current I_tst and the detection current Idet, and supplies the correction data C_data to the writing circuit WRC. The writing circuit WRC supplies the supplied correction data C_data to the external terminal T3 of the semiconductor device 1_0 via the external terminal TS_T3.

[0072] In Figure 12B , steps S3_B0 to S3_B2 illustrate steps mainly performed by the Figure 13 shown tester TST, and step S3_LS illustrates steps mainly performed by the Figure 13 shown semiconductor device 1_0 (corresponding to Figure 1The steps performed corresponding to the semiconductor device 1 therein.

[0073] In step S3_B0, the control circuit CNT of the tester TST ( Figure 13 ) stores the test setting data TT_en and the offset value Offset in a register (not shown) in the control circuit 22 ( Figure 1 ) via the external terminal T4 of the semiconductor device 1_0. As a result, the control circuit 22 generates a test signal Test_en for the conduction switch 21 and also outputs the offset value Offset. In addition, the control circuit CNT generates a test current I_tst and supplies this current to the external terminal T1 of the semiconductor device 1_0 ( Figure 13 ). As a result, in the semiconductor device 1_0, a related current Il ( Figure 1 ) related to the test current I_tst is supplied to the current detection circuit 7, and the current detection circuit 7 outputs a detection current Isig having a value corresponding to the test current I_tst.

[0074] In step S3_LS, in the semiconductor device 1_0, the AD conversion circuit 8 ( Figure 1 ) converts the detection current Isig output from the current detection circuit 7 into a digital signal by oversampling. The digital detection signal obtained by the conversion (output from the output terminal d) is output via the arithmetic circuit 18, the correction circuit 9, the averaging circuit 11, and the downsampling circuit 12 as a detection current Idet corresponding to the test current I_tst. At this time, the switch 21 ( Figure 1 ) is in the conduction state, so the detection current Idet is supplied to the control circuit CNT of the tester TST via the switch 21, the external terminal T2 of the semiconductor device 1_0, and the external terminal TS_T2 of the tester TST.

[0075] In step S3_B1, the control circuit CNT of the tester TST generates correction data C_data such that when the test current I_tst is AD-converted, the supplied detection current Idet coincides with the ideal value, and outputs the correction data C_data to the writing circuit WRC.

[0076] Next, in step S3_B2, the writing circuit WRC in the tester TST supplies the correction data C_data to the memory circuit 10 via the external terminal T3 of the semiconductor device 1_0 and writes the correction data C_data into the memory circuit 10.

[0077] As a result, the manufacturing of the semiconductor device 1_0 is completed. The semiconductor device includes a memory circuit 10, correction data C_data for correcting errors occurring in the analog block including the AD conversion circuit is written into the memory circuit 10, and implementationFigure 12A Step S4 in

[0078] <Reducing errors and problems that occur in the simulation module>

[0079] Figure 14 is a block diagram showing the reduction of errors and accompanying problems that occur in the simulation block. Figure 14 The figure shows when Figure 12B the configuration of the semiconductor device 1_0 when the step S3_LS shown is being implemented. Figure 14 Similar to Figure 1 . The main difference is that Figure 14 only the current detection circuit 7, the AD conversion circuit 8, the correction circuit 9, the storage circuit 10, the averaging circuit 11, the downsampling circuit 12, and the external terminals T1 to T3 are shown.

[0080] In analog blocks such as the current detection circuit 7 and the AD conversion circuit 8, errors occur due to changes in manufacturing conditions and the like. The correction circuit 9 corrects the errors based on the correction data C_data supplied from the storage circuit 10.

[0081] To generate the correction data C_data, the tester TST supplies a predetermined fixed current as the test current I_tst to the external terminal T1 of the semiconductor device 1_0, and measures the detection current Idet output from the external terminal T2 of the semiconductor device 1_0 at that point. That is, the current detection circuit 7 detects the current based on the test current I_tst, which is a predetermined fixed current with little noise, and the detection current Isig is oversampled and converted into a digital signal. Since there is almost no noise, it is considered that even if oversampling is performed, the multiple digital values obtained thereby will be the same value (output code), so the averaging effect of the averaging circuit 11 may not be obtained. If the averaging effect is not achieved, the output of the downsampling circuit 12 will have the original resolution of the AD conversion circuit 8. For example, if the AD conversion circuit 8 has a resolution of 10 bits, the output of the downsampling circuit 12 will also have an accuracy of 10 bits.

[0082] As a countermeasure, it is possible to intentionally change the test current I_tst. To intentionally change the test current I_tst, for example, Figure 13 the control circuit CNT of the tester TST shown needs to generate a test current that changes at a frequency in the range from several kHz to several tens of kHz. Alternatively, when generating the correction data C_data using a mass production board on which the semiconductor device 1_0 is actually mounted instead of Figure 13 the tester TST shown, components (passive components and active components) need to be added to the mass production board to change the test current I_tst. In either case, the test cost of the semiconductor device increases, which is not practical.

[0083] As another countermeasure, it is also conceivable to install a high-precision (for example, a resolution higher than 10 bits) AD conversion circuit in the semiconductor device. However, in this case, the occupied area occupied by the AD conversion circuit increases, and the cost of the semiconductor chip increases, which is not desirable.

[0084] <Superposition and offset removal of dispersion current>

[0085] In the semiconductor device according to the first embodiment, during the test step, a dispersion current Idac as shown in Figure 2 is generated in the semiconductor device 1. The dispersion current Idac is a current that periodically changes at the frequency and period (1 / Fpwm) of Fpwm. As shown in Figure 1 , the generated dispersion current Idec is superimposed on the detection current Isig output from the current detection circuit 7 and supplied to the AD conversion circuit 8. Further, with the detection current Isig as a reference, the dispersion current Idac fluctuates above and below a value higher than the offset value Offset. In step S3_LS in Figure 12B , as shown in bold, the superposition of the dispersion current Idac (dispersion current superposition) and the removal of the offset value Offset (offset removal) are performed.

[0086] That is, during the test step, the dispersion current Idac is superimposed on the detection current Isig corresponding to the test current I_tst. In other words, the periodically changing dispersion current Idac is superimposed on the input of the AD conversion circuit 8 as periodic noise. As a result, the AD conversion circuit 8 converts a plurality of values obtained by oversampling into different digital values, allowing the effect of averaging by the averaging circuit to be achieved. That is, it is possible to achieve a resolution higher than the original resolution of the AD conversion circuit 8. As a result, a high-precision detection current Idet can be obtained via the external terminal T2 during the test, while preventing an increase in the test cost and also suppressing an increase in the cost of the semiconductor chip. Therefore, in the control circuit CNT of the tester TST, high-precision correction data C_data can be generated, and during the test, the high-precision correction data C_data can be written into the storage circuit 10.

[0087] When the semiconductor device 1 is actually used, errors in the analog block are corrected based on the high-precision correction data C_data, thereby allowing an accurate digital signal to be obtained. In the example of the semiconductor device 1 shown in Figure 1 , it is possible to output an output current I_out that more accurately matches the target current value Iset.

[0088] Further, in the first embodiment, the output from the AD conversion circuit 8 is subtracted from the value corresponding toFigure 2 The numerical value corresponding to the offset value Offset shown. Accordingly, the configuration of the AD conversion circuit 8 and the configuration of the circuit block for generating the dispersion current Idac can be simplified.

[0089] <<Configuration for generating the dispersion current>>

[0090] Returning to Figure 1 , the configuration for generating the dispersion current will be specifically described.

[0091] The dispersion current Idac is generated by the logic circuit 20, the decoder 16, and the DA conversion circuit 17.

[0092] The logic circuit 20 is supplied with the output signal (count value) output from the output terminal ca of the counter 14 and the test signal Test_en. When the test signal Test_en indicates the test state, the logic circuit 20 becomes conductive and supplies the output signal of the counter 14 to the decoder 16. The decoder 16 decodes the supplied output signal and outputs a digital output signal din corresponding to the dispersion current Idac. In the first embodiment, the decoder 16 outputs 4-bit parallel digital signals din0 to din3 as the output signal din based on the output signal from the counter 14, although there is no particular limitation thereto. The decoder 16 outputs the output signal din, which forms a triangular waveform within one cycle (1 / Fpwm) when converted into an analog signal, as the dispersion current Idac shown in Figure 2 , and this occurs as the clock signal CLK_AD supplied to the counter 14 changes, resulting in a change in the logic values of the digital signals din0 to din3. Naturally, the output signal din is not limited to a 4-bit digital signal.

[0093] The output signal din is converted into an analog dispersion current Idac by the DA conversion circuit 17. The output of the DA conversion circuit 17 and the output of the current detection circuit 7 are connected at a connection node (first node) N_cnt, and the detection current Isig output from the current detection circuit 7 is superimposed on the dispersion current Idac output from the DA conversion circuit 17 and supplied to the AD conversion circuit 8.

[0094] In addition, the output of the logic circuit 19 is supplied to the arithmetic circuit 18 connected to the output terminal d of the AD conversion circuit 8. The logic circuit 19 is supplied with the test signal Test_en and the offset value Offset. When the test signal Test_en indicates the test state, the logic circuit 19 becomes conductive and supplies the offset value Offset to the arithmetic circuit 18. The arithmetic circuit 18 subtracts the offset value Offset from the output signal supplied from the AD conversion circuit 8 and supplies the subtracted result to the correction circuit 9 from the output terminal e.

[0095] Although there is no particular limitation, the offset value Offset is determined in advance and stored in the control circuit CNT ( Figure 13 ) of the tester TST ( Figure 13 ). In step S3 ( Figure 12A ) as a test step, the control circuit CNT supplies the offset value Offset to the control circuit 22 of the semiconductor device 1 via the external terminal TS_T4 of the tester TST and the external terminal T4 of the semiconductor device 1.

[0096] <<Superposition of the dispersion current>>

[0097] <<<Example of the current detection circuit 7>>>

[0098] Figure 3 is a block diagram for illustrating the superposition of the dispersion current according to the first embodiment. Figure 3 Illustrated is a part corresponding to the AD conversion circuit 8, DA conversion circuit 17, logic circuit 19, arithmetic circuit 18, and current detection circuit 7 shown in Figure 1 . In particular, in Figure 3 , a part corresponding to the current detection circuit 7 is illustrated in detail. Figure 3 Illustrated is a state in which a test current I_tst is supplied from the tester TST ( Figure 13 ) to the current detection circuit 7 during the test. For ease of explanation, the test current I_tst is illustrated as a current source in Figure 3 .

[0099] The current detection circuit 7 includes a P-type MOS transistor P1 and a resistor element R1 connected in series between the power supply voltage Vdd and the ground voltage Vss, and a P-type MOS transistor P2 and a current source I_tst connected in series between the power supply voltage Vdd and the ground voltage Vss. The gate electrode of the P-type MOS transistor P2 is connected to the drain terminal of the P-type MOS transistor P2 and the gate of the P-type MOS transistor P1, forming a current mirror circuit with the P-type MOS transistors P1 and P2.

[0100] The output terminal of the DA conversion circuit 17 and the input terminal of the AD conversion circuit 8 are connected to the connection node N_cnt between the drain terminal of the P-type MOS transistor P1 and the resistor element R1. Next, Figure 4Describe an example of the DA conversion circuit 17. The DA conversion circuit 17 forms a triangular-wave distributed current Idac. Therefore, the triangular-wave distributed current Idac formed by the DA conversion circuit 17 is superimposed on the detection current Isig proportional to the test current I_tst and flows through the resistor element R1. As a result, in the resistor element R1, a voltage corresponding to the detection current Isig is generated, the distributed current Idac is superimposed on the detection current Isig, and the voltage changes according to the periodic change of the distributed current Idac. This voltage is converted into a digital output signal by the AD conversion circuit 8. The connection node N_cnt can be regarded as a superimposing circuit that superimposes the distributed current Idac on the detection current Isig.

[0101] <<<<An example of the DA conversion circuit 17>>>>

[0102] Figure 4 is a circuit diagram showing an example of the DA conversion circuit according to the first embodiment. Figure 4 Illustrates Figure 1 the case where the illustrated decoder 16 supplies 4-bit digital signals din0 to din3 as the output signal din to the DA conversion circuit 17.

[0103] The DA conversion circuit 17 includes P-type MOS transistors P3 to P7, a constant current source I_dc, and four switches SS_0 to SS_3 that are switched by 4-bit digital signals from the decoder 16. The source of the P-type MOS transistor P3 is connected to the power supply voltage Vdd, and the drain is connected to the ground voltage Vss via the constant current source I_dc and is connected to the gates of the P-type MOS transistors P4 to P7. In addition, the sources of the P-type MOS transistors P4 to P7 are connected to the power supply voltage Vdd. Therefore, a current mirror circuit is formed by the P-type MOS transistors P3 to P7. In the first embodiment, the P-type MOS transistors P4 to P7 have the same size, and the currents flowing when the corresponding switches SS_0 to SS_3 are turned on have the same value.

[0104] The decoder 16 according to the first embodiment outputs a signal in which the digital signals din0 to din3 sequentially change to high level as the output signal din, and after all the digital signals reach high level, the digital signals din3 to din0 change to low level. As a result, a distributed current Idac that changes in a triangular wave as shown in Figure 3 is formed.

[0105] As shown in Figure 3As shown, the dispersion current Idac is a current that changes in a triangular waveform above a reference value with the detected current Isig as the reference value. To obtain an average effect, it is desirable for the current input to the AD conversion circuit 8 to change above and below the detected current Isig as the center. Therefore, in the dispersion current Idac, the intermediate value between the reference value and, for example, the maximum value of the dispersion current Idac, that is, the center value between the peaks of the dispersion current Idac, is set as the offset value Offset.

[0106] During the test, the logic circuit 19 is turned on by the test signal Test_en, the offset value Offset is subtracted from the output signal of the AD conversion circuit 8 by the arithmetic circuit 18, and the subtraction result is supplied to the tester TST via the correction circuit 9 and the averaging circuit 11. In this way, a code corresponding to the triangular wave is digitally generated, converted to analog by the DA conversion circuit 17, and superimposed on the detected current Isig, thereby suppressing an increase in the occupied area. In addition, the offset is removed by digital calculation, which results in simplicity. Further, the offset removal can be performed only when necessary, such as during the test.

[0107] <<Schematic operation waveform during test>>

[0108] Next, the operation during the test will be described using schematic waveforms. Figure 5 and Figure 6 are schematic waveform diagrams for illustrating the operation during the test of the semiconductor device according to the first embodiment.

[0109] Hereinafter, reference will be made to Figure 1 and Figures 4 to 6 to describe the operation during the test. For ease of understanding, as described above, Figure 5 and Figure 6 are schematic waveform diagrams.

[0110] In the following description, it is assumed that the frequency of the clock signal CLK_DS is set to 1 / 8 of the frequency of the clock signal CLK_AD, as shown in the example of Figure 1 . Therefore, as shown in Figure 5 , eight cycles of the clock signal CLK_AD are generated in one cycle (one PWM cycle) of the clock signal CLK_DS.

[0111] When the clock signal CLK_AD changes, the decoder 16 supplies the output signal din (din0 to din3) as shown in Figure 5 to Figure 4The shown DA conversion circuit 17. Therefore, taking the detection current Isig from the current detection circuit 7 as a reference value, the DA conversion circuit 17 outputs a dispersion current Idac that varies in a triangular waveform within one PWM cycle. That is, within the 1 / 2 cycle of the PWM cycle, the dispersion current Idac rises stepwise with the detection current Isig as a reference, reaches the maximum value (peak value), and then decreases stepwise from the maximum value to the reference (Isig) during the remaining cycle.

[0112] In Figure 5 , SP_0 to SP_7 indicate the sampling timing of the AD conversion circuit 8 and the values of the output codes of the AD conversion circuit 8, similar to the black circle SP described for the output terminal d in Figure 2 .

[0113] In Figure 5 , CDE_1 to CDE_3 indicate the output codes of the AD conversion circuit 8. Here, it is assumed that the corresponding analog values increase from the output code CDE_1 to CDE_3. Adjacent output codes (e.g., CDE_2 and CDE_3) correspond to a single level AD_LV of the AD conversion circuit 8. For example, using the center values REF_1 and REF_2 of each single level AD_LV as thresholds, the AD conversion circuit 8 outputs an output code higher than the threshold or an output code lower than the threshold depending on whether the value obtained during sampling exceeds the threshold. That is, the AD conversion circuit 8 sequentially converts the analog values obtained at the sampling timing into output codes in the order of the black circles SP_0 to SP_7. The output code is a digital signal, and the output code to be converted is determined by comparing the obtained analog value with the threshold.

[0114] For example, at the sampling time of the black circle (●) SP_0, the value of the detection current Isig with the superimposed dispersion current Idac is lower than the threshold REF_1 between the output codes CDE_1 and CDE_2. Therefore, the AD conversion circuit 8 outputs the output code CDE_1 lower than the threshold REF_1 as the output code of the black circle SP_0.

[0115] Furthermore, for example, at the sampling time of the black circle (●) SP_1, the value of the detection current Isig with the superimposed dispersion current Idac exceeds the threshold REF_1 between the output codes CDE_1 and CDE_2. Therefore, the AD conversion circuit 8 outputs the output code CDE_2 higher than the threshold REF_1 as the output code of the black circle SP_1. In addition, at the sampling time of the black circle (●) SP_2, the value of the detection current Isig with the superimposed dispersion current Idac is lower than the threshold REF_2 between the output codes CDE_2 and CDE_3. Therefore, the AD conversion circuit 8 outputs the output code CDE_2 lower than the threshold REF_2 as the output code of the black circle SP_2.

[0116] Similarly, hereinafter, the AD conversion circuit 8 determines the output code to be output depending on whether the value of the detection current Isig superimposed with the dispersion current Idac exceeds a threshold value. As a result, even if the value of the detection current Isig remains unchanged, the output code represented by the output signal output from the AD conversion circuit 8 changes.

[0117] Figure 5 The figure illustrates the state in which the dispersion current Idac changes with the detection current Isig as a reference (basis). That is, the figure illustrates the state in which the dispersion current Idac having an offset value Offset is superimposed on the detection current Isig. In the first embodiment, as Figure 1 shown, the arithmetic circuit 18 subtracts the offset value Offset from the output signal from the AD conversion circuit 8, and the digital signal from which the offset has been removed is supplied to the averaging circuit 11 via the correction circuit 9. The bit string of the digital signal representing the offset value Offset corresponds to the least significant bit in the output signal output from the AD conversion circuit 8. Therefore, even if the offset value Offset is subtracted from the output signal from the AD conversion circuit 8 by the arithmetic circuit 18 after the conversion by the AD conversion circuit 8, there is almost no influence on the detection current Isig.

[0118] Next, the state in which the offset value Offset has been removed and averaging is performed will be described with reference to Figure 6 the figure.

[0119] Figure 6 Similar to Figure 5 the figure. The main difference is that in Figure 6 the figure, the clock signals CLK_AD, CLK_DS, and the output signal din of the decoder 16 are omitted, the dispersion current Idac_nf after the offset value Offset has been removed is illustrated by a thin solid line, the averaging area AVA_0 in which the averaging circuit 11 averages all signals at once is illustrated, circles SD_0 indicating the sampling timing and the output code are added, and the threshold value REF_0 and the output code CDE_0 are clearly illustrated.

[0120] By removing the offset value Offset, the dispersion current Idac is shifted downward, that is, shifted to the lower value side, as Figure 6 shown, and becomes the dispersion current Idac_nf. Since the dispersion current Idac_nf has been shifted to the lower value side, the output code CDE_0 smaller than the output code CDE_1 and the threshold value REF_0 for determination are clearly illustrated. By removing the offset value Offset, the black circles SP_0 to SP_7 indicating the sampling timing and the output code as shown in Figure 5 the figure are also shifted to the lower value side and become SP_n0 to SP_n7, as Figure 6 shown.

[0121] The averaging circuit 11 averages the output codes of the black circles SP_n0 to SP_n7 included in one PWM cycle (averaging region) to obtain an average value. The obtained average value is sampled by the decimation circuit 12. In Figure 6 , the output code obtained by sampling by the decimation circuit 12 (the code represented by the output of the decimation circuit 12) is indicated by the circle SD_0.

[0122] <<<Error>>>

[0123] In Figure 5 , the dashed circles SP_00 to SP_07 indicate the sampling times and output codes when only the detected current Isig is converted by the AD conversion circuit 8 without superimposing the scattered current Idac on the detected current Isig. As shown in the reference Figure 13 , during the test, a test current I_tst as a predetermined fixed current is applied to the terminal T1, so the detected current Isig has a constant value. In Figure 5 's example, since the value of the detection signal Isig is lower than the threshold REF_1, the AD conversion circuit 8 outputs this output code CDE_1 as the output code at the sampling timings of the dashed circles SP_00 to SP_07. That is, the AD conversion circuit 8 outputs output codes (CDE_1) of the same value. Therefore, even if the averaging circuit averages these values, these values are the same. In Figure 5 , the dashed circle SD_00 indicates the sampling timing of the decimation circuit 12 and the output code output by the decimation circuit 12. Since this value does not change even when the averaging circuit 11 performs averaging, the output code output by the decimation circuit 12 becomes CDE_1, as shown by the dashed circle SD_00.

[0124] During the test, the output code of the dashed circle SD_00 is output to the tester TST as the detected current Idet via the external terminal T2. As Figure 5 shows, the difference between the dashed circle SD_00 (output code) and the detected current Isig is the error ERR_00, and this error ERR_00 is transmitted to the tester TST.

[0125] However, when the scattered current Idac is superimposed on the detected current Isig as in the first embodiment, the output codes of the black circles SP_n0 to SP_n7 included in the averaging region AVA_0 are scattered, as Figure 6As shown. The averaging circuit 11 determines the average value of the output codes (black circles SP_n0 to SP_n7) included in the averaging region AVA_0, and the downsampling circuit 12 determines the output code (circle SD_0) corresponding to this average value. The difference between the output code of the obtained circle SD_0 and the detection current Isig is the error ERR_0. From Figure 5 and Figure 6 it can be understood that according to the first embodiment, the error in the AD conversion circuit 8 can be reduced.

[0126] That is to say, during the test, a measurement value with reduced error can be obtained while suppressing the increase in cost.

[0127] <<<Comparative Example>>>

[0128] In Figure 5 and Figure 6 an example in which one period of the PWM (=one period of the clock signal CLK_DS) and one period of the dispersion current Idac coincide with each other has been described. As a result, in one PWM period corresponding to one downsampling period, the output codes of one period of the dispersion current Idac can be superimposed on the detection current Isig, thereby improving the averaging effect and reducing the error, as Figure 6 shown.

[0129] However, for example, if one period of the dispersion current Idac corresponds to multiple periods of the PWM, the dispersion of the output codes of the dispersion current Idac will span multiple periods of the PWM. In other words, in one PWM period, the output codes of the dispersion current Idac become biased, and the effect of reducing the error is reduced.

[0130] Figure 7 is a waveform diagram showing a comparative example according to the first embodiment. Figure 7 Similar to Figure 6 . The main difference is that in Figure 7 as shown by the dispersion current Idac, one period of the dispersion current Idac corresponds to two periods of the PWM.

[0131] Furthermore, in Figure 7 the difference from Figure 6 is that AD conversion at two adjacent sampling timings results in output codes with the same value being output from the AD conversion circuit, which is also the difference between Figure 6 and Figure 7 . For example, taking two adjacent black circles SP_n0 and SP_n1 as an example, one period of the dispersion current Idac (the dispersion current Idac_nf after offset removal) is Figure 6twice as long as that in, so the AD conversion circuit 8 samples the scattered current Idac_nf of the same value at the sampling timings of the black circles SP_n0 and SP_n1. In Figure 7 In the example of, since the value obtained at the sampling timing is lower than the threshold REF_0, the values of the output codes indicated by the black circles SP_n0 and SP_n1 are both CDE_0. Similarly, regarding the output codes indicated by the other black circles SP_n2 to SP_n7, the values of the output codes indicated by two adjacent black circles are the same.

[0132] From Figure 7 As can be understood from the black circles SP_n0 to SP_n7 shown, during one PWM cycle, the output code of the scattered current Idac_nf (Idac) just increases (or decreases) and becomes offset. As a result, the output code of the downsampling circuit obtained by averaging the output codes included in the average region AVA_0 and downsampling it has the value of the output code CDE_1, as indicated by the circle SD_0. As a result, the error as the difference between the detected current Isig and the output code CDE_1 indicated by the circle SD_0 becomes large, and the reduction effect decreases.

[0133] To enhance the reduction effect, it is necessary to set the period of the scattered current Idac to an integer fraction of one PWM cycle.

[0134] <<Schematic waveforms during testing>>

[0135] Figures 8A to 8D is a waveform diagram illustrating the operation of the semiconductor device according to the first embodiment during testing. Figure 8A Illustrates Figure 1 the waveform at the output terminal d of the AD conversion circuit 8 shown, and Figure 8B Illustrates Figure 1 the waveform at the output terminal e of the arithmetic circuit 18 shown. In addition, Figure 8C Illustrates Figure 1 the waveform at the output terminal g of the averaging circuit 11 shown, and Figure 8D Illustrates Figure 1 the waveform at the output terminal h of the downsampling circuit 12 shown.

[0136] Figures 8A to 8D Each of those in is similar to Figure 5 and Figure 6 . That is, Figure 8A Illustrates Figure 5 the detected current Isig and the scattered current Idac shown, and also illustrates the black circles SP_1 to SP_7 indicating the sampling timing and the values of the output codes. The scattered current Idac is superimposed on the detected current Isig, and at Figure 8AThe timing of the black circle SP shown samples the detection current with a scattered current superimposed thereon, and converts it into a value of an output code indicated by the black circle SP.

[0137] The arithmetic circuit 18 subtracts the offset value from the digital signal at the output terminal d. As a result, as Figure 8B shown, the black circles SP_n0 to SP_n7 indicating the output code values of the scattered current are shifted downward. In Figure 8B , the waveform Idac_n is formed by connecting the output codes indicated by the black circles SP_n0 to SP_n7, and indicates the waveform of the scattered current generated by removing the offset value after AD conversion.

[0138] Figure 8B The detection current with the scattered current Idac_n superimposed thereon as illustrated in is averaged by the averaging circuit 11 via the correction circuit 9. In Figure 8C , AVA_0 is an averaging area including the black circles SP_n0 to SP_n7. The average of the output codes indicated by the black circles SP_n0 to SP_n7 included in the averaging area AVA_0 is performed by the averaging circuit 11 at the first timing. The average value obtained by averaging at the first timing is indicated by the circle SD_0.

[0139] In addition, in Figure 8C , AVA_1 is an averaging area including the black circles SP_n1 to SP_n0. The average of the output codes indicated by the black circles SP_n1 to SP_n0 included in the averaging area AVA_1 is performed by the averaging circuit 11 at the second timing following the first timing, and the average value obtained by the performance is indicated by the circle SD_1. Further, in Figure 8C , AVA_2 is an averaging area including the black circles SP_n2 to SP_n1. The average of the output codes indicated by the black circles SP_n2 to SP_n1 included in the averaging area AVA_2 is performed by the averaging circuit 11 at the third timing following the second timing, and the average value obtained by the performance is indicated by the circle SD_2.

[0140] As a result of sampling by the decimation circuit 12, the averaging circuit 11 acquires the average value obtained at the first timing (the value indicated by the circle SD_0), as Figure 8D shown. The obtained average value is supplied to the tester TST ( Figure 13 ) via the switch 21 and the external terminal T2. Thereafter, the average value (dashed circle SD_1) obtained at the second timing and the average value (dashed circle SD_2) obtained at the third timing are supplied to the tester TST in this order.

[0141] The tester TST generates correction data C_data using the supplied average value and the like.

[0142] (Second Embodiment)

[0143] In the first embodiment, as Figure 1 shown, the output of the counter 14 for generating the PWM frequency is used to generate a digital output signal din for generating the dispersed current Idac. In the second embodiment, a counter for generating the output signal din is newly added.

[0144] Figure 9 is a block diagram of a semiconductor device according to the second embodiment. Figure 10 is a waveform diagram illustrating the operation of the semiconductor device according to the second embodiment. Figure 9 Only illustrates Figure 1 the components required for the second embodiment in the circuit blocks shown. Figure 1 illustrated in Figure 9 but not illustrated in Figure 1 are the same as the components in

[0145] Figure 1 The frequency generator 13 shown is configured with Figure 1 the oscillation circuit (OSC) 13_1 and the frequency divider circuit (frequency divider) 13_2 in Figure 9 . The oscillation circuit 13_1 generates the above-mentioned clock signal CLK_FS and the clock signal CLK_BC. The clock signal CLK_BC is divided by the frequency divider circuit 13_2 and supplied to the counter 14. In Figure 1 , the output of the counter 14 is supplied to the clock terminal ck of the downsampling circuit 12 as the clock signal CLK_DS. Naturally, similar to

[0146] , the output of the counter 14 can be supplied to the PWM frequency generation circuit 15, and the PWM frequency generation circuit 15 can generate the clock signal CLK_DS.

[0147] Figure 10 Illustrates Figure 9Waveforms of the clock signals CLK_AD, CLK_DS, the output signal din, and the dispersion current Idac shown. By providing the dedicated counter 23 to generate the dispersion current Idac, it becomes possible for the output signal din to have two cycles in one cycle of the clock signal CLK_DS, as Figure 10 shown, and generate the dispersion current Idac having a triangular waveform twice. That is, the period of the dispersion current Idac can be arbitrarily set in one cycle of the clock signal CLK_DS.

[0148] As Figure 5 shown, when sufficient average effect cannot be obtained by using the dispersion current Idac of a single cycle in one PWM cycle, it is possible to increase the number of dispersion periods, and improve the average effect by increasing the period of the dispersion current Idac as in the second embodiment.

[0149] (Third Embodiment)

[0150] In the first embodiment, an example of removing the offset digitally has been illustrated, while in the third embodiment, an example of removing the offset analogously will be illustrated.

[0151] Figure 11 is a block diagram for explaining the semiconductor device according to the third embodiment. Figure 11 Similar to Figure 3 . The main difference is that Figure 11 illustrates a correction circuit 9, an averaging circuit 11, and a downsampling circuit 12 connected to the output terminal d of the AD conversion circuit 8, and illustrates a configuration for removing the offset similarly.

[0152] The configuration for removing the offset is configured analogously by a switch 24 and a constant current source Ioffset connected in series between the drain of the P-type MOS transistor P1 and the ground voltage Vss.

[0153] During the test, the switch 24 enters the conductive state through the test signal Test_en. The constant current source Ioffset is a current source that generates a constant current corresponding to the offset value Offset. When the switch 24 enters the on state, the offset current value included in the dispersion current Idac flows through the constant current source Ioffset. Therefore, offset removal is performed during the test. Further, in the third embodiment, as Figure 1 shown, the arithmetic circuit 18 and the logic circuit 19 are not necessary.

[0154] For example, when the process for manufacturing the semiconductor device 1 is not a fine process, the configuration for removing the offset similarly can suppress an increase in the occupied area. In this case, as described above, the arithmetic circuit 18 and the logic circuit 19 are also unnecessary, thus also suppressing an increase in the occupied area.

[0155] According to the first to third embodiments, since there is no need to install components (active components, passive components, etc.) for generating an AC signal on the test board, it is possible to increase the number of semiconductor devices to be installed during testing. For example, it is possible to increase the number of semiconductor devices to be measured simultaneously. In addition, when generating an AC signal on the test board, delays may occur due to the generation of the AC signal and its supply to the semiconductor device, which can extend the test time. However, in this embodiment, since a dispersion current corresponding to the AC signal is generated and superimposed within the semiconductor device, it is possible to shorten the test time. In addition, although a test design for generating an AC signal on the test board is required, in the first to third embodiments, it is sufficient to supply a fixed current to the semiconductor device during testing, allowing a reduction in the design man-hours related to testing.

[0156] Naturally, it is possible to provide a high-resolution semiconductor device without installing a high-resolution AD conversion circuit on the semiconductor device; thus, it is possible to reduce the chip cost.

[0157] In Figure 1 In the semiconductor device 1 shown, the arithmetic circuit 18 can be regarded as an offset removal circuit that removes the offset value Offset. Additionally, the current generation circuit can be considered to be composed of the counter 14 or 23, the decoder 16, and the DA conversion circuit 17.

[0158] When considered in this way, in the test step of step S3 shown in FIG. 12, the following process can be considered to be being carried out.

[0159] The current generation circuit (DA conversion circuit 17) generates a second signal (dispersion current Idac) of the first period (1 / Fpwm).

[0160] The second signal is superimposed on the detection current (Isig: first signal) from the current detection circuit 7 at the first node ( Figure 1 N_cnt in) to generate a third signal.

[0161] The third signal is converted into a digital fourth signal by the AD conversion circuit 8, and the offset generated by superimposing the second signal on the first signal is removed from the fourth signal by the offset removal circuit to generate a fifth signal.

[0162] The generated fifth signal is averaged by the average filter (average circuit 11) to generate a sixth signal. The generated sixth signal is downsampled by the downsampler (downsampling circuit 12) and thinned into data having a period that is an integer fraction of one period to generate a seventh signal.

[0163] During the test process, the seventh signal is output from the semiconductor device 1 to the tester TST( Figure 13 ), where correction data C_data is generated in the tester TST. Above, the invention made by the inventors of the present application has been specifically described based on the embodiments. However, needless to say, the present invention is not limited to the foregoing embodiments, and various modifications and changes can be made within the scope of the present invention.

Claims

1. A semiconductor device, comprising: First terminal; an oscillator circuit that generates a first clock signal and a second clock signal, the second clock signal having a frequency that is an integer fraction of the first clock signal; an AD conversion circuit that oversamples a detection current corresponding to the current flowing through the first terminal according to the first clock signal and converts the detection current into a digital signal; a correction circuit that corrects the digital signal obtained by the AD conversion circuit based on correction data stored in the storage circuit and outputs the digital signal; an averaging circuit that operates according to the first clock signal and averages the digital signal output from the correction circuit; a sampling circuit for down-sampling the digital signal averaged by the averaging circuit according to the second clock signal; a current generating circuit that generates a current based on an output of the sampling circuit and target current data, and supplies the current to the first terminal; as well as a superposition circuit that superimposes the dispersion current on the detection current when generating the correction data, wherein the correction data is generated based on the output of the sampling circuit when the dispersion current is superimposed on the detection current, and the correction data is stored in the storage circuit.

2. The semiconductor device according to claim 1, further comprising: a second terminal for outputting the output of the sampling circuit to the outside of the semiconductor device when the dispersion current is superimposed on the detection current; as well as a third terminal provided outside the semiconductor device and to which the correction data generated based on the output of the sampling circuit output from the second terminal is supplied, The correction data supplied to the third terminal is written into the storage circuit.

3. The semiconductor device according to claim 2, further comprising: A DA conversion circuit generates the dispersion current, The DA conversion circuit generates the dispersion current which changes periodically.

4. The semiconductor device according to claim 3, further comprising: a current detection circuit connected to the first terminal and outputting a detection current corresponding to a current flowing through the first terminal; as well as an operation circuit connected between the AD conversion circuit and the correction circuit, Wherein, when the correction data is generated, a predetermined current is supplied to the first terminal, the current detection circuit outputs the detection current corresponding to the predetermined current, a digital signal corresponding to the detection current superimposed with the dispersion current and a digital signal corresponding to the offset caused by superimposing the dispersion current are supplied to the operation circuit, and the operation circuit subtracts the digital signal corresponding to the offset from the digital signal corresponding to the detection current superimposed with the dispersion current.

5. A method for manufacturing a semiconductor device, comprising the following steps: (a), preparing a semiconductor substrate; (b) forming a plurality of circuits, the plurality of circuits including a first circuit that outputs a first signal corresponding to target current data via a first terminal on a surface of the semiconductor substrate; as well as (c), calibrating the first circuit, The first circuit comprises A current sensing circuit is connected to the first terminal, The AD conversion circuit is connected to the current detection circuit, A correction circuit is connected to the AD conversion circuit, an averaging filter, connected to the correction circuit, and The downsampler, connected to the averaging filter, The plurality of circuits further include An offset removal circuit is connected to the AD conversion circuit, and a current generating circuit connected to a first node connecting the current detecting circuit and the AD conversion circuit, and Wherein said step (c) comprises the following steps (c1) superimposing a second signal having a first period generated by the current generating circuit on the first signal at the first node to generate a third signal, (c2), after step (c1), converting the third signal as an analog signal into a digital signal in the AD conversion circuit to generate a fourth signal, (c3) after step (c2), removing an offset caused by superimposing the second signal included in the fourth signal on the first signal using the offset removal circuit to generate a fifth signal, (c4), after step (c3), averaging the fifth signal using the averaging filter to generate a sixth signal, (c5), after step (c4), using the downsampler to thin out the data at a period that is an integer fraction of the first period to generate a seventh signal, and (c6) After step (c5), output the seventh signal to the outside.

6. The method for manufacturing a semiconductor device according to claim 5, The second signal is a signal having a triangular waveform.

7. The method for manufacturing a semiconductor device according to claim 6, The current generating circuit comprises: counter, decoder, is connected to the counter, and DA conversion circuit, is connected to the decoder, and The DA conversion circuit includes a current mirror circuit, and the current mirror circuit includes a switch turned on / off by the output of the decoder.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the counter is the same as the counter used to obtain a period that is an integer fraction of the first period.

9. The method for manufacturing a semiconductor device according to claim 5, The seventh signal output in the step (c6) is supplied to an externally provided tester, and the tester generates correction data to be used for the correction circuit.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the plurality of circuits include a storage circuit connected to the correction circuit, and wherein the storage circuit stores the correction data generated by the tester, and the correction circuit performs correction based on the correction data stored in the storage circuit.

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