Band-pass analog-to-digital converter based on time domain interleaving noise shaping successive approximation type architecture

Abstract

The invention discloses a band-pass analog-to-digital converter based on a time domain interleaving noise shaping successive approximation type architecture. The band-pass analog-to-digital converter comprises a front-end clock frequency divider, at least two parallel SARADC channels, a noise shaping module and a parallel-serial conversion output module, the front-end clock frequency divider is used for generating at least two paths of clock signals which are sequentially staggered with fixed phases to control the channel to work; the SARADC channel comprises a sampling hold circuit, a CDAC capacitor array, a dynamic comparator and SAR logic, the sampling hold circuit collects an input differential signal to the CDAC capacitor array to obtain a differential residual voltage, and the dynamic comparator takes the differential residual voltage of the current system period and integral voltages before three system periods as input; the output comparison result is the output of the current channel period of the SARADC channel, and meanwhile, the comparison result is fed back to the CDAC capacitor array through SAR logic to control the CDAC capacitor array to overturn; and the noise shaping module takes the differential residual voltage of the current system period as input, outputs integral voltage and sends the integral voltage to the dynamic comparators after the three system periods.

Description

Technical Field

[0001] The present invention relates to the technical fields of communication and analog-to-digital converters, and particularly relates to a band-pass analog-to-digital converter based on a time-interleaved noise shaping successive approximation architecture. Background Art

[0002] Band-pass analog-to-digital converters can directly process intermediate frequency signals and are widely used in communication systems. For example, in software-defined radio technology, high-precision band-pass analog-to-digital converters are usually required to complete the quantization processing of input signals.

[0003] Band-pass noise shaping SAR (Successive Approximation Register) ADCs have received attention due to their high energy efficiency advantages. Time-interleaved technology is applied to band-pass noise shaping SAR ADCs to improve the system sampling rate. Currently, the existing two-channel time-interleaved band-pass noise shaping SAR ADCs have achieved an increase in the system sampling rate, but their drawback is that they face serious inter-channel mismatch problems, thus limiting the system accuracy. In time-interleaved technology, there are mainly two types of inter-channel mismatches:

[0004] 1. Offset mismatch, whose position is at

[0005]

[0006] 2. Sampling time mismatch and gain mismatch, whose position is at

[0007]

[0008] Among them, f s is the system sampling frequency, M is the number of channels, and f in is the input signal frequency.

[0009] For a two-channel time-interleaved band-pass ADC, if the system center frequency, i.e., the input signal frequency, is f in = f s / 4, then in the first Nyquist zone, its offset mismatch is located at f mis1 = f s / 2, and its sampling time mismatch and gain mismatch are located at . This means that the spectra of the sampling time mismatch and gain mismatch overlap with the input signal spectrum, that is, the harmonics fall into the passband, which will cause a decrease in the system accuracy, as shown in Figure 1 . Summary of the Invention

[0010] In view of the problem that the inter-channel mismatch in the system in the above-mentioned prior art causes a serious decrease in system accuracy, the present invention proposes a bandpass analog-to-digital converter based on a time-domain interleaved noise shaping successive approximation architecture, which can convert an intermediate frequency analog input signal into a digital signal with higher accuracy and speed, thereby fundamentally solving the problem of decreased accuracy caused by inter-channel mismatch.

[0011] A bandpass analog-to-digital converter based on a time-domain interleaved noise shaping successive approximation architecture comprises: a front-end clock divider, at least two parallel SARADC channels, a noise shaping module and a parallel-to-serial conversion output module; the front-end clock divider is used to generate at least two clock signals with fixed phases staggered in sequence, respectively controlling the at least two parallel SARADC channels to work; the SARADC channel comprises a sampling and holding circuit, a CDAC capacitor array, a dynamic comparator and a SAR logic, wherein the sampling and holding circuit samples an input differential signal to the CDAC capacitor array to obtain a differential residual voltage, and the dynamic comparator obtains a differential residual voltage. The dynamic comparator takes the differential residual voltage of the current system cycle and the integrated voltage three system cycles ago as inputs, outputs a comparison result as the output of the SARADC channel in the current channel cycle, and at the same time, the comparison result is fed back to the CDAC capacitor array through the SAR logic to control the flipping of the CDAC capacitor array; the noise shaping module is connected to the CDAC capacitor array of the SARADC channel and the dynamic comparator, and is used to: take the differential residual voltage of the current system cycle as input, output an integrated voltage, and send the integrated voltage to the dynamic comparator three system cycles later for quantization.

[0012] Furthermore, the fixed phase is T s,ch / M, where T s,ch is a channel cycle of the SARADC channel, and M is the number of SARADC channels.

[0013] Furthermore, the sampling and holding circuit includes a first S / H sampling and holding circuit and a second S / H sampling and holding circuit, which are respectively used to sample the positive and negative signals of the input differential signal; the CDAC capacitor array includes a first CDAC capacitor array and a second CDAC capacitor array, which are respectively connected to the first S / H sampling and holding circuit and the second S / H sampling and holding circuit to receive the positive and negative sampled differential signals.

[0014] Furthermore, the process by which the dynamic comparator performs comparison on its input includes: summing the positive-terminal residual voltage of the differential residual voltage in the current system cycle with the positive-terminal signal of the integration voltage three system cycles ago to obtain the positive-terminal sum; and summing the negative-terminal residual voltage of the differential residual voltage in the current system cycle with the negative-terminal signal of the integration voltage three system cycles ago to obtain the negative-terminal sum; and comparing the positive-terminal sum with the negative-terminal sum and outputting the comparison result.

[0015] Furthermore, the system transfer function of the band-pass analog-to-digital converter is

[0016] Y out (z) = V in (z) + (1 - a * z -3 )E(z)

[0017] where V in (z), Y out (z) are the system input and output respectively, E(z) is the system quantization noise, a is a coefficient greater than 0 and less than or equal to 1, and z -3 represents a delay of three system cycles.

[0018] Furthermore, the system noise transfer coefficient of the band-pass analog-to-digital converter is

[0019] NTF = (1 - a * z -3 )

[0020] where the positions of the three notches of the system noise transfer coefficient are distributed as follows: one notch is at direct current, and the other two notches are at F s / 3, where F s is the sampling frequency of the system;

[0021] Select F s / 3 as the frequency F in of the system input signal, that is, F in = F s / 3.

[0022] Furthermore, when the system center frequency, that is, the frequency of the system input signal, is F s / 3, then in the first Nyquist zone, the system offset mismatch is at f mis1 = F s / 2, and the sampling time mismatch and gain mismatch are at f mis2 = -F in + F s / 2 = -F s / 3 + F s / 2 = F s / 6, which does not overlap with the system center frequency. Therefore, the inter-channel mismatch does not affect the system accuracy.

[0023] Further, within one channel period T s,ch it includes three stages, which are respectively:

[0024] The 1st stage, sample and hold, is implemented by the sample and hold circuit;

[0025] The 2nd stage, SAR conversion i.e., quantization stage, is jointly implemented by the CDAC capacitor array, the dynamic comparator and the SAR logic;

[0026] The 3rd stage, integration stage, is implemented by the noise shaping module.

[0027] Further, the noise shaping module includes three groups of feedback paths, denoted as feedback path 1, feedback path 2 and feedback path 3 respectively; the at least two parallel SAR ADC channels are respectively denoted as channel 1, channel 2, …, channel M;

[0028] When M = 2, the working process of the band-pass analog-to-digital converter includes: First, channel 1 samples, samples the input differential signal onto the CDAC capacitor array, and then enters the quantization stage; after quantization, channel 1 performs charge sharing between the differential residual voltage output by the CDAC capacitor array and the feedback capacitor of feedback path 1 through feedback path 1 to implement the integration process and obtain the integration voltage. Thus, channel 1 completes one channel period T s,ch ; when channel 1 works for half of a channel period, channel 2 samples, also samples the input differential signal at this time onto the CDAC capacitor array, and then performs the quantization stage and the integration stage; the integration voltages generated after channel 1 and channel 2 complete their respective each channel period T s,ch are all sent to the corresponding channels three system periods later through the corresponding feedback paths to participate in quantization, realizing the z -3 delay of the integration voltage;

[0029] When M = 3, the working process of the band-pass analog-to-digital converter includes: First, channel 1 samples, samples the input differential signal onto the CDAC capacitor array, and then enters the quantization stage; after quantization, channel 1 sends the differential residual voltage output by the CDAC capacitor array to the noise shaping module through feedback path 1 to implement the integration process and obtain the integration voltage. Thus, channel 1 completes one channel period T s,ch ; since M = 3, it is three-channel time-domain interleaving, and the channel three system periods later is still this channel. Therefore, the integration voltage is sent to this channel three system periods later to participate in quantization, and there is no coupling of the integration voltage between different channels; the working processes of channel 2 and channel 3 are the same as that of channel 1, and the working time sequence is delayed by T s,ch / 3; therefore, the M = 3 channels also realize the z of the integration voltage-3 Delay

[0030] Furthermore, the parallel-to-serial conversion output module is configured to perform parallel-to-serial conversion on the outputs of the at least two parallel SAR ADC channels to obtain the final system output of the bandpass analog-to-digital converter.

[0031] The beneficial effects of the technical solution of the present invention are as follows: The bandpass analog-to-digital converter based on the time-interleaved noise shaping successive approximation architecture proposed by the present invention, through the collaborative work of the integral processing of the noise shaping module and the quantization stage of the SAR ADC channels, integrates the differential residual voltage of the current system cycle and sends it to the dynamic comparator of the corresponding channel three system cycles later to participate in quantization, so that the center frequency of the system is located at F s / 3, and its gain mismatch and sampling time mismatch fall to F s / 6, and the system offset mismatch falls to F s / 2. When the passband bandwidth ≤ F s / 6, these mismatch tones are significantly outside the passband, fundamentally solving the problem of serious degradation of the system accuracy caused by inter-channel mismatch.

[0032] In addition, during the process of transferring the notch position of the system noise transfer coefficient (NTF) from DC (direct current) to IF (intermediate frequency), a notch position at F s / 3 is innovatively proposed. Compared with the traditional F s / 4, a higher intermediate frequency is achieved from the system architecture level. The time-interleaving of the noise shaping SAR ADC is realized without using the midway feedback technology, so there will be no overload effect, thereby reducing the system redundant bits and expanding the system bandwidth. Description of the Drawings

[0033] Figure 1 is a schematic diagram of the limitation of system accuracy by inter-channel mismatch in the prior art.

[0034] Figure 2 is a system architecture diagram of the bandpass analog-to-digital converter based on the time-interleaved noise shaping successive approximation architecture according to an embodiment of the present invention.

[0035] Figure 3 is a working schematic diagram of the two-channel time-interleaved noise shaping successive approximation architecture bandpass analog-to-digital converter according to Embodiment 1 of the present invention.

[0036] Figure 4 is a working schematic diagram of the three-channel time-interleaved noise shaping successive approximation architecture bandpass analog-to-digital converter according to Embodiment 2 of the present invention.

[0037] Figure 5 is a schematic diagram of the inter-channel mismatch not affecting the system accuracy of the present invention. Detailed Embodiments

[0038] The present invention will be further described below in conjunction with the accompanying drawings and specific implementation methods and examples. It should be noted that the purpose of providing the examples is only to illustrate, not to limit.

[0039] The specific embodiment of the present invention proposes a bandpass analog-to-digital converter based on a time-domain interleaved noise shaping successive approximation architecture, referring to Figure 2 The bandpass analog-to-digital converter includes: a front-end clock divider, at least two parallel SARADC channels (such as Figure 2 The channel shown in <1> ,aisle <2> ), a noise shaping module and a parallel-to-serial conversion output module P2S. The front-end clock divider Divider is used to generate at least two clock signals with fixed phases staggered in sequence, and respectively control the at least two parallel SARADC channels to work, for example Figure 2 As shown in the figure, the front-end clock divider Divider generates two clock signals CLK1 and CLK2 to control the channels respectively. <1> and Channel <2> Since the internal structure of the parallel SARADC channels is the same, for simplicity, Figure 2 Only channels are shown <1> The internal structure of Figure 2 The two SAR ADC channels in the embodiment are only exemplary. The number of parallel SAR ADC channels in the bandpass analog-to-digital converter of the present invention can be more than 2; accordingly, the front-end clock divider Divider generates a corresponding number of clock signals. For example, when M parallel SAR ADC channels are included, the front-end clock divider Divider generates M clock signals, and the M clock signals are staggered with a fixed phase T in sequence. s,ch / M, where T s,ch It is one channel cycle of SARADC channel.

[0040] Continue to refer Figure 2, taking channel <1> as an example, the SARADC channel includes an S / H sample-and-hold circuit, a CDAC capacitor array, a dynamic comparator, and SAR logic. Since the input is a differential signal, there are two S / H sample-and-hold circuits to receive a pair of input differential signals VIP and VIN. Correspondingly, there are also two CDAC capacitor arrays CDACP and CDACN to receive the sampled differential signals respectively. Among them, the S / H sample-and-hold circuit samples the input differential signals VIP and VIN into CDACP and CDACN respectively, obtaining a differential residual voltage (including a positive-terminal residual voltage and a negative-terminal residual voltage). The obtained differential residual voltage is sent to the dynamic comparator on the one hand and to the noise shaping module on the other hand. After the differential residual voltage is sent to the noise shaping module, the corresponding integral voltage is obtained; the integral voltage is then delayed for three system cycles and sent to the dynamic comparator to participate in quantization, thus realizing the z -3 delay. It can be seen that in the input of the dynamic comparator in the current system cycle, on the one hand, it includes two signals of the differential residual voltage output by the CDAC capacitor array in the current system cycle, and on the other hand, it also includes two signals of the integral voltage from three system cycles ago (reaching the current system cycle after being delayed for three system cycles), a total of four signals. The working principle of the dynamic comparator is: sum the positive-terminal residual voltage of the differential residual voltage in the current system cycle and the positive-terminal signal of the integral voltage from three system cycles ago to obtain the positive-terminal sum, and at the same time sum the negative-terminal residual voltage of the differential residual voltage in the current system cycle and the negative-terminal signal of the integral voltage from three system cycles ago to obtain the negative-terminal sum, and then compare the "positive-terminal sum" with the "negative-terminal sum", and the output comparison result is used as the output of the SARADC channel in the current channel cycle. At the same time, this comparison result is also fed back to the CDAC capacitor array through the SAR logic to control the flip of the CDAC capacitor array.

[0041] The parallel-to-serial conversion output module P2S is used to perform parallel-to-serial conversion on the outputs of the at least two parallel SARADC channels to obtain the final output Dout of the band-pass analog-to-digital converter.

[0042] In some specific embodiments, the noise shaping module includes three groups of feedback paths, denoted as feedback path 1, feedback path 2, and feedback path 3. Each group of feedback paths is composed of feedback capacitors, which will not be elaborated here. In Figure 3 and Figure 4 the example, feedback paths 1, 2, and 3 are respectively represented by red arrows, blue arrows, and green arrows. The at least two parallel SARADC channels are respectively denoted as channel 1, channel 2,..., channel M. Each channel includes the following three working stages within its respective one channel cycle:

[0043] The first stage, sample and hold, is realized through the sample-and-hold circuit;

[0044] The second stage, SAR conversion or quantization stage, is realized by the CDAC capacitor array, the dynamic comparator and the SAR logic in coordination;

[0045] The third stage, the integration stage, is implemented by the noise shaping module.

[0046] The working principle of the bandpass analog-to-digital converter of the present invention is described in detail below by taking 2-channel and 3-channel time-domain interleaved noise shaping SAR as examples.

[0047] Embodiment 1:

[0048] The passband analog-to-digital converter of this embodiment includes two parallel SARADC channels. Figure 3 , denoted as channel 1 (CH1) and channel 2 (CH2). The channel cycle length of each channel is the same, denoted as T s,ch , phase shift T s,ch / 2, system period T s =T s,ch / 2. The working principle of the bandpass analog-to-digital converter of this embodiment is:

[0049] First, channel 1 (CH1) is sampled (expressed as S / H). After the input differential signal is sampled onto the CDAC capacitor array, it enters the quantization stage (expressed as Conversion). Quantization is completed by the CDAC, dynamic comparator and SAR logic, which is a common working stage of SARADC and will not be described here. After quantization, channel 1 is fed back through feedback path 1 ( Figure 3 The differential residual voltage output by the CDAC capacitor array is shared with the feedback capacitor of feedback path 1 (red arrow in the middle), and the integration process is realized (CS represents the integration stage), and the integrated voltage is obtained. At this point, channel 1 completes a channel cycle T s,ch (a purple dotted box). When channel 1 works for half a channel cycle, channel 2 (CH2) starts working. Similarly, sampling is performed first, and the input differential signal at this time is sampled onto the CDAC capacitor array, followed by the quantization stage and the integration stage. Channel 1 and channel 2 complete each channel cycle T s,ch The integral voltage generated after the operation is sent to the corresponding channel after three system cycles through the corresponding feedback path to participate in quantization, thus achieving the integral voltage z -3 For example, after channel 1 completes the first channel cycle, the resulting integrated voltage is sent to the three T s The subsequent channel 2 participates in quantization, achieving the z value of the integrated voltage -3 After channel 2 completes its first channel cycle, the resulting integrated voltage is sent to the three T sThe subsequent Channel 1 participates in quantization. After Channel 1 completes its second channel cycle, the resulting integrated voltage is sent to three Ts through feedback path 3 (green). s The subsequent Channel 2 participates in quantization. After Channel 2 completes its second channel cycle, the resulting integrated voltage is sent to three Ts through feedback path 1 (red). s The subsequent Channel 1 participates in quantization. And so on, the three groups of feedback paths take turns to participate in the work, thus realizing a band-pass filter. In this way, the transfer function of the system is:

[0050] Y out (z) = V in (z) + (1 - *z -3 )E(z) (1)

[0051] Where, V in (z), Y out (z) are the system input and output respectively, and E(z) is the system quantization noise; a is a coefficient greater than 0 and less than or equal to 1, and the specific value is jointly determined by the ratio of the feedback capacitance to the CDAC capacitance and the gain provided by the noise shaping module. z -3 represents a delay of three system cycles.

[0052] According to Equation (1), the system noise transfer coefficient NTF of the band-pass analog-to-digital converter in the embodiment of the present invention is:

[0053] NTF = (1 - a*z -3 ) (2)

[0054] The position distribution of its three notches is: one notch is at direct current (DC), and the other two notches are located at F s / 3, where F s is the sampling frequency of the system. Therefore, the noise suppression effect is good at F s / 3, and F s / 3 is selected as the system input signal frequency F in , that is

[0055] F in = F s / 3 (3)

[0056] Refer to Figure 5 , when the system center frequency (i.e., the input signal frequency) is F s / 3, then in the first Nyquist zone, the system offset mismatch is located at f mis1 = F s / 2, and the sampling time mismatch and gain mismatch are located at f mis2 = -F in + F s / 2 = -F s / 3 + F s / 2=F s / 6, and the system center frequency F s / 3 do not overlap, so mismatch between channels does not affect system accuracy.

[0057] Embodiment 2:

[0058] The passband analog-to-digital converter of this embodiment includes three parallel SARADC channels. Figure 4 , denoted as channel 1 (CH1), channel 2 (CH2) and channel 3 (CH3). The channel cycle length of each channel is the same, denoted as T s,ch , phase shift T s,ch / 3, system period T s =T s,ch / 3. The working principle of the bandpass analog-to-digital converter of this embodiment is:

[0059] First, channel 1 samples and samples the input differential signal onto the CDAC capacitor array, and then enters the quantization stage. After quantization, channel 1 sends the differential residual voltage output by the CDAC capacitor array to the noise shaping module through feedback path 1 to implement the integration process and obtain the integrated voltage. At this point, channel 1 completes a channel cycle T s,ch ; Since M = 3, it is a three-channel time domain interleaving, and the channel after three system cycles of delay is still the current channel, so the integrated voltage is sent to the current channel after three system cycles to participate in quantization, and there is no coupling of integrated voltages between different channels; the working process of channel 2 and channel 3 is the same as that of channel 1, and the working sequence is delayed by T s,ch / 3; it can be seen that the M = 3 channel also achieves the z of the integrated voltage -3 Delay realizes the same system transfer function and thus the same function.

[0060] The system center frequency of the traditional two-channel time-domain interleaved noise-shaping SAR bandpass ADC is located at F s / 4, however, in the design of two-channel time-domain interleaving, the mismatch between channels (including gain mismatch and sampling time mismatch, etc.) just falls back to F s / 4, it will inevitably overlap with the passband, causing a significant reduction in SFDR, which becomes a bottleneck in system accuracy.

[0061] The bandpass analog-to-digital converter is divided into a signal path and a noise path. In order to restore the signal losslessly, the gain of the signal path is preferably one, and in order to achieve the bandpass shaping effect, the transfer function of the noise path needs to be constructed in a bandpass form. The present invention is based on the design of a bandpass analog-to-digital converter with a time-domain interleaved noise shaping successive approximation architecture, and realizes the noise transfer coefficient NTF = (1-a*z -3 ), a reasonable notch position is constructed so that the center frequency of the system is located at F sAt the position of / 3, the gain mismatch and sampling time mismatch fall to F s At / 6, the system offset mismatch falls to F s At / 2, the inter-channel mismatch caused by time-domain interleaving is shifted outside the passband, fundamentally solving the problem of serious degradation of system accuracy caused by the overlap between the inter-channel mismatch (including gain mismatch and sampling time mismatch, etc.) and the passband when there are more than two channels in time-domain interleaving.

[0062] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those skilled in the technical field to which the present invention belongs, without departing from the concept of the present invention, several equivalent substitutions or obvious modifications can be made, and if the performance or use is the same, they should all be regarded as belonging to the protection scope of the present invention.

Claims

1. A bandpass analog-to-digital converter based on a time-domain interleaved noise shaping successive approximation architecture, characterized in that: include: Front-end clock divider, at least two parallel SARADC channels, noise shaping module and parallel-to-serial conversion output module; The front-end clock divider is used to generate at least two clock signals with fixed phases staggered in sequence, and respectively control the at least two parallel SARADC channels to work; The SARADC channel comprises a sampling and holding circuit, a CDAC capacitor array, a dynamic comparator and a SAR logic, wherein the sampling and holding circuit samples the input differential signal to the CDAC capacitor array to obtain a differential residual voltage, the dynamic comparator takes the differential residual voltage of the current system cycle and the integrated voltage three system cycles ago as input, and outputs a comparison result as the output of the SARADC channel in the current channel cycle, and the comparison result is fed back to the CDAC capacitor array through the SAR logic to control the flipping of the CDAC capacitor array; The noise shaping module is connected to the CDAC capacitor array and the dynamic comparator of the SARADC channel, and is used to: take the differential residual voltage of the current system cycle as input, output an integrated voltage, and send the integrated voltage to the dynamic comparator after three system cycles for quantization.

2. The bandpass analog-to-digital converter according to claim 1, wherein: The fixed phase is T s,ch / M, where T s,ch is a channel cycle of the SARADC channel, and M is the number of SARADC channels.

3. The bandpass analog-to-digital converter according to claim 1 or 2, characterized in that: The sampling and holding circuit includes a first S / H sampling and holding circuit and a second S / H sampling and holding circuit, which are respectively used to sample the positive and negative signals of the input differential signal; the CDAC capacitor array includes a first CDAC capacitor array and a second CDAC capacitor array, which are respectively connected to the first S / H sampling and holding circuit and the second S / H sampling and holding circuit to receive the positive and negative sampled differential signals.

4. The bandpass analog-to-digital converter according to claim 1 or 2, characterized in that: The process of the dynamic comparator performing comparison on its input includes: summing the positive end residual voltage of the differential residual voltage of the current system cycle with the positive end signal of the integrated voltage three system cycles ago to obtain the positive end sum; and summing the negative end residual voltage of the differential residual voltage of the current system cycle with the negative end signal of the integrated voltage three system cycles ago to obtain the negative end sum; and comparing the positive end sum with the negative end sum, and outputting the comparison result.

5. The bandpass analog-to-digital converter according to claim 2, characterized in that: The system transfer function of the bandpass analog-to-digital converter is Y out (from)=in in (z)+(1-a*z -3 )E(z) Among them, V in (z), Y out (z) are the system input and output, E(z) is the system quantization noise, a is a coefficient greater than 0 and less than or equal to 1, z -3 Indicates a delay of three system cycles.

6. The bandpass analog-to-digital converter according to claim 5, characterized in that: The system noise transfer coefficient of the bandpass analog-to-digital converter is NTF=(1-a*z -3 ) Among them, the positions of the three notches of the system noise transfer coefficient are distributed as follows: one notch is at DC, and the other two notches are located at F s / 3, where F s is the sampling frequency of the system; Select F s / 3 is initially used as the frequency F of the system input signal in , that is, F in =F s / 3.

7. The bandpass analog-to-digital converter according to claim 6, characterized in that: When the system center frequency, i.e. the frequency of the system input signal, is F s / 3, then in the first Nyquist zone, the system offset mismatch is located at f mis1 =F s / 2, the sampling time mismatch and gain mismatch are located at f mis2 =-F in +F s / 2=-F s / 3+F s / 2=F s / 6, which does not overlap with the system center frequency, so the mismatch between channels does not affect the system accuracy.

8. The bandpass analog-to-digital converter according to claim 6, characterized in that: In a channel cycle T s,ch It includes three stages: The first stage, sampling and holding, is implemented by the sampling and holding circuit; The second stage, SAR conversion or quantization stage, is realized by the CDAC capacitor array, the dynamic comparator and the SAR logic in coordination; The third stage, the integration stage, is implemented by the noise shaping module.

9. The bandpass analog-to-digital converter according to claim 8, characterized in that: The noise shaping module comprises three groups of feedback paths, which are respectively recorded as feedback path 1, feedback path 2 and feedback path 3; the at least two parallel SARADC channels are respectively recorded as channel 1, channel 2, ..., channel M; When M=2, the working process of the bandpass analog-to-digital converter includes: first, channel 1 performs sampling, and after sampling the input differential signal onto the CDAC capacitor array, enters the quantization stage; after completing quantization, channel 1 performs charge sharing between the differential residual voltage output by the CDAC capacitor array and the feedback capacitor of the feedback path 1 through the feedback path 1, realizes the integration process, and obtains the integrated voltage. At this point, channel 1 completes a channel cycle T s,ch ; When channel 1 works for half a channel cycle, channel 2 is sampled, and the input differential signal is sampled to the CDAC capacitor array, followed by the quantization stage and the integration stage; channel 1 and channel 2 complete each channel cycle T s,ch The integral voltage generated after the operation is sent to the corresponding channel after three system cycles through the corresponding feedback path to participate in quantization, thus achieving the integral voltage z -3 Delay; When M=3, the working process of the bandpass analog-to-digital converter includes: first, channel 1 performs sampling, and after sampling the input differential signal onto the CDAC capacitor array, enters the quantization stage; after completing the quantization, channel 1 sends the differential residual voltage output by the CDAC capacitor array to the noise shaping module through feedback path 1 to implement the integration process and obtain the integrated voltage. At this point, channel 1 completes a channel cycle T s,ch ; Since M = 3, it is a three-channel time domain interleaving, and the channel after three system cycles of delay is still the current channel, so the integrated voltage is sent to the current channel after three system cycles to participate in quantization, and there is no coupling of integrated voltages between different channels; the working process of channel 2 and channel 3 is the same as that of channel 1, and the working sequence is delayed by T s,ch / 3; therefore, M = 3 channels also achieve the z of the integrated voltage -3 Delay.

10. The bandpass analog-to-digital converter according to any one of claims 1 to 9, characterized in that: The parallel-to-serial conversion output module is used to perform parallel-to-serial conversion on the outputs of the at least two parallel SARADC channels to obtain the final system output of the bandpass analog-to-digital converter.

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