Continuous time pipeline analog-to-digital converter based on open-loop operational amplifier

Abstract

The invention discloses a continuous time pipeline analog-to-digital converter based on an open-loop operational amplifier. The continuous time pipeline analog-to-digital converter comprises at least two stages of pipelines and a post-stage quantization unit, each stage of assembly line comprises a delay network, a quantization unit and a residual error processing unit, wherein the delay network and the quantization unit form two parallel input processing paths; the residual processing unit comprises a passive RC network and an open-loop operational amplifier, the passive RC network is used for performing low-pass filtering on a residual signal obtained by subtracting the output of the time delay unit from the output of the quantization unit, and the open-loop operational amplifier is used for amplifying the residual signal subjected to low-pass filtering to obtain pipeline output; wherein the open-loop operational amplifier adopts a transconductance constant structure to ensure the stability of inter-stage gain; and the rear-stage quantization unit is connected to the output end of the last-stage assembly line and is used for performing final quantization processing on the output of the last-stage assembly line.

Description

Technical Field

[0001] The present invention relates to the technical fields of communication and analog-to-digital converters, and particularly relates to a continuous-time pipelined analog-to-digital converter based on an open-loop operational amplifier. Background Art

[0002] With the rapid development of communication technologies, the requirements for high-speed and high-precision analog-to-digital converters are also constantly increasing. On the basis of maintaining the pipelined structure that takes into account both speed and accuracy, the continuous-time pipelined ADC (analog-to-digital converter) removes the front-end sample-and-hold circuit, making its external input a resistive load that is easy to drive and not limited by the settling time. Therefore, it has important research significance.

[0003] Figure 1 Shown in Figure 1 is a typical architecture of a three-stage continuous-time pipelined ADC. The first two stages are both composed of a delay network, active filtering, Flash ADC (flash analog-to-digital converter), and RDAC (resistive digital-to-analog converter). The last stage is a quantization unit (such as a four-channel ASAR ADC (successive approximation asynchronous sampling ADC) structure) that can meet the system accuracy requirements. Among them, the active filtering part generally uses a structure based on a closed-loop operational amplifier to achieve a second-order low-pass filtering effect while ensuring a stable inter-stage gain. The common structure is in the form of MFB (Multiple Feedback, multi-terminal negative feedback circuit), as shown in Figure 1 In a continuous-time pipelined ADC, the design requirements for the closed-loop operational amplifier in the active low-pass are relatively high, mainly reflected in the gain-bandwidth product (GBW). In order to meet the requirements of speed and accuracy, a closed-loop operational amplifier usually needs to have a large GBW. However, when the GBW is large, the circuit design of the closed-loop operational amplifier is difficult and the power consumption is high. Summary of the Invention

[0004] In view of this, the present invention proposes a continuous-time pipelined analog-to-digital converter based on an open-loop operational amplifier, and solves the technical problems of difficult circuit design and high power consumption when the existing continuous-time pipelined ADC has a large GBW by introducing a structure combining an open-loop operational amplifier and a passive RC network.

[0005] To solve the above technical problems, the present invention proposes the following technical solutions:

[0006] A continuous-time pipelined analog-to-digital converter based on an open-loop operational amplifier, comprising: at least two stages of pipelines and a post-stage quantization unit; each stage of the pipeline includes a delay network, a quantization unit, and a residue processing unit, wherein the delay network and the quantization unit form two parallel input processing paths; the residue processing unit includes a passive RC network and an open-loop operational amplifier, the passive RC network is used for low-pass filtering the residue signal obtained by subtracting the output of the delay unit from the output of the quantization unit, and the open-loop operational amplifier is used for amplifying the residue signal after low-pass filtering to obtain the pipeline output; wherein, the open-loop operational amplifier adopts a constant transconductance structure to ensure the stability of the inter-stage gain; the post-stage quantization unit is connected to the output end of the last stage of the pipeline and is used for performing final quantization processing on the output of the last stage of the pipeline.

[0007] Further, the open-loop operational amplifier realizes constant transconductance in a compensated form, that is, the changes of the two-stage transconductance of the open-loop operational amplifier show opposite trends with the change of the input signal amplitude, so as to ensure the stability of the inter-stage gain within the -3dB bandwidth of the open-loop operational amplifier.

[0008] Further, the passive RC network includes two or more groups of RC filtering structures for second-order or multi-order filtering.

[0009] Further, the passive RC network includes two groups of RC filtering structures, and its equivalent transfer function H(s) cascaded with the open-loop operational amplifier is:

[0010]

[0011] where s represents the Laplace transform domain, R1, R2, C1, and C2 are the resistance and capacitance elements of the passive RC network, and A is the inter-stage gain of the open-loop operational amplifier.

[0012] Further, when the open-loop operational amplifier can be approximated as a single-pole system, the requirement for the gain-bandwidth product GBW open_loop of the continuous-time pipelined analog-to-digital converter is only:

[0013] GBW open_loop = A × Bandwidth ADC

[0014] where A is the inter-stage gain of the open-loop operational amplifier, and Bandwidth ADC is the system bandwidth.

[0015] Further, the quantization unit includes:

[0016] FlashADC, which is used for coarsely quantifying the input signal to generate a digital code;

[0017] The RDAC is used to further quantize the digital code to generate a step signal.

[0018] Furthermore, the post-stage quantization unit is a quantization unit that can meet system requirements, and is used to perform final quantization processing on the residual signal that has been low-pass filtered and amplified, and output a final digital signal.

[0019] Furthermore, the residual processing unit first performs low-pass filtering and then performs an amplification operation, which can effectively filter out out-of-band noise and improve system accuracy.

[0020] Furthermore, the gain-bandwidth product of the open-loop operational amplifier is determined by the system bandwidth of the continuous-time pipeline analog-to-digital converter and is smaller than the gain-bandwidth product requirement of the closed-loop operational amplifier to reduce system power consumption.

[0021] Furthermore, in the continuous-time pipeline ADC with an actual design sampling rate of 800MS / s, after simulation, under the premise of meeting the system speed and accuracy, the gain-bandwidth product of the closed-loop operational amplifier needs to reach 2 to 3 times the system sampling rate, and the oversampling rate is 4, the inter-stage gain is 8 times, and the system bandwidth is 100MHz. At this time, the theoretical calculation requires that the gain-bandwidth product of the open-loop operational amplifier is only 800MHz. For the continuous-time pipeline ADC using a closed-loop operational amplifier with the same sampling rate, in the actual simulation process, the gain-bandwidth product of the closed-loop operational amplifier is required to reach about 2G.

[0022] The beneficial effect of the technical solution of the present invention is embodied in that the present invention introduces a structure of a passive RC network combined with an open-loop operational amplifier in a continuous-time pipeline ADC, wherein the passive RC network realizes second-order low-pass filtering and the open-loop operational amplifier realizes inter-stage gain, thereby avoiding the use of a closed-loop operational amplifier, thereby greatly reducing system power consumption and design difficulty. The present invention adopts a passive RC network combined with an open-loop operational amplifier in a continuous-time pipeline ADC, which not only ensures the consistency of the system transfer function, but also reduces the circuit design difficulty and greatly reduces power consumption.

[0023] The present invention is suitable for application in communication systems, introduces a passive RC network combined with an open-loop operational amplifier, greatly optimizes system power consumption, and has the characteristics of both pipeline ADC speed and accuracy. This system structure has certain advantages in overall performance indicators.

[0024] In the preferred solution, low-pass filtering is performed first and then amplification is performed, which can effectively filter out out-of-band noise, improve the accuracy of the system, and further enhance the overall performance of the system. The present invention is particularly suitable for high-speed and high-precision communication system applications.

[0025] Other beneficial effects of the technical solution of the present invention will be further analyzed and described below. Brief Description of the Drawings

[0026] Figure 1 is a typical architecture diagram of a three-stage continuous-time pipelined ADC.

[0027] Figure 2 is the architecture diagram of the continuous-time pipelined analog-to-digital converter based on an open-loop operational amplifier according to an embodiment of the present invention. Detailed Embodiment

[0028] The present invention will be further described below in conjunction with the accompanying drawings, specific embodiments and examples. Those skilled in the art should understand that the purpose of providing the embodiments is only for illustration and not for any limitation.

[0029] An embodiment of the present invention provides a continuous-time pipelined analog-to-digital converter based on an open-loop operational amplifier, including: at least two stages of pipelines and a post-stage quantization unit; each stage of the pipeline has basically the same structure, and each stage of the pipeline includes a delay network, a quantization unit and a residue processing unit, wherein the delay network and the quantization unit form two parallel input processing paths; the residue processing unit includes a passive RC network and an open-loop operational amplifier, the passive RC network is used to perform low-pass filtering on the residue signal obtained by subtracting the output of the delay unit from the output of the quantization unit, and the open-loop operational amplifier is used to amplify the residue signal after low-pass filtering to obtain the pipeline output; the post-stage quantization unit is connected to the output end of the last stage of the pipeline and is used to perform final quantization processing on the output of the last stage of the pipeline to obtain the final output of the analog-to-digital converter. Among them, the post-stage quantization unit can be a four-channel ASAR ADC (successive approximation asynchronous sampling ADC), or other ADC structures that meet the accuracy requirements, and the present invention does not limit this.

[0030] Please refer to Figure 2 , this embodiment includes N + 2 stages (N≥0) of pipelines. The post-stage pipelines take the output of the previous stage of the pipeline as the input, and the output of the last stage of the pipeline enters the post-stage quantization unit for final quantization processing to output the final digital signal D n+3 . Since the structures of each pipeline stage are basically the same, in this embodiment, the first stage is taken as an example to illustrate the structure and working principle of the pipeline. It should be noted that in the second stage, the passive RC network and the open-loop operational amplifier are simplified as "filtering". As Figure 2As shown, on one hand, the input signal enters the delay unit for processing, and on the other hand, it enters the quantization unit composed of a Flash ADC (Flash Analog-to-Digital Converter) and an RDAC (Resistive Digital-to-Analog Converter) for quantization processing. The residual signal obtained by subtracting the signals from these two processing paths is processed by the residual processing unit with a transfer function of H(s) to obtain the output of this stage of the pipeline. Specifically, after the input signal is roughly quantized by the Flash ADC of the first stage of the pipeline, the control code D1 of the first stage is output. The control code D1 then enters the RDAC for quantization to obtain a stepped signal, which is already in the opposite direction to the input signal. After the input signal is processed by the delay unit, it is sent to the adder together with the output of the RDAC. Since the stepped signal after RDAC quantization is already in the opposite direction, the subtraction of the two signals is achieved through the adder to obtain the residual signal. This residual signal then enters the residual processing unit cascaded by a passive RC network and an open-loop operational amplifier. First, the passive RC network performs low-pass filtering, and then the open-loop operational amplifier amplifies the filtered signal. The amplified signal is the output of this stage of the pipeline.

[0031] The passive RC network in the embodiment of the present invention may include two or more groups of RC filtering structures for second-order or multi-order filtering. In Figure 2 the example shown, the passive RC network includes two groups of RC filtering structures for realizing second-order low-pass filtering of the residual signal and effectively filtering out out-of-band noise. The equivalent transfer function H(s) of the cascade of the passive RC network and the open-loop operational amplifier is:

[0032]

[0033] where s represents the Laplace transform domain, R1, R2, C1, and C2 are the resistor and capacitor elements of the passive RC network, and A is the inter-stage gain of the open-loop operational amplifier.

[0034] For Figure 1 the structure shown that uses a closed-loop operational amplifier to realize second-order low-pass filtering, its transfer function can be expressed as:

[0035]

[0036] Its inter-stage gain (i.e., the DC gain) is:

[0037]

[0038] By adjusting the values of R2 and R1 in the MFB structure to reach the DC gain of the target design, and its -3dB bandwidth of the transfer function can be obtained as:

[0039]

[0040] After comparing the transfer function H(s) of the present invention with Figure 1 the transfer function H(s)' of the existing structure shown, it can be seen that the structure of cascading an open-loop operational amplifier and a passive RC network in the present invention will not change its transfer function in a continuous-time pipelined ADC system, can ensure the consistency of the system transfer function, and has the same function as a closed-loop operational amplifier, and can achieve the effects of second-order low-pass filtering and amplification.

[0041] Starting from the consistency of the transfer function, the present invention first performs low-pass filtering and then amplification by using an open-loop operational amplifier combined with a passive RC filter network, and realizes the same filtering and amplification effect as the closed-loop operational amplifier scheme by adjusting the values of the resistor R and capacitor C of the RC filter network.

[0042] In the embodiment of the present invention, the open-loop operational amplifier adopts a constant transconductance structure to ensure the stability of the inter-stage gain. Specifically, the open-loop operational amplifier realizes constant transconductance in a compensated form, that is, the changes in the transconductance of the two stages of the open-loop operational amplifier show opposite trends with the change of the input signal amplitude, so as to ensure the stability of the inter-stage gain within the -3dB bandwidth of the open-loop operational amplifier.

[0043] Regarding the determination of the gain-bandwidth product GBW of the open-loop operational amplifier in the system open_loop it can be determined by the system bandwidth of the entire ADC. If the system bandwidth is Bandwidth ADC , and the inter-stage gain is A, then when the open-loop operational amplifier can be equivalent to a single-pole system, the requirement for the GBW open_loop of the open-loop operational amplifier by the continuous-time pipelined ADC is only:

[0044] CBW open_loop = A × Bandwidth ADC

[0045] It can be seen that the gain-bandwidth product of the open-loop operational amplifier in the present invention is greatly reduced compared with that of the closed-loop operational amplifier.

[0046] Taking the specific simulation analysis in the present invention as an example, in terms of power consumption, in a continuous-time pipelined ADC with an actual design sampling rate of 800 MS / s, after simulation, on the premise of meeting the system speed and accuracy, the GBW of the closed-loop operational amplifier needs to reach 2 to 3 times the system sampling rate (about 2 GHz). The oversampling rate is 4 and the inter-stage gain is 8 times, so the system bandwidth is 100 MHz. At this time, the theoretical calculation shows that the GBW of the open-loop operational amplifier required for the system of the present invention is only 800 MHz. However, for a pipelined ADC with a closed-loop operational amplifier of the same sampling rate in the actual simulation process, the GBW of the closed-loop operational amplifier needs to reach about 2 G. Therefore, it can be seen that the requirement for the GBW of the open-loop operational amplifier of the pipelined ADC based on the combination of the open-loop operational amplifier and the passive RC network in the embodiment of the present invention is much lower than that of the system using the closed-loop operational amplifier. Therefore, the design of the present invention can greatly reduce the power consumption.

[0047] The present invention combines an open-loop operational amplifier and an RC passive filter network in a continuous-time pipelined ADC to replace the traditional closed-loop operational amplifier structure, which can greatly reduce the system power consumption and improve the system performance. In the design process, it mainly starts from ensuring the consistency of the system transfer function, that is, each stage of the system has the functions of filtering and amplification. Therefore, it can be considered that the system generates residuals, first performs filtering processing and then amplification operations. Compared with first performing amplification and then filtering, it can better filter out out-of-band noise and improve the system accuracy. In the actual simulation comparison process, the overall performance of this solution is also better.

[0048] An open-loop operational amplifier structure is introduced into the continuous-time pipelined ADC and combined with a passive RC filter network. Under the condition of ensuring the consistency of the system transfer function, the operation of filtering and amplifying the residuals is realized. Compared with using a closed-loop operational amplifier, the design using an open-loop operational amplifier is simpler. The GBW of the open-loop operational amplifier can be determined by the system bandwidth. In the case of a high sampling rate, the GBW of the open-loop operational amplifier is much smaller than that of the closed-loop operational amplifier. Therefore, the system power consumption can be greatly reduced. In the closed-loop operational amplifier, due to the existence of feedback in the closed-loop structure, the requirement for the GBW of the operational amplifier is higher, while the function of the open-loop operational amplifier is only amplification, and the requirement for its GBW is only related to the bandwidth of the whole system.

[0049] The present invention ensures the consistency of the system transfer function, and introduces an open-loop operational amplifier combined with a passive RC filter network into a continuous-time pipeline ADC to form a new structural form. The present invention solves the problems of high difficulty in designing the operational amplifier of the continuous-time pipeline ADC and high system power consumption. Therefore, the greatest advantage of the present invention is that it reduces the design difficulty of the operational amplifier in the system and optimizes the power consumption of the system. Further, the open-loop operational amplifier is optimized. The open-loop operational amplifier used in the present invention adopts a constant transconductance structure to maintain the stability of the inter-stage gain, which is achieved through two-stage structural compensation.

[0050] The present invention is suitable for communication systems, and introduces a structure of an open-loop operational amplifier combined with a passive RC filter network, which greatly optimizes system power consumption and has the characteristics of balancing the speed and accuracy of a pipeline ADC. This system structure has certain advantages in overall performance indicators.

[0051] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art of the present invention, several equivalent substitutions or obvious variations can be made without departing from the concept of the present invention, and the performance or use is the same, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. A continuous-time pipeline analog-to-digital converter based on an open-loop operational amplifier, characterized in that: include: At least two pipeline stages and a post-quantization unit; Each stage of the pipeline includes a delay network, a quantization unit and a residual processing unit, wherein the delay network and the quantization unit constitute two parallel input processing paths; the residual processing unit includes a passive RC network and an open-loop operational amplifier, wherein the passive RC network is used to perform low-pass filtering on the residual signal obtained by subtracting the output of the delay unit from the output of the quantization unit, and the open-loop operational amplifier is used to amplify the residual signal after low-pass filtering to obtain the pipeline output; wherein the open-loop operational amplifier adopts a transconductance constant structure to ensure the stability of the inter-stage gain; The post-stage quantization unit is connected to the output end of the last stage of the pipeline and is used to perform final quantization processing on the output of the last stage of the pipeline.

2. The continuous time pipeline analog-to-digital converter of claim 1, wherein: The open-loop operational amplifier uses compensation to achieve constant transconductance, that is, the changes in the two-stage transconductance of the open-loop operational amplifier show opposite trends as the input signal amplitude changes, so as to ensure the stability of the inter-stage gain within the -3dB bandwidth of the open-loop operational amplifier.

3. The continuous time pipeline analog to digital converter according to claim 1 or 2, characterized in that: The passive RC network includes two or more groups of RC filtering structures to perform second-order or multi-order filtering.

4. The continuous time pipeline analog-to-digital converter of claim 3, wherein: The passive RC network includes two groups of RC filter structures, and the equivalent transfer function H(s) of the passive RC network and the open-loop operational amplifier cascaded is: Wherein, s represents the Laplace transform domain, R1, R2, C1, C2 are the resistance and capacitance elements of the passive RC network, and A is the inter-stage gain of the open-loop operational amplifier.

5. The continuous time pipeline analog-to-digital converter according to claim 1 or 2, characterized in that: When the open-loop operational amplifier is effectively a single-pole system, the continuous-time pipeline analog-to-digital converter has a gain-bandwidth product GBW for the open-loop operational amplifier. open_loop The requirements are only: GBW open_loop =A×Bandwidth ADC Where A is the interstage gain of the open-loop operational amplifier, Bandwidth ADC is the system bandwidth.

6. The continuous time pipeline analog-to-digital converter according to claim 1 or 2, characterized in that: The quantization unit comprises: Flash ADC, used to perform coarse quantization on the input signal and generate digital code; The RDAC is used to further quantize the digital code to generate a step signal.

7. The continuous time pipeline analog-to-digital converter according to any one of claims 1 or 2, characterized in that: The post-stage quantization unit is a quantization unit that can meet the system accuracy requirements, and is used to perform final quantization processing on the residual signal that has been low-pass filtered and amplified, and output a final digital signal.

8. The continuous time pipeline analog-to-digital converter according to any one of claims 1 to 7, characterized in that: The residual processing unit first performs low-pass filtering and then performs an amplification operation, which can effectively filter out out-of-band noise and improve system accuracy.

9. The continuous time pipeline analog-to-digital converter according to any one of claims 1 to 7, characterized in that: The gain-bandwidth product of the open-loop operational amplifier is determined by the system bandwidth of the continuous-time pipeline analog-to-digital converter and is smaller than the gain-bandwidth product requirement of the closed-loop operational amplifier to reduce system power consumption.

10. The continuous time pipeline analog-to-digital converter according to any one of claims 9, characterized in that: In the actual design of a continuous-time pipeline ADC with a sampling rate of 800MS / s, after simulation, it was found that under the premise of meeting the system speed and accuracy, the gain-bandwidth product of the closed-loop operational amplifier must reach 2 to 3 times the system sampling rate, and the oversampling rate is 4, the inter-stage gain is 8 times, and the system bandwidth is 100MHz. At this time, the theoretical calculation requires the gain-bandwidth product of the open-loop operational amplifier to be only 800MHz. For the continuous-time pipeline ADC using a closed-loop operational amplifier with the same sampling rate, the gain-bandwidth product of the closed-loop operational amplifier is required to reach about 2G in the actual simulation process.

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