A continuous time linear equalizer and electronic device

Abstract

The application provides a continuous-time linear equalizer and electronic equipment, wherein an output end of a transconductance amplification circuit is connected to an input end of a transimpedance amplification circuit; a bias voltage output end of a common-mode voltage calibration circuit is connected to the transconductance amplification circuit, and a switch signal output end of the common-mode voltage calibration circuit is connected to the transimpedance amplification circuit; the common-mode voltage calibration circuit provides corresponding bias voltage to the transconductance amplification circuit according to the current common-mode voltage in the common-mode voltage calibration circuit; the common-mode voltage calibration circuit provides corresponding switch signal to the transimpedance amplification circuit according to the current common-mode voltage in the common-mode voltage calibration circuit and a preset reference voltage, and the switch signal is used for adjusting the common-mode voltage component in the transimpedance amplification circuit output. Through the common-mode voltage calibration of the common-mode voltage calibration circuit, the linearity is improved, the common-mode voltage calibration circuit has little influence on the high-speed performance of the continuous-time linear equalizer, the area and power consumption are small, and the application scenarios are wide.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular to a continuous-time linear equalizer and electronic equipment. Background Art

[0002] In high-speed signal transmission systems, signal transmission rates are increasing. The parasitic distribution parameters of signal transmission media (package bonding wires, PCB transmission lines, etc.) will cause severe insertion loss (Insert loss) on high-frequency signals, causing the signal to be severely affected by inter-symbol interference (ISI), resulting in deterioration of eye diagram quality and increased bit error rate.

[0003] To compensate for the insertion loss caused by the channel, a continuous time linear equalizer (CTLE) can be used at the receiver front end. The CTLE has high-pass transmission characteristics that complement the low-pass characteristics of the channel, achieving frequency compensation and ultimately producing a relatively flat frequency response.

[0004] As a crucial component of high-speed signal transmission systems, how to ensure or improve the linearity of a continuous-time linear equalizer (CTLE) has become a challenging issue that continues to attract attention from those skilled in the art. Summary of the Invention

[0005] The object of the present invention is to provide a continuous-time linear equalizer and an electronic device to improve the above-mentioned problem.

[0006] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0007] In a first aspect, an embodiment of the present invention provides a continuous-time linear equalizer, the continuous-time linear equalizer comprising a transconductance amplifier circuit, a transimpedance amplifier circuit, and a common-mode voltage calibration circuit;

[0008] The first output terminal of the transconductance amplifier circuit is connected to the first input terminal of the transimpedance amplifier circuit, and the second output terminal of the transconductance amplifier circuit is connected to the second input terminal of the transimpedance amplifier circuit;

[0009] The bias voltage output terminal of the common-mode voltage calibration circuit is connected to the bias voltage input terminal of the transconductance amplifier circuit, and the switch signal output terminal of the common-mode voltage calibration circuit is connected to the transimpedance amplifier circuit;

[0010] The common-mode voltage calibration circuit is used to provide a corresponding bias voltage to the transconductance amplifier circuit according to the current common-mode voltage inside the common-mode voltage calibration circuit;

[0011] The common-mode voltage calibration circuit is further configured to provide a corresponding switching signal to the transimpedance amplifier circuit based on the current common-mode voltage within the circuit and a preset reference voltage. The switching signal is configured to adjust the common-mode voltage component in the output of the transimpedance amplifier circuit.

[0012] The common-mode voltage is calibrated through the common-mode voltage calibration circuit, thereby improving the linearity. The common-mode voltage calibration circuit has little effect on the high-speed performance of the continuous-time linear equalizer, uses very little area and power consumption, and has a wide range of application scenarios.

[0013] Optionally, the transimpedance amplifier circuit includes a transimpedance amplifier, a first resistor, a second resistor, a first inductor, and a second inductor;

[0014] One end of the first inductor is connected to the first output end of the transimpedance amplifier, and one end of the second inductor is connected to the second output end of the transimpedance amplifier;

[0015] One end of the first resistor is connected to the first input end of the transimpedance amplifier;

[0016] One end of the second resistor is connected to the second input end of the transimpedance amplifier, and the other end of the second resistor is connected to the other end of the second inductor;

[0017] The control end of the transimpedance amplifier is connected to the switch signal output end of the common-mode voltage calibration circuit.

[0018] Optionally, the transimpedance amplifier includes a first current source and two amplifying branches, and the amplifying branches include a first NMOS transistor and a first PMOS array;

[0019] The source of the first PMOS array is connected to a corresponding power supply;

[0020] The drain of the first PMOS array is connected to the drain of the first NMOS transistor, and a terminal is connected between the two to serve as the output end of the transimpedance amplifier;

[0021] The gate of the first PMOS array is connected to the gate of the first NMOS transistor, and a terminal is connected between the two to serve as the input end of the transimpedance amplifier;

[0022] The control end of the first PMOS array is connected to the switch signal output end of the common mode voltage calibration circuit;

[0023] The source of the first NMOS transistor is connected to one end of the first current source, and the other end of the first current source is grounded.

[0024] The first PMOS array is flexibly controlled by a switching signal to ensure the stability of the common-mode voltage component in the output of the transimpedance amplifier, thereby improving the linearity of the continuous-time linear equalizer.

[0025] Optionally, the first PMOS array includes N first PMOS transistors and N second PMOS transistors;

[0026] The sources of the N first PMOS transistors serve together as the source of the first PMOS array and are connected to a corresponding power supply;

[0027] The drain of the nth first PMOS transistor is connected to the source of the nth second PMOS transistor, 1≤n≤N;

[0028] The drains of the N second PMOS transistors serve together as the drain of the first PMOS array and are connected to the drain of the first NMOS transistor;

[0029] The gates of the N second PMOS transistors serve together as the gate of the first PMOS array and are connected to the gate of the first NMOS transistor;

[0030] The gate of the nth first PMOS transistor serves as the nth control terminal of the first PMOS array and is connected to the switch signal output terminal of the common-mode voltage calibration circuit.

[0031] By splitting the first PMOS array into N paths, the N paths are flexibly adjusted according to the switching signal, so as to ensure the stability of the common-mode voltage component in the output of the transimpedance amplifier.

[0032] Optionally, the common-mode voltage calibration circuit includes a second NMOS transistor, a second PMOS array, a common-mode feedback unit, a comparator, a calibration unit, and a second current source;

[0033] The source of the second PMOS array is connected to a corresponding power supply;

[0034] The drain of the second PMOS array is connected to the drain of the second NMOS transistor, and a terminal is led out from the connection between the two, which is connected to the input end of the common-mode feedback unit and the first input end of the comparator, and the second input end of the comparator is used to access the reference voltage;

[0035] The gate of the second PMOS array is connected to the gate of the second NMOS transistor, and the gate of the second NMOS transistor is also connected to the drain of the second NMOS transistor;

[0036] The source of the second NMOS transistor is connected to one end of the second current source, and the other end of the second current source is grounded;

[0037] The output end of the common-mode feedback unit serves as the bias voltage output end of the common-mode voltage calibration circuit;

[0038] The output end of the comparator is connected to the input end of the calibration unit, and the output end of the calibration unit serves as the switching signal output end of the common-mode voltage calibration circuit;

[0039] The control end of the second PMOS array is connected to the output end of the calibration unit.

[0040] The second PMOS array is regulated by the switching signal, thereby completing the common mode voltage calibration accurately and quickly.

[0041] Optionally, the nth output terminal in the calibration unit serves as the nth switch signal output terminal of the common-mode voltage calibration circuit;

[0042] The calibration unit is used to control one or more high-level output terminals to switch to output a low level when the current common-mode voltage inside the common-mode voltage calibration circuit is lower than the reference voltage;

[0043] The calibration unit is used to control one or more low-level output terminals in the common-mode voltage calibration circuit to switch to output a high level when the current common-mode voltage in the common-mode voltage calibration circuit is greater than the reference voltage.

[0044] Optionally, the transconductance amplifier circuit includes a third NMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third current source, a fourth current source, a source degeneration resistor, and a source degeneration capacitor;

[0045] The source of the fifth PMOS transistor and the source of the sixth PMOS transistor are connected to corresponding power supplies;

[0046] A connection terminal is led out from the connection between the gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor, serving as a bias voltage access terminal of the transconductance amplifier circuit;

[0047] The drain of the fifth PMOS transistor is connected to the drain of the third NMOS transistor, and a connection terminal is led out at the connection between the two to serve as the first output end of the transconductance amplifier circuit;

[0048] The drain of the sixth PMOS transistor is connected to the drain of the fourth NMOS transistor, and a connection terminal is led out at the connection between the two to serve as the second output end of the transconductance amplifier circuit;

[0049] The gate of the third NMOS transistor serves as the first input terminal of the transconductance amplifier circuit, and the gate of the fourth NMOS transistor serves as the second input terminal of the transconductance amplifier circuit;

[0050] The source of the third NMOS transistor is connected to one end of the third current source, the source of the fourth NMOS transistor is connected to one end of the fourth current source, and the other end of the third current source and the other end of the fourth current source are grounded;

[0051] One end of the source degeneration resistor is connected to the source of the third NMOS transistor, and the other end of the source degeneration resistor is connected to the source of the fourth NMOS transistor;

[0052] One end of the source degeneration capacitor is connected to the source of the third NMOS transistor, and the other end of the source degeneration capacitor is connected to the source of the fourth NMOS transistor.

[0053] A high-pass characteristic is generated by the source degeneration resistance and source degeneration capacitance.

[0054] Optionally, the transconductance amplifier circuit further includes a third resistor, a fourth resistor, a first capacitor and a second capacitor;

[0055] One end of the third resistor is connected to the gate of the fifth PMOS transistor, and the other end of the third resistor is connected to the bias voltage input terminal;

[0056] One end of the fourth resistor is connected to the gate of the sixth PMOS transistor, and the other end of the fourth resistor is connected to the bias voltage input terminal;

[0057] One end of the first capacitor is connected to the gate of the fifth PMOS transistor, and the other end of the first capacitor is connected to the gate of the third NMOS transistor;

[0058] One end of the second capacitor is connected to the gate of the sixth PMOS transistor, and the other end of the second capacitor is connected to the gate of the fourth NMOS transistor.

[0059] Through passive high-pass filtering, the high-frequency gain of the transconductance amplifier circuit is improved. Under the condition of the same equalization capability, the power consumption is lower, and the time constant of the high-pass filter can be flexibly adjusted to compensate for the low-frequency channel insertion loss.

[0060] In a second aspect, an embodiment of the present invention provides an electronic device including the above-mentioned continuous-time linear equalizer.

[0061] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0063] Figure 1 A schematic diagram of the structure of a continuous-time linear equalizer provided by an embodiment of the present invention.

[0064] Figure 2 A schematic diagram of the structure of a transimpedance amplifier provided in an embodiment of the present invention.

[0065] Figure 3 This is a structural diagram of a common-mode voltage calibration circuit provided by an embodiment of the present invention.

[0066] Figure 4 This is one of the structural diagrams of the transconductance amplifier circuit provided by an embodiment of the present invention.

[0067] Figure 5 This is a second structural diagram of the transconductance amplifier circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0068] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0069] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0070] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are used only to distinguish the description and should not be understood as indicating or implying relative importance.

[0071] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0072] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0073] In an optional embodiment, a continuous-time linear equalizer (CTLE) may employ a transconductance amplifier-transimpedance amplifier (Gm-TIA) structure. This improved structure utilizes a transimpedance amplifier (TIA) as a load resistor, providing a higher output swing and ensuring higher linearity at low power supply voltages. Because a transimpedance amplifier (TIA) is used as a load, the negative feedback characteristics of the TIA result in lower input and output impedances, enabling this CTLE to achieve a higher bandwidth.

[0074] However, the continuous time linear equalizer (CTLE) with a transconductance-transimpedance (Gm-TIA) structure has the risk of excessive output common-mode voltage variation, affecting the overall linearity of the CTLE. This is because the common-mode voltage is obtained through the self-biasing of an amplifier with a similar ratio to the transimpedance amplifier (TIA). Due to deviations in temperature, power supply voltage, and process, the common-mode voltage can vary significantly. When the output swing of the CTLE is large, the deviation in the common-mode voltage will cause the linearity of the CTLE to degrade.

[0075] To this end, an embodiment of the present invention provides a continuous time linear equalizer (CTLE) that calibrates the common mode voltage to keep the output common mode voltage of the transimpedance amplifier (TIA) stable, including but not limited to being close to half of the power supply voltage of the transimpedance amplifier (TIA), so that the output common mode voltage does not affect the linearity of the continuous time linear equalizer (CTLE). For details, please refer to Figure 1 , Figure 1 A schematic diagram of the structure of a continuous-time linear equalizer provided by an embodiment of the present invention.

[0076] The continuous time linear equalizer includes a transconductance amplifier circuit, a transresistance amplifier circuit and a common mode voltage calibration circuit.

[0077] The first output terminal of the transconductance amplifier circuit is connected to the first input terminal of the transimpedance amplifier circuit, the second output terminal of the transconductance amplifier circuit is connected to the second input terminal of the transimpedance amplifier circuit, the input terminal of the transconductance amplifier circuit is the input terminal of the continuous-time linear equalizer, and the output terminal of the transimpedance amplifier circuit is the output terminal of the continuous-time linear equalizer.

[0078] The bias voltage output terminal of the common-mode voltage calibration circuit is connected to the bias voltage input terminal of the transconductance amplifier circuit, and the switch signal output terminal of the common-mode voltage calibration circuit is connected to the transimpedance amplifier circuit.

[0079] The common-mode voltage calibration circuit is used to provide a corresponding bias voltage Vbias to the transconductance amplifier circuit according to the current common-mode voltage inside the common-mode voltage calibration circuit.

[0080] The common-mode voltage calibration circuit is also used to provide a corresponding switching signal to the transimpedance amplifier circuit based on the current common-mode voltage inside it and the preset reference voltage Vref. The switching signal is used to adjust the common-mode voltage component in the output of the transimpedance amplifier circuit so that it is close to the reference voltage, and the deviation between the two is less than the preset value.

[0081] Optionally, the common-mode voltage calibration circuit may also adjust its internal common-mode voltage according to the switching signal generated thereby, so that its internal common-mode voltage is close to the reference voltage.

[0082] In the continuous-time linear equalizer provided in an embodiment of the present invention, the common-mode voltage is calibrated by a common-mode voltage calibration circuit, thereby improving linearity. In addition, the common-mode voltage calibration circuit has little effect on the high-speed performance of the continuous-time linear equalizer, and the area and power consumption used are very small, and the application scenarios are wide.

[0083] Please continue to refer to Figure 1 The transimpedance amplifier circuit includes a transimpedance amplifier, a first resistor R1, a second resistor R2, a first inductor L1 and a second inductor L2.

[0084] One end of the first inductor L1 is connected to the first output end of the transimpedance amplifier, and one end of the second inductor L2 is connected to the second output end of the transimpedance amplifier.

[0085] One end of the first resistor R1 is connected to the first input end of the transimpedance amplifier (serving as the first input end of the transimpedance amplifier circuit), and the other end of the first resistor R1 is connected to the other end of the first inductor L1. A terminal is connected at the connection between the two to serve as the first output end Vout1 of the transimpedance amplifier circuit.

[0086] One end of the second resistor R2 is connected to the second input end of the transimpedance amplifier (serving as the second input end of the transimpedance amplifier circuit), and the other end of the second resistor R2 is connected to the other end of the second inductor L2. A terminal is connected at the connection between the two to serve as the second output end Vout2 of the transimpedance amplifier circuit.

[0087] The control end of the transimpedance amplifier is connected to the switch signal output end of the common-mode voltage calibration circuit.

[0088] On the basis of the above, regarding how to ensure the stability of the common-mode voltage component in the output of the transimpedance amplifier, thereby improving the linearity of the continuous-time linear equalizer, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 2 , Figure 2 A schematic diagram of the structure of a transimpedance amplifier provided in an embodiment of the present invention.

[0089] The transimpedance amplifier includes a first current source I1 and two amplifying branches (such as Figure 2 The first amplifying branch and the second amplifying branch are shown in FIG. 1 . The amplifying branch includes a first NMOS transistor NM1 and a first PMOS array.

[0090] The source of the first PMOS array is connected to a corresponding power source (Vcc1).

[0091] The drain of the first PMOS array is connected to the drain of the first NMOS transistor NM1 , and a connection terminal is led out from the connection between the two to serve as the output end of the transimpedance amplifier.

[0092] The gate of the first PMOS array is connected to the gate of the first NMOS transistor NM1 , and a connection terminal is led out from the connection between the two to serve as an input end of the transimpedance amplifier.

[0093] The input end of the first amplifying branch is the first input end (VinN) of the transimpedance amplifier, the output end of the first amplifying branch is the first output end (Vout1) of the transimpedance amplifier, the input end of the second amplifying branch is the second input end (VinP) of the transimpedance amplifier, and the output end of the second amplifying branch is the second output end (Vout2) of the transimpedance amplifier.

[0094] The control end of the first PMOS array is connected to the switch signal output end of the common mode voltage calibration circuit.

[0095] The PMOS transistor in the first PMOS array, which is connected to the switch signal output terminal of the common-mode voltage calibration circuit, switches between the on state and the off state when triggered by the switch signal, thereby controlling and adjusting the common-mode voltage component inside the transimpedance amplifier circuit.

[0096] A source of the first NMOS transistor NM1 is connected to one end of the first current source I1 , and the other end of the first current source I1 is grounded.

[0097] The first current source I1 is used to draw a corresponding fixed current.

[0098] Regarding how the first PMOS array is flexibly adjusted according to the switching signal to ensure the stability of the common-mode voltage component in the output of the transimpedance amplifier, the embodiment of the present invention also provides an optional implementation method, please continue to refer to Figure 2 .

[0099] The first PMOS array includes N first PMOS transistors PM1 and N second PMOS transistors PM2 .

[0100] The sources of the N first PMOS transistors PM1 serve together as the source of the first PMOS array and are connected to the corresponding power supply (Vcc1).

[0101] The drain of the nth first PMOS transistor PM1 is connected to the source of the nth second PMOS transistor PM2 , 1≤n≤N.

[0102] The drains of the N second PMOS transistors PM2 serve together as the drain of the first PMOS array and are connected to the drain of the first NMOS transistor NM1 . A connection terminal is drawn out at the connection between the two to serve as the output end of the transimpedance amplifier.

[0103] The gates of the N second PMOS transistors PM2 serve together as the gate of the first PMOS array and are connected to the gate of the first NMOS transistor NM1 .

[0104] The gate of the nth first PMOS transistor PM1 serves as the nth control terminal of the first PMOS array and is connected to the switch signal output terminal of the common mode voltage calibration circuit.

[0105] Optionally, the gate of the nth first PMOS transistor PM1 is connected to the nth switch signal output terminal (outputting the nth switch signal) of the common-mode voltage calibration circuit.

[0106] The nth first PMOS transistor PM1 is switched to an on state or an off state when triggered by the nth switching signal.

[0107] exist Figure 1 On the basis of how the common mode voltage calibration circuit can accurately and quickly complete the common mode voltage calibration, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 3 , Figure 3 This is a structural diagram of a common-mode voltage calibration circuit provided by an embodiment of the present invention.

[0108] The common-mode voltage calibration circuit includes a second NMOS transistor NM2, a second PMOS array, a common-mode feedback unit, a comparator, a calibration unit, and a second current source I2. The second PMOS array is identical to the first PMOS array. The fixed current drawn by the second current source I2 is half the fixed current drawn by the first current source I1.

[0109] The source of the second PMOS array is connected to a corresponding power source (Vcc1).

[0110] The drain of the second PMOS array is connected to the drain of the second NMOS transistor NM2, and a terminal (outputting a common-mode voltage Vcm) is connected to the connection between the two. This terminal is connected to the input of the common-mode feedback unit and the first input of the comparator (which can be either the non-inverting input or the inverting input). The second input of the comparator is used to access a reference voltage (Vref).

[0111] The first input terminal of the comparator may be a non-inverting input terminal or an inverting input terminal, and the second input terminal of the comparator is the remaining other terminal.

[0112] The gate of the second PMOS array is connected to the gate of the second NMOS transistor NM2 , and the gate of the second NMOS transistor NM2 is also connected to the drain of the second NMOS transistor NM2 .

[0113] A source of the second NMOS transistor NM2 is connected to one end of the second current source I2 , and the other end of the second current source I2 is grounded.

[0114] The second current source I2 is used to draw a corresponding fixed current.

[0115] The output end of the common-mode feedback unit serves as the bias voltage output end of the common-mode voltage calibration circuit, and is used to provide a corresponding bias voltage Vbias to the transconductance amplifier circuit according to the current common-mode voltage inside the common-mode voltage calibration circuit.

[0116] The output end of the comparator is connected to the input end of the calibration unit, and the output end of the calibration unit serves as the switching signal output end of the common mode voltage calibration circuit.

[0117] The control terminal of the second PMOS array is connected to the output terminal of the calibration unit.

[0118] The PMOS transistor in the second PMOS array connected to the switch signal output terminal of the common-mode voltage calibration circuit switches between the on state and the off state under the triggering of the switch signal, thereby controlling and adjusting the common-mode voltage component inside it.

[0119] Optionally, the calibration unit is provided with N output terminals, and the nth output terminal in the calibration unit serves as the nth switch signal output terminal of the common-mode voltage calibration circuit.

[0120] The calibration unit is used to control one or more high-level output terminals to switch to output low level when the current common-mode voltage inside the common-mode voltage calibration circuit is lower than the reference voltage, if there are still high-level output terminals in the calibration unit.

[0121] The calibration unit is used to control one or more low-level output terminals to switch to output high level when the current common-mode voltage inside the common-mode voltage calibration circuit is greater than the reference voltage, if there are still low-level output terminals in the calibration unit.

[0122] It should be noted that when the common-mode voltage is lower than the reference voltage, the common-mode voltage inside the common-mode voltage calibration circuit needs to be increased, and the equivalent resistance of the second PMOS array needs to be further reduced. At this time, it is necessary to control more ports in the calibration unit to output low levels to control more MOS tubes in the second PMOS array to be turned on. Through the parallel structure, the equivalent resistance is reduced, thereby increasing the current common-mode voltage inside the common-mode voltage calibration circuit.

[0123] When the common-mode voltage is greater than the reference voltage, the common-mode voltage inside the common-mode voltage calibration circuit needs to be reduced, and the equivalent resistance of the second PMOS array needs to be further increased. At this time, it is necessary to control more ports in the calibration unit to output high levels to reduce the number of MOS tubes that are turned on in the second PMOS array, thereby increasing its equivalent resistance and reducing the current common-mode voltage inside the common-mode voltage calibration circuit.

[0124] In an alternative embodiment, please refer to Figure 3 The second PMOS array includes N third PMOS transistors PM3 and N fourth PMOS transistors PM4.

[0125] The sources of the N third PMOS transistors PM3 serve together as the source of the second PMOS array and are connected to the corresponding power supply (Vcc1).

[0126] The drain of the nth third PMOS transistor PM3 is connected to the source of the nth fourth PMOS transistor PM4 .

[0127] The drains of the N fourth PMOS transistors PM4 serve together as the drain of the second PMOS array and are connected to the drain of the second NMOS transistor NM2 .

[0128] The gates of the N fourth PMOS transistors PM4 serve together as the gate of the second PMOS array and are connected to the gate of the second NMOS transistor NM2 .

[0129] The gate of the nth third PMOS transistor PM3 serves as the nth control terminal of the second PMOS array and is connected to the switch signal output terminal of the common mode voltage calibration circuit.

[0130] The gate of the nth third PMOS transistor PM3 is connected to the nth switch signal output terminal of the common mode voltage calibration circuit.

[0131] The nth third PMOS transistor PM3 is switched to an on state or an off state when triggered by the nth switching signal. It should be understood that the nth third PMOS transistor PM3 of the second PMOS array and the nth first PMOS transistor PM1 of the first PMOS array receive the same switching signal, and their states remain consistent.

[0132] On the basis of the above, regarding the structure of the transconductance amplifier circuit, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 4 , Figure 4 This is one of the structural diagrams of the transconductance amplifier circuit provided by an embodiment of the present invention.

[0133] The transconductance amplifier circuit includes a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a third current source I3, a fourth current source I4, a source degeneration resistor Rs, and a source degeneration capacitor Cs.

[0134] The source of the fifth PMOS transistor PM5 and the source of the sixth PMOS transistor PM6 are connected to corresponding power supplies (Vcc2).

[0135] A connection terminal is led out from the connection between the gate of the fifth PMOS transistor PM5 and the gate of the sixth PMOS transistor PM6 as a bias voltage input terminal of the transconductance amplifier circuit, connected to the bias voltage output terminal of the common-mode voltage calibration circuit, and inputting the bias voltage Vbias.

[0136] The drain of the fifth PMOS transistor PM5 is connected to the drain of the third NMOS transistor NM3 , and a connection terminal is led out from the connection between the two to serve as the first output terminal ( Vout1 ) of the transconductance amplifier circuit.

[0137] The drain of the sixth PMOS transistor PM6 is connected to the drain of the fourth NMOS transistor NM4 , and a connection terminal is led out from the connection between the two to serve as the second output end ( Vout2 ) of the transconductance amplifier circuit.

[0138] The gate of the third NMOS transistor NM3 serves as the first input terminal (VinN) of the transconductance amplifier circuit, and the gate of the fourth NMOS transistor NM4 serves as the second input terminal (VinP) of the transconductance amplifier circuit.

[0139] The source of the third NMOS transistor NM3 is connected to one end of the third current source I3 , the source of the fourth NMOS transistor NM4 is connected to one end of the fourth current source I4 , and the other ends of the third current source I3 and the fourth current source I4 are grounded.

[0140] One end of the source degeneration resistor Rs is connected to the source of the third NMOS transistor NM3 , and the other end of the source degeneration resistor Rs is connected to the source of the fourth NMOS transistor NM4 .

[0141] One end of the source degeneration capacitor Cs is connected to the source of the third NMOS transistor NM3 , and the other end of the source degeneration capacitor Cs is connected to the source of the fourth NMOS transistor NM4 .

[0142] A high-pass characteristic is generated by the source degeneration resistance Rs and the source degeneration capacitance Cs.

[0143] On the basis of the above, regarding how to further improve the high-frequency gain of the transconductance amplifier circuit and reduce power consumption, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 5 , Figure 5 This is a second structural diagram of the transconductance amplifier circuit provided by an embodiment of the present invention.

[0144] The transconductance amplifier circuit further includes a third resistor R3, a fourth resistor R4, a first capacitor C1 and a second capacitor C2.

[0145] One end of the third resistor R3 is connected to the gate of the fifth PMOS transistor PM5 , and the other end of the third resistor R3 is connected to the bias voltage input terminal.

[0146] One end of the fourth resistor R4 is connected to the gate of the sixth PMOS transistor PM6 , and the other end of the fourth resistor R4 is connected to the bias voltage input terminal.

[0147] One end of the first capacitor C1 is connected to the gate of the fifth PMOS transistor PM5 , and the other end of the first capacitor C1 is connected to the gate of the third NMOS transistor NM3 .

[0148] One end of the second capacitor C2 is connected to the gate of the sixth PMOS transistor PM6 , and the other end of the second capacitor C2 is connected to the gate of the fourth NMOS transistor NM4 .

[0149] The third resistor R3 and the first capacitor C1 form a passive high-pass filter structure, and the fourth resistor R4 and the second capacitor C2 form a passive high-pass filter structure.

[0150] Through passive high-pass filtering, the high-frequency gain of the transconductance amplifier circuit is improved. Under the condition of the same equalization capability, the power consumption is lower, and the time constant of the high-pass filter can be flexibly adjusted to compensate for the low-frequency channel insertion loss.

[0151] It should be noted that the first resistor R1 , the second resistor R2 , the third resistor R3 and the fourth resistor R4 in the embodiment of the present invention may be, but are not limited to, variable resistors.

[0152] An embodiment of the present invention further provides an electronic device including the above-mentioned continuous-time linear equalizer. The electronic device may be a server, a vehicle-mounted computer, a mobile phone, or other device.

[0153] In summary, an embodiment of the present invention provides a continuous-time linear equalizer and electronic device, wherein the continuous-time linear equalizer includes a transconductance amplifier circuit, a transimpedance amplifier circuit, and a common-mode voltage calibration circuit; the first output terminal of the transconductance amplifier circuit is connected to the first input terminal of the transimpedance amplifier circuit, and the second output terminal of the transconductance amplifier circuit is connected to the second input terminal of the transimpedance amplifier circuit; the bias voltage output terminal of the common-mode voltage calibration circuit is connected to the bias voltage access terminal of the transconductance amplifier circuit, and the switch signal output terminal of the common-mode voltage calibration circuit is connected to the transimpedance amplifier circuit; the common-mode voltage calibration circuit provides a corresponding bias voltage to the transconductance amplifier circuit based on the current common-mode voltage within the common-mode voltage calibration circuit; the common-mode voltage calibration circuit provides a corresponding switch signal to the transimpedance amplifier circuit based on the current common-mode voltage within the common-mode voltage calibration circuit and a preset reference voltage, and the switch signal is used to adjust the common-mode voltage component in the output of the transimpedance amplifier circuit. By calibrating the common-mode voltage through the common-mode voltage calibration circuit, linearity is improved, and the common-mode voltage calibration circuit has little effect on the high-speed performance of the continuous-time linear equalizer, uses very little area and power consumption, and has a wide range of application scenarios.

[0154] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

[0155] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A continuous-time linear equalizer, characterized in that The continuous time linear equalizer includes a transconductance amplifier circuit, a transresistance amplifier circuit and a common mode voltage calibration circuit; The first output terminal of the transconductance amplifier circuit is connected to the first input terminal of the transimpedance amplifier circuit, and the second output terminal of the transconductance amplifier circuit is connected to the second input terminal of the transimpedance amplifier circuit; The bias voltage output terminal of the common-mode voltage calibration circuit is connected to the bias voltage input terminal of the transconductance amplifier circuit, and the switch signal output terminal of the common-mode voltage calibration circuit is connected to the transimpedance amplifier circuit; The common-mode voltage calibration circuit is used to provide a corresponding bias voltage to the transconductance amplifier circuit according to the current common-mode voltage inside the common-mode voltage calibration circuit; The common-mode voltage calibration circuit is further configured to provide a corresponding switching signal to the transimpedance amplifier circuit according to a current common-mode voltage within the common-mode voltage calibration circuit and a preset reference voltage, wherein the switching signal is configured to adjust a common-mode voltage component in an output of the transimpedance amplifier circuit; The common-mode voltage calibration circuit includes a second NMOS transistor, a second PMOS array, a common-mode feedback unit, a comparator, a calibration unit, and a second current source; The source of the second PMOS array is connected to a corresponding power supply; The drain of the second PMOS array is connected to the drain of the second NMOS transistor, and a terminal is led out from the connection between the two, which is connected to the input end of the common-mode feedback unit and the first input end of the comparator, and the second input end of the comparator is used to access the reference voltage; The gate of the second PMOS array is connected to the gate of the second NMOS transistor, and the gate of the second NMOS transistor is also connected to the drain of the second NMOS transistor; The source of the second NMOS transistor is connected to one end of the second current source, and the other end of the second current source is grounded; The output end of the common-mode feedback unit serves as the bias voltage output end of the common-mode voltage calibration circuit; The output end of the comparator is connected to the input end of the calibration unit, and the output end of the calibration unit serves as the switching signal output end of the common-mode voltage calibration circuit; The nth output terminal in the calibration unit serves as the nth switch signal output terminal of the common-mode voltage calibration circuit; the calibration unit is configured to control one or more high-level output terminals therein to switch to output a low level when the current common-mode voltage inside the common-mode voltage calibration circuit is less than the reference voltage; and to control one or more low-level output terminals therein to switch to output a high level when the current common-mode voltage inside the common-mode voltage calibration circuit is greater than the reference voltage; The control end of the second PMOS array is connected to the output end of the calibration unit; The transimpedance amplifier circuit includes a transimpedance amplifier, which includes two amplification branches. The amplification branches include a first PMOS array for adjusting the common-mode voltage component in the output of the transimpedance amplifier circuit, and the control end of the first PMOS array is connected to the switching signal output end of the common-mode voltage calibration circuit.

2. The continuous time linear equalizer according to claim 1, wherein The transimpedance amplifier circuit further includes a first resistor, a second resistor, a first inductor, and a second inductor; One end of the first inductor is connected to the first output end of the transimpedance amplifier, and one end of the second inductor is connected to the second output end of the transimpedance amplifier; One end of the first resistor is connected to the first input end of the transimpedance amplifier; One end of the second resistor is connected to the second input end of the transimpedance amplifier, and the other end of the second resistor is connected to the other end of the second inductor; The control end of the transimpedance amplifier is connected to the switch signal output end of the common-mode voltage calibration circuit.

3. The continuous time linear equalizer according to claim 2, wherein: The transimpedance amplifier further includes a first current source, and the amplifying branch further includes a first NMOS transistor; The source of the first PMOS array is connected to a corresponding power supply; The drain of the first PMOS array is connected to the drain of the first NMOS transistor, and a terminal is connected between the two to serve as the output end of the transimpedance amplifier; The gate of the first PMOS array is connected to the gate of the first NMOS transistor, and a terminal is connected between the two to serve as the input end of the transimpedance amplifier; The source of the first NMOS transistor is connected to one end of the first current source, and the other end of the first current source is grounded.

4. The continuous time linear equalizer according to claim 3, wherein: The first PMOS array includes N first PMOS transistors and N second PMOS transistors; The sources of the N first PMOS transistors serve together as the source of the first PMOS array and are connected to a corresponding power supply; The drain of the nth first PMOS transistor is connected to the source of the nth second PMOS transistor, 1≤n≤N; The drains of the N second PMOS transistors serve together as the drain of the first PMOS array and are connected to the drain of the first NMOS transistor; The gates of the N second PMOS transistors serve together as the gate of the first PMOS array and are connected to the gate of the first NMOS transistor; The gate of the nth first PMOS transistor serves as the nth control terminal of the first PMOS array and is connected to the switch signal output terminal of the common-mode voltage calibration circuit.

5. The continuous time linear equalizer according to claim 1, wherein The second PMOS array includes N third PMOS transistors and N fourth PMOS transistors; The sources of the N third PMOS transistors serve together as the source of the second PMOS array and are connected to a corresponding power supply; The drain of the nth third PMOS tube is connected to the source of the nth fourth PMOS tube; The drains of the N fourth PMOS transistors serve together as the drain of the second PMOS array and are connected to the drain of the second NMOS transistor; The gates of the N fourth PMOS transistors serve together as the gate of the second PMOS array and are connected to the gate of the second NMOS transistor; The gate of the nth third PMOS transistor serves as the nth control terminal of the second PMOS array and is connected to the switch signal output terminal of the common-mode voltage calibration circuit.

6. The continuous time linear equalizer according to claim 1, wherein The transconductance amplifier circuit includes a third NMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third current source, a fourth current source, a source degeneration resistor, and a source degeneration capacitor; The source of the fifth PMOS transistor and the source of the sixth PMOS transistor are connected to corresponding power supplies; A connection terminal is led out from the connection between the gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor, serving as a bias voltage access terminal of the transconductance amplifier circuit; The drain of the fifth PMOS transistor is connected to the drain of the third NMOS transistor, and a connection terminal is led out at the connection between the two to serve as the first output end of the transconductance amplifier circuit; The drain of the sixth PMOS transistor is connected to the drain of the fourth NMOS transistor, and a connection terminal is led out at the connection between the two to serve as the second output end of the transconductance amplifier circuit; The gate of the third NMOS transistor serves as the first input terminal of the transconductance amplifier circuit, and the gate of the fourth NMOS transistor serves as the second input terminal of the transconductance amplifier circuit; The source of the third NMOS transistor is connected to one end of the third current source, the source of the fourth NMOS transistor is connected to one end of the fourth current source, and the other end of the third current source and the other end of the fourth current source are grounded; One end of the source degeneration resistor is connected to the source of the third NMOS transistor, and the other end of the source degeneration resistor is connected to the source of the fourth NMOS transistor; One end of the source degeneration capacitor is connected to the source of the third NMOS transistor, and the other end of the source degeneration capacitor is connected to the source of the fourth NMOS transistor.

7. The continuous time linear equalizer according to claim 6, wherein: The transconductance amplifier circuit further includes a third resistor, a fourth resistor, a first capacitor and a second capacitor; One end of the third resistor is connected to the gate of the fifth PMOS transistor, and the other end of the third resistor is connected to the bias voltage input terminal; One end of the fourth resistor is connected to the gate of the sixth PMOS transistor, and the other end of the fourth resistor is connected to the bias voltage input terminal; One end of the first capacitor is connected to the gate of the fifth PMOS transistor, and the other end of the first capacitor is connected to the gate of the third NMOS transistor; One end of the second capacitor is connected to the gate of the sixth PMOS transistor, and the other end of the second capacitor is connected to the gate of the fourth NMOS transistor.

8. An electronic device, characterized in that: The continuous time linear equalizer comprises the continuous time linear equalizer according to any one of claims 1-7.

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