Flash memory device and preparation method thereof

Abstract

The invention discloses a flash memory device and a preparation method thereof, and the method comprises the steps: providing a substrate, forming a plurality of gate structures on the substrate, forming a source region and a drain region on the two sides of the gate structures, and preparing a hard mask layer on the gate structures; filling a doped conductive layer with a first thickness in the source region and the drain region, wherein the first thickness is smaller than the thickness of the gate structure; arranging a photomask on the doped conductive layer of the gate structure and the source region, and removing the doped conductive layer on the drain region; the photomask and the hard mask layer are removed; and forming a self-aligned silicide layer on the gate structure, the doped conductive layer of the source electrode region and the drain electrode region. The method has the advantages that the resistivity of the Source Line is greatly reduced, and the problems of overhigh voltage drop, overhigh power consumption and the like caused by overhigh resistivity of the Source Line are avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and particularly to a flash memory device and a method for manufacturing the same. Background Art

[0002] Currently, ETOX (EPROM Tunnel Oxide) Flash on the market usually requires the common connection of the Source Line to achieve the effects of convenient control and area saving. In traditional ETOX Flash, the etching process is usually used to remove all the OX (STI) on the Source Line to expose the Si, so as to realize the common connection of the Source Line. At the same time, the IMP (ion implantation process) is also used to reduce the resistance of this Source Line to form the final SAS (Safe Align Source). However, the resistance of the existing Source Line is still too high, which is likely to cause problems such as voltage drop and power consumption, greatly reducing the efficiency of the device. Therefore, how to effectively reduce the resistance of the Source Line is a technical problem that needs to be solved urgently.

[0003] It can be understood that the above statements only provide the background art related to the present invention and do not necessarily constitute the prior art. Summary of the Invention

[0004] Based on the foregoing technical problems, the object of the present invention is to provide a flash memory device and a method for manufacturing the same. The method innovatively uses a doped conductive layer filling and forms a Salicide on the basis of the doped conductive layer to form a common connection Source Line of ETOX. This method solves the problem of too high resistance of the common connection Source end of ETOX Flash, thereby avoiding the influence of the Source Line on the performance of ETOX Flash (such as voltage drop, power consumption, etc.).

[0005] To achieve the above object, the present invention is realized through the following technical solutions:

[0006] A method for manufacturing a flash memory device, comprising:

[0007] Providing a substrate, forming a plurality of gate structures and source regions and drain regions located on both sides of the gate structures on the substrate, and preparing a hard mask layer on the gate structures;

[0008] Filling a doped conductive layer with a first thickness in the source region and the drain region, the first thickness being less than the thickness of the gate structure;

[0009] A photomask is disposed on the gate structure and the doped conductive layer of the source region, and the doped conductive layer on the drain region is removed;

[0010] The photomask and the hard mask layer are removed;

[0011] A self-aligned silicide layer is formed on the gate structure, the doped conductive layer of the source region, and the drain region.

[0012] Optionally, filling the source region and the drain region with a doped conductive layer of a first thickness includes:

[0013] Filling the source region and the drain region with the doped conductive layer;

[0014] Processing the doped conductive layer filled in the source region and the drain region so that the top surface of the doped conductive layer is flush with the top surface of the hard mask layer;

[0015] Removing a part of the doped conductive layer in the source region and the drain region so that the source region and the drain region have a doped conductive layer of a first thickness.

[0016] Optionally, using CMP to process the doped conductive layer filled in the source region and the drain region so that the top surface of the doped conductive layer is flush with the top surface of the hard mask layer;

[0017] Removing a part of the doped conductive layer in the source region and the drain region through an etching process.

[0018] Optionally, the range of the first thickness is greater than 1000 angstroms and less than 2000 angstroms.

[0019] Optionally, the doped conductive layer includes doped amorphous silicon.

[0020] Optionally, the gate structure includes:

[0021] A tunneling oxide layer, a floating gate layer, an ONO structure, and a control gate layer formed in sequence on the substrate.

[0022] Optionally, a flash memory device, the flash memory device is prepared by the preparation method of the foregoing flash memory device, and the flash memory device includes:

[0023] A substrate;

[0024] A gate structure formed on the substrate and source regions and drain regions located on both sides of the gate structure, and a doped conductive layer is formed on the source region;

[0025] A self-aligned silicide layer formed on the gate structure, the doped conductive layer of the source region, and the drain region.

[0026] Optionally, the gate structure includes: a tunneling oxide layer, a floating gate layer, an ONO structure, and a control gate layer, which are sequentially formed on the substrate.

[0027] The present invention has the following advantages compared with the prior art:

[0028] In a flash memory device and a manufacturing method thereof according to the present invention, the method innovatively uses a doped conductive layer filling and forms a Salicide on the basis of the doped conductive layer to form a common-connected Source Line of ETOX. Compared with the Source Line in the hundreds of ohms level formed by the traditional method, the resistivity of the Source Line formed by the manufacturing method of the present invention is in the single-digit ohm level, which is hundreds of times smaller than the resistivity of the Source Line formed by the traditional solution, greatly reducing problems such as power consumption and voltage drop caused by too high resistance of the Source Line. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solution of the present invention, the drawings required for description will be briefly introduced below. Obviously, the drawings in the following description are an embodiment of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts:

[0030] Figures 1a to 1c It is a schematic diagram of the formation of a traditional ETOX Flash Source Line;

[0031] Figures 2a to 2d It is a schematic diagram of the manufacturing process of a traditional ETOX Flash;

[0032] Figure 3 It is a schematic diagram of the manufacturing method of a flash memory device according to the present invention;

[0033] Figures 4a to 4f It is a schematic diagram of the manufacturing process of a flash memory device according to the present invention;

[0034] Figure 5 It is a cross-sectional schematic diagram of the Source Line direction of a flash memory device according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0036] It should be noted that in this article, the terms "include", "comprise", "have" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or elements inherent to such process, method, article or terminal device. Without further limitation, the elements defined by the statement "include..." or "comprise..." do not exclude the existence of additional elements in the process, method, article or terminal device including the said elements.

[0037] It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, only for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0038] As Figures 1a to 1c shown, it is a schematic diagram of the formation of a traditional ETOX Flash Source Line. As Figure 1a shown, the formation of the isolation trench (STI) 110 is shown. The isolation trench 110 is filled with an isolation material (usually a kind of SiO2) to achieve an isolation effect. Then, the isolation material in the isolation trench 110 is removed through an etching process (please refer to Figure 1b ), and at this time, the entire Si is exposed on the surface, achieving the result of the common connection of the entire Source Line (source line). However, the resistance of the Source Line is very large at this time. Usually, an IMP process is used to perform ion implantation to form a doped layer 120 to reduce the resistance of the Source Line, thereby forming the final SAS (please refer to Figure 1c ).

[0039] Based on the above method, as Figures 2a to 2d shown, when preparing a traditional ETOX Flash, a hard mask layer 220 (Hard Mask Layer) is formed on the top of the gate structure (Gate) 210, and a photomask 230 is added to block the hard mask layer 220 and the drain region 240 to remove the oxide, i.e., the isolation material, in the Source Line STI part, forming a Si-based Source Line as Figure 2a shown. In order to increase the conductivity, at the same time, the photomask 230 is used for heavy doping to reduce the SourceLine resistance, and IMP ion implantation is performed on the Source Line to achieve heavy doping, so that the resistivity of the Source Line drops to the order of several hundred. Subsequently, the photomask 230 (please refer to Figure 2b ) and the hard mask layer 220 (please refer to Figure 2c), and form Salicide (self-aligned silicide layer) 250 at the end of the gate structure 210 and the drain region 240 respectively (please refer to Figure 2d ), so as to prepare for the subsequent CT (Contact Trench) connection. However, in the ETOX Flash formed based on the above method, the resistance of the SourceLine is still too large, thus affecting the performance of the Flash (such as voltage drop, power consumption, etc.).

[0040] Based on the above, the present invention proposes a method for manufacturing a flash memory device. This method breaks through the limitation of using ion implantation to prepare the Source Line in the traditional method, and innovatively uses a doped conductive layer 360 filled and forms a Salicide (self-aligned silicide layer) 380 on the basis of the doped conductive layer 360 to form a common-connected Source Line of ETOX. Compared with the traditional process, the resistance of the common-connected Source Line formed in the method for manufacturing a flash memory device of the present invention is greatly reduced, effectively reducing the loss on the circuit, and meeting the requirements of the Array (memory array) of the new generation of ETOX Flash.

[0041] Specifically, as Figure 3 、 Figures 4a to 4f Combined with the figure shown, a method for manufacturing a flash memory device of the present invention includes:

[0042] S1. Provide a substrate 310, form a plurality of gate structures 320 and source (Source, abbreviated as S) regions 330 and drain (Drain, abbreviated as D) regions 340 located on both sides of the gate structures 320 on the substrate 310, and prepare a hard mask layer 350 on the gate structures 320. Among them, the top surface of the gate structure 320 is higher than the top surfaces of the source region 330 and the drain region 340.

[0043] As Figure 4a shown, in an embodiment, the gate structure 320 includes: a tunneling oxide layer (not shown in the figure), a floating gate layer (Floating Gate, abbreviated as FG) 321, an ONO structure 322, and a control gate layer (Control Gate, abbreviated as CG) 323 formed on the substrate 310 in sequence from bottom to top. In this embodiment or some other embodiments, the ONO structure 322 is formed by stacking an oxide layer, a nitride layer, and an oxide layer (OXIDE - SIN - OXIDE) from bottom to top. On the other hand, the hard mask layer 350 can be SIN, which is used to protect the gate structure 320 (especially the control gate layer 323) to avoid damage to the gate structure 320 in the subsequent process flow. It can be understood that in this embodiment, the processes of forming the gate structure 320 and the hard mask layer 350 are the same as those in the prior art, and will not be elaborated here.

[0044] S2. Fill a doped conductive layer 360 with a first thickness in the source region 330 and the drain region 340, where the first thickness is less than the thickness of the gate structure 320.

[0045] In one embodiment, after the gate structure 320 and the hard mask layer 350 of ETOX are formed, S2 includes: S21. Fill a doped conductive layer 360 in the source region 330 and the drain region 340; S22. Process the doped conductive layer 360 filled in the source region 330 and the drain region 340 so that the top surface of the doped conductive layer 360 is flush with the top surface of the hard mask layer 350 (please refer to Figure 4b ); S23. Remove a part of the doped conductive layer 360 in the source region 330 and the drain region 340 so that the source region 330 and the drain region 340 have a doped conductive layer 360 with a first thickness (please refer to Figure 4c ).

[0046] In practical applications, due to factors such as actual process limitations, the upper surface of the doped conductive layer 360 filled in the source region 330 and the drain region 340 in S21 usually protrudes above the upper surface of the hard mask layer 350. Based on this, in S22, a CMP (chemical mechanical polishing) process or other planarization process is performed on the doped conductive layer 360 filled in the source region 330 and the drain region 340, and the CMP process stops at the top surface of the hard mask layer 350 so that the top surface of the doped conductive layer 360 is flush with the top surface of the hard mask layer 350 (on the same horizontal plane) (please refer to Figure 4b ). Further, in S23, without adding any photomask, using the different selectivity ratios of the hard mask layer 350 and the doped conductive layer 360, a full-chip etching is performed to remove a part of the doped conductive layer 360 in the source region 330 and the drain region 340, and at the same time, the hard mask layer 350 (SIN) will not be lost much. That is, in S23, a part of the doped conductive layer 360 in the source region 330 and the drain region 340 is etched away through an etching process so that the source region 330 and the drain region 340 have a doped conductive layer 360 with a first thickness (please refer to Figure 4c ). It can be understood that the specific steps of S2 are not limited to the above, and under the condition that technical conditions permit, other methods can also be used to implement S2.

[0047] In the present invention, the doped conductive layer 360 is a material layer on which a Salicide 380 layer can be formed. In this embodiment, the doped conductive layer 360 includes doped amorphous silicon (Poly) (such as doped with phosphorus). In practical applications, the thickness range of the gate structure 320 is 2000 angstroms to 2500 angstroms. Optionally, the range of the first thickness is greater than 1000 angstroms and less than 2000 angstroms.

[0048] S3. Provide a photomask 370 on the doped conductive layer 360 of the gate structure 320 and the source region 330, and remove the doped conductive layer 360 on the drain region 340.

[0049] As Figure 4d shown, in S3, by using the shielding effect of the photomask 370, i.e., photoresist, on the gate structure 320 and the source region 330, the doped conductive layer 360 of the drain region 340, i.e., the drain end, is removed through an etching process, so that only the source region 330, i.e., the source end, has the doped conductive layer 360, in order to form Salicide 380 subsequently.

[0050] S4. Remove the photomask 370 and the hard mask layer 350 (please refer to Figure 4e ).

[0051] In practical applications, the hard mask layer 350 can be removed through an acid bath etching process. Of course, other existing methods can also be used for removal, and the present invention does not limit this. Similarly, the present invention does not limit the method for removing the photomask 370.

[0052] S5. Form Salicide 380 on the gate structure 320, the doped conductive layer 360 of the source region 330, and the drain region 340 (please refer to Figure 4f ). As Figure 5 shown, it is a cross-sectional schematic diagram in the Source Line direction of a flash memory device prepared by using the method for preparing a flash memory device of the present invention.

[0053] As described above, in the method for manufacturing a flash memory device according to the present invention, the filling doped conductive layer 360 is innovatively utilized, and the Salicide 380 is formed on the basis of the doped conductive layer 360 to form the common-connected Source Line of the ETOX. Compared with the traditional method, the manufacturing method of the present invention changes the structure of the ETOX Source end. Without adding a photomask 370, the present invention utilizes the existing process conditions to form the Salicide 380, that is, the Source Line, with a resistivity basically in the single digits. Compared with the Source Line with a resistivity in the hundreds of ohms formed by ion implantation in the traditional solution, the resistivity of the Source Line formed in the present invention is reduced by several hundred times, greatly reducing the resistivity of the Source Line and avoiding problems such as voltage drop and excessive power consumption caused by too high resistivity of the Source Line.

[0054] Furthermore, in the method for manufacturing a flash memory device according to the present invention, while manufacturing the Source Line, an effective method is used to remove the doped conductive layer 360 at the drain end, so that the drain end can still form the Salicide 380 on the AA (active region) as an independently controlled drain end, meeting the requirements of the device and the circuit.

[0055] Based on the same inventive concept, the present invention also provides a flash memory device, which includes: a substrate 310; a gate structure 320 formed on the substrate 310, and source regions 330 and drain regions 340 located on both sides of the gate structure 320, and a doped conductive layer 360 is formed on the source regions 330; a self-aligned silicide layer formed on the gate structure 320, the doped conductive layer 360 of the source regions 330, and the drain regions 340.

[0056] Among them, the gate structure 320 includes: a tunneling oxide layer, a floating gate layer 321, an ONO structure 322, and a control gate layer 323 formed on the substrate 310 in sequence from bottom to top.

[0057] It can be understood that along the horizontal direction, isolation layers are provided between adjacent functional layers of the flash memory device for isolation. For example, isolation layers are provided on both sides of the floating gate layer 321 and the control gate layer 323 to electrically isolate them from the conductive doped layer, thereby ensuring the performance of the flash memory device.

[0058] In summary, in a flash memory device and a method for manufacturing the same according to the present invention, the method innovatively utilizes a filled doped conductive layer 360 and forms a Salicide 380 on the basis of the doped conductive layer 360 to form a common-connected SourceLine of ETOX. Compared with the Source Line with a resistivity in the hundreds of ohms level formed by the traditional method, the resistivity of the Source Line formed by the manufacturing method of the present invention is in the single-digit level, which is several hundred times smaller than the resistivity of the Source Line formed by the traditional solution, greatly reducing the resistivity of the Source Line and avoiding problems such as voltage drop and excessive power consumption caused by too high resistivity of the Source Line.

[0059] Furthermore, the manufacturing method is highly cost-effective and is easily implemented in the manufacturing of ETOX Flash. The method effectively utilizes the existing mature processes, solves the problem of too large Source Line resistance, and at the same time does not add an additional photomask, which plays a huge role in solving voltage drop and reducing power consumption.

[0060] Furthermore, in the manufacturing method of the flash memory device of the present invention, while manufacturing the Source Line, an effective method is used to remove the doped conductive layer 360 at the drain end, so that a Salicide 380 can still be formed on the AA at the drain end as an independently controlled drain end, meeting the requirements of the device and the circuit.

[0061] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and alternatives to the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A method for preparing a flash memory device, characterized in that: Include: Providing a substrate, forming a plurality of gate structures and a source region and a drain region located on both sides of the gate structures on the substrate, and preparing a hard mask layer on the gate structures; Filling the source region and the drain region with a doped conductive layer having a first thickness, wherein the first thickness is less than a thickness of the gate structure; Disposing a photomask on the gate structure and the doped conductive layer in the source region to remove the doped conductive layer on the drain region; removing the photomask and the hard mask layer; A salicide layer is formed on the gate structure, the doped conductive layer in the source region, and the drain region.

2. The method for preparing a flash memory device according to claim 1, wherein: Filling the source region and the drain region with a doped conductive layer having a first thickness comprises: Filling the doped conductive layer into the source region and the drain region; Processing the doped conductive layer filled in the source region and the drain region so that the top surface of the doped conductive layer is flush with the top surface of the hard mask layer; Part of the doped conductive layer in the source region and the drain region is removed so that the source region and the drain region have a doped conductive layer with a first thickness.

3. The method for preparing a flash memory device according to claim 2, wherein: Processing the doped conductive layer filled in the source region and the drain region by CMP so that the top surface of the doped conductive layer is flush with the top surface of the hard mask layer; Part of the doped conductive layer in the source region and the drain region is removed by an etching process.

4. The method for preparing a flash memory device according to claim 1, wherein: The first thickness is in a range of greater than 1000 angstroms and less than 2000 angstroms.

5. The method for preparing a flash memory device according to claim 1, wherein: The doped conductive layer includes doped amorphous silicon.

6. The method for preparing a flash memory device according to claim 1, wherein: The gate structure comprises: A tunneling oxide layer, a floating gate layer, an ONO structure and a control gate layer are sequentially formed on the substrate.

7. A flash memory device, characterized in that: The flash memory device is prepared by the flash memory device preparation method according to any one of claims 1 to 6, and the flash memory device comprises: substrate; A gate structure formed on the substrate and a source region and a drain region located on both sides of the gate structure, wherein a doped conductive layer is formed on the source region; A salicide layer is formed on the gate structure, the doped conductive layer in the source region, and the drain region.

8. The flash memory device according to claim 7, wherein: The gate structure comprises: A tunneling oxide layer, a floating gate layer, an ONO structure and a control gate layer are sequentially formed on the substrate.

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