A high-efficiency thermal management planar gate silicon carbide VDMOS and its preparation method

Abstract

The present invention provides a high-efficiency thermal management planar gate silicon carbide VDMOS and a preparation method thereof. The method comprises: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; performing epitaxial growth on the side of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, and ion implanting to respectively form a first P-type source region, a second P-type source region, a P-type well region, a gate protection region, and an N-type source region; reforming the barrier layer, etching, and depositing metal to form a Schottky metal layer; reforming the barrier layer, etching, and depositing metal to form an insulating dielectric layer; reforming the barrier layer, etching, and depositing metal to form a gate metal layer; reforming the barrier layer, etching, and depositing metal to form a source metal layer; removing the barrier layer to complete the preparation, and designing a Schottky metal layer in contact with the N-type source region, thereby reducing the source contact resistance of the device, reducing heat generation, and improving the thermal management capability of the device.

Description

Technical Field

[0001] The present invention relates to a high-efficiency thermal management planar gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS devices have lower thermal management risks due to their wide bandgap and high thermal conductivity. However, the mainstream gate metal is aluminum. The thermal conductivity of gate metal alloys is generally 180-190W / (m·K), which is similar to that of doped silicon carbide materials (120-270W / (m·K)). Therefore, the gate metal has limited effect on the thermal management of silicon carbide VDMOS devices. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a high-efficiency thermal management planar gate silicon carbide VDMOS and a preparation method thereof. The Schottky metal designed to be in lateral contact with the N-type source region reduces the source contact resistance of the device, reduces heat generation, and improves the thermal management capability of the device.

[0004] In a first aspect, the present invention provides a method for preparing a high-efficiency thermal management planar gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; and epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a first P-type source region and a second P-type source region;

[0007] Step 3: remove the barrier layer in step 2, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a P-type well region and a gate protection region respectively;

[0008] Step 4: remove the barrier layer in step 3, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form an N-type source region;

[0009] Step 5: removing the barrier layer of step 4, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer to the upper side of the first P-type source region, and depositing metal to form a Schottky metal layer;

[0010] Step 6: remove the barrier layer of step 5, re-form the barrier layer, etch the barrier layer to form a through hole, and deposit to form an insulating dielectric layer;

[0011] Step 7: removing the barrier layer of step 6, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a gate metal layer;

[0012] Step 8: remove the barrier layer of step 7, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0013] In a second aspect, the present invention provides a high-efficiency thermal management planar gate silicon carbide VDMOS, which is prepared using the method for preparing a high-efficiency thermal management planar gate silicon carbide VDMOS described in the first aspect.

[0014] The advantages of the present invention are:

[0015] First, the present invention constructs a Schottky metal layer in contact with the N-type source region, achieving metal contact with the N-type source region in both the top and lateral directions, which can effectively reduce the source ohmic contact resistance of the device, reduce the on-resistance of the device, and reduce the heat source of the device. The Schottky metal layer directly contacts the drift layer, the first P-type source region, and the second P-type source region inside the device, reducing the on-resistance from the source metal layer to the body diode of the device and reducing the heat source of the device.

[0016] Second, the Schottky metal layer in contact with the N-type source region in the present invention constructs a low thermal resistance path from the device body to the source metal layer. The device parasitic body diode can dissipate heat through the low thermal resistance channel of the Schottky metal layer, thereby increasing the metal contact area between the N-type source region and the device surface, reducing the source thermal resistance of the device, and thus improving the thermal management capability of the device.

[0017] 3. The present invention constructs a composite body diode structure in the device body diode area, with a Schottky metal layer on the top, and a first P-type source region, a second P-type source region and a drift region distributed side by side at the bottom of the Schottky metal layer. This reduces the freewheeling loss while ensuring the freewheeling capability of the device body diode. When the drain is subjected to a large voltage, the drift layer will form a space charge region with the first P-type source region and the second P-type source region, which can improve the voltage resistance of the parasitic Schottky diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0019] Figure 1 This is a schematic diagram of a high-efficiency thermal management planar gate silicon carbide VDMOS according to the present invention.

[0020] Figure 2 This is a cross-sectional view of the process of a high-efficiency thermal management planar gate silicon carbide VDMOS of the present invention Figure 1 .

[0021] Figure 3 This is a cross-sectional view of the process of a high-efficiency thermal management planar gate silicon carbide VDMOS of the present invention Figure 2 .

[0022] Figure 4 This is a cross-sectional view of the process of a high-efficiency thermal management planar gate silicon carbide VDMOS of the present invention Figure 3 .

[0023] Figure 5 This is a cross-sectional view of the process of a high-efficiency thermal management planar gate silicon carbide VDMOS of the present invention Figure 4 .

[0024] Figure 6 This is a cross-sectional view of the process of a high-efficiency thermal management planar gate silicon carbide VDMOS of the present invention Figure 5 .

[0025] Figure 7 This is a cross-sectional view of the process of a high-efficiency thermal management planar gate silicon carbide VDMOS of the present invention Figure 6 .

[0026] Figure 8 This is a cross-sectional view of the process of a high-efficiency thermal management planar gate silicon carbide VDMOS of the present invention Figure 7 .

[0027] Figure 9 This is a cross-sectional view of the process of a high-efficiency thermal management planar gate silicon carbide VDMOS of the present invention Figure 8 .

[0028] Figure 10 This is a cross-sectional view of the process of a high-efficiency thermal management planar gate silicon carbide VDMOS of the present invention Figure 9 . DETAILED DESCRIPTION

[0029] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0031] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0032] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, an element or feature described as "under" or "beneath" or "beneath" the other elements would be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "under" may encompass both the upper and lower orientations. Additionally, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0033] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] like Figures 1 to 10 As shown, the embodiment of the present application provides a method for preparing a high-efficiency thermal management planar gate silicon carbide VDMOS, comprising the following steps:

[0035] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 9; and epitaxially growing on the side of the silicon carbide substrate 1 to form a drift layer 2;

[0036] Step 2: forming a barrier layer 100 on the drift layer 2, etching the barrier layer 100 to form a through hole, and implanting ions to form a first P-type source region 22 and a second P-type source region 23;

[0037] Step 3: removing the barrier layer 100 in step 2, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form a P-type well region 5 and a gate protection region 211;

[0038] Step 4: removing the barrier layer 100 in step 3, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form an N-type source region 4;

[0039] Step 5: remove the barrier layer 100 of step 4, re-form the barrier layer 100, etch the barrier layer 100 to form a through hole, etch the drift layer 2 to the upper side of the first P-type source region 22, and deposit metal to form a Schottky metal layer 3;

[0040] Step 6: removing the barrier layer 100 of step 5, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and depositing to form an insulating dielectric layer 6;

[0041] Step 7: removing the barrier layer 100 of step 6, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and depositing metal to form a gate metal layer 7;

[0042] Step 8: remove the barrier layer 100 of step 7, re-form the barrier layer 100, etch the barrier layer 100 to form a through hole, deposit metal to form a source metal layer 8, remove the barrier layer 100, and complete the preparation.

[0043] In this embodiment, preferably, the Schottky metal layer 3 , the N-type source region 4 , the P-type well region 5 and the gate protection region 211 have the same thickness.

[0044] In this embodiment, preferably, the width of the first P-type source region 22 is smaller than the width of the second P-type source region 23 .

[0045] In this embodiment, preferably, the doping concentration of the P-type well region 5 is lower than the doping concentration of the drift layer 2 .

[0046] In this embodiment, preferably, the doping concentration of the P-type well region 5 is lower than the doping concentration of the N-type source region 4 ; the doping concentration of the P-type well region 5 is lower than the doping concentration of the second P-type source region 23 .

[0047] In this embodiment, preferably, the silicon carbide substrate 1 and the drift layer 2 are both N-type, and the gate protection area 211 is P-type.

[0048] like Figure 1 As shown, the planar gate silicon carbide VDMOS obtained by the above manufacturing method includes:

[0049] Silicon carbide substrate 1,

[0050] a drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, the drift layer 2 is provided with a raised portion 21, and a gate protection region 211 is provided within the raised portion 21; a first P-type source region 22 and a second P-type source region 23 are provided on the drift layer 2, and the second P-type source region 23 is located inside the first P-type source region 22;

[0051] a Schottky metal layer 3 , wherein the lower side of the Schottky metal layer 3 is connected to the upper side of the drift layer 2 , the upper side of the first P-type source region 22 , and the second P-type source region 23 ;

[0052] An N-type source region 4, wherein the lower side of the N-type source region 4 is connected to the upper side of the second P-type source region 23, and the outer side of the N-type source region 4 is connected to the inner side of the Schottky metal layer 3;

[0053] A P-type well region 5, wherein the lower side of the P-type well region 5 is connected to the upper side of the second P-type source region 23, the outer side of the P-type well region 5 is connected to the N-type source region 4, and the inner side of the P-type well region 5 is connected to the outer side of the protrusion 21;

[0054] an insulating dielectric layer 6, wherein the lower side of the insulating dielectric layer 6 is respectively connected to the P-type well region 5, the raised portion 21 and the gate protection region 211;

[0055] a gate metal layer 7, wherein the lower side of the gate metal layer 7 is connected to the upper side of the insulating dielectric layer 6;

[0056] a source metal layer 8 , the source metal layer 8 being connected to the Schottky metal layer 3 and the N-type source region 4 ;

[0057] and a drain metal layer 9 , wherein the drain metal layer 9 is connected to the lower side of the silicon carbide substrate 1 .

[0058] In another embodiment of the present invention, the doping concentration of the silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of drift layer 2 is 1-8e17cm -3 , the doping concentration of the P-type well region 5 is 1-5e15cm -3 The doping concentrations of the first P-type source region 22 and the second P-type source region 23 are both 5-9e18cm -3The material of the insulating dielectric layer 6 can be silicon dioxide, and the doping concentration of the N-type source region 4 is 2-8e18cm -3 The Schottky metal layer 3 is made of the same material as the source metal layer 8, which is nanosilver with a thermal conductivity of 429W / (m·K). Embedded in the device structure, it can improve the thermal conductivity from the device to the source metal, improve the device's thermal management capabilities, improve the device's source thermal conductivity, and form a stronger contact with the bonding wire during device packaging, forming heat conduction from the device pad to the device packaging structure.

[0059] The doping concentration of the silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 9, thereby reducing the overall on-resistance of the device. The doping concentration of the drift layer 2 is a compromise between the reverse withstand voltage and on-resistance of the device. Due to the doping concentrations of the first P-type source region 22 and the second P-type source region 23, as well as the structural distribution of the Schottky metal layer 3, the doping concentration of the drift layer 2 can be increased while ensuring the withstand voltage of the device.

[0060] The doping concentration of the first P-type source region 22 and the second P-type source region 23 is designed for two reasons: first, to reduce the contact resistance between the first P-type source region 22 and the second P-type source region 23 and the Schottky metal layer 3, thereby reducing the conduction loss of the parasitic pn junction diode of the device; second, to reduce the diffusion speed of the space charge region located in the first P-type source region 22 and the second P-type source region 23 to the device gate and source when the drain voltage is high. The doping concentration of the P-type well region 5 is to reduce the gate-controlled charge of the device gate and improve the switching speed of the device.

[0061] The thickness of the silicon carbide substrate 1 of the device is 1 μm, and the thickness of the drift layer 2 is 50-80 μm. It is adjusted within the above range according to the different requirements for the withstand voltage characteristics of the device. The thickness of the first P-type source region 22 and the second P-type source region 23 are both 300 nm, and the thickness of the Schottky metal layer 3, the N-type source region 4, the P-type well region 5 and the gate protection region 211 are all 600 nm. This is to increase the longitudinal contact area between the Schottky metal layer 3 and the N-type source region 4, thereby reducing the ohmic contact resistance between the N-type source region 4 and the source metal layer 8 of the device, and reducing the device The on-resistance is increased, and the contact area between the internal structure of the device and the high thermal conductivity metal is increased, thereby improving the thermal management efficiency. The thickness of the gate protection area 211 is equal to the thickness and doping concentration of the P-type well region 5. This is to complete the production of the P-type well region 5 and the gate protection area 211 in a single process, reducing the number of process steps and reducing the device manufacturing cost. The Schottky metal layer 3 forms a Schottky junction with the drift layer 2, but the Schottky metal layer 3 forms an ohmic contact with the N-type source region 4. The thickness of the insulating dielectric layer 6 is 50nm, which is to ensure the switching characteristics of the device and control the gate charge.

[0062] The width of the first P-type source region 22 is 1 μm, the width of the drift layer 2 between the first P-type source region 22 and the second P-type source region 23 is 500 nm, the width of the second P-type source region is 2 μm, the width of the Schottky metal layer 3 is 2 μm, and the width of the N-type source region 4 is 1 μm. This design is to form an ohmic contact with the Schottky metal layer 3 above the second P-type source region 23 to avoid the formation of an ohmic conductive channel from the N-type source region 4 to the drift layer 2. The drift layer 2 between the first P-type source region 22 and the second P-type source region 23 is to construct a Schottky body diode and form a space charge region when the device is reversely withstand voltage to ensure the withstand voltage characteristics of the device;

[0063] The width of the P-type well region 5 is 500nm, the width of the insulating dielectric layer 6 is 4μm, the width of the gate metal layer 7 is 3μm, and the width of the gate protection region 211 is 1μm. This is to improve the reliability of the device gate, shield the gate-drain capacitance, and increase the switching speed of the device; the distance from the P-type well region 5 to the gate protection region 211 is 500nm, which is to improve the reliability of the device gate while ensuring that the device conductive channel is not affected.

[0064] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a high-efficiency thermal management planar gate silicon carbide VDMOS, characterized by: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; and epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a first P-type source region and a second P-type source region; Step 3: remove the barrier layer in step 2, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a P-type well region and a gate protection region respectively; Step 4: remove the barrier layer in step 3, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form an N-type source region; Step 5: removing the barrier layer of step 4, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer to the upper side of the first P-type source region, and depositing metal to form a Schottky metal layer; Step 6: remove the barrier layer of step 5, re-form the barrier layer, etch the barrier layer to form a through hole, and deposit to form an insulating dielectric layer; Step 7: removing the barrier layer of step 6, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a gate metal layer; Step 8: remove the barrier layer of step 7, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a high-efficiency thermal management planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thicknesses of the Schottky metal layer, the N-type source region, the P-type well region and the gate protection region are equal.

3. The method for preparing a high-efficiency thermal management planar gate silicon carbide VDMOS according to claim 1, characterized in that: The width of the first P-type source region is smaller than the width of the second P-type source region.

4. The method for preparing a high-efficiency thermal management planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type well region is lower than the doping concentration of the drift layer.

5. The method for preparing a high-efficiency thermal management planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type well region is less than the doping concentration of the N-type source region; and the doping concentration of the P-type well region is less than the doping concentration of the second P-type source region.

6. The method for preparing a high-efficiency thermal management planar gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate and the drift layer are both N-type, and the gate protection zone is P-type.

7. A highly efficient thermal management planar gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 6.

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