Semiconductor device

Abstract

The semiconductor device includes a base insulating layer. The gate structure extends in a first direction on the base insulating layer. The first source / drain structure and the second source / drain structure are arranged on one side of the gate structure and are spaced apart from each other in the first direction. An etch stop layer is disposed between a second peripheral source / drain region of the second source / drain structure and the second molding layer. The etch stop layer includes a material different from a material of the second peripheral source / drain region and the second molding layer. A first central source / drain region of the first source / drain structure has a first conductivity type, and a second central source / drain region of the second source / drain structure has a second conductivity type different from the first conductivity type.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0186071, filed with the Korean Intellectual Property Office on December 19, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor device. Background Art

[0003] With an increasing demand for semiconductor devices having high performance, high speed, and / or multi-functionality, the integration degree of semiconductor devices has increased. A backside power delivery network (BSPDN) structure in which power rails are disposed on a back surface of a wafer is being developed to provide a semiconductor device having a high integration degree. Additionally, in order to overcome limitations in operating characteristics due to a reduction in the size of a planar metal oxide semiconductor field effect transistor (FET) (MOSFET), research is being conducted to develop a semiconductor device including a fin field effect transistor (FinFET) having a three-dimensional channel. Summary of the Invention

[0004] Aspects of the inventive concept may lie in providing a semiconductor device having increased reliability.

[0005] According to an embodiment of the present disclosure, a semiconductor device includes a substrate insulating layer. A gate structure extends on the substrate insulating layer in a first direction. A first source / drain structure and a second source / drain structure are disposed on one side of the gate structure and are spaced apart from each other in the first direction. The first source / drain structure includes a first central source / drain region, a first peripheral source / drain region surrounding side and bottom surfaces of the first central source / drain region, and a first molding layer directly contacting a bottom surface of the first peripheral source / drain region. The second source / drain structure includes a second central source / drain region, a second peripheral source / drain region surrounding side and bottom surfaces of the second central source / drain region, and a second molding layer disposed under the second peripheral source / drain region. An etch stop layer is disposed between the second peripheral source / drain region and the second molding layer. The etch stop layer includes a material different from materials of the second peripheral source / drain region and the second molding layer. The first central source / drain region has a first conductivity type, and the second central source / drain region has a second conductivity type different from the first conductivity type.

[0006] According to an embodiment of the present disclosure, a semiconductor device includes a base insulating layer. A gate structure extends in a first direction on the base insulating layer. A plurality of source / drain structures are spaced apart from each other in the first direction on one side of the gate structure. The plurality of source / drain structures includes a first group of source / drain structures and a second group of source / drain structures. A backside contact plug penetrates the base insulating layer and is connected to the first group of source / drain structures. Each of the plurality of source / drain structures includes a central source / drain region and a peripheral source / drain region surrounding the central source / drain region. The second group of source / drain structures further includes a molding layer directly contacting a lower surface of the peripheral source / drain region.

[0007] According to an embodiment of the present disclosure, a semiconductor device includes: a gate structure extending in one direction; source / drain structures disposed outside the gate structure; a backside contact plug electrically connected to the source / drain structures and disposed below the source / drain structures; the source / drain structures including a central source / drain region and a peripheral source / drain region surrounding the central source / drain region; the peripheral source / drain region including a plurality of protrusions protruding toward the gate structure; the peripheral source / drain region including a first concentration of a non-silicon element; the central source / drain region including a first epitaxial layer including a second concentration of the non-silicon element, the second concentration being higher than the first concentration; the first epitaxial layer covering an inner surface of the peripheral source / drain region; a second epitaxial layer including a third concentration of the non-silicon element, the third concentration being higher than the second concentration; the second epitaxial layer disposed on the first epitaxial layer; and the backside contact plug directly contacting the peripheral source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features, and advantages of embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a schematic plan view showing a semiconductor device according to an exemplary embodiment.

[0010] Figure 2 and Figure 3 is a schematic cross-sectional view showing a semiconductor device according to an exemplary embodiment.

[0011] Figure 4 is a schematic plan view showing a semiconductor device according to an exemplary embodiment.

[0012] Figures 5 to 10 is a schematic plan view showing a semiconductor device according to an exemplary embodiment.

[0013] Figures 11A to 11B is a schematic process flowchart showing a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0014] Figures 12A to 12O is a view showing a process sequence of a method of manufacturing a semiconductor device according to an exemplary embodiment. Detailed Description

[0015] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings. Hereinafter, it is understood that, unless otherwise indicated, terms such as "on", "upper", "upper part", "upper surface", "under", "lower", "lower part", "lower surface", "side surface", etc. may be represented by reference numerals and referred to the accompanying drawings.

[0016] Figure 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment.

[0017] Figure 2 shows a schematic cross-sectional view of a semiconductor device illustrating an exemplary embodiment. Figure 2 shows a cross-section of the semiconductor device taken along lines I-I' and II-II'. For ease of explanation, only some components of the semiconductor device are shown in Figure 1 . Figure 1 Only some components of the semiconductor device are shown.

[0018] Referring to Figures 1 to 2 , in one embodiment, the semiconductor device 100 may include a substrate insulating layer 194, gate structures 160 longitudinally extending in one direction (e.g., the Y direction) on the substrate insulating layer 194 and each including a gate electrode 165, a channel structure 140 including first to fourth channel layers 141, 142, 143, and 144 disposed on the substrate insulating layer 194 and vertically spaced apart from each other (e.g., in the Z direction), a source / drain structure 150 contacting the channel structure 140, a backside contact plug 180 passing through the substrate insulating layer 194 (e.g., in the Z direction) and connected to the source / drain structure 150, and a lower interconnect 195 connected to the backside contact plug 180. The semiconductor device 100 may further include a first interlayer insulating layer 192 and a second interlayer insulating layer 196.

[0019] The substrate insulating layer 194 may have an upper surface extending in the X and Y directions. In one embodiment, the substrate insulating layer 194 may be a layer formed by removing and / or oxidizing a substrate 101 formed of a semiconductor material (see Figure 12A ) during a manufacturing process. In one embodiment, the substrate insulating layer 194 may be formed of an insulating material and may include, for example, an oxide, a nitride, or a combination thereof. According to an embodiment, the substrate insulating layer 194 may include a plurality of insulating layers.

[0020] In one embodiment, the gate structure 160 may be arranged to longitudinally extend in one direction (e.g., the Y direction) on the base insulating layer 194. The channel region of the transistor may be formed in the channel structure 140 intersecting with the gate electrode 165 of the gate structure 160. The gate structures 160 may be arranged to be spaced apart from each other in the X direction. In one embodiment, each of the gate structures 160 may include a gate dielectric layer 162, a gate spacer layer 164, and a gate electrode 165. In an exemplary embodiment, each of the gate structures 160 may further include a capping layer on the upper surface of the gate electrode 165.

[0021] The gate dielectric layer 162 may be disposed between the base insulating layer 194 and the gate electrode 165 and between the channel structure 140 and the gate electrode 165, and may be arranged to cover at least a portion of the surface of the gate electrode 165. For example, in one embodiment, the gate dielectric layer 162 may be arranged to surround the surface of the gate electrode 165 (such as the lateral side surface and the bottom surface of the gate electrode 165), and may expose the uppermost surface of the gate electrode 165. The gate dielectric layer 162 may extend between the gate electrode 165 and the gate spacer layer 164 (e.g., directly between the gate electrode 165 and the gate spacer layer 164). However, embodiments of the present disclosure are not necessarily limited thereto. The gate dielectric layer 162 may include an oxide, a nitride, or a high-k material. The high-k material may represent a dielectric material having a higher dielectric constant than the silicon oxide film (SiO2). In one embodiment, the high-k material may be, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicate (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicate (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminate (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminate (HfAl x O y ), and praseodymium oxide (Pr2O3). According to an embodiment, the gate dielectric layer 162 may have a multilayer structure.

[0022] In one embodiment, the gate electrode 165 may include a conductive material and may include, for example, metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN)), metal materials (such as aluminum (Al), tungsten (W), or molybdenum (Mo), etc.), and / or semiconductor materials (such as doped polysilicon), etc. According to an embodiment, the gate electrode 165 may have a multilayer structure. In one embodiment, the gate electrode 165 may be connected in one region to an upper contact plug disposed on the gate electrode 165.

[0023] The channel structure 140 may be disposed on the base insulating layer 194 to intersect with the gate structure 160. In one embodiment, each of the channel structures 140 may include a first channel layer to a fourth channel layer 141, 142, 143, and 144, and the first channel layer to the fourth channel layer 141, 142, 143, and 144 may be two or more channel layers arranged to be spaced apart from each other in the Z direction. The channel structure 140 may be connected to the source / drain structure 150. In one embodiment, the channel structure 140 may have a width in the X direction equal to or similar to the width of the gate structure 160. In a cross-section in the Y direction, among the first channel layer to the fourth channel layer 141, 142, 143, and 144, the channel layer disposed in the lower part may have a width equal to or greater than the width (e.g., the length in the Y direction) of the channel layer disposed in the upper part. In some embodiments, compared with the gate structure 160, the channel structure 140 may have a reduced width such that the side surfaces of the channel structure 140 are located below the gate structure 160 in the X direction (e.g., the side surfaces of the channel structure 140 may be located between the side surfaces of the gate structure 160 in the X direction).

[0024] In one embodiment, the channel structure 140 may be formed of a semiconductor material and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). However, the embodiments of the present disclosure are not necessarily limited thereto, and the number and shape of the channel layers forming one channel structure 140 may be changed in various embodiments.

[0025] In the semiconductor device 100 according to an embodiment, the gate electrode 165 may be disposed (e.g., in the Z direction) between the first channel layer to the fourth channel layer 141, 142, 143, and 144 of the channel structure 140 and disposed on the channel structure 140 (e.g., directly above the channel structure 140). Therefore, the semiconductor device 100 may include a transistor having an MBCFET TM (multi-bridge channel field effect transistor (FET)) structure, and a transistor having an MBCFET TM (multi-bridge channel field effect transistor (FET)) structure may be a gate-all-around field effect transistor.

[0026] The source / drain structure 150 may be disposed on both sides of the gate structure 160 to directly contact the channel structure 140. For example, in one embodiment, the source / drain structure 150 may be arranged to cover the side surfaces of each of the first to fourth channel layers 141, 142, 143, and 144 of the channel structure 140 in the X direction. The source / drain structure 150 may be connected to the backside contact plug 180 through the lower surface or the lower end of the source / drain structure 150. The lower region of the source / drain structure 150 may have a concave shape due to the backside contact plug 180. The source / drain structure 150 may be electrically connected to the lower interconnect 195 through the backside contact plug 180 and may receive power. In one embodiment, the upper surface of the source / drain structure 150 may be at a higher level than the lower surface of the gate electrode 165 on the channel structure 140. However, embodiments of the present disclosure are not necessarily limited thereto, and the upper surface of the source / drain structure 150 may be at an equal or similar level to the lower surface of the gate electrode 165 on the channel structure 140, and the level may be changed in various embodiments.

[0027] The source / drain structure 150 may include a peripheral source / drain region 152, a central source / drain region 154, and a central source / drain region 156 arranged in sequence from the bottom. In one embodiment, the central source / drain region may include a first epitaxial layer 154 and a second epitaxial layer 156. The peripheral source / drain region 152 may cover the side surfaces of each of the first to fourth channel layers 141, 142, 143, and 144 in the X direction, and may cover the side surfaces of the gate structure 160 below each of the first to fourth channel layers 141, 142, 143, and 144 in the X direction. The peripheral source / drain region 152 may cover the inner surface of the recessed region RC (see Figure 12F ) in which the source / drain structure 150 is provided, and may be arranged to be spaced apart from an adjacent peripheral source / drain region 152 by the backside contact plug 180. In one embodiment, the peripheral source / drain region 152 may include a plurality of protrusions 153 extending from the side surface of the peripheral source / drain region 152 facing the gate structure 160 and protruding toward the gate structure 160. Accordingly, the peripheral source / drain region 152 may have an outer surface protruding convexly toward the gate structure 160, and a bend may occur in the outer surface. The plurality of protrusions 153 may be arranged to protrude toward the gate structure 160 from below (e.g., in the X direction) each of the first to fourth channel layers 141, 142, 143, and 144 stacked vertically. In one embodiment, a part of the surface in the lower region of the peripheral source / drain region 152 may be in direct contact with the backside contact plug 180 and may have a curved shape following the shape of the backside contact plug 180.

[0028] The central source / drain regions (154 and 156) may cover the peripheral source / drain region 152 and may fill the recessed region RC (see Figure 12F ). In one embodiment, the lower surface of the central source / drain regions (154 and 156) may be in contact with the back-side contact plug 180 and may have a curved surface following the shape of the back-side contact plug 180. The central source / drain regions (154 and 156) may include a first epitaxial layer 154 covering a part of the upper surface of the back-side contact plug 180 and the inner surface of the peripheral source / drain region 152, and a second epitaxial layer 156 disposed on the first epitaxial layer 154 and covering the inner surface of the first epitaxial layer 154 and the upper surfaces of the peripheral source / drain region 152 and the first epitaxial layer 154.

[0029] In one embodiment, the source / drain structure 150 may include a semiconductor material (e.g., at least one of silicon (Si) and germanium (Ge)), and may also include impurities. The peripheral source / drain region 152, the first epitaxial layer 154, and the second epitaxial layer 156 may be epitaxial layers grown epitaxially and may have different compositions from each other. In one embodiment, the peripheral source / drain region 152, the first epitaxial layer 154, and the second epitaxial layer 156 may include the same non-silicon elements, but the concentrations of the non-silicon elements in each structure may be different from each other. For example, the peripheral source / drain region 152 may have a concentration of non-silicon elements that may be a first concentration, the first epitaxial layer 154 may have a concentration of non-silicon elements that may be a second concentration, and the second epitaxial layer 156 may have a concentration of non-silicon elements that may be a third concentration. In one embodiment, the third concentration may be greater than the second concentration, and the second concentration may be greater than the first concentration. The non-silicon element may be, for example, germanium (Ge) and / or a doping element.

[0030] In one embodiment, the semiconductor device 100 may be, for example, a p-type FET (pFET). In this embodiment, the source / drain structure 150 may include silicon germanium (SiGe), and the non-silicon element may be germanium (Ge). The source / drain structure 150 may include doping elements (such as impurities). In one embodiment, the impurities in the source / drain structure 150 of the semiconductor device 100 that may be a pFET may be at least one of boron (B), gallium (Ga), and indium (In).

[0031] The back contact plug 180 may be disposed under the source / drain structure 150. The back contact plug 180 may pass through the substrate insulating layer 194 (e.g., in the Z direction) and may be connected to the source / drain structure 150. The back contact plug 180 may be arranged such that a lower region of the source / drain structure 150 is partially recessed and is in direct contact with a recessed lower surface of the source / drain structure 150. The back contact plug 180 may have an upper surface that protrudes in an upward direction (e.g., an upper surface that protrudes in a direction toward the source / drain structure 150). In one embodiment, the upper end of the back contact plug 180 may be at a higher height than the lower end of the gate structure 160. In one embodiment, the upper surface of the back contact plug 180 may be in direct contact with the peripheral source / drain region 152 of the source / drain structure 150 and the central source / drain region (such as the lower surface of the first epitaxial layer 154). The height of the upper end of the back contact plug 180 may be higher than the height of the lower end of the source / drain structure 150. The back contact plug 180 may have a kink portion k having a minimum width between the upper end and the lower end of the back contact plug 180. In one embodiment, the distance H1 (e.g., the length in the Z direction) between the kink portion k and the upper end of the back contact plug 180 may be smaller than the distance H2 (e.g., the length in the Z direction) between the kink portion k and the lower end of the back contact plug 180. For example, the kink portion may be located between the upper end and the lower end of the back contact plug 180 and may be closer to the upper end of the back contact plug 180. The lower surface of the back contact plug 180 may be coplanar with the lower surface of the substrate insulating layer 194 (e.g., in the Z direction).

[0032] In one embodiment, the back contact plug 180 may include a metal-semiconductor compound layer 184 and a conductive layer 186. The metal-semiconductor compound layer 184 may be located on the upper end of the back contact plug 180 and may form at least a part of the upper surface of the back contact plug 180. The metal-semiconductor compound layer 184 may define the upper surface of the back contact plug 180. In one embodiment, the metal-semiconductor compound layer 184 may be disposed at least in a region where the back contact plug 180 is in direct contact with the source / drain structure 150. However, in an embodiment, the scope of the metal-semiconductor compound layer 184 need not be limited to the shown scope. The metal-semiconductor compound layer 184 may be, for example, a metal silicide layer. In one embodiment, the conductive layer 186 may form the back contact plug 180 together with the metal-semiconductor compound layer 184 and may be arranged to fill the contact hole CTH (see Figure 12N). The conductive layer 186 may include a metallic material (such as, aluminum (Al), tungsten (W), molybdenum (Mo), etc.). In an exemplary embodiment, the number and arrangement of the conductive layers constituting the back contact plug 180 may be changed. In some embodiments, the metal-semiconductor compound layer 184 may be omitted.

[0033] In this embodiment, since the peripheral source / drain region 152 may include a plurality of protrusions 153, the back contact plug 180 and the gate electrode 165 may be arranged to be stably spaced apart from each other. In one embodiment, when forming the back contact plug 180 (see Figure 12M ), the peripheral source / drain region 152 may be used as an etch stop element, the process may be simplified, and a semiconductor device with increased reliability may be provided.

[0034] The lower interconnect 195 may be connected to (e.g., directly connected to) the lower end or the lower surface of the back contact plug 180. The lower interconnect 195 may form a backside power delivery network (BSPDN) for applying power or ground voltage together with the back contact plug 180, and may also be referred to as a back power rail or an embedded power rail. For example, in one embodiment, the lower interconnect 195 may be a buried interconnect line that extends longitudinally in one direction (e.g., the Y direction) below the back contact plug 180. However, the embodiments of the present disclosure are not necessarily limited thereto, and the shape of the lower interconnect 195 may vary. For example, in some embodiments, the lower interconnect 195 may include a via region and / or a line region. The upper surface of the lower interconnect 195 may be coplanar with the upper surface of the second interlayer insulating layer 196. In one embodiment, the width of the upper surface of the lower interconnect 195 (e.g., the length in the X direction) may be larger than the width of the lower surface of the back contact plug 180 (e.g., the length in the X direction). In one embodiment, the width of the lower interconnect 195 may continuously increase from the upper part to the lower part of the lower interconnect 195. However, the embodiments of the present disclosure are not necessarily limited thereto. In one embodiment, the lower interconnect 195 may include a conductive material (e.g., at least one of tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), and molybdenum (Mo)).

[0035] The first interlayer insulating layer 192 may be provided to cover the upper surfaces of the source / drain structure 150 and the gate structure 160. The second interlayer insulating layer 196 may be provided to cover the lower surface of the base insulating layer 194 and surround the lower interconnect 195.

[0036] In one embodiment, the first interlayer insulating layer 192 and the second interlayer insulating layer 196 may include at least one of an oxide, a nitride, and a oxynitride, and may include, for example, a low-k material. According to an embodiment, each of the first interlayer insulating layer 192 and the second interlayer insulating layer 196 may include a plurality of insulating layers.

[0037] The semiconductor device 100 may be turned upside down and encapsulated with Figure 2 a structure such that the lower interconnect 195 is located in the upper part. However, embodiments of the present disclosure are not necessarily limited thereto, and the encapsulation form of the semiconductor device 100 may vary. Since the source / drain structure 150 may be connected to (e.g., electrically connected to) the lower interconnect 195 disposed in the lower part through the backside contact plug 180, the integration degree may be increased.

[0038] In the following description of the embodiments, for ease of description, descriptions overlapping with the above description with reference to Figure 1 and Figure 2 may be omitted.

[0039] Figure 3 is a schematic cross-sectional view showing a semiconductor device according to an exemplary embodiment.

[0040] Referring to Figure 3 , the peripheral source / drain region 152 of the semiconductor device 100A may cover the lower surface of the central source / drain regions (154 and 156), and the backside contact plug 180 and the central source / drain regions (154 and 156) may be spaced apart from each other (e.g., in the Z direction). In one embodiment, the peripheral source / drain region 152 of the semiconductor device 100A may cover a part of the side surface of the central source / drain regions (154 and 156). The upper surface of the backside contact plug 180 may be formed along the lower surface of the source / drain structure 150, and may have a shape protruding in the downward direction toward the lower interconnect 195. The protrusion length D1 of the protrusion 153 in the X direction between the end of the protrusion 153 and the peripheral source / drain region 152 and the distance D2 (e.g., the length in the Z direction) between the lower end of the central source / drain regions (154 and 156) and the lower end of the peripheral source / drain region 152 may be changed according to an embodiment. In one embodiment, the protrusion length D1 may be greater than the distance D2 between the lower end of the central source / drain regions (154 and 156) and the lower end of the peripheral source / drain region 152. In one embodiment, the protrusion length D1 may be less than or substantially equal to the distance D2 between the lower end of the central source / drain regions (154 and 156) and the lower end of the peripheral source / drain region 152.

[0041] Figure 4 is a schematic plan view showing a semiconductor device according to an exemplary embodiment.

[0042] Figure 5 A schematic cross-sectional view showing a semiconductor device according to an exemplary embodiment is shown. Figure 5 A cross-section of the semiconductor device taken along lines III-III' and IV-IV' is shown. For ease of explanation, only some components of the semiconductor device are shown in Figure 4 the semiconductor device. Figure 4 In

[0043] Referring to Figure 4 and Figure 5 , the semiconductor device 100B may include a first region R1 and a second region R2. According to an embodiment, the first region R1 and the second region R2 may be adjacent regions, or may be any regions spaced apart from each other. In the embodiment shown in Figure 4 , the first region R1 and the second region R2 may be spaced apart from each other in the Y direction. However, embodiments of the present disclosure are not necessarily limited thereto. In the first region R1, the semiconductor devices 100 and 100A described above with reference to Figures 1 to 3 may be provided. Among the configurations described with reference to Figures 1 to 3 , the source / drain structure 150, the backside contact plug 180, and the lower interconnect 195 may be referred to as a first source / drain structure 150, a first backside contact plug 180a, and a first lower interconnect 195a, respectively. The first source / drain structure 150 may have a first conductivity type, and the second source / drain structure 130 may have a second conductivity type different from the first conductivity type. For example, in an embodiment in which the first conductivity type of the first source / drain structure 150 in the first region R1 is P-type, the second conductivity type of the second source / drain structure 130 in the second region R2 may be N-type.

[0044] The second region R2 may include substantially the same configuration as the first region R1, except that a second source / drain structure 130, a plurality of inner spacers 138, a second backside contact plug 180b, and a second lower interconnect 195b are included and the first source / drain structure 150, the first backside contact plug 180a, and the first lower interconnect 195a are not included in the second region R2.

[0045] In one embodiment, the first source / drain structure 150 and the second source / drain structure 130 having different conductivity types have different structures according to each conductivity type, so that the reliability of the semiconductor device can be increased.

[0046] The second source / drain structure 130 may include a second peripheral source / drain region 132 and a second central source / drain region 134. The second peripheral source / drain region 132 may cover side surfaces of the first through fourth channel layers 141, 142, 143, and 144 in the X direction. The second peripheral source / drain regions 132 may be arranged to be spaced apart in the X direction by the second backside contact plug 180b in one second source / drain structure 130. A part of the surface in the lower region of the second peripheral source / drain region 132 may be in direct contact with the second backside contact plug 180b and may have a curved shape following the shape of the second backside contact plug 180b. In one embodiment, the second peripheral source / drain region 132 may include the same material as the first peripheral source / drain region 152 (e.g., silicon germanium (SiGe)), and may have the same concentration of a non-silicon element as the first peripheral source / drain region 152 that can be used as a first concentration.

[0047] The second central source / drain region 134 may be disposed on the second peripheral source / drain region 132 (e.g., directly on the second peripheral source / drain region). The second central source / drain region 134 may include a doped element (such as an impurity). In one embodiment, the first central source / drain regions (154 and 156) may have a first conductivity type, and the second central source / drain region 134 may have a second conductivity type. For example, the second central source / drain region 134 may have an N-type conductivity type, and the impurity may be at least one of phosphorus (P), arsenic (As), and antimony (Sb).

[0048] A plurality of inner spacers 138 may be disposed on side surfaces of the second source / drain structure 130. The plurality of inner spacers 138 may extend into the gate structure 160 (e.g., protrude toward the gate structure 160) below each of the plurality of vertically stacked channel layers 141, 142, 143, and 144, and may cover side surfaces of the gate structure 160 in the X direction below each of the plurality of channel layers 141, 142, 143, and 144 of the channel structure 140. In one embodiment, the plurality of inner spacers 138 may include a material different from that of the second source / drain structure 130. In one embodiment, the plurality of inner spacers 138 may be formed of an insulating material and may include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0049] Except for the connection with the second source / drain structure 130, the second backside contact plug 180b and the second lower interconnect 195b may have substantially the same characteristics as the first backside contact plug 180a and the first lower interconnect 195a, respectively.

[0050] In Figures 6 to 10In the following description, for ease of explanation, content overlapping with the above description may be omitted. Unless otherwise explained, it can be understood that the first source / drain structure 150 has a first conductivity type, and the second source / drain structure 130 has a second conductivity type different from the first conductivity type. In one embodiment, the first conductivity type may be P-type, and the second conductivity type may be N-type.

[0051] Figure 6 FIG. shows a schematic cross-sectional view illustrating a semiconductor device according to an exemplary embodiment.

[0052] Referring Figure 6 , in the semiconductor device 100C, the first source / drain structure 150 having the first conductivity type in the first region R1 may be connected to the back-side contact plug 180, and the second source / drain structure 130 having the second conductivity type in the second region R2 may be connected to the front-side contact plug 170. In one embodiment, the front-side contact plug 170 may extend into the second source / drain structure 130 through the first interlayer insulating layer 192 (e.g., in the Z direction). The front-side contact plug 170 may be arranged such that an upper portion of the second central source / drain region 134 is partially recessed. Except for the position or shape to be set, the front-side contact plug 170 may have the same or similar characteristics as the back-side contact plug 180. In one embodiment, the front-side contact plug 170 may include a metal material (such as aluminum (Al), tungsten (W), molybdenum (Mo), etc.), and according to an embodiment, a semiconductor compound layer contacting the second source / drain structure 130 may be included in the front-side contact plug 170.

[0053] The second source / drain structure 130 may further include an etch stop layer 124 and a second molding layer 122 disposed on a lower surface of the second peripheral source / drain region 132. In one embodiment, the etch stop layer 124 may include a material different from the material of the second peripheral source / drain region 132 and the material of the second molding layer 122. In one embodiment, the etch stop layer 124 may include an oxide, a nitride, etc.

[0054] The second molding layer 122 may be arranged to directly contact the lower surface of the etch stop layer 124. In one embodiment, the second molding layer 122 may include a semiconductor material (e.g., at least one of silicon (Si) and germanium (Ge)), and may further include impurities. In one embodiment, the second molding layer 122 may include germanium (Ge) (or silicon germanium (SiGe)) and / or a non-silicon element that can be used as a doping element, and may have a non-silicon element concentration substantially the same as that of the non-silicon element in the first molding layer 151.

[0055] Figure 7 FIG. shows a schematic cross-sectional view illustrating a semiconductor device according to an exemplary embodiment.

[0056] Referring to Figure 7 , the semiconductor device 100D may include a 1-1 region R1 and a 1-2 region R1' in which a source / drain structure 150 of a first conductivity type is provided. The 1-1 region R1 and the 1-2 region R1' may be adjacent to each other or may be spaced apart from each other. In one embodiment, a first group of source / drain structures 150 provided in the 1-1 region R1 may be connected to a backside contact plug 180, and a second group of source / drain structures provided in the 1-2 region R1' may be connected to a frontside contact plug 170.

[0057] The second group of source / drain structures 150 connected to the frontside contact plug 170 may further include a first molding layer 151. The first molding layer 151 may be in direct contact with the lower surface of the peripheral source / drain region 152. In one embodiment, the first molding layer 151 may include a semiconductor material (e.g., at least one of silicon (Si) and germanium (Ge)), and may further include impurities. In one embodiment, the first molding layer 151 may include germanium (Ge) (or silicon germanium (SiGe)) and / or a non-silicon element that can be used as a doping element, and the concentration of the non-silicon element in the first molding layer 151 may be greater than a first concentration and a second concentration. The first concentration may be the concentration of the non-silicon element in the peripheral source / drain region 152, and the second concentration may be the concentration of the non-silicon element in the first epitaxial layer 154. The concentration of the non-silicon element in the first molding layer 151 may be substantially the same as a third concentration, and the third concentration may be the concentration of the non-silicon element in the second epitaxial layer 156.

[0058] In the second group of source / drain structures 150 provided in the 1-2 region R1', the distance D1' (e.g., the length in the X direction) by which the protrusion 153 protrudes from the side surface of the peripheral source / drain region 152 may be smaller than the distance D2' (e.g., the length in the Z direction) between the lower end of the central source / drain region (154 and 156) (such as the lower end of the first epitaxial layer 154) and the lower end of the peripheral source / drain region 152. However, embodiments of the present disclosure are not necessarily limited thereto, and according to embodiments, the dimensional relationship between the distance D1' and the distance D2' may be changed in various ways.

[0059] Referring to Figure 8 , in the semiconductor device 100E, as compared with Figure 7Unlike the semiconductor device 100D, the second set of source / drain structures 150 in the 1-2 region R1' can be a dummy structure that is not electrically connected to different components (e.g., other components). Different from the first set of source / drain structures 150 connected to the back contact plug 180, the second set of source / drain structures 150 as a dummy structure may include a first molding layer 151 in a lower portion (such as directly contacting the lower surface of the first peripheral source / drain region 152).

[0060] Referring Figure 9 , the first source / drain structure 150 of the semiconductor device 100F can be disposed in the first region R1, and the second source / drain structure 130 can be disposed in the second region R2. In one embodiment, both the first source / drain structure 150 and the second source / drain structure 130 can be dummy structures that are not electrically connected to different components (e.g., other components). The first source / drain structure 150 may include a first molding layer 151 below (e.g., directly below) the first peripheral source / drain region 152, and the second source / drain structure 130 may include an etch stop layer 124 and a second molding layer 122 below the second peripheral source / drain region 132. In one embodiment, the distance D3 (e.g., the length in the Z direction) between the lower ends of the central source / drain regions (154 and 156) of the first source / drain structure 150 (such as the lower end of the first epitaxial layer 154) and the lower end of the peripheral source / drain region 152 can be larger than the distance D4 (e.g., the length in the Z direction) between the lower end of the peripheral source / drain region 152 and the lower end of the first molding layer 151.

[0061] Referring Figure 10 , in the semiconductor device 100G according to an embodiment, different from the semiconductor device 100F in the Figure 9 embodiment, the lower surface of the peripheral source / drain region 152 of the first source / drain structure 150 in the first region R1 can be at a height substantially equal to the height of the lower surface of the gate structure 160. The distance D3' (e.g., the length in the Z direction) between the lower end of the first central source / drain region (154 and 156) (such as the lower end of the first epitaxial layer 154) and the central portion of the lower surface of the first peripheral source / drain region 152 can be smaller than the height D4' (e.g., the length in the Z direction) of the first molding layer 151 disposed directly on the lower surface of the peripheral source / drain region 152. For example, the height D4' of the first molding layer 151 can be the distance (e.g., the length in the Z direction) between the lower end of the first peripheral source / drain region 152 and the lower end of the first molding layer 151.

[0062] Referring Figures 5 to 10Embodiments of the described regions can be combined in various ways within a compatible range. For example, the first source / drain structure 150 in each region can be connected to the first backside contact plug 180a, or the second source / drain structure 130 in each region can be connected to the second backside contact plug 180b.

[0063] Figures 11A to 11B is a schematic process flowchart showing a method of manufacturing a semiconductor device according to an exemplary embodiment. Figures 12A to 12O is a diagram showing the process sequence of a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0064] Referring to Figure 11A and Figure 12A , in block S10, a plurality of sacrificial layers 120 and a plurality of channel layers 141, 142, 143, and 144 can be alternately stacked on the substrate 101 (e.g., in the Z direction).

[0065] In one embodiment, the substrate 101 can include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The substrate 101 can include a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0066] In one embodiment, the plurality of channel layers 141, 142, 143, and 144 can include a first channel layer to a fourth channel layer 141, 142, 143, and 144. As Figure 2 shown, the sacrificial layer 120 can be a layer that can be replaced by a gate dielectric layer 162 and a gate electrode 165 under the fourth channel layer 144 through a subsequent process. In one embodiment, the sacrificial layer 120 can be formed of a material having an etching selectivity for each of the first channel layer to the fourth channel layer 141, 142, 143, and 144. The first channel layer to the fourth channel layer 141, 142, 143, and 144 can include a material different from that of the sacrificial layer 120. In one embodiment, the sacrificial layer 120 and the first channel layer to the fourth channel layer 141, 142, 143, and 144 can include, for example, a semiconductor material including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but can include different materials and can include impurities or not include impurities. For example, the sacrificial layer 120 can include silicon germanium (SiGe), and the first channel layer to the fourth channel layer 141, 142, 143, and 144 can include silicon (Si).

[0067] In one embodiment, the sacrificial layer 120 and the first channel layer to the fourth channel layer 141, 142, 143, and 144 can be formed by performing an epitaxial growth process on the stacked structure. The number of alternately stacked sacrificial layers 120 and channel layers can be changed respectively in various embodiments.

[0068] Reference Figure 11A and Figure 12B In block S20, the sacrificial layer 120, the first to fourth channel layers 141, 142, 143, and 144, and the substrate 101 may be partially removed to form an active structure including the active region 105, and the device isolation layer 110 may be formed.

[0069] The active structure may include the active region 105, the sacrificial layer 120, and the first to fourth channel layers 141, 142, 143, and 144. In one embodiment, the active structure may be formed in a linear shape that extends longitudinally in one direction (e.g., the X direction) and may be formed to be spaced apart from adjacent active structures in the Y direction. The side surfaces of the active structure in the Y direction may be coplanar with each other and may be located on a straight line.

[0070] After filling the region from which a portion of the active region 105, a portion of the sacrificial layer 120, and a portion of the first to fourth channel layers 141, 142, 143, and 144 have been removed with an insulating material, the device isolation layer 110 may be formed by partially removing the insulating material such that the active region 105 protrudes. In one embodiment, the upper surface of the device isolation layer 110 may be formed to be lower than the upper surface of the active region 105.

[0071] Reference Figure 11A and Figure 12C In block S30, a sacrificial gate structure 200 and a gate spacer layer 164 may be formed on the active structure.

[0072] As Figure 2 shown, the sacrificial gate structure 200 may be a sacrificial structure formed by a subsequent process in a region where the gate dielectric layer 162 and the gate electrode 165 are disposed on the channel structure 140. In one embodiment, the sacrificial gate structure 200 may have a linear shape that intersects the active structure and extends longitudinally in one direction. For example, in one embodiment, the sacrificial gate structure 200 may extend in the Y direction and may be arranged to be spaced apart from each other in the X direction.

[0073] In one embodiment, the sacrificial gate structure 200 may include (e.g., in the Z direction) a first sacrificial gate layer 202, a second sacrificial gate layer 205, and a mask pattern layer 206 stacked sequentially. The mask pattern layer 206 may be used to pattern the first sacrificial gate layer 202 and the second sacrificial gate layer 205. In one embodiment, the first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be an insulating layer and a conductive layer, respectively. However, embodiments of the present disclosure are not necessarily limited thereto, and the first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be formed as a single layer. For example, the first sacrificial gate layer 202 may include silicon oxide, and the second sacrificial gate layer 205 may include polysilicon. The mask pattern layer 206 may include silicon oxide and / or silicon nitride.

[0074] Gate spacer layers 164 may be formed on two sidewalls of the sacrificial gate structure 200. The gate spacer layers 164 may be formed of a low-k material and may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0075] Referring Figure 11A and Figure 12D , in block S40, an etching process may be performed using the sacrificial gate structure 200 as an etching mask to form a recessed area that passes through the active structure and exposes the active region 105.

[0076] The sacrificial layer 120 exposed from the sacrificial gate structure 200 and the first to fourth channel layers 141, 142, 143, and 144 may be partially removed to form a recessed area RC, and the active region 105 may be partially removed. As a result, the first to fourth channel layers 141, 142, 143, and 144 may form a channel structure 140 "having a limited length in the X direction".

[0077] Referring Figure 11A and Figure 12E , in block S50, a liner L may be formed on the side surfaces of the sacrificial gate structure 200, the side surfaces of the exposed plurality of sacrificial layers 120, and the side surfaces of the exposed plurality of channel layers 141, 142, 143, and 144, and a first molding layer 151 may be formed on the exposed active region 105.

[0078] In one embodiment, the first molded layer 151 may be formed by growing, for example, via a selective epitaxy process from the active region 105 exposed through the bottom surface of the recessed region RC. Due to the liner L, the selective epitaxy process may not be performed on the side surfaces of the sacrificial gate structure 200, the side surfaces of the plurality of sacrificial layers 120, and the side surfaces of the plurality of channel layers 141, 142, 143, and 144. The first molded layer 151 may have a different composition from the peripheral source / drain regions 152 to be formed subsequently. For example, the first molded layer 151 may include a relatively higher concentration of germanium (Ge) than the subsequently formed peripheral source / drain regions 152. The first molded layer 151 may be spaced apart from the sacrificial layer 120 and the first through fourth channel layers 141, 142, 143, and 144. In an embodiment, the relative thickness of the first molded layer 151 may be varied in various ways within the range in which the first molded layer 151 is spaced apart from the sacrificial layer 120 and the first through fourth channel layers 141, 142, 143, and 144.

[0079] Referring to Figure 11A and Figure 12F , in block S60, the liner L may be removed, and a part of each of the side surfaces of the exposed plurality of sacrificial layers 120 and a part of the upper surface of the first molded layer 151 may be etched.

[0080] In one embodiment, the sacrificial layer 120 may be selectively etched for the channel structure 140 by, for example, a wet etching process, and the sacrificial layer 120 may be removed by a predetermined depth from the side surface of the sacrificial layer 120 in the X direction. The sacrificial layer 120 may have a side surface that is recessed in the inward direction by lateral etching as described above. However, embodiments of the present disclosure are not limited thereto, and the specific shape of the side surface of the sacrificial layer 120 may be different from Figure 12F the specific shape of the side surface of the sacrificial layer 120 shown in

[0081] The first molded layer 151 may be etched together with the sacrificial layer 120, and the first molded layer 151 may be removed by a predetermined depth from the upper surface of the first molded layer 151. Depending on the difference in the composition of the materials included in the first molded layer 151 and the sacrificial layer 120, etching selectivity may occur and the degree of etching may be changed. For example, when an etching material that reacts more strongly with a high concentration of germanium (Ge) is used and the concentration of germanium (Ge) included in the first molded layer 151 is higher than the concentration of germanium (Ge) included in the sacrificial layer 120, the upper surface of the first molded layer 151 may be etched deeper than the side surface of the sacrificial layer 120.

[0082] Referring to Figure 11A and Figures 12G to 12H, in block S70, the peripheral source / drain regions 152 can be formed on each of the side surfaces of the plurality of sacrificial layers 120, on each of the side surfaces of the plurality of channel layers 141, 142, 143, and 144, and on the first molding layer 151, and in block S80, the first epitaxial layer 154 and the second epitaxial layer 156 can be sequentially formed (e.g., in the Z direction) on the peripheral source / drain regions 152 to form the central source / drain regions (154 and 156) that fill the recessed regions RC.

[0083] In one embodiment, the peripheral source / drain regions 152 and the central source / drain regions (154 and 156) can be grown on the upper surface of, for example, the active region 105, the upper surface of the first molding layer 151, and the side surfaces of the channel structure 140 by a selective epitaxial process and formed from the upper surface of, for example, the active region 105, the upper surface of the first molding layer 151, and the side surfaces of the channel structure 140. The peripheral source / drain regions 152, the first epitaxial layer 154, and the second epitaxial layer 156 can be formed sequentially. The peripheral source / drain regions 152, the first epitaxial layer 154, and the second epitaxial layer 156 can contain impurities by in-situ doping and can have different compositions and / or doping concentrations from each other.

[0084] Referring to Figure 11B and Figure 12I , in one embodiment, in block S90, the first interlayer insulating layer 192 can be partially formed, and the sacrificial gate structure and the sacrificial layer can be removed.

[0085] In one embodiment, the first interlayer insulating layer 192 can be formed by forming an insulating film covering the sacrificial gate structure 200 and the central source / drain regions (154 and 156) and performing a planarization process.

[0086] The sacrificial gate structure 200 and the sacrificial layer 120 can be selectively removed for the gate spacer layer 164, the first interlayer insulating layer 192, and the channel structure 140. In one embodiment, the sacrificial gate structure 200 can be removed first to form the upper gap region UR, and then the sacrificial layer 120 exposed through the upper gap region UR can be removed to form the lower gap region LR.

[0087] For example, in an embodiment where the sacrificial layer 120 includes silicon germanium (SiGe) and the channel structure 140 includes silicon (Si), the sacrificial layer 120 can be selectively removed for the channel structure 140 by performing a wet etching process. For example, in an embodiment where the sacrificial layer 120 includes a relatively high concentration of germanium (Ge) and the peripheral source / drain regions 152 include a relatively low concentration of germanium (Ge), the sacrificial layer 120 can be selectively removed for the peripheral source / drain regions 152.

[0088] Referring toFigure 11B and Figure 12J In block S100, a gate dielectric layer 162 and a gate electrode 165 can be formed to fabricate a gate structure 160.

[0089] The gate dielectric layer 162 and the gate electrode 165 can be formed to fill the upper gap region UR and the lower gap region LR. The gate dielectric layer 162 can be formed to conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. The gate electrode 165 can be formed to completely fill the upper gap region UR and the lower gap region LR, and then the gate electrode 165 together with the gate dielectric layer 162 can be removed from the top by a predetermined depth in the upper gap region UR.

[0090] After that, a first interlayer insulating layer 192 can be further formed on the gate structure 160.

[0091] Referring to Figure 11B and Figure 12K In block S110, the entire structure formed by referring to Figures 12A to 12J can be attached to a carrier substrate, the substrate 101 can be removed, and a substrate insulating layer 194 can be formed.

[0092] In one embodiment, contact plugs and interconnects connected to the gate structure 160 can be further formed on the gate structure 160. The carrier substrate SUB can be attached to the first interlayer insulating layer 192 to perform a process on the lower surface of the substrate 101 in Figure 12J In the following figures, for the sake of facilitating understanding, the entire structure is shown as being rotated or inverted as a mirror image of the structure shown in Figure 12J The substrate 101 can be removed from the upper surface of the substrate 101. In one embodiment, the substrate 101 can be removed and thinned by, for example, a lapping process, a grinding process, or a polishing process, and the remaining regions can also be removed by an etching process and / or an oxidation process. However, the thickness by which the substrate 101 is removed can be varied in various embodiments. In some embodiments, the substrate 101 may not be completely removed, and a part of the substrate 101 may be retained. In this embodiment, the active region 105 can be retained on the uppermost surface of the gate structure 160.

[0093] The substrate insulating layer 194 can be formed in the region from which the substrate 101 has been removed. When a part of the device isolation layer 110 is retained without being removed together with the substrate 101, the substrate insulating layer 194 can include the remaining device isolation layer 110.

[0094] The substrate insulating layer 194 can be formed in the region from which the substrate 101 has been removed. When a part of the device isolation layer 110 is retained without being removed together with the substrate 101, the substrate insulating layer 194 can include the remaining device isolation layer 110.

[0095] Referring to Figure 11B and Figure 12L, in block S120, a contact hole CTH (e.g., in the Z direction) may be formed through the base insulating layer 194 to expose the first molded layer 151.

[0096] In one embodiment, the contact hole CTH may be formed along the Figure 2 lower side surface of the kink portion k of the back contact plug 180 to pass through the base insulating layer 194 (e.g., in the Z direction). The first molded layer 151 may be exposed through the contact hole CTH. In one embodiment, the contact hole CTH may have a width (e.g., length in the X direction) that increases as the distance from the first molded layer 151 increases.

[0097] Referring to Figure 11B and Figure 12M , in block S130, the first molded layer 151 may be removed to expose the peripheral source / drain regions 152.

[0098] In one embodiment, the first molded layer 151 exposed through the contact hole CTH may be selectively removed by an etching process. In this operation, the peripheral source / drain regions 152 may be exposed, and the peripheral source / drain regions 152 may be used as an etch stop. Therefore, the peripheral source / drain regions 152 may be used without forming a separate etch stop layer, the process may be simplified, the cost of the process may be reduced, and the reliability of the semiconductor device may be increased.

[0099] Referring to Figure 11B and Figure 12N , in block S140, a part of the peripheral source / drain regions 152 and a part of the first epitaxial layer 154 may be etched.

[0100] In one embodiment, the first epitaxial layer 154 may be exposed by removing the part of the peripheral source / drain regions 152 surrounding the contact hole CTH and the part of the first epitaxial layer 154 surrounding the contact hole CTH. As a result, the shape of the lower surface of the source / drain structure 150 may be formed in a manner similar to that of the semiconductor device 100 of Figure 2 . In an embodiment where the process of "etching or removing the part of the peripheral source / drain regions 152 and the part of the first epitaxial layer 154" is not performed in the current process, the shape of the lower surface of the source / drain structure 150 of the semiconductor device 100A as shown in Figure 3 may be formed.

[0101] Referring to Figure 11B and Figure 12O , in block S150, a back contact plug filling the contact hole CTH may be formed.

[0102] A metal-semiconductor compound layer 184 may be formed on the exposed peripheral source / drain regions 152 and the first epitaxial layer 154. In one embodiment, the metal-semiconductor compound layer 184 may be formed by performing a metal-semiconductor process (such as a silicidation process, etc.) using the exposed source / drain structure 150.

[0103] In one embodiment, in conjunction with Figure 2 and with reference to Figure 11B and Figure 12O , at block S160, a lower interconnect 195 may be formed. The lower interconnect 195 may be prepared by forming a second interlayer dielectric layer 196 covering the substrate insulating layer 194 and the backside contact plug 180, and then removing a portion of the second interlayer dielectric layer 196 to expose the backside contact plug 180.

[0104] As a result, the semiconductor device 100 of Figure 1 and Figure 2 may be fabricated. The semiconductor device 100 may be packaged with the lower interconnect 195 in an upper position. However, embodiments of the present disclosure are not necessarily limited thereto.

[0105] The source / drain regions may be reused as an etch stop layer in a backside process to provide a semiconductor device with a simplified process and increased reliability.

[0106] The various advantages and effects of the embodiments of the present disclosure are not limited to the above.

[0107] Although non-limiting example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure.

Claims

1. A semiconductor device comprising: Base insulation layer; A gate structure extending in a first direction on the base insulating layer; as well as A first source / drain structure and a second source / drain structure are arranged on both sides of the gate structure, and the first source / drain structure and the second source / drain structure are spaced apart from each other in a first direction, The first source / drain structure includes a first central source / drain region, a first peripheral source / drain region and a first molding layer, the first peripheral source / drain region surrounds the side surface and the lower surface of the first central source / drain region, and the first molding layer directly contacts the lower surface of the first peripheral source / drain region. The second source / drain structure includes a second central source / drain region, a second peripheral source / drain region, a second molding layer, and an etching stop layer, wherein the second peripheral source / drain region surrounds the side surface and the lower surface of the second central source / drain region, the second molding layer is disposed below the second peripheral source / drain region, and the etching stop layer is disposed between the second peripheral source / drain region and the second molding layer. the etch stop layer comprises a material different from a material of the second peripheral source / drain region and a material of the second molding layer, The first central source / drain region has a first conductivity type, and The second central source / drain region has a second conductivity type different from the first conductivity type.

2. The semiconductor device according to claim 1, wherein The first peripheral source / drain region includes: a plurality of protrusions extending from a side surface of the first peripheral source / drain region facing the gate structure and protruding toward the gate structure.

3. The semiconductor device according to claim 2, wherein: A protrusion length of each of the plurality of protrusions is greater than a distance between a lower end of the first central source / drain region and a lower end of the first peripheral source / drain region.

4. The semiconductor device according to claim 1, further comprising: a plurality of inner spacers extending from a side surface of the second peripheral source / drain region facing the gate structure and protruding toward the gate structure, Wherein, the plurality of inner spacers include a material different from a material of the second peripheral source / drain region.

5. The semiconductor device according to claim 4, wherein: The plurality of inner spacers include silicon nitride; and The second peripheral source / drain region includes silicon germanium.

6. The semiconductor device according to claim 1, wherein A distance between a lower end of the first central source / drain region and a lower end of the first peripheral source / drain region is smaller than a distance between a lower end of the first peripheral source / drain region and a lower end of the first molding layer.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The first conductivity type is P type; and The second conductivity type is N type.

8. The semiconductor device according to claim 7, wherein: the second central source / drain region comprises at least one of phosphorus, arsenic, and antimony; and The second peripheral source / drain region includes silicon germanium.

9. The semiconductor device according to claim 7, wherein: The first central source / drain region and the first peripheral source / drain region include silicon germanium, The germanium concentration of the first central source / drain region is greater than the germanium concentration of the first peripheral source / drain region.

10. The semiconductor device according to claim 9, wherein The first mold layer includes silicon germanium, The germanium concentration of the first molding layer is greater than the germanium concentration of the first peripheral source / drain region.

11. The semiconductor device according to claim 9, wherein The second peripheral source / drain region and the second molding layer include silicon germanium, The germanium concentration of the second molding layer is greater than the germanium concentration of the second peripheral source / drain region.

12. A semiconductor device comprising: Base insulation layer; A gate structure extending in a first direction on the base insulating layer; a plurality of source / drain structures spaced apart from each other in a first direction on both sides of the gate structure, the plurality of source / drain structures comprising a first group of source / drain structures and a second group of source / drain structures; as well as A backside contact plug passes through the base insulating layer and is connected to the first set of source / drain structures, Each of the plurality of source / drain structures includes a central source / drain region and a peripheral source / drain region surrounding the central source / drain region. The second set of source / drain structures also includes a molding layer directly contacting the lower surface of the peripheral source / drain region.

13. The semiconductor device according to claim 12, wherein: The lower surface of the back contact plug is coplanar with the lower surface of the base insulating layer, The lower interconnection is electrically connected to the backside contact plug and is disposed on a lower surface of the backside contact plug.

14. The semiconductor device according to claim 12 or 13, further comprising: A front side contact plug is connected to the second set of source / drain structures and is disposed above the second set of source / drain structures.

15. A semiconductor device comprising: A gate structure extending in one direction; A source / drain structure is disposed outside the gate structure; as well as a backside contact plug electrically connected to the source / drain structure and disposed below the source / drain structure, The source / drain structure includes a central source / drain region and a peripheral source / drain region surrounding the central source / drain region. The peripheral source / drain region includes a plurality of protrusions protruding toward the gate structure, The peripheral source / drain region includes a first concentration of a non-silicon element, The central source / drain region includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer includes the non-silicon element at a second concentration, the second concentration is higher than the first concentration, the first epitaxial layer covers the inner surface of the peripheral source / drain region, the second epitaxial layer includes the non-silicon element at a third concentration, the third concentration is higher than the second concentration, the second epitaxial layer is disposed on the first epitaxial layer, and The backside contact plug is in direct contact with the peripheral source / drain regions.

16. The semiconductor device according to claim 15, wherein: The non-silicon element is germanium.

17. The semiconductor device according to claim 15, wherein: The backside contact plug has an upper surface that protrudes in an upward direction, the upper surface of the backside contact plug being in direct contact with the central source / drain region; and The upper end of the backside contact plug is located at a height higher than the lower end of the gate structure.

18. The semiconductor device according to claim 15, wherein: The peripheral source / drain region covers at least a portion of the side surface and the lower surface of the central source / drain region; The backside contact plug has an upper surface that protrudes in a downward direction; and The central source / drain region and the backside contact plug are spaced apart from each other.

19. The semiconductor device according to any one of claims 15 to 18, wherein: The backside contact plug includes a metal-semiconductor compound layer defining an upper surface of the backside contact plug.

20. The semiconductor device according to any one of claims 15 to 18, wherein: The backside contact plug includes a kink portion having a minimum width; and The kink portion is located between the upper end of the backside contact plug and the lower end of the backside contact plug and is closer to the upper end of the backside contact plug.

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