Silicon carbide semiconductor device and method for manufacturing same

Abstract

The present application relates to a silicon carbide semiconductor device and a method for manufacturing the same, the silicon carbide semiconductor device including a silicon carbide substrate formed of a first conductivity type silicon carbide, a drift layer formed of the first conductivity type silicon carbide, and a plurality of bulk layers formed of a second conductivity type silicon carbide on the drift layer, a plurality of source layers, which are made of silicon carbide of the first conductivity type and have a higher impurity concentration than the drift layer, over each of the plurality of body layers; a gate insulating film formed in contact with the body layers and the source layers; a gate electrode formed on the gate insulating film; an interlayer insulating film covering the gate electrode; the silicon carbide semiconductor device includes a source electrode, an interlayer insulating film, a source wiring electrode covering the source electrode and the interlayer insulating film, a sealing portion covering the source wiring electrode, and a barrier layer formed between the source wiring electrode and the sealing portion for suppressing hydrogen transmission, whereby reliability of the silicon carbide semiconductor device can be improved.

Description

Technical Field

[0001] The present application relates to semiconductor technology, and particularly to a silicon carbide semiconductor device and a manufacturing method thereof. Background Art

[0002] Semiconductor devices using silicon carbide (SiC) as a substrate and a drift layer (epitaxial layer) can achieve higher breakdown voltage, lower loss, and higher speed than semiconductor devices using silicon (Si) as a substrate, and are therefore used as power semiconductor devices, for example.

[0003] For example, SiC-MOSFET as a silicon carbide semiconductor device is disclosed in Patent Document [Japanese Patent Laid-Open No. 2021-93496]. It is pointed out in Non-Patent Document 1 [DOI 10.1109 / JEDS.2021.3109347, Journal of the Institute of Electrical and Electronics Engineers, Inc. Electron Devices Society] that in trench-type power SiC-MOSFETs, when hydrogen ions (H+) enter the device, they will affect the reliability of the HTRB (High Temperature Reverse Bias) test. As a countermeasure, an interlayer insulating film material with a high phosphorus concentration is used to adsorb hydrogen ions, thereby preventing hydrogen ions from entering the interior of the semiconductor device and improving the reliability of the semiconductor device. Silicon carbide semiconductor devices, such as SiC-MOSFETs, are usually encapsulated with resin. Hydrogen ions released from the resin pass through the source wiring electrode, then pass through the gate electrode, gate insulating film, or source electrode, etc., and finally reach the channel region of the body layer, affecting the reliability of the HTRB (high temperature reverse voltage) test and causing fluctuations in the gate threshold voltage (Vth) or an increase in leakage current of the semiconductor device. Therefore, it is necessary to prevent hydrogen ions from reaching the channel region. Summary of the Invention

[0004] The present application is made to overcome the above problems. The object of the present application is to provide a silicon carbide semiconductor device that can prevent hydrogen ions from passing through the source wiring electrode, thereby improving the reliability of the silicon carbide semiconductor device.

[0005] In a first aspect, in an embodiment of the present application, a silicon carbide semiconductor device is provided, including: A silicon carbide substrate formed of silicon carbide of a first conductivity type; A first conductivity type silicon carbide drift layer formed on a first surface of the silicon carbide substrate; A plurality of body layers formed of silicon carbide of a second conductivity type on the drift layer; A plurality of source layers formed of silicon carbide of a first conductivity type and having an impurity concentration higher than that of the drift layer on the body layer; A gate insulating film formed in contact with the body layer and the source layer; A gate electrode formed on the gate insulating film; An interlayer insulating film covering the gate electrode and the gate insulating film; A source electrode formed on the source layer; A source wiring electrode covering the source electrode and the interlayer insulating film; A package portion covering the source wiring electrode; And a barrier layer formed between the source wiring electrode and the package portion for suppressing hydrogen permeation.

[0006] In a second aspect, an embodiment of the present application provides a method for manufacturing a silicon carbide semiconductor device, including the following steps: A step of forming a drift layer on a silicon carbide substrate; A step of forming a body layer and a source layer on the drift layer by ion implantation; A step of forming a gate insulating film in contact with the body layer and the source layer; A step of forming a gate electrode on the gate insulating film; A step of forming an interlayer insulating film covering the gate electrode; A step of forming a source electrode covering the source layer; A step of forming a source wiring electrode covering the interlayer insulating film and the source electrode; A step of bonding a bonding wire to the source wiring electrode; A step of depositing a barrier layer on the source wiring electrode; A step of filling resin to cover the barrier layer and performing packaging.

[0007] According to the embodiment of the present application, due to the provision of a barrier layer between the source wiring electrode and the package portion, the hydrogen ion permeation rate of this barrier layer is relatively low, which can prevent the hydrogen ions precipitated from the resin of the package portion from entering the channel region of the silicon carbide semiconductor device through the source wiring electrode, thereby improving the reliability of the silicon carbide semiconductor device.

[0008] Details of one or more embodiments of the present application are set forth in the following drawings and description, so that other features, objects, and advantages of the present application become more concise and understandable. Description of the Drawings

[0009] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application.

[0010] Figure 1 It is a plan view of a semiconductor chip showing the first embodiment of the silicon carbide semiconductor device of the present application; Figure 2 It is a cross-sectional view showing the first embodiment of the silicon carbide semiconductor device of the present application; Figure 3 It shows Figure 2Cross-sectional view of a part of the planar MOSFET manufacturing process shown; Figure 4 It represents Figure 2 Cross-sectional view of a part of the planar MOSFET manufacturing process shown; Figure 5 It represents Figure 2 Cross-sectional view of a part of the planar MOSFET manufacturing process shown; Figure 6 It represents Figure 2 Cross-sectional view of a part of the planar MOSFET manufacturing process shown; Figure 7 It is a cross-sectional view showing the second embodiment of the silicon carbide semiconductor device of the present application.

[0011] 1-1A Semiconductor device; 2 - Silicon carbide substrate; 3 - Drift layer; 4 - Body layer; 5 - Source layer; 6 - Body contact layer; 7 - Gate insulating film; 8 - Gate electrode; 9 - Interlayer insulating film; 10 - Source electrode; 11 - Source wiring electrode; 11a, 11B - Junction; 12 - Drain electrode; 13 - Bonding wire (wiring); 13a - Spherical part; 14 - Resin (encapsulation part); 15 - Bonding wire (wiring); 16, 16A - Barrier layer; 50 - Semiconductor chip; 51 - Source pad; 52 - Gate pad; 30 - First surface; 31 - Second surface; 20, 21, 23 - Mask. Detailed implementation mode

[0012] To more clearly understand the purpose, technical solution and advantages of the present application, the present application will be described and illustrated below with reference to the accompanying drawings and embodiments.

[0013] Unless otherwise defined, technical or scientific terms used in this application shall have the ordinary meanings as understood by those of ordinary skill in the technical field to which this application belongs. In this application, words such as "a", "an", "one kind", "the", "these", etc. do not indicate a limitation in quantity and can be singular or plural. The terms "comprising", "including", "having" and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent in these processes, methods, products or devices. The terms "connected", "coupled", etc. used in this application do not limit to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" used in this application means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may mean: A exists alone, A and B exist simultaneously, and B exists alone. Usually, the character " / " indicates that the objects associated before and after are in an "or" relationship. The terms "first", "second", "third", etc. used in this application only distinguish similar objects and do not represent a specific order for the objects.

[0014] In the following-described embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may also be set to p-type and the second conductivity type may be set to n-type.

[0015] In addition, regarding words indicating directions such as up and down, left and right, side, inner, outer, etc., for Figure 2 convenient description, they may be different from the directions of the actual product. In addition, the drawings are schematic, and the relationships between thickness and planar dimensions, the ratios of the thicknesses of each layer, etc. are different from the actual situation. There are also parts with different dimensional relationships and ratios between different drawings.

[0016] First Embodiment: An example of the silicon carbide semiconductor device of this application will be described with the first embodiment. Figure 1 It is a plan view of the semiconductor chip 50 of the silicon carbide semiconductor device 1 of this embodiment. Figure 1The semiconductor chip 50 therein represents the state where the bonding wire 13 and the bonding wire 15 have been joined before being encapsulated by the resin 14 described later. The shape of the semiconductor chip 50 is, for example, rectangular in a plan view. An anode pad 51 and a gate pad 52 are provided on the plane of the semiconductor chip, and a plurality of element regions (not shown) are arranged below them in a plan view. Inside these element regions, a plurality of silicon carbide semiconductor devices 1 each serving as a minimum unit structure of a MOSFET are respectively arranged.

[0017] The gate pad 52 is electrically connected to the gate electrodes of the respective silicon carbide semiconductor devices 1. The source pad 51 also functions as a source wiring electrode 11 (described later) of each silicon carbide semiconductor device 1. The source pad 51 is joined by the bonding wire 13, and the bonding wire 13 is joined, for example, to a wiring component such as a lead frame for encapsulation (not shown).

[0018] The gate pad 52 is joined by the bonding wire 15. In addition, a drain pad is provided on the bottom surface (back surface) of the semiconductor chip (not shown), and the drain pad is electrically connected to the drain electrodes of the respective silicon carbide semiconductor devices 1. The shapes of the source pad 51 and the gate pad 52 of the semiconductor chip 50 can have various variations. The shapes, arrangements, and numbers of the bonding wire 13 and the bonding wire 15 can also have various variations, and thus are not limited to Figure 1 the embodiments.

[0019] Figure 2 is a cross-sectional view of the silicon carbide semiconductor device of the present embodiment as a planar SiC-MOSFET. Figure 2 In this, the silicon carbide semiconductor device 1 includes a silicon carbide substrate 2, a drift layer 3, two body layers 4, two source layers 5, two body contact layers 6, a gate insulating film 7, a gate electrode 8, an interlayer insulating film 9, two source electrodes 10, a source wiring electrode 11, and a drain electrode 12.

[0020] As Figure 2 shown, a planar MOSFET is formed on the n+-type silicon carbide substrate 2. The upper main surface of the silicon carbide substrate 2 in Figure 2 is the first surface 30, and the lower main surface is the second surface 31. The thickness of the silicon carbide substrate 2 is about 350 μm for a 6-inch wafer and about 500 μm for an 8-inch wafer, but before the process of forming the drain electrode 12 described later, it can be thinned to about 100 - 200 μm in order to improve the heat dissipation performance.

[0021] On the first surface 30 of the silicon carbide substrate 2 ( Figure 2 the upper surface in

[0022] On the upper surface of the n-type drift layer 3 (the surface opposite to the silicon carbide substrate 2), two p-type body layers 4 are formed at intervals. The thickness of the body layer 4 is approximately 1 μm. The p-type body layer 4 is formed, for example, by aluminum ion implantation.

[0023] Above each p-type body layer 4, an n+-type source layer 5 with a high impurity concentration is provided. The impurity concentration of the n+-type source layer 5 is higher than that of the n-type drift layer 3. The thickness of the n+-type source layer 5 is, for example, 0.3 - 0.4 μm. Above the p-type body layer 4 and outside the n+-type source layer 5, a p+-type body contact layer 6 is provided. The impurity concentration of the p+-type body contact layer 6 is higher than that of the p-type body layer 4.

[0024] In addition, the body layer 4 is disposed between the n+-type source layer 5 and the drift layer 3 and is in contact with the gate insulating film 7. The gate insulating film 7 is disposed above the drift layer 3, the body layer 4, and the source layer 5, and a gate electrode 8 is provided above it. The gate electrode 8 is made of, for example, polysilicon doped with an n-type impurity (such as phosphorus [P]) to improve conductivity. The gate electrode 8 is electrically connected to the gate pad 52 through a contact hole provided in the interlayer insulating film 9 (not shown due to different cross-sections). Figure 2 For different cross-sections, it is not shown).

[0025] To cover a part of the gate insulating film 7 and the gate electrode 8, the interlayer insulating film 9 is formed. One of the functions of the interlayer insulating film 9 is to isolate the gate electrode 8 from other conductive components such as the source wiring electrode 11. In this embodiment, specifically, the interlayer insulating film 9 is composed of two layers, a BPSG (Boro-phospho-silicate Glass) film covering the gate electrode 8 and a TEOS (Tetraethyl orthosilicate) oxide film covering the BPSG film. The hydrogen ion transmittance of the interlayer insulating film 9 is lower than that of aluminum or an alloy mainly composed of aluminum, so it also has the function of preventing hydrogen ions from passing through the source wiring electrode 11, passing through the interlayer insulating film 9 and the gate insulating film 7, and reaching the channel region.

[0026] The source electrode 10 is formed on the source layer 5 and the body contact layer 6. The source electrode 10 is made of, for example, nickel silicide (NiSi). The source wiring electrode 11 is electrically connected to the source electrode 10 and is provided on the source electrode 10 and the interlayer insulating film 9. The material of the source wiring electrode 11 is, for example, aluminum, or an alloy mainly composed of aluminum. An alloy mainly composed of aluminum refers to an alloy in which the total content of components other than aluminum does not exceed 3% by weight, and more preferably, the total content of components other than aluminum is about 1.5% by weight. Alloys mainly composed of aluminum include, for example, aluminum-silicon-magnesium alloy (Al-Si-Mg) and aluminum-silicon alloy (Al-Si).

[0027] As Figure 2As shown, above the source wiring electrode 11, the bonding wire 13 is bonded at the bonding portion 11a. A spherical portion 13a is provided at the front end of the bonding wire 13. The material of the bonding wire 13 is, for example, aluminum or an aluminum-copper alloy (Al-Cu).

[0028] As Figure 2 shown, between the source wiring electrode 11 and the resin 14 serving as the encapsulation portion, a barrier layer 16 for suppressing hydrogen permeation is provided. The barrier layer 16 is made of aluminum oxide (Al2O3). The hydrogen permeation rate of aluminum oxide is significantly lower than that of aluminum. Therefore, it is possible to prevent (or greatly suppress) the hydrogen ions precipitated from the resin 14 from moving to the source wiring electrode 11. Therefore, by using aluminum oxide as the barrier layer 16, it is possible to prevent hydrogen ions from reaching the channel region, thereby improving the reliability of the silicon carbide semiconductor device 1. The hydrogen permeation rate of aluminum is 1×10 -12 [ m -1 ·s -1 ·Pa -0.5 , and the hydrogen permeation rate of aluminum oxide is 9×10 -17 [m -1 ·s -1 ·Pa -0.5 . The difference between these two values is five orders of magnitude, and the gap is significant. The unit of the hydrogen permeation rate can also be expressed as [ / (m·s·Pa 0.5 ) ].

[0029] In addition, as Figure 2 shown, since aluminum oxide has insulating properties, the barrier layer 16 is not formed at the bonding portion 11a of the source wiring electrode 11. In this way, it is possible to prevent an increase in the resistance value due to the insulating properties of the barrier layer 16. In addition, after the bonding wire 13 is bonded (bonded), depositing aluminum oxide by means of oxygen plasma oxidation or sputtering film formation will not cause serious deterioration of the bonding wire 13, which is one of the advantages of aluminum oxide.

[0030] The thickness of the barrier layer 16 is preferably 20 nm to 100 nm. A thickness of 20 nm or more can fully exert the effect of preventing hydrogen permeation, while exceeding 100 nm, the improvement in the hydrogen blocking effect by increasing the thickness is limited.

[0031] Table 1 below is a comparison table of the hydrogen diffusion blocking effect (H diffusion block effect) calculated for aluminum (Al) and aluminum oxide (Al2O3).

[0032]

Table 1

[0033] Table 1 shows an example of the film combination from A to G. Film combination A is pure aluminum, but film combinations B to G are stacks of aluminum (thickness according to "Al thickness" in Table 1) and aluminum oxide as the barrier layer 16 (thickness according to "Al2O3 thickness" in Table 1), and the hydrogen permeation time is calculated. The hydrogen diffusion time (H Diffusion time) is calculated by the following formula: (Diffusion time: HDiffusion time) = (Thickness: Thickness) / (Hydrogen permeability: H Permeability). In terms of hydrogen permeability (HPermeability), the hydrogen permeability of aluminum is 1×10 -12 [ m -1 ·s -1 ·Pa -0.5 , and the hydrogen permeability of aluminum oxide is 9×10 -17 [m -1 ·s -1 ·Pa -0.5 . A value such as 5.00E+06 represents 5.00×10 6 .

[0034] When explaining film combination C in Table 1, film combination C is a stacked combination of 4.98 μm of aluminum and 0.02 μm (20 nm) of aluminum oxide. The hydrogen permeation time of this film combination C ("Total hydrogen diffusion time" in Table 1) is that the time for hydrogen to permeate through aluminum is 5×10 8 seconds, and the time for hydrogen to permeate through aluminum oxide is 2.3×10 8 seconds. After adding them together and rounding, the total hydrogen diffusion time of film combination C is 2.3×10 8 seconds, which is about 7 years when converted to years. In addition, the total hydrogen diffusion time of film combination C is about twice that of film combination B, so it can be considered to have sufficient hydrogen barrier effect. Film combination B is calculated considering that the oxide film naturally formed on the aluminum surface is about 0.01 μm (10 nm), and its total hydrogen diffusion time is 1.2×10 8 seconds.

[0035] As shown in Table 1, the aluminum oxide thickness of film combination E is 0.1 μm (100 nm), and its total hydrogen diffusion time is 1.10×10 9 seconds, which is about 34 years when converted to years. 34 years is long enough as the service life of an electronic device, so the benefit of increasing the thickness of aluminum oxide beyond 100 nm is limited. Therefore, the film thickness of aluminum oxide is preferably between 20 nm and 100 nm. In addition, when the total hydrogen diffusion time exceeds 10 years, it is more ideal, so the film thickness of aluminum oxide is more preferably between 30 nm and 50 nm.

[0036] In the planar SiC-MOSFET configured as such and serving as the silicon carbide semiconductor device 1, in the above-mentioned body layer 4, the region near the contact with the gate insulating film 7 is the channel region. By using this channel region as the current path, the electron current flows from the source electrode 10 through the source layer 5 and the drift layer 3 to the drain electrode 12. Additionally, by controlling the applied voltage of the gate electrode 8, the width of the depletion layer formed in the channel region is controlled, thereby controlling the current passing through the channel region and further controlling the current between the source electrode 10 and the drain electrode 12.

[0037] In the present embodiment, since a barrier layer 16 made of alumina is provided between the source wiring electrode 11 and the resin 14 serving as the encapsulation portion, it is possible to prevent hydrogen ions precipitated from the encapsulation portion resin 14 from moving to the source wiring electrode 11. Therefore, it is possible to prevent hydrogen ions from reaching the channel region of the body layer 4 and causing characteristic fluctuations, improving the reliability of the silicon carbide semiconductor device 1.

[0038] Manufacturing process of the first embodiment: Reference Figures 3 to 6 Describe the manufacturing process of the silicon carbide semiconductor device 1 of the present embodiment. As Figure 3 shown in (A), an n+-type silicon carbide substrate 2 of the first conductivity type is prepared. Subsequently, epitaxial growth of the n-type drift layer 3 is performed on the first surface 30 ( Figure 1 the upper surface in) of the silicon carbide substrate 2.

[0039] Next, on the surface of the n-type drift layer 3, for example, SiO2 or the like is formed as a mask, and through a photolithography process, the upper part of the predetermined formation region of the second conductivity type p-type body layer 4 is exposed to form a mask 20. Then, ion implantation of the p-type impurity aluminum (Al) is performed from above the mask 20. The thickness of the body layer 4 is, for example, 1 μm. In the present embodiment, Al is used as the p-type impurity, but B (boron) or BF2 (boron difluoride) may also be used.

[0040] Next, as Figure 3 shown in (B), using the self-alignment method, a material (for example, SiO2) the same as that of the mask 20 is stacked on the main surface of the silicon carbide substrate 2, and through anisotropic etching, a mask 21 wider than the mask 20 is formed. The formed mask 21 exposes the upper part of the predetermined formation region of the n-type source layer 5. Then, ion implantation of an n-type impurity such as nitrogen (N) is performed from above the mask 21. Nitrogen is used as the n-type impurity in the present embodiment, but phosphorus (P) may also be used.

[0041] Next, as Figure 3As shown in (C), after removing the mask 21, a mask 23 such as SiO2 is formed. Subsequently, through a photolithography process, the predetermined formation area of the p+-type body contact layer 6 is exposed to form the mask 23. Then, in the predetermined formation area of the body contact layer 6, ions of aluminum (Al) are implanted as a p-type impurity to form the body contact layer 6.

[0042] Next, after removing the mask 23, annealing is performed at, for example, 1600 °C. Through this annealing, the p-type body layer 4, the n+-type source layer 5, and the body contact layer 6 are activated.

[0043] Next, as shown in Figure 4 (A), a gate insulating film 7 such as SiO2 is formed. Specifically, SiO2 is formed by thermal oxidation in the upper region including the body layer 4, the n+-type source layer 5, and the body contact layer 6 by heating to 900 - 1350 °C, and the gate insulating film 7 is patterned using a photoresist formed through a photolithography and etching process as a mask.

[0044] Next, as shown in Figure 4 (B), a gate electrode 8 is formed on the surface of the gate insulating film 7. Specifically, to improve conductivity, a polysilicon layer doped with n-type impurities is formed, for example, and then patterned using a photoresist formed through a photolithography and etching process as a mask.

[0045] Next, as shown in Figure 4 (C), an interlayer insulating film 9 covering the gate electrode 8 is formed. The interlayer insulating film 9 can be, for example, a single-layer structure of BPSG, TEOS, or PSG, or a multi-layer structure. For example, in the case of a two-layer structure of a BPSG insulating film and a TEOS film, a BPSG insulating film can be formed above the gate electrode 8, and a TEOS insulating film can be formed thereon. At this time, a BPSG film can be formed on the entire main surface of the wafer including the gate electrode 8, and the BPSG film can be patterned using a photoresist formed through a photolithography and etching process as a mask to form the first interlayer insulating film composed of BPSG. Then, a TEOS film is formed on the entire main surface of the wafer including the BPSG first interlayer insulating film, and the TEOS film is patterned using a photoresist formed through a photolithography and etching process as a mask to form the TEOS insulating film as the second interlayer insulating film.

[0046] Next, as Figure 5As shown in (A), a source electrode 10 made of, for example, nickel silicide (NiSi) is formed. Specifically, first, nickel (Ni) is deposited on the main surface of the substrate 2 including the source layer 5 and the body contact layer 6 by sputtering. Then, an alloying annealing process is performed. Specifically, the silicon carbide substrate 2 on which nickel (Ni) has been deposited is subjected to laser heat treatment at, for example, a temperature between 900 °C and 1100 °C for about 5 minutes. As a result, at least a part of the source electrode 10 (the contact part between the source layer 5 and the body contact layer 6 and the nickel film) is silicided to become nickel silicide. After that, the unsilicided nickel (Ni) part is removed, thereby forming the source electrode 10 that makes an ohmic contact with the source layer 5 and the body contact layer 6.

[0047] Next, as Figure 5 shown in (B), a source wiring electrode 11 is formed. Specifically, the source wiring electrode 11 is formed by sputtering, for example, on the basis of covering the source electrode 10, the interlayer insulating film 9, and the barrier layer 16.

[0048] Next, as Figure 6 shown in (A), a drain electrode 12 made of, for example, NiSi is formed on the second surface 31 of the silicon carbide substrate 2. The drain electrode 12 is formed by depositing nickel (Ni) by, for example, sputtering method and then heating it by, for example, laser annealing. As a result, at least a part of the nickel is silicided. After that, the unsilicided nickel is removed, thereby forming the drain electrode 12.

[0049] Next, as Figure 6 shown in (A), the bonding wire 13 is bonded to the source wiring electrode 11 (wire bonding).

[0050] Next, as Figure 6 shown in (B), the surface of the source wiring electrode 11 is oxidized by plasma oxidation to form an alumina thin film. Specific conditions for plasma oxidation are as follows: vacuum pressure 100 Pa, oxygen (O2) flow rate 20 [sccm], substrate temperature 150 - 250 °C, high-frequency power supply power 200 [W]. The film thickness is adjusted by controlling the plasma oxidation time. For example, the surface of the source wiring electrode 11 made of aluminum or an alloy mainly composed of aluminum is subjected to plasma oxidation for about 1 hour to form an alumina film with a thickness of 50 nm.

[0051] As Figure 6 shown in (B), since the barrier layer 16 is formed by plasma oxidation, its cross-sectional shape is from Figure 6The surface of the source wiring electrode 11 shown in (A) extends vertically. Moreover, an aluminum oxide film serving as the barrier layer 16 is not formed at the joint portion 11a on the source wiring electrode 11 where the bonding wire 13 is joined. This is because during the plasma oxidation process, the joint portion 11a is covered by the spherical portion 13a, and the surface of the source wiring electrode 11 is not oxidized. Although an aluminum oxide film is also formed on the surface of the bonding wire 13 and the spherical portion 13a, since this surface oxide film is extremely thin relative to the diameter of the bonding wire 13, its representation is omitted in Figure 6 (B) and Figure 2 is omitted.

[0052] Next, as shown in Figure 2 , the resin 14 is filled into the space between the barrier layer 16 and the bonding wire 13 and encapsulated. The portion encapsulated by the resin 14 constitutes the encapsulation portion. Specifically, the resin 14 is filled on the main surface covering the source wiring electrode 11, and the encapsulation portion is provided. In this way, the silicon carbide semiconductor device 1 is manufactured.

[0053] Second Embodiment: Figure 7 shows a second embodiment according to the present application. Parts having the same functions as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. Figure 7 The silicon carbide semiconductor device 1A in Figure 7 is constituted by a planar SiC-MOSFET. The silicon carbide semiconductor device 1A in

[0054] forms the barrier layer 16A by sputtering. The barrier layer 16A is made of aluminum oxide. The barrier layer 16A is not formed on the bonding wire 13 joint portion 11B of the source wiring electrode 11. This is because during the manufacturing process of the silicon carbide semiconductor device 1A in the second embodiment, after the bonding wire 13 of the source wiring electrode 11 is joined, the barrier layer 16A is formed by sputtering. Therefore, since there is no barrier layer 16A on the joint portion 11B of the source wiring electrode 11, the barrier layer 16A does not cause an increase in the resistance value.

[0055] Figure 7 The silicon carbide semiconductor device 1A of the present embodiment shown in Figure 2 is different from the silicon carbide semiconductor device 1 in the first embodiment shown in Figure 7 in that the boundaries between the barrier layers 16, 16A and the source wiring electrode 11 are different. This is due to the different film-forming methods of the barrier layers 16, 16A. In the silicon carbide semiconductor device 1A in

[0056] In addition, in the first embodiment, since the plasma oxidation used for forming the barrier layer 16 forms a film by oxidizing the surface of the source wiring electrode 11, the film thickness is limited. In contrast, the sputtering method used in the manufacturing method of the second embodiment is not subject to this limitation, and the film thickness can be freely adjusted.

[0057] Similar to the first embodiment, in the silicon carbide semiconductor device 1A of the second embodiment, the barrier layer 16A can effectively block hydrogen ions precipitated from the resin 14 from entering the source wiring electrode 11, thereby preventing the hydrogen ions from reaching the channel region of the body layer 4. Therefore, the reliability of the silicon carbide semiconductor device 1A can be improved.

[0058] Alternatively, in the manufacturing method of the first embodiment, alumina can be further formed by sputtering on the alumina formed by plasma oxidation. In this case, the limitation of the film thickness formed by plasma oxidation can be exceeded, and an alumina thin film having a conductive barrier layer 16 can be formed.

[0059] In the above embodiments, an example of applying the silicon carbide semiconductor device of the present application to a planar SiC-MOSFET has been explained, but it can also be applied to an IGBT (insulated gate bipolar transistor).

[0060] The above-described embodiments merely represent several embodiments of the present application, and the description thereof is relatively specific and detailed. However, it should not be construed as a limitation of the scope of patent protection. It should be noted that for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A silicon carbide semiconductor device, characterized in that: include: a silicon carbide substrate formed of first conductivity type silicon carbide; a drift layer formed of first conductivity type silicon carbide on a first surface of the silicon carbide substrate; a plurality of body layers formed of second conductivity type silicon carbide on the drift layer; On each of the plurality of body layers, a plurality of source layers are formed of first conductivity type silicon carbide and have a higher impurity concentration than the drift layer; a gate insulating film formed in contact with the body layer and the source layer; a gate electrode formed on the gate insulating film; an interlayer insulating film covering the gate electrode and the gate insulating film; forming a source electrode on the source layer; a source wiring electrode covering the source electrode and the interlayer insulating film; a packaging portion covering the source wiring electrode; and a barrier layer for suppressing hydrogen gas permeation formed between the source wiring electrode and the sealing portion.

2. The silicon carbide semiconductor device according to claim 1, wherein: The barrier layer is composed of aluminum oxide.

3. The silicon carbide semiconductor device according to claim 2, wherein: The barrier layer has a thickness of not less than 20 nm and not more than 100 nm.

4. The silicon carbide semiconductor device according to claim 3, wherein: The thickness of the barrier layer is between 30 nm and 50 nm.

5. The silicon carbide semiconductor device according to claim 2, wherein: The hydrogen permeability of the aluminum oxide is 9×10 -17 [m -1 ·s -1 ·Pa -0.5 ].

6. The silicon carbide semiconductor device according to claim 1, wherein: A bonding wire is included which is bonded to the source wiring electrode, the source wiring electrode has a bonding portion which is bonded to the bonding wire, and no barrier layer is formed on the bonding portion of the source wiring electrode.

7. A method for manufacturing a silicon carbide semiconductor device, characterized in that: The method comprises: forming a drift layer on a silicon carbide substrate; forming a body layer and a source layer on the drift layer by ion implantation; forming a gate insulating film in contact with the body layer and the source layer; forming a gate electrode on the gate insulating film; forming an interlayer insulating film covering the gate electrode; forming a source electrode covering the source layer; forming a source wiring electrode covering the interlayer insulating film and the source electrode; a step of bonding a bonding wire to the source wiring electrode; a step of depositing a barrier layer for inhibiting hydrogen gas permeation on the source wiring electrode; The step of filling the barrier layer with resin and performing encapsulation is performed.

8. The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein: The barrier layer is composed of aluminum oxide.

9. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein: The step of depositing a barrier layer for inhibiting hydrogen permeation on the source wiring electrode comprises: A barrier layer for suppressing hydrogen permeation is deposited on the source wiring electrode by plasma oxidation.

10. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein: The step of depositing a barrier layer for inhibiting hydrogen permeation on the source wiring electrode comprises: A barrier layer for suppressing hydrogen gas permeation is deposited on the source wiring electrode by sputtering.

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