Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises at least one MOSFET, and the MOSFET comprises a first electrode, a substrate, an epitaxial layer, a current expansion layer, a first doping layer, a second doping layer, a second electrode, a gate, a gate dielectric layer, a bottom shielding layer and at least one first shielding layer; the gate dielectric layer and the gate extend along a second direction; the bottom shielding layer is arranged on the side, close to the first electrode, of the gate dielectric layer and extends in the second direction; the first shielding layer is in contact with at least part of the bottom shielding layer, and the first shielding layer at least surrounds part of the gate dielectric layer in the first direction; the first shielding layer and the grid electrode are arranged in a crossed manner, and the length of the first shielding layer in the second direction is relatively small, so that the influence on the conduction characteristic of the device caused by the overlarge area of the first shielding layer is avoided, and the device has relatively good conduction characteristic while a relatively good shielding effect is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the rapid development of semiconductor technology, wide-bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), aluminum nitride (AlN), etc. have more advantages in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity compared to silicon (Si). The power devices prepared, such as diodes, transistors, and power modules, have more excellent electrical properties, can overcome the defects that silicon-based devices cannot meet the application requirements of high power, high voltage, high frequency, high temperature, etc., and are also one of the breakthrough paths to exceed Moore's Law. Therefore, they are widely used in the new energy field (for example, the photovoltaic field or the energy storage field, etc.).

[0003] Reference Figure 1 As shown, it is a metal-oxide-semiconductor field-effect transistor (MOSFET) structure based on SiC material. A bottom P-type masking layer 10 is provided below the gate dielectric layer 40 to achieve the masking effect of the electric field at the bottom of the gate dielectric layer 40; deep P-type masking layers 20 are provided on both sides of the gate 30 to achieve the masking effect of the electric field at the trench corners of the gate 30. However, there is a contradiction between the masking effect of the electric field at the trench corners of the gate 30 and the device conduction characteristics that cannot be balanced (tradeoff), that is, when the masking effect of the electric field at the trench corners of the gate 30 is improved, the device conduction characteristics become worse.

[0004] Therefore, how to achieve good device conduction characteristics while having a good masking effect is an urgent technical problem to be solved. Summary of the Invention

[0005] In view of this, the purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, which can achieve good device conduction characteristics while having a good masking effect.

[0006] To achieve the above purpose, the present application has the following technical solutions:

[0007] The present application provides a semiconductor device, which includes at least one metal-oxide-semiconductor field-effect transistor MOSFET, and the MOSFET includes:

[0008] A first electrode, a substrate, an epitaxial layer, a current spreading layer, a first doping layer, a second doping layer, and a second electrode stacked in sequence; the substrate, the epitaxial layer, the current spreading layer, and the second doping layer are of a first conductivity type, and the first doping layer is of a second conductivity type;

[0009] A trench that at least penetrates through the first doped layer and the second doped layer, the surface of the trench being covered by a gate dielectric layer, and the trench being filled with a gate; the gate dielectric layer and the gate extend along a second direction, the second direction being perpendicular to a third direction, and the third direction being perpendicular to the surface where the first electrode is located;

[0010] A bottom shielding layer, the bottom shielding layer being disposed on a side of the trench close to the first electrode, and the bottom shielding layer extending along the second direction; the bottom shielding layer is of a second conductivity type;

[0011] At least one first shielding layer, the first shielding layer being of a second conductivity type; the first shielding layer is located between the epitaxial layer and the second electrode, the first shielding layer is in contact with at least a part of the bottom shielding layer, and the first shielding layer at least surrounds a part of the gate dielectric layer in a first direction; the first shielding layer extends along the first direction, the first direction being perpendicular to the second direction and the third direction; along the second direction, the length of the first shielding layer is 1 / N of the length of the bottom shielding layer, and N is at least greater than 1.

[0012] Optionally, the trench includes a first-stage trench and a second-stage trench, and the second-stage trench is located on a side of the first-stage trench close to the first electrode;

[0013] Along the first direction, the length of the second-stage trench is less than the length of the first-stage trench;

[0014] The first-stage trench at least penetrates through the first doped layer and the second doped layer to the current spreading layer;

[0015] The second-stage trench is located in the current spreading layer or in the epitaxial layer.

[0016] Optionally, the bottom shielding layer is disposed on a side of the second-stage trench close to the first electrode, and along the first direction, the length of the second-stage trench is less than the length of the bottom shielding layer.

[0017] Optionally, a gate dielectric layer is provided between the gate filled in the first-stage trench and the gate filled in the second-stage trench.

[0018] Optionally, along the first direction, the length of the first shielding layer is the same as the length of the epitaxial layer; the first shielding layer surrounds the gate dielectric layer in the first direction;

[0019] Along the second direction, the length of the bottom shielding layer is the same as the length of the gate;

[0020] The first shielding layer is periodically arranged in the second direction.

[0021] Optionally, the MOSFET further includes: at least two second shielding layers;

[0022] The second shielding layer is located between the epitaxial layer and the second electrode; along the first direction, the at least two second shielding layers are respectively disposed on both sides of the gate, and the distance between the second shielding layer and the gate is greater than a distance threshold; the distance between the positive projections of the second shielding layer and the bottom shielding layer in the first direction is greater than or equal to 0; the second shielding layer extends along the second direction.

[0023] Optionally, the MOSFET includes four second shielding layers;

[0024] Along the first direction, two of the second shielding layers are oppositely disposed; along the second direction, the first shielding layer is between the two second shielding layers; the distance between the positive projections of the second shielding layer and the bottom shielding layer in the first direction is greater than 0.

[0025] Optionally, the MOSFET includes four second shielding layers;

[0026] Along the first direction, two of the second shielding layers are oppositely disposed; along the second direction, the first shielding layer is between the two second shielding layers; the distance between the positive projections of the second shielding layer and the bottom shielding layer in the first direction is equal to 0.

[0027] Optionally, the semiconductor device includes a first MOSFET and a second MOSFET;

[0028] The first shielding layer of the first MOSFET is connected to the first shielding layer of the second MOSFET;

[0029] The first shielding layer of the first MOSFET surrounds a part of the gate dielectric layer in the first direction; the first shielding layer of the second MOSFET surrounds all of the gate dielectric layer in the first direction.

[0030] Optionally, the semiconductor device includes a first MOSFET and a second MOSFET;

[0031] The distance between the positive projections of the first shielding layer of the first MOSFET and the first shielding layer of the second MOSFET in the first direction is greater than 0;

[0032] The first shielding layer of the first MOSFET surrounds all of the gate dielectric layer in the first direction; the first shielding layer of the second MOSFET surrounds all of the gate dielectric layer in the first direction.

[0033] The present application provides a method for manufacturing a semiconductor device, including:

[0034] Forming an epitaxial layer and a current spreading layer on a substrate in sequence;

[0035] Performing ion implantation on the current spreading layer to form a first doped layer, a second doped layer, and at least one first shielding layer respectively. The substrate, the epitaxial layer, the current spreading layer, and the second doped layer are of a first conductivity type, and the first doped layer is of a second conductivity type;

[0036] Etching at least the first doped layer and the second doped layer to form a trench;

[0037] Performing ion implantation on the bottom of the trench to form a bottom shielding layer; the bottom shielding layer extends along a second direction, the second direction is perpendicular to a third direction, and the third direction is perpendicular to the surface where the substrate is located; the bottom shielding layer is of a second conductivity type;

[0038] Forming a gate dielectric layer and a gate in the trench; the gate dielectric layer and the gate extend along the second direction;

[0039] Forming a first electrode on a side of the substrate away from the epitaxial layer, and forming a second electrode on a side of the second doped layer away from the substrate;

[0040] The first shielding layer is in contact with at least part of the bottom shielding layer, and the first shielding layer at least surrounds part of the gate dielectric layer in a first direction; the first shielding layer extends along the first direction, and the first direction is perpendicular to the second direction and the third direction; along the second direction, the length of the first shielding layer is 1 / N of the length of the bottom shielding layer, and N is at least greater than 1.

[0041] The present application provides a semiconductor device. The semiconductor device includes at least one metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes: a first electrode, a substrate, an epitaxial layer, a current spreading layer, a first doped layer, a second doped layer, a second electrode, a gate, a gate dielectric layer, a bottom shielding layer, and at least one first shielding layer. Among them, the first electrode, the substrate, the epitaxial layer, the current spreading layer, the first doped layer, the second doped layer, and the second electrode are stacked in sequence. The substrate, the epitaxial layer, the current spreading layer, and the second doped layer are of a first conduction type, and the first doped layer is of a second conduction type. The MOSFET includes a trench that penetrates at least the first doped layer and the second doped layer. The surface of the trench is covered by the gate dielectric layer, and the trench is filled with the gate. The gate dielectric layer and the gate extend along a second direction, and the second direction is perpendicular to a third direction, where the third direction is the direction perpendicular to the surface where the first electrode is located. The bottom shielding layer is disposed on one side of the trench close to the first electrode. The bottom shielding layer extends along the second direction. The bottom shielding layer is of the second conduction type, that is, the bottom shielding layer can be disposed at the bottom of the gate dielectric layer in the second direction, so as to realize the electric field masking at the bottom of the gate dielectric layer by using the bottom shielding layer. The first shielding layer is of the second conduction type. The first shielding layer is located between the epitaxial layer and the second electrode. The first shielding layer contacts at least a part of the bottom shielding layer. The first shielding layer at least surrounds a part of the gate dielectric layer in a first direction, that is, the first shielding layer is disposed at least on one side of the trench and contacts the bottom shielding layer, so as to realize the grounding of the bottom shielding layer and the electric field shielding effect. The first shielding layer extends along the first direction, and the first direction is perpendicular to the second direction and the third direction. Along the second direction, the length of the first shielding layer is 1 / N of the length of the bottom shielding layer, where N is at least greater than 1, that is, the first shielding layer and the gate are cross-set and the length of the first shielding layer in the second direction is small, so as to avoid the influence on the conduction characteristics of the device due to the too large area of the first shielding layer. That is to say, by setting the first shielding layer that extends along the first direction, contacts the bottom shielding layer, and has a small length in the second direction, it is possible to achieve good conduction characteristics of the device while having a good masking effect. Description of the Drawings

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0043] Figure 1 Fig. shows a schematic structural diagram of a metal-oxide-semiconductor field-effect transistor structure based on SiC material;

[0044] Figure 2Shows a three-dimensional structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0045] Figure 3 Shows Figure 2 A cross-sectional structural schematic diagram of the semiconductor device shown along the BB' direction;

[0046] Figure 4 Shows Figure 2 A cross-sectional structural schematic diagram of the semiconductor device shown along the CC' direction;

[0047] Figure 5 Shows Figure 2 A cross-sectional structural schematic diagram of the semiconductor device shown along the DD' direction;

[0048] Figure 6 Shows Figure 2 A top-view structural schematic diagram of the semiconductor device shown;

[0049] Figure 7 Shows a top-view structural schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0050] Figure 8 Shows a three-dimensional structural schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0051] Figure 9 Shows Figure 8 A top-view structural schematic diagram of the semiconductor device shown;

[0052] Figure 10 Shows Figure 8 A cross-sectional structural schematic diagram of the semiconductor device shown along the AA' direction;

[0053] Figure 11 Shows Figure 8 A cross-sectional structural schematic diagram of the semiconductor device shown along the BB' direction;

[0054] Figure 12 Shows Figure 8 A cross-sectional structural schematic diagram of the semiconductor device shown along the CC' direction;

[0055] Figure 13 Shows Figure 8 A cross-sectional structural schematic diagram of the semiconductor device shown along the DD' direction;

[0056] Figure 14 Shows a three-dimensional structural schematic diagram of yet another semiconductor device provided by an embodiment of the present application;

[0057] Figure 15 Shows a top-view structural schematic diagram of yet another semiconductor device provided by an embodiment of the present application;

[0058] Figure 16(a) shows a schematic structural diagram of a cell structure of a semiconductor device provided by an embodiment of the present application;

[0059] Figure 16(b) shows a schematic structural diagram of another cell structure of a semiconductor device provided by an embodiment of the present application;

[0060] Figure 17 shows a schematic top view structure diagram of still another semiconductor device provided by an embodiment of the present application;

[0061] Figure 18 shows a schematic top view structure diagram of yet another semiconductor device provided by an embodiment of the present application;

[0062] Figure 19 shows a schematic diagram of the blocking characteristic current-voltage (I-V) change curves of a MOSFET with a conventional structure and a MOSFET with a two-stage gate trench structure provided by the present application;

[0063] Figure 20 shows a schematic diagram of the electric field distribution at breakdown of a MOSFET with a conventional structure and a MOSFET with a two-stage gate structure provided by the present application;

[0064] Figure 21 shows a schematic diagram of the on-state characteristic current-voltage (I-V) change curves of a MOSFET with a conventional structure and a MOSFET with a two-stage gate structure provided by the present application;

[0065] Figure 22 shows a schematic flow diagram of a manufacturing method of a semiconductor device provided by an embodiment of the present application;

[0066] Figures 23 - 27 shows a schematic structural diagram of a semiconductor device manufactured by the manufacturing method of a semiconductor device provided by an embodiment of the present application. Detailed Embodiments

[0067] To make the above objects, features, and advantages of the present application more apparent and understandable, the following describes the detailed embodiments of the present application in conjunction with the accompanying drawings.

[0068] In the following description, many specific details are set forth to facilitate a thorough understanding of the present application. However, the present application may be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0069] This application will be described in detail with reference to the schematic diagrams. When describing the embodiments of this application, for the convenience of explanation, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of this application herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0070] Referring to Figure 1 As shown, it is a metal-oxide-semiconductor field-effect transistor (MOSFET) structure based on SiC material. The high electric field in the drift layer 50 results in a very high electric field on the gate dielectric layer 40, and it is aggravated at the corners of the gate 30 trench, thus causing the gate dielectric layer 40 to break down rapidly under high drain voltage. In addition, for this structure, the electrostatic effect in a harsh environment and the tolerance to high-voltage spikes in the circuit are poor. A bottom P-type masking layer 10 can be provided under the gate dielectric layer 40, and deep P-type masking layers 20 are provided on both sides of the gate 30. There is a certain distance between the deep P-type masking layer 20 and the gate 30 as a current channel, so as to achieve the masking effect of the electric field at the bottom of the gate dielectric layer 40 and the masking effect of the electric field at the corners of the gate 30 trench. However, due to ion scattering, the lateral expansion of the deep P-type masking layers 20 on both sides of the gate 30 is relatively serious, thus aggravating the junction field-effect transistor (JFET) effect between the bottom P-type masking layer 10 and the deep P-type masking layers 20 on both sides of the gate 30, and degrading the on-state characteristics of the device. In addition, there is a contradiction that cannot be balanced (tradeoff) between the masking effect of the electric field at the corners of the gate 30 trench and the on-state characteristics of the device, that is, when the masking effect of the electric field at the corners of the gate trench is improved, the on-state characteristics of the device become worse. In addition, due to the deep P-type masking layers 20 being provided on both sides of the trench, the device cell size is large, and a smaller cell size cannot be achieved.

[0071] Therefore, how to achieve good on-state characteristics of the device while having a good masking effect is a technical problem to be solved urgently.

[0072] Based on this, the present application provides a semiconductor device. The semiconductor device includes at least one metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes: a first electrode, a substrate, an epitaxial layer, a current spreading layer, a first doped layer, a second doped layer, a second electrode, a gate, a gate dielectric layer, a bottom shielding layer, and at least one first shielding layer. Among them, the first electrode, the substrate, the epitaxial layer, the current spreading layer, the first doped layer, the second doped layer, and the second electrode are stacked in sequence. The substrate, the epitaxial layer, the current spreading layer, and the second doped layer are of a first conductivity type, and the first doped layer is of a second conductivity type. The MOSFET includes a trench that at least penetrates the first doped layer and the second doped layer. The surface of the trench is covered by the gate dielectric layer, and the trench is filled with the gate. The gate dielectric layer and the gate extend along a second direction, and the second direction is perpendicular to a third direction, where the third direction is the direction perpendicular to the surface where the first electrode is located. The bottom shielding layer is disposed on one side of the trench close to the first electrode, and the bottom shielding layer extends along the second direction. The bottom shielding layer is of the second conductivity type, that is, the bottom shielding layer can be disposed at the bottom of the gate dielectric layer in the second direction, so as to realize the masking of the electric field at the bottom of the gate dielectric layer by using the bottom shielding layer. The first shielding layer is of the second conductivity type. The first shielding layer is located between the epitaxial layer and the second electrode. The first shielding layer is in contact with at least part of the bottom shielding layer. The first shielding layer at least surrounds part of the gate dielectric layer in a first direction, that is, the first shielding layer is at least disposed on one side of the trench and in contact with the bottom shielding layer, so as to realize the grounding of the bottom shielding layer and the electric field shielding effect. The first shielding layer extends along the first direction, and the first direction is perpendicular to the second direction and the third direction. Along the second direction, the length of the first shielding layer is 1 / N of the length of the bottom shielding layer, and N is at least greater than 1, that is, the first shielding layer and the gate are cross-set and the length of the first shielding layer in the second direction is small, so as to avoid the influence on the conduction characteristics of the device due to the too large area of the first shielding layer. That is to say, by setting the first shielding layer that extends along the first direction, is in contact with the bottom shielding layer, and has a small length in the second direction, it is possible to achieve good conduction characteristics of the device while having a good masking effect.

[0073] To better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0074] Refer to Figure 2 As shown, it is a three-dimensional structure schematic diagram of a semiconductor device provided by an embodiment of the present application. The semiconductor device provided by the embodiment of the present application includes at least one metal-oxide-semiconductor field-effect transistor (MOSFET), that is, the semiconductor device can include one or more MOSFETs.

[0075] Figure 2The MOSFET shown is a three-dimensional structure, i.e., extending in three mutually perpendicular directions (the first direction, the second direction, and the third direction). The MOSFET can be sectioned along the planes BB’, CC’, and DD’ to obtain respectively Figures 3 - 5 .

[0076] The MOSFET includes: a first electrode 210, a substrate 110, an epitaxial layer 120, a current spreading layer 130, a first doping layer 140, a second doping layer 150, a second electrode 220, a gate 310, a gate dielectric layer 320, a bottom shielding layer 410, and at least one first shielding layer 420.

[0077] In an embodiment of the present application, the first electrode 210, the substrate 110, the epitaxial layer 120, the current spreading layer 130, the first doping layer 140, the second doping layer 150, and the second electrode 220 are stacked in sequence, as shown in Figure 3 . The third direction is perpendicular to the surface where the first electrode 110 is located. Along the third direction, the substrate 110 is located on the first electrode 210, the epitaxial layer 120 is located on the substrate 110, the current spreading layer 130 is located on the epitaxial layer 120, the first doping layer 140 is located on the current spreading layer 130, the second doping layer 150 is located on the first doping layer 140, and the second electrode 220 is located on the second doping layer 150.

[0078] Specifically, the first electrode 210 or the second electrode 220 is made of a material with good conductivity, such as a metal material. As an example, the first electrode 210 is a drain electrode and the second electrode 220 is a source electrode.

[0079] In an embodiment of the present application, the substrate 110, the epitaxial layer 120, the current spreading layer 130, and the second doping layer 150 are of a first conduction type, and the first doping layer 140 is of a second conduction type.

[0080] As an example, the first conduction type is N-type and the second conduction type is P-type, i.e., the substrate 110, the epitaxial layer 120, the current spreading layer 130, and the second doping layer 150 are N-type, and the first doping layer 140 is P-type.

[0081] The material of the substrate 110 can be a wide bandgap semiconductor material, such as SiC, GaN, Ga2O3, C, or AlN. The epitaxial layer 110 can be formed on the substrate 110 by an epitaxial process. The current spreading layer 130 can be formed by ion implanting a partial thickness of the epitaxial layer 110, or the current spreading layer 130 can be formed on the surface of the epitaxial layer 110 by an epitaxial process. The first doping layer 140 and the second doping layer 150 can be formed by ion implanting a partial thickness of the current spreading layer 130 in sequence.

[0082] In an embodiment of the present application, the MOSFET includes: a trench that at least penetrates the first doped layer 140 and the second doped layer 150, and the trench may extend to the current spreading layer 130 or the epitaxial layer 120, as shown in reference Figure 3 shown.

[0083] The surface of the trench is covered by a gate dielectric layer 320, that is, the sidewalls and the bottom of the trench are covered by the gate dielectric layer 320. The trench is filled with a gate 310, that is, the gate dielectric layer 320 isolates the gate 310 from the first doped layer 140, the second doped layer 150, the current spreading layer 130 or the epitaxial layer 120.

[0084] As an example, the material of the gate dielectric layer 320 may be silicon oxide, and the material of the gate 310 may be polysilicon.

[0085] The gate dielectric layer 320 and the gate 310 extend along a second direction, and the second direction is perpendicular to a third direction, as shown in reference Figure 6 shown, Figure 6 which schematically shows a top view structural diagram of a semiconductor device provided by an embodiment of the present application.

[0086] As an example, the length of the gate 310 and the gate dielectric layer 320 along the second direction is the same as the length of the current spreading layer 130, that is, the gate 310 and the gate dielectric layer 320 may span the entire current spreading layer 130.

[0087] In an embodiment of the present application, the bottom shielding layer 410 is of a second conduction type. The bottom shielding layer 410 is disposed on a side of the trench close to the first electrode 210, and the bottom shielding layer 410 is disposed on a side of the gate dielectric layer 320 close to the first electrode 210, that is, the bottom shielding layer 410 is disposed below the gate dielectric layer 320. Based on the different conduction types of the bottom shielding layer 410 and the current spreading layer 130 or the epitaxial layer 120, and combined with the fact that the bottom shielding layer 410 is disposed below the gate dielectric layer 320, the electric field shielding of the bottom and the corners of the trench is realized by using the bottom shielding layer 410.

[0088] The bottom shielding layer 410 extends along the second direction, that is, the extending direction of the bottom shielding layer 410 is the same as that of the gate 310 or the gate dielectric layer 320, so as to achieve the electric field shielding effect.

[0089] As a possible implementation manner, in the second direction, the length of the bottom shielding layer 410 is less than the length of the gate 310, that is, the bottom shielding layer 410 with a length less than that of the gate 310 in the second direction protects the bottom and the corners of the trench, as shown in reference Figure 6 shown.

[0090] As another possible implementation, in the second direction, the length of the bottom shielding layer 410 is the same as that of the gate 310, that is, in the second direction, the continuous bottom shielding layer 410 is adopted to protect the bottom and corners of the trench. Refer to Figure 7 as shown.

[0091] In the embodiment of the present application, the MOSFET may be provided with at least one first shielding layer 420. The first shielding layer 420 is of the second conduction type, which is different from the conduction type of the current spreading layer 130 or the epitaxial layer 120, so as to achieve the electric field shielding effect. The first shielding layer 420 is located between the epitaxial layer 120 and the second electrode 220. That is to say, along the second direction, the first shielding layer 420 truncates the current spreading layer 130, the first doping layer 140, and the second doping layer 150, so that the current spreading layer 130, the first doping layer 140, and the second doping layer in some regions are discontinuous in the second direction. Refer to Figure 5 as shown.

[0092] The first shielding layer 420 does not truncate the bottom shielding layer 410, the gate 310, and the gate dielectric layer 320. The first shielding layer 420 is in contact with at least part of the bottom shielding layer 410, that is, the first shielding layer 420 is grounded through contact with at least part of the bottom shielding layer 410. The first shielding layer 420 at least surrounds part of the gate dielectric layer 320 in the first direction, that is, the first shielding layer 420 shields the electric field at the bottom and corners of the trench by surrounding at least part of the gate dielectric layer 320.

[0093] As a possible implementation, the first shielding layer 420 at least surrounds part of the gate dielectric layer 320 in the first direction means that the first shielding layer 420 is only arranged on one side of the trench in the first direction and is in contact with the gate dielectric layer 320 and the bottom shielding layer 410 on that side. Refer to Figure 17 as shown. At this time, the side of the trench where the first shielding layer 420 is not provided can be normally switched by using the gate 310 without being affected by the grounding of the bottom shielding layer 410.

[0094] The first shielding layer 420 extends along the first direction, and the first direction is perpendicular to the second direction and the third direction, that is, the first shielding layer 420 is arranged crosswise with the gate 310 or the gate dielectric layer 320. Along the second direction, the length of the first shielding layer 420 is 1 / N of the length of the bottom shielding layer 410, and N is at least greater than 1. Refer to Figure 6 as shown, that is, the length of the first shielding layer 420 in the second direction is small, so as to avoid the influence on the conduction characteristics of the device due to the too large area of the first shielding layer 420.

[0095] That is to say, by providing the first shielding layer 420 that extends along the first direction, contacts the bottom shielding layer 410, and has a smaller length in the second direction, it is possible to achieve good masking effect while the device has good conduction characteristics.

[0096] In the embodiments of the present application, the trench includes a first-level trench 610 and a second-level trench 620, forming a two-level trench structure. The second-level trench 620 is located on the side of the first-level trench 610 close to the first electrode 210, that is, the second-level trench 620 is located below the first-level trench 610. Along the first direction, the length of the second-level trench 620 is less than the length of the first-level trench 610; the first-level trench 610 at least penetrates the first doping layer 140 and the second doping layer 150 to the current spreading layer 130; the second-level trench 620 is located in the current spreading layer 130 or in the epitaxial layer 120, refer to Figures 8 - 13 as shown. Figure 8 The MOSFET shown is a three-dimensional structure, that is, it extends in three mutually perpendicular directions (the first direction, the second direction, and the third direction). Figure 9 It is a top view structural schematic diagram of the MOSFET. The MOSFET can be sectioned along the planes AA’, BB’, CC’, and DD’ respectively to obtain Figures 10 - 13 .

[0097] That is to say, the corner of the first-level trench 610 is set in the current spreading layer 130, and the corner of the second-level trench 620 can be set in the current spreading layer 130 or in the epitaxial layer 120. The first-level trench 610 and the second-level trench 620 are both provided with the gate 310, and both the first-level trench 610 and the second-level trench 620 have corners. Thus, the two-level trench structure can have 4 corners, and the 4 corners can disperse the electric field lines of the electric field, thereby reducing the peak electric field inside the gate dielectric layer 320, reducing the probability of breakdown of the gate dielectric layer 320, improving the high-voltage spike tolerance in the circuit, and ultimately improving the reliability of the gate dielectric layer 320.

[0098] In the embodiments of the present application, the bottom shielding layer 410 is provided on the side of the second-level trench 620 close to the first electrode 110, that is, the bottom shielding layer 410 is provided below the second-level trench 620, refer to Figure 12 as shown. Along the first direction, the length of the second-level trench 620 is less than the length of the bottom shielding layer 410. Based on the fact that the bottom shielding layer 410 is provided below the second-level trench 620, the distance between the bottom shielding layer 410 and the first doping layer 140 is relatively far, the bottom shielding layer 410 is far from the first doping layer 140, and the JFET effect between the bottom shielding layer 410 and the first doping layer 140 is greatly weakened, which can improve the conduction characteristics of the device.

[0099] In an embodiment of the present application, the first-level trench 610 and the second-level trench 620 are both provided with a gate 310, and the gate 310 can be arranged in the first-level trench 610 and the second-level trench 620 in the following two ways.

[0100] The first arrangement is that the gates 310 of the first-level trench 610 and the second-level trench 620 can be connected to each other, that is, the gates 310 filled in the first-level trench 610 and the second-level trench 620 are of an integral structure, as shown in Figures 8 - 13 shown.

[0101] The second arrangement is that a gate dielectric layer 320 is provided between the gate 310 filled in the first-level trench 610 and the gate 310 filled in the second-level trench 620, as shown in Figure 14 shown, that is, the gates 310 of the first-level trench 610 and the second-level trench 620 may not be connected to each other, and the gates 310 of the first-level trench 610 and the second-level trench 620 are separated by the gate dielectric layer 320. By providing the gate dielectric layer 320 between the gates 310 of the first-level trench 610 and the second-level trench 620, the gate-drain capacitance of the device can be reduced.

[0102] In an embodiment of the present application, the first shielding layer 420 is in contact with the bottom shielding layer 410, and the first shielding layer 420 at least surrounds part of the gate dielectric layer 320. The length of the first shielding layer 420 in the first direction also affects the performance of the device.

[0103] As a possible implementation, along the first direction, the first shielding layer 420 surrounds all of the gate dielectric layer 320 in the first direction. Along the first direction, the length of the first shielding layer 420 is less than the length of the epitaxial layer 120. Along the second direction, the length of the bottom shielding layer 410 is less than the length of the gate 310. That is to say, when the length of the bottom shielding layer 410 in the second direction is small, a first shielding layer 420 with a small length can also be arranged in the first direction to avoid the loss of the on-state characteristics of the device caused by the large area of the first shielding layer 420, as shown in Figure 18 shown.

[0104] As another possible implementation, along the first direction, the first shielding layer 420 surrounds the entire gate dielectric layer 320 in the first direction. Along the first direction, the length of the first shielding layer 420 is equal to the length of the epitaxial layer 120, that is, the first shielding layer 420 spans the entire length of the epitaxial layer 120. The first shielding layer 420 completely cuts off the current spreading layer 130, the first doping layer 140, and the second doping layer 150 in the second direction. Along the second direction, the length of the bottom shielding layer 410 is less than the length of the gate 310. That is to say, when the length of the bottom shielding layer 410 in the second direction is small, a first shielding layer 420 with a longer length can also be set in the first direction, thereby improving the electric field masking effect. Refer to Figure 9 and Figure 13 as shown

[0105] As yet another possible implementation, along the first direction, the first shielding layer 420 surrounds the entire gate dielectric layer 320 in the first direction. Along the first direction, the length of the first shielding layer 420 is equal to the length of the epitaxial layer 120, that is, the first shielding layer 420 spans the entire length of the epitaxial layer 120. The first shielding layer 420 completely cuts off the current spreading layer 130, the first doping layer 140, and the second doping layer 150 in the second direction. Along the second direction, the length of the bottom shielding layer 410 is equal to the length of the gate 310, and the first shielding layer 420 is periodically arranged in the second direction. That is to say, an uninterrupted bottom shielding layer 410 is used to protect the bottom and corners of the trench in the second direction, and multiple first shielding layers 420 can also be periodically arranged in the second direction, thereby improving the electric field masking effect. Refer to Figure 7 as shown Figure 7 The top view cross-sectional view shown schematically shows the realization of the electric field masking effect and the grounding of the bottom shielding layer 410 by periodically arranging multiple first shielding layers 420.

[0106] In the embodiment of the present application, the MOSFET further includes at least two second shielding layers 430, and the second shielding layer 430 is of the second conduction type. The second shielding layer 430 is located between the epitaxial layer 120 and the second electrode 220. Refer to Figure 8 、 Figure 9 and Figure 10 as shown. Along the first direction, at least two second shielding layers 430 are respectively arranged on both sides of the gate 310, and the distance between the second shielding layer 430 and the gate 310 is greater than the distance threshold, that is, the distance between the second shielding layer 430 and the gate 310 is relatively far, avoiding the narrowing of the channel due to a relatively close distance. That is to say, by arranging second shielding layers 430 that do not contact the gate on both sides of the gate 310, further electric field shielding of the bottom and corners of the trench is realized, that is, the trench is further protected.

[0107] The second shielding layer 430 extends along the second direction. The distance between the second shielding layer 430 and the orthographic projection of the bottom shielding layer 410 in the first direction is greater than or equal to 0, that is, the orthographic projections of the second shielding layer 430 and the bottom shielding layer 410 in the first direction do not overlap, that is, when the second shielding layer 430 extends along the second direction, it will not extend to the position where the bottom shielding layer 410 is located. The second shielding layer 430 and the bottom shielding layer 410 are not in the same cross-section. Therefore, there is no serious JFET effect between the second shielding layer 430 and the bottom shielding layer 410, further improving the conduction characteristics of the device.

[0108] As a possible implementation, the MOSFET includes four second shielding layers 430, as shown in Figure 15 shown. Along the first direction, two second shielding layers 430 are arranged oppositely, that is, two second shielding layers 430 are arranged oppositely on both sides of the gate 130. Along the second direction, the first shielding layer 420 is between the two second shielding layers 430, that is, along the second direction, the two second shielding layers 430 are arranged on both sides of the first shielding layer 420. Since the first shielding layer 420 is in contact with the bottom shielding layer 410, and the orthographic projections of the second shielding layer 430 and the bottom shielding layer 410 in the first direction do not overlap, then along the second direction, the two second shielding layers 430 are arranged on both sides of the bottom shielding layer 410. The distance between the second shielding layer 430 and the orthographic projection of the bottom layer shielding layer 410 in the first direction is equal to 0, that is, in the direction parallel to the plane where the substrate 110 is located, the side of the second shielding layer 430 close to the bottom shielding layer 410 and the side of the bottom shielding layer 410 close to the second shielding layer 430 are flush, that is, the second shielding layer 430 and the bottom shielding layer 410 have a cross-section on the same plane. Therefore, there is no Figure 11 BB' cross-section shown in the figure, so as to achieve a balance between the electric field masking effect and the conduction characteristics of the device while reducing the JFET effect between the second shielding layer 430 and the bottom shielding layer 410, and the second shielding layer 430 has sufficient area and can have sufficient electric field masking effect.

[0109] As another possible implementation, the MOSFET includes four second shielding layers 430, as shown in Figure 9As shown. Along the first direction, two second shielding layers 430 are oppositely arranged, that is, the two second shielding layers 430 are oppositely arranged on both sides of the gate 130. Along the second direction, the first shielding layer 420 is located between the two second shielding layers 430, that is, along the second direction, the two second shielding layers 430 are arranged on both sides of the first shielding layer 420. Since the first shielding layer 420 is in contact with the bottom shielding layer 410, and the orthographic projections of the second shielding layer 430 and the bottom shielding layer 410 in the first direction do not overlap, along the second direction, the two second shielding layers 430 are arranged on both sides of the bottom shielding layer 410. The distance between the orthographic projections of the second shielding layer 430 and the bottom shielding layer 410 in the first direction is greater than 0, that is, in the direction parallel to the plane where the substrate 110 is located, the side of the second shielding layer 430 close to the bottom shielding layer 410 and the side of the bottom shielding layer 410 close to the second shielding layer 430 are not flush, that is, no cross-section of the second shielding layer 430 and the bottom shielding layer 410 is in the same plane, thereby maximizing the reduction of the JFET effect between the second shielding layer 430 and the bottom shielding layer 410 and further improving the conduction characteristics of the device.

[0110] In an embodiment of the present application, the MOSFET further includes an interlayer dielectric layer 160, and the interlayer dielectric layer 160 is disposed between the gate 310 and the second electrode 220.

[0111] In an embodiment of the present application, along the second direction, the second doping layer 150, the first masking layer 420, and the second masking layer 430 are staggered, which can effectively reduce the cell size of the device and increase the cell density of the device.

[0112] Specifically, the cell structure of the semiconductor device can be in the shape of a square or a hexagon, etc., as shown in FIGS. 16(a) and 16(b). In FIGS. 16(a) and 16(b), the first masking layer 420 and the second masking layer 430 can be connected, and the shape of the bottom shielding layer 410 can be in the shape of a cross or three rectangular gear shapes.

[0113] In an embodiment of the present application, the semiconductor device includes a first MOSFET and a second MOSFET. The first shielding layer 420 of the first MOSFET is connected to the first shielding layer 420 of the second MOSFET, as shown in Figure 17 As shown. The first shielding layer 420 of the first MOSFET surrounds a part of the gate dielectric layer 320 in the first direction, and the first shielding layer 420 of the second MOSFET surrounds all of the gate dielectric layer 320 in the first direction. That is to say, the first shielding layer 420 of the first MOSFET only surrounds one side of the gate dielectric layer 320, and the first shielding layer 420 of the second MOSFET surrounds all of the gate dielectric layer 320, so as to meet various MOSFET structure designs in actual semiconductor device manufacturing.

[0114] In an embodiment of the present application, a semiconductor device includes a first MOSFET and a second MOSFET. The first shielding layer 420 of the first MOSFET surrounds the entire gate dielectric layer 320 in a first direction, and the first shielding layer 420 of the second MOSFET surrounds the entire gate dielectric layer 320 in the first direction, that is, the first shielding layer 420 of the first MOSFET and the first shielding layer 420 of the second MOSFET both surround the entire gate dielectric layer 320. Along the first direction, the length of the first shielding layer 420 may be less than or equal to the length of the epitaxial layer 120. The distance between the orthographic projections of the first shielding layer 420 of the first MOSFET and the first shielding layer 420 of the second MOSFET in the first direction is greater than 0, that is, the first shielding layer 420 of the first MOSFET and the first shielding layer 420 of the second MOSFET are not connected, and the first shielding layer 420 of the first MOSFET and the first shielding layer 420 of the second MOSFET are not in the same plane in a second direction, and there is no overlap between them in the first direction. The first shielding layers 420 of different MOSFET devices are staggered in the second direction. Refer to Figure 18 As shown. Since the channel is not conducting at the position where the first shielding layer 420 is located, the staggered distribution of the first shielding layers 420 of different MOSFET devices in the second direction can further optimize the current distribution of the semiconductor device, thereby improving the conduction characteristics of the device.

[0115] Refer to Figures 19 - 21 As shown, Figure 19 The schematic diagram of the blocking characteristic current-voltage (I-V) change curve of the MOSFET with a traditional structure and the MOSFET with a two-stage gate trench structure provided by the present application is shown. Refer to Figure 20 As shown, Figure 20 The schematic diagram of the electric field distribution at breakdown of the MOSFET with a traditional structure and the MOSFET with a two-stage gate structure provided by the present application is shown. Refer to Figure 20 As shown, Figure 21 The schematic diagram of the conduction characteristic current-voltage (I-V) change curve of the MOSFET with a traditional structure and the MOSFET with a two-stage gate structure provided by the present application is shown. Figure 19 It is shown that the voltage withstand capabilities of the two structures are not much different. The two-stage gate trench structure and the traditional structure are 1765V and 1803V respectively. However, the peak electric field of the gate oxide layer of the two-stage gate trench structure is less than that of the traditional structure. Refer to Figure 20 As shown, they are 1.85MV / cm and 2.23MV / cm respectively, reducing the probability of the gate dielectric layer being broken down, thereby improving the device performance. The conduction characteristics of the two-stage gate trench structure are better than those of the traditional structure. Refer to Figure 21As shown, the current of the traditional structure quickly saturates as the voltage increases, while the two-stage gate trench structure basically shows a linear change. That is to say, the two-stage gate trench structure provided by this application has better conduction characteristics and blocking characteristics compared with the traditional structure, and the device performance is improved.

[0116] Based on the semiconductor device provided by the above embodiments, the embodiments of this application also provide a manufacturing method of a semiconductor device. Refer to Figure 22 As shown, it is a schematic flowchart of a manufacturing method of a semiconductor device provided by the embodiments of this application.

[0117] The manufacturing method of the semiconductor device provided by the embodiments of this application includes the following steps:

[0118] S101, form an epitaxial layer and a current spreading layer on the substrate in sequence.

[0119] In the embodiments of this application, the material of the substrate 110 can be a wide-bandgap semiconductor material, such as SiC, GaN, Ga2O3, C or AlN. An epitaxial layer 120 and a current spreading layer 130 can be formed on the substrate 110 in sequence. Refer to Figure 23 As shown.

[0120] Specifically, the epitaxial layer 110 can be formed on the substrate 110 by an epitaxial process. The current spreading layer 130 can be formed by ion-implanting a part of the thickness of the epitaxial layer 110, or a current spreading layer 130 can be formed on the surface of the epitaxial layer 110 by an epitaxial process.

[0121] In the embodiments of this application, the substrate 110, the epitaxial layer 120, and the current spreading layer 13 are of the first conduction type.

[0122] As an example, the first conduction type is N-type, that is, the substrate 110, the epitaxial layer 120, and the current spreading layer 130 are N-type.

[0123] S102, perform ion implantation on the current spreading layer to form a first doped layer, a second doped layer, and at least one first shielding layer respectively. The substrate, the epitaxial layer, the current spreading layer, and the second doped layer are of the first conduction type, and the first doped layer is of the second conduction type.

[0124] In the embodiments of this application, after forming the current spreading layer 130, ion implantation can be performed on the current spreading layer 130 to form a first doped layer 140, a second doped layer 150, and at least one first shielding layer 420 respectively. Refer to Figure 24 As shown.

[0125] Specifically, the second doped layer 150 is of the first conduction type, and the first doped layer 140 is of the second conduction type; the first shielding layer 420 is located between the epitaxial layer 120 and the second electrode 220 formed subsequently.

[0126] The first doping layer 140 and the second doping layer 150 can be formed by ion-implanting the current spreading layer 130 with a partial thickness in sequence.

[0127] When ion-implanting the current spreading layer 130, a second shielding layer 430 is also formed. The first shielding layer 420 and the second shielding layer 430 can be formed by using the same mask with the same process, or can be formed by using different masks with two processes.

[0128] S103: Etch at least the first doping layer and the second doping layer to form a trench.

[0129] In an embodiment of the present application, after forming the first doping layer 140 and the second doping layer 150, the first doping layer 140 and the second doping layer 150 can be etched at least to the current spreading layer 130 to form a trench.

[0130] As a possible implementation, the trench includes a first-stage trench 610 and a second-stage trench 620. The second-stage trench 620 is located on a side of the first-stage trench 610 close to the first electrode 210, that is, the second-stage trench 620 is located below the first-stage trench 610. The first doping layer 140 and the second doping layer 150 can be etched to the current spreading layer 130 by a dry etching process to form the first-stage trench 610, and then a sidewall is formed on the sidewall of the first-stage trench 610 by depositing and etching silicon oxide. The position of the second-stage trench 620 is defined by the sidewall, and the current spreading layer 130 is etched again to the epitaxial layer 120 with the sidewall as a mask to form the second-stage trench 620, as shown in Figure 25 shown.

[0131] S104: Ion-implant the bottom of the trench to form a bottom shielding layer; the bottom shielding layer extends along a second direction, the second direction is perpendicular to a third direction, and the third direction is a direction perpendicular to the surface of the substrate; the bottom shielding layer is of a second conductivity type.

[0132] In an embodiment of the present application, after forming the trench, the bottom of the trench can be ion-implanted to form a bottom shielding layer 410. The bottom shielding layer 410 extends along a second direction, the second direction is perpendicular to a third direction, and the third direction is a direction perpendicular to the surface of the substrate 110; the bottom shielding layer 410 is of a second conductivity type.

[0133] As a possible implementation, the trench includes a first-stage trench 610 and a second-stage trench 620. The bottom of the second-stage trench 620 can be ion-implanted to form a bottom shielding layer 410, as shown in Figure 26 shown.

[0134] The first shielding layer 420 is in contact with at least a part of the bottom shielding layer 410, and the first shielding layer 420 at least surrounds a part of the gate dielectric layer 320 in a first direction; the first shielding layer 410 extends along the first direction, and the first direction is perpendicular to the second direction and the third direction; along the second direction, the length of the first shielding layer 420 is 1 / N of the length of the bottom shielding layer 410, and N is at least greater than 1.

[0135] S105. Form a gate dielectric layer and a gate in the trench; the gate dielectric layer and the gate extend along the second direction.

[0136] In an embodiment of the present application, after forming the trench, a gate dielectric layer 320 and a gate 310 are formed in the trench; the gate dielectric layer 320 and the gate 310 extend along the second direction.

[0137] As a possible implementation manner, the trench includes a first-stage trench 610 and a second-stage trench 620. The gate dielectric layer 320 is formed by a thermal oxidation process, and then polysilicon is deposited and etched to form the gate 310.

[0138] An interlayer dielectric layer 160 is deposited and etched on the gate 310, refer to Figure 27 as shown.

[0139] S106. Form a first electrode on the side of the substrate away from the epitaxial layer, and form a second electrode on the side of the second doped layer away from the substrate.

[0140] In an embodiment of the present application, a first electrode 210 is formed on the side of the substrate 110 away from the epitaxial layer 120, and a second electrode 220 is formed on the side of the second doped layer 150 away from the substrate 110, refer to Figure 8 as shown.

[0141] Specifically, the first electrode 210 or the second electrode 220 is made of a material with good conductivity, such as a metal material. As an example, the first electrode 210 is a drain electrode, and the second electrode 220 is a source electrode.

[0142] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key points of each embodiment are the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the structure embodiments, they are described relatively simply, and the relevant parts can refer to the description of the structure embodiments.

[0143] The above are only the preferred embodiments of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solution of the present application shall still be within the scope of protection of the technical solution of the present application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises at least one metal oxide semiconductor field effect transistor MOSFET, wherein the MOSFET comprises: A first electrode, a substrate, an epitaxial layer, a current spreading layer, a first doped layer, a second doped layer, and a second electrode are stacked in sequence; the substrate, the epitaxial layer, the current spreading layer, and the second doped layer are of a first conductivity type, and the first doped layer is of a second conductivity type; a groove at least penetrating the first doped layer and the second doped layer, the surface of the groove being covered by a gate dielectric layer, and the groove being filled with a gate; the gate dielectric layer and the gate extending along a second direction, the second direction being perpendicular to a third direction, and the third direction being perpendicular to a surface direction where the first electrode is located; A bottom shielding layer, the bottom shielding layer is arranged on a side of the groove close to the first electrode, the bottom shielding layer extends along the second direction; the bottom shielding layer is of the second conductivity type; At least one first shielding layer, the first shielding layer is of the second conductivity type; the first shielding layer is located between the epitaxial layer and the second electrode, the first shielding layer is in contact with at least a portion of the bottom shielding layer, and the first shielding layer at least surrounds a portion of the gate dielectric layer in a first direction; the first shielding layer extends along a first direction, and the first direction is perpendicular to the second direction and the third direction; along the second direction, the length of the first shielding layer is 1 / N of the length of the bottom shielding layer, and N is at least greater than 1.

2. The semiconductor device according to claim 1, wherein: The grooves include a first-level groove and a second-level groove, wherein the second-level groove is located on a side of the first-level groove close to the first electrode; Along the first direction, the length of the second-level groove is smaller than the length of the first-level groove; The first-level trench at least penetrates the first doping layer and the second doping layer to the current spreading layer; The second-level trench is located in the current spreading layer or in the epitaxial layer.

3. The semiconductor device according to claim 2, characterized in that The bottom shielding layer is disposed on a side of the second-level trench close to the first electrode, and along the first direction, the length of the second-level trench is smaller than the length of the bottom shielding layer.

4. The semiconductor device according to claim 2, characterized in that A gate dielectric layer is arranged between the gate filled with the first-level trench and the gate filled with the second-level trench.

5. The semiconductor device according to claim 1, wherein: Along the first direction, the length of the first shielding layer is the same as the length of the epitaxial layer; the first shielding layer surrounds the gate dielectric layer in the first direction; Along the second direction, the length of the bottom shielding layer is the same as the length of the gate; The first shielding layers are periodically arranged in the second direction.

6. The semiconductor device according to claim 1, wherein: The MOSFET further comprises: at least two second shielding layers; The second shielding layer is located between the epitaxial layer and the second electrode; along the first direction, the at least two second shielding layers are respectively arranged on both sides of the gate, and the distance between the second shielding layer and the gate is greater than a distance threshold; the distance between the second shielding layer and the orthographic projection of the bottom shielding layer in the first direction is greater than or equal to 0; the second shielding layer extends along the second direction.

7. The semiconductor device according to claim 6, characterized in that The MOSFET includes four second shielding layers; Along the first direction, two second shielding layers are arranged opposite to each other; along the second direction, the first shielding layer is between the two second shielding layers; and a distance between the orthographic projections of the second shielding layer and the bottom shielding layer in the first direction is greater than 0.

8. The semiconductor device according to claim 6, characterized in that The MOSFET includes four second shielding layers; Along the first direction, two second shielding layers are arranged opposite to each other; along the second direction, the first shielding layer is between the two second shielding layers; and the distance between the orthographic projections of the second shielding layer and the bottom shielding layer in the first direction is equal to 0.

9. The semiconductor device according to claim 1, wherein: The semiconductor device comprises a first MOSFET and a second MOSFET; The first shielding layer of the first MOSFET is connected to the first shielding layer of the second MOSFET; The first shielding layer of the first MOSFET surrounds a portion of the gate dielectric layer in a first direction; The first shielding layer of the second MOSFET surrounds the entire gate dielectric layer in a first direction.

10. The semiconductor device according to claim 1, wherein: The semiconductor device comprises a first MOSFET and a second MOSFET; A distance between the orthographic projections of the first shielding layer of the first MOSFET and the first shielding layer of the second MOSFET in the first direction is greater than 0; The first shielding layer of the first MOSFET surrounds the entire gate dielectric layer in the first direction; the first shielding layer of the second MOSFET surrounds the entire gate dielectric layer in the first direction.

11. A method for manufacturing a semiconductor device, characterized in that: include: forming an epitaxial layer and a current spreading layer on the substrate in sequence; Performing ion implantation on the current spreading layer to form a first doping layer, a second doping layer and at least one first shielding layer, respectively, the substrate, the epitaxial layer, the current spreading layer and the second doping layer are of the first conductivity type, and the first doping layer is of the second conductivity type; etching at least the first doping layer and the second doping layer to form a groove; Ion implantation is performed on the bottom of the trench to form a bottom shielding layer; the bottom shielding layer extends along the second direction, the second direction is perpendicular to the third direction, and the third direction is perpendicular to the surface direction of the substrate; The bottom shielding layer is of the second conductivity type; A gate dielectric layer and a gate are formed in the trench; the gate dielectric layer and the gate extend along a second direction; forming a first electrode on a side of the substrate away from the epitaxial layer, and forming a second electrode on a side of the second doped layer away from the substrate; The first shielding layer is in contact with at least a portion of the bottom shielding layer, and the first shielding layer surrounds at least a portion of the gate dielectric layer in a first direction; The first shielding layer extends along a first direction, the first direction being perpendicular to the second direction and the third direction; Along the second direction, the length of the first shielding layer is 1 / N of the length of the bottom shielding layer, and N is at least greater than 1.

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