950V Super Junction MOS Device with Deep Trench Filling Structure and Its Manufacturing Method

Abstract

The present invention discloses a 950V superjunction MOS device with a deep trench filling structure and its fabrication method. The device features discontinuous polysilicon deposition and a separate gate-source ESD protection zone. The entire device undergoes secondary epitaxial growth using an N-type substrate, expanding multiple functional layers under optimal conditions. This invention alleviates charge imbalance caused by uneven trench widths due to etching angles by using a twice-epitaxy N-type substrate. The device also etches polysilicon to separate cells, connecting one half to the gate metal and the other half to the source metal, forming a dummy structure with a 1:1 ratio of true to dummy cells. This effectively addresses the issue of excessive input capacitance and optimizes the device's dynamic characteristics without compromising withstand voltage and dynamic on-resistance. Furthermore, ESD protection is provided between the gate and source electrodes to prevent device damage from transient high voltage and high current conditions.

Description

Technical Field

[0001] The present invention relates to the field of electronic science and technology, and more particularly to a 950V super junction MOS device with a deep trench filling structure and a manufacturing method thereof. Background Art

[0002] Power devices with a voltage rating of 950V are widely used in industrial variable-frequency drives, solar inverters, and uninterruptible power supplies (UPS). Due to the physical limitations of traditional power MOSFETs, the on-resistance and breakdown voltage exhibit a difficult-to-break 2.5-power relationship. This means that as the breakdown voltage increases, the on-resistance increases dramatically, leading to increased conduction losses and reduced efficiency. To alleviate this problem, the superjunction (SuperJunction) structure has been developed. Its principle is to introduce alternating P-type and N-type pillars in the drift region to optimize the electric field distribution, thereby increasing the breakdown voltage while reducing the on-resistance. Superjunction structures are primarily fabricated using two processes: multiple epitaxial growth and deep trench filling. Currently, most 950V SuperJunction MOSFETs on the market use a multiple epitaxial growth process, with six to seven epitaxial growth passes.

[0003] For the convenience of combining the instructions with the attached drawings Figure 3 Give an explanation, Figure 3 This is a schematic cross-sectional view of a conventional deep trench fill high-voltage super-junction MOS device structure. It includes an N+ substrate 301, a primary N-type epitaxial growth 302, a JFET implant region 303, a deep trench fill P-pillar region 304, a Pbody implant region 305, a gate oxide layer 306, a polysilicon deposition 307, an N+ source implant region 308, a dielectric layer 309, a front metal electrode 310, and a back metal electrode 311. The polysilicon deposition 307 forms a continuous, integrated structure. Deep trench fill presents several challenges at high voltages above 950V. For example, due to the high voltage level of 950V, the thickness of the epitaxial wafer typically reaches approximately 75µm, while the depth of the P-pillar formed by the deep trench etch reaches 65µm. Such a deep P-pillar trench etch inevitably creates a significant width difference between the trench surface and bottom due to the etch angle, making it impossible to precisely control the doping concentration and size of the pillars of different conductivity types in the super-junction structure. This results in a failure to further increase the device's breakdown voltage and makes it difficult to achieve an ideal balance between the device's breakdown voltage and on-resistance. Furthermore, existing manufacturing processes can introduce numerous defects, impacting device reliability and stability. Furthermore, due to the limited cell size at a 950V withstand voltage, switching losses remain high, limiting performance in high-frequency applications. Summary of the Invention

[0004] In view of the deficiencies in the prior art, the present invention aims to provide a 950V super junction MOS device with a deep trench filling structure and a method for manufacturing the same, so as to solve one or more of the above problems.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A 950V superjunction MOS device with a deep trench filling structure comprises an N+ substrate, wherein a primary N-type epitaxial layer and a secondary N-type epitaxial layer are sequentially provided on the front side of the N+ substrate upward, a recessed JFET injection region is provided on the secondary N-type epitaxial layer, deep trench filling P column regions are provided on both sides of the primary N-type epitaxial layer and the secondary N-type epitaxial layer, a Pbody injection region is provided on the surface of the deep trench filling P column region, a gate oxide layer is provided on the surface of the Pbody injection region and the secondary N-type epitaxial layer, a polysilicon deposition is provided on the gate oxide layer, the polysilicon deposition is discontinuous, a recessed N+ source injection region is further provided on the gate oxide layer, the N+ source injection region contacts the Pbody injection region, and a dielectric layer is further provided on the gate oxide layer, the dielectric layer covers the polysilicon deposition and contacts the N+ source injection region and the JFET injection region;

[0007] A back metal electrode is provided on the back of the N+ substrate, a front metal electrode is provided on the front of the gate oxide layer, and the front metal electrode covers the dielectric layer and contacts the N+ source injection region.

[0008] Furthermore, a gate-source ESD protection zone is provided on the gate oxide layer, the top periphery of the gate-source ESD protection zone is the source metal, the top center of the gate-source ESD protection zone is the gate metal, the source metal corresponds to the front metal electrode, an ESD diode string N-type region is provided in the gate-source ESD protection zone, and the back metal electrode corresponds to the drain metal.

[0009] Furthermore, all parts of the gate-source ESD protection zone except the N-type zone of the ESD diode string are P-type zones, and the N-type zone of the ESD diode string shares a common plate with the N+ source injection zone.

[0010] Furthermore, the JFET implantation region on the secondary N-type epitaxy is an N-type region, and the polysilicon deposition is in the active region.

[0011] A method for manufacturing a 950V super junction MOS device with a deep trench filling structure, comprising the following steps:

[0012] S1. Prepare an N+ substrate, and sequentially grow a primary N-type epitaxial layer and a secondary N-type epitaxial layer on the N+ substrate;

[0013] S2, growing a thin pre-oxidation layer on the secondary N-type epitaxial growth, and performing N-type JFET implantation to form a JFET implantation region, and removing the thin pre-oxidation layer;

[0014] S3, deep trench etching and P-type epitaxial filling are performed on the primary N-type epitaxy and the secondary N-type epitaxy to form P pillars, and a sacrificial oxide layer is grown on the surface and completely removed to keep the surface smooth;

[0015] S4. Grow a thin pre-oxidation layer on the flat surface, and perform high-dose, low-energy P-type body implantation, and push the junction at high temperature to form the Pbody implantation region;

[0016] S5. Thermally depositing a field oxide layer on the surface, etching the active area, growing a gate oxide layer in the active area, depositing gate polysilicon to form a polysilicon deposition, and etching and separating the gate;

[0017] Deposit the oxide layer, then perform general implantation and etching to form ESD polysilicon in the gate PAD area to form ESD protection for the device;

[0018] S6. Etch the oxide layer and inject it to form the N+ source injection area, activate the source and ESD protection area, deposit and reflow the ILD, open the hole to complete the metal deposition and etching, deposit and etch the surface medium and organic matter to form the front metal electrode, and metallize the back of the N+ substrate to form the back metal electrode.

[0019] Furthermore, the resistivity of the first N-type epitaxy and the second N-type epitaxy in step S1 is different, the thickness of the thin pre-oxidation layer in step S2 is 200 angstroms, and the injection condition of the JFET injection region is 2e12cm -2 / 60keV.

[0020] Furthermore, the deep trench etching in step S3 is performed by wet etching, with a trench depth of 65 μm, a trench width of 5 μm, an etching angle of 88.8°, and a P-type epitaxial filling concentration of 4.2e15 cm -2 .

[0021] Furthermore, the thickness of the thin pre-oxidation layer in step S4 is 200 angstroms, and the implantation condition of the P-body region is 6e13cm -2 / 60keV, annealing condition is 1100℃, annealing time is 180min.

[0022] Furthermore, in step S5, the ambient temperature of the surface thermal deposition is 980°C, the thickness of the field oxide layer is 8000 angstroms; the growth temperature of the gate oxide layer is 1050°C, the growth thickness is 1000 angstroms, and the growth time is 90 minutes; the self-doping concentration of the polysilicon deposition is 4.3e20cm -3 , with a thickness of 4000 angstroms; the polysilicon gate area in the middle of each cell in the gate area is etched 1.6μm for Dummy design; the oxide layer deposition thickness before general injection is 2000 angstroms to facilitate the isolation of the ESD polysilicon in the gate PAD area; the ESD polysilicon thickness of the gate PAD area is 6000 angstroms, and the general injection condition is 1e14cm -2 / 80keV.

[0023] Furthermore, the remaining thickness of the oxide layer after etching in step S6 is 200 angstroms; the injection activation condition of the source region and the ESD protection zone is 5e15cm of arsenic ions. -2 / 50keV, annealing temperature is 950℃, annealing time is 30min; ILD interlayer dielectric thickness is 11200 angstroms, dense reflow temperature is 900℃, dense reflow time is 30min; the opening size before metal deposition etching is 3μm, and the hole injection condition is 1.25e15cm of boron difluoride. -2 / 40keV, 3.5e15cm for boron -2 / 80keV, and perform rapid annealing for 15s; deposit 4μm aluminum-copper alloy front metal electrode and back metal electrode.

[0024] In summary, the present invention has the following beneficial effects:

[0025] 1. The top trench of the entire superjunction structure is 5μm wide, 65μm deep, and etched at an angle of 88.8°. Due to the high voltage level, the trench is deep, and the etching angle makes the trench width in the lower half narrower. A single epitaxial growth is difficult to ensure withstand voltage, so double epitaxy is required to alleviate this problem. The N-type substrate with two epitaxies can alleviate the charge imbalance caused by the uneven trench width caused by the etching angle.

[0026] 2. By etching and separating the polysilicon of the cell, half is connected to the gate metal and the other half is connected to the source metal to form a dummy structure. The ratio of real and dummy cells is 1:1, which effectively solves the problem of excessive input capacitance and effectively optimizes the dynamic characteristics of the device without affecting the withstand voltage and dynamic on-resistance.

[0027] 3. By setting ESD protection between the gate and source electrodes, the device is prevented from being damaged in transient high voltage and high current conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic cross-sectional view of an embodiment of the present invention;

[0029] Figure 2 A schematic top view of a gate-source ESD protection zone in accordance with an embodiment of the present invention;

[0030] Figure 3 A schematic cross-sectional view of the structure of a conventional deep trench-filled high-voltage super-junction MOS device provided by the present invention;

[0031] Figure 4 IV comparison curve diagram provided by the present invention and the prior art;

[0032] Figure 5A comparison graph of the Ciss-V provided by the present invention and the prior art;

[0033] Figure 6 This is a structural diagram of step S1 of the manufacturing method according to an embodiment of the present invention;

[0034] Figure 7 This is a structural diagram of step S2 of the manufacturing method according to an embodiment of the present invention;

[0035] Figure 8 This is a structural diagram of step S3 of the manufacturing method according to an embodiment of the present invention;

[0036] Figure 9 This is a structural diagram of step S4 of the manufacturing method according to an embodiment of the present invention;

[0037] Figure 10 This is a structural diagram of step S5 of the manufacturing method according to an embodiment of the present invention;

[0038] Figure 11 This is a structural diagram of the implementation of step S6 of the manufacturing method provided by one embodiment of the present invention.

[0039] In the figure: 101, N+ substrate; 102, primary N-type epitaxy; 103, secondary N-type epitaxy; 104, JFET implant region; 105, deep trench filling P column region; 106, Pbody implant region; 107, gate oxide layer; 108, polysilicon deposition; 109, N+ source implant region; 110, dielectric layer; 111, front metal electrode; 112, back metal electrode; 201, gate PAD region ESD polysilicon; 202, ESD diode string N-type region; 203, source metal; 204, gate metal;

[0040] 301. N+ substrate; 302. Primary N-type epitaxy; 303. JFET implantation region; 304. Deep trench filling P column region; 305. Pbody implantation region; 306. Gate oxide layer; 307. Polysilicon deposition; 308. N+ source implantation region; 309. Dielectric layer; 310. Front metal electrode; 311. Back metal electrode. DETAILED DESCRIPTION

[0041] Example:

[0042] The following is combined with Figure 1-11 The present invention is described in further detail.

[0043] A method for manufacturing a 950V super junction MOS device with a deep trench filling structure mainly includes six steps:

[0044] S1. Prepare an N-type doped substrate to form an N+ substrate 101. Clean the original wafer and grow the first N-type epitaxial layer and the second N-type epitaxial layer to form a primary N-type epitaxial 102 and a secondary N-type epitaxial 103. The primary N-type epitaxial 102 and the secondary N-type epitaxial 103 are designed to be two epitaxial layers with different resistivities. The resistivity of the primary N-type epitaxial 102 is higher than that of the secondary N-type epitaxial 103. Since there is an etching angle in the subsequent deep trench etching based on the two epitaxial layers, the deeper the area, the narrower the trench width, and the lower the total amount of charge of the corresponding P column, so the resistivity of the primary N-type epitaxial 102 is slightly higher. In contrast, the resistivity of the secondary N-type epitaxial 103 is lower because the total amount of charge of the P column in the upper half of the etching where it is located is higher, and the following is obtained: Figure 6 Device with the structure shown.

[0045] Among them, an arsenic-doped N-type substrate with a resistivity of 0.002~0.003Ω·cm is preferably selected, and a first N-type epitaxial layer 102 is grown at a temperature of 1000°C. The doping element of the first N-type epitaxial layer 102 is phosphorus, the thickness is 42μm, and the resistivity is 3.4Ω·cm; then a second N-type epitaxial layer 103 is grown at a temperature of 1000°C. The doping element of the second N-type epitaxial layer 103 is phosphorus, the thickness is 33μm, and the resistivity is 2.0Ω·cm.

[0046] S2. On the basis of the secondary N-type epitaxy 103, a thin pre-oxidation layer with a thickness of 200 angstroms is grown. The N-type JFET injection region 104 is defined by photolithography. N-type impurities are injected at high energy to form the JFET injection region 104 of the N-type planar gate MOS. The injection angle is 7°, the injection energy is 60 keV, and the injection dose is 2e12 cm -2 After the injection is completed, the surface oxide layer is removed and the Figure 7 Device with the structure shown.

[0047] S3. Continue to perform deep trench etching on the chip by wet etching, with an etching angle of 88.8°, an etching depth of 65 μm, and an etching width of 5 μm. After the etching is completed, perform P column epitaxial filling to form a deep trench filled P column area 105. The impurity of the epitaxial filling is boron, the filling thickness is 65 μm, and the filling concentration is 4.2e15 cm -2 The trench depth, trench width and P column concentration directly affect the voltage resistance performance of the super junction MOS tube.

[0048] Continue to grow a sacrificial oxide layer on the surface at a growth temperature of 900°C. The thickness of the sacrificial oxide layer is 1265 angstroms. The oxide layer is completely removed using the CMP process to keep the surface flat. Figure 8 Device with the structure shown.

[0049] S4. Continue to grow a thin pre-oxidation layer with a thickness of about 200 angstroms on the flat surface at a growth temperature of 950°C, and perform high-dose, low-energy P-type body implantation. The implanted impurity is boron, the implantation angle is 7°, and the implantation dose is 6e13cm -2 The injection energy is 60keV, the high temperature junction is formed into the Pbody injection region 106, the junction temperature is 1100℃, the junction time is 180min, and the entire region is actually the active region. Figure 9 Device with the structure shown.

[0050] S5. After the implantation and push-in of the active area is completed, a field oxide layer is thermally deposited on the chip surface. The thermal deposition temperature is 980°C, the thickness of the field oxide layer is 8000 angstroms, and the active area is etched.

[0051] A gate oxide layer 107 is grown in the active area at a growth temperature of 1050°C, a growth thickness of 1000 angstroms, and a growth time of 90 minutes. Gate polysilicon is deposited to form a polysilicon deposition 108, and the self-doping concentration of the polysilicon deposition 108 is 4.3e20cm -3 , thickness is 4000 angstroms;

[0052] The polysilicon gate region in the middle of each cell in the gate area is etched 1.6μm to create a dummy design. Half of the polysilicon in a single cell is connected to the source and half is connected to the gate. The ratio of true to false cells in the dummy structure is 1:1. The device's withstand voltage remains unchanged, but the resistance increases slightly by the resistance of the JFET region's accumulation layer. However, the input capacitance and reverse transfer capacitance can be reduced to half of their original values.

[0053] Etching and separating the gate;

[0054] like Figure 2 As shown, an oxide layer is deposited with a thickness of 2000 angstroms. The purpose of this operation is to facilitate the isolation of the gate PAD region ESD polysilicon 201; undoped ESD polysilicon is deposited 108 with a deposition thickness of 6000 angstroms; and then general implantation and etching are performed to form the gate PAD region ESD polysilicon 201 to form the ESD protection of the device. The gate PAD region ESD polysilicon 201 has a thickness of 6000 angstroms. The general implanted impurity is boron, the implantation angle is 7°, and the implantation dose is 1e14 cm -2 , the injection energy is 80keV, and the remaining etching thickness is 200 angstroms; the dotted part is the built-in ESD diode string N-type region 202, and the other areas of the ESD polysilicon are P-type regions. The N-type region, active region and subsequent N+ source injection region 109 share a common plate. The bottom periphery of the region is gate metal 204, and the center is source metal 203. Figure 10 Device with the structure shown.

[0055] S6. The etched oxide layer is photolithographically defined and implanted to form an N+ source implant region 109, activating the source and ESD protection zone. The implanted object is arsenic ions with an implantation energy of 50 keV and an implantation dose of 5e15 cm -2 The annealing activation temperature is 950℃ and the annealing activation time is 30min.

[0056] Plasma-enhanced chemical vapor deposition was used to deposit and reflow the ILD. The ILD interlayer dielectric thickness was 11,200 angstroms, the dense reflow temperature was 900°C, and the dense reflow time was 30 minutes.

[0057] The hole is defined by photolithography and etched using a wet-and-dry process. The metal deposition and etching are completed. After the passivation layer is deposited, the lead area is photolithographically etched again. The hole size before metal deposition and etching is 3μm, and the hole injection condition is 1.25e15cm of boron difluoride. -2 / 40keV, 3.5e15cm for boron -2 / 80keV, and rapid annealing for 15s;

[0058] The surface dielectric and organic matter are deposited and etched to form a front metal electrode 111, the back of the N+ substrate 101 is metallized to form a back metal electrode 112, and a 4μm aluminum-copper alloy front metal electrode 111 and a back thinned metal electrode are deposited to obtain the following: Figure 11 Device with the structure shown.

[0059] The 950V super junction MOS device with deep trench filling structure obtained by the above process, such as Figure 1As shown, a continuous primary N-type epitaxy 102 and a secondary N-type epitaxy 103 are sequentially provided on the front side of an N+ substrate 101, a recessed JFET injection region 104 is provided on the secondary N-type epitaxy 103, deep trench filling P column regions 105 are provided on both sides of the primary N-type epitaxy 102 and the secondary N-type epitaxy 103, a Pbody injection region 106 is provided on the surface of the deep trench filling P column region 105, a gate oxide layer 107 is provided on the surface of the Pbody injection region 106 and the secondary N-type epitaxy 103, a polysilicon deposition 108 is provided on the gate oxide layer 107, and the polysilicon deposition 108 is provided on the gate oxide layer 107. 8 is a discontinuous structure, a recessed N+ source injection region 109 is further provided on the gate oxide layer 107, the N+ source injection region 109 contacts the Pbody injection region 106, a dielectric layer 110 is further provided on the gate oxide layer 107, the dielectric layer 110 covers the polysilicon deposition 108 and contacts the N+ source injection region 109 and the JFET injection region 104; a back metal electrode 112 is provided on the back side of the N+ substrate 101, and a front metal electrode 111 is provided on the front side of the gate oxide layer 107, the front metal electrode 111 covers the dielectric layer 110 and contacts the N+ source injection region 109. That is, a primary N-type epitaxial growth 102 and a secondary N-type epitaxial growth 103 are grown on an N+ substrate 101, and after the second epitaxial growth, a JFET injection region 104 is formed by injection. After deep trench etching and P-type epitaxial filling, a deep trench filling P column region 105 is formed. After sacrificial oxygen treatment, the surface of the flat device is injected to activate the Pbody injection region 106, and a gate oxide layer 107 is continuously grown. Polysilicon deposition 108 is deposited on the gate oxide layer 107, and after etching the oxide layer, an N+ source injection region 109 is formed by injection. An ILD dense reflow is deposited to form a dielectric layer 110. After hole etching and hole injection, a front metal electrode 111 is deposited, and the back side is thinned and metalized to form a back side metal electrode 112.

[0060] A gate-source ESD protection zone is provided on the gate oxide layer 107 to protect the gate from transient voltage and high current between the gate and source. The top edge of the gate-source ESD protection zone is the source metal 204, and the top center of the gate-source ESD protection zone is the gate metal 203. The source metal 203 corresponds to the front metal electrode 111. The gate-source ESD protection zone contains the ESD diode string N-type region 202, and the back metal electrode 112 corresponds to the drain metal. The source metal 203 is formed by depositing metal on the device surface and a portion of the polysilicon source electrode. The drain metal is formed below the N+ substrate 101, and the gate metal 204 is formed on another portion of the polysilicon deposition 108.

[0061] like Figure 4As shown, the IV comparison curve of the present application and the existing structure is a two-dimensional simulated line current. The breakdown voltage of the device of the present application is much higher than that of the conventional super junction MOS tube. The two structures differ greatly in voltage magnitude. The breakdown voltage of the conventional super junction MOS tube can only reach 980V, which cannot reach the required 1100V voltage level. This is mainly due to the single-epitaxial super junction MOS structure. Due to the deep trench etching angle problem, the charge is unbalanced, and the device cannot achieve charge balance like the case of 90° etching.

[0062] like Figure 5 As shown, it is a comparison curve of the Ciss-V characteristics of the present application and the existing structure. Due to the limitations of the deep trench etching super junction process, the cells of the existing structure are generally smaller. Under the same area, it will cause the dynamic parameters such as capacitance charge to be larger. The structure of the present application has a double epitaxial Dummy feature, which can optimize the internal charge imbalance and optimize the electric field distribution at the bottom and top of the P column and N column, similar to the double super junction MOS structure. In addition, the polysilicon gate is etched and the origin and gate are connected respectively to form a Dummy structure, which effectively optimizes the dynamic parameters such as the device input capacitance and reverse transfer capacitance.

[0063] The total charge of the entire primary N-type epitaxy 102 is essentially equal to the total positive and negative charge of the P-pillar in the lower half of the deep trench-filled P-pillar region 105. The total charge of the secondary N-type epitaxy 103 is essentially equal to the total positive and negative charge of the P-pillar in the upper half of the deep trench-filled P-pillar region 105. The purpose of the double N-type epitaxy is to alleviate the charge imbalance problem caused by the P-pillar trench etching angle. By adjusting the resistivity of the double epitaxy and the epitaxial concentration of the P-pillar, the voltage resistance of the super-junction MOS transistor can be adjusted. Simply by adjusting the concentration of the primary N-type epitaxy 102 and the secondary N-type epitaxy 103 to maintain balance with the charge of the P-pillar, a deep trench-filled high-voltage super-junction MOS device with a controllable breakdown voltage exceeding 950V and up to 1150V can be manufactured. The implantation dose and implantation energy of the Pbody implantation region 106 can adjust the threshold voltage of the super-junction MOS transistor. By separating and etching the polysilicon deposit 108, the cell is connected to the source on one side and the gate on the other side to form a Dummy structure. Without affecting the withstand voltage and on-resistance, the input capacitance and Miller capacitance can be reduced by nearly half, achieving low dynamic characteristics.

[0064] After optimizing the structural design and manufacturing process, this application effectively reduces the on-resistance, improves the breakdown voltage level and related stability, while reducing switching losses, and significantly improves the overall performance.

[0065] It should be noted that this specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to this embodiment as needed, but as long as they are within the scope of the claims of the present invention, they are protected by patent law.

Claims

1. A 950V super junction MOS device with a deep trench filling structure, characterized in that: The invention comprises an N+ substrate, wherein a first N-type epitaxial layer and a second N-type epitaxial layer are sequentially provided on the front side of the N+ substrate upward, a recessed JFET injection region is provided on the second N-type epitaxial layer, deep trench-filled P-pillar regions are provided on both sides of the first N-type epitaxial layer and the second N-type epitaxial layer respectively, a Pbody injection region is provided on the surface of the deep trench-filled P-pillar region, a gate oxide layer is provided on the surface of the Pbody injection region and the second N-type epitaxial layer, a polysilicon deposition is provided on the gate oxide layer, the polysilicon deposition is a discontinuous structure, a recessed N+ source injection region is further provided on the gate oxide layer, the N+ source injection region contacts the Pbody injection region, and a dielectric layer is further provided on the gate oxide layer, the dielectric layer covers the polysilicon deposition and contacts the N+ source injection region and the JFET injection region; A back metal electrode is provided on the back of the N+ substrate, a front metal electrode is provided on the front of the gate oxide layer, the front metal electrode covers the dielectric layer and contacts the N+ source injection region; A gate-source ESD protection zone is provided on the gate oxide layer. The top periphery of the gate-source ESD protection zone is the source metal, the top center of the gate-source ESD protection zone is the gate metal, the source metal corresponds to the front metal electrode, an ESD diode string N-type region is provided in the gate-source ESD protection zone, and the back metal electrode corresponds to the drain metal.

2. The 950V super junction MOS device with a deep trench filling structure according to claim 1, wherein: Except for the N-type region of the ESD diode string, the rest of the gate-source ESD protection zone is a P-type region, and the N-type region of the ESD diode string shares a common plate with the N+ source injection region.

3. The 950V super junction MOS device with a deep trench filling structure according to claim 2, wherein: The JFET injection region on the secondary N-type epitaxy is an N-type region, and the polysilicon deposition is in the active region.

4. A method for fabricating a 950V super junction MOS device with a deep trench filling structure, characterized in that: Here are the steps: S1. Prepare an N+ substrate, and sequentially grow a primary N-type epitaxial layer and a secondary N-type epitaxial layer on the N+ substrate; S2, growing a thin pre-oxidation layer on the secondary N-type epitaxial growth, and performing N-type JFET implantation to form a JFET implantation region, and removing the thin pre-oxidation layer; S3, deep trench etching and P-type epitaxial filling are performed on the primary N-type epitaxy and the secondary N-type epitaxy to form P pillars, and a sacrificial oxide layer is grown on the surface and completely removed to keep the surface smooth; S4. Grow a thin pre-oxidation layer on the flat surface, and perform high-dose, low-energy P-type body implantation, and push the junction at high temperature to form the Pbody implantation region; S5. Thermally depositing a field oxide layer on the surface, etching the active area, growing a gate oxide layer in the active area, depositing gate polysilicon to form a polysilicon deposition, and etching and separating the gate; Deposit an oxide layer, then implant and etch to form ESD polysilicon in the gate PAD area to form ESD protection for the device. A gate-source ESD protection zone is provided on the gate oxide layer. The top edge of the gate-source ESD protection zone is the source metal, and the top center of the gate-source ESD protection zone is the gate metal. The source metal corresponds to the front metal electrode. An ESD diode string N-type region is provided in the gate-source ESD protection zone, and the back metal electrode corresponds to the drain metal. S6. Etch the oxide layer and inject it to form the N+ source injection area, activate the source and ESD protection area, deposit and reflow the ILD, open the hole to complete the metal deposition and etching, deposit and etch the surface medium and organic matter to form the front metal electrode, and metallize the back of the N+ substrate to form the back metal electrode.

5. The method for manufacturing a MOS device according to claim 4, wherein: The resistivity of the first N-type epitaxy and the second N-type epitaxy in step S1 is different. The thickness of the thin pre-oxidation layer in step S2 is 200 angstroms. The injection condition of the JFET injection region is 2e12cm -2 / 60keV.

6. The method for manufacturing a MOS device according to claim 4, wherein: In step S3, the deep trench etching method is wet etching, the trench depth of the etching area is 65 μm, the trench width is 5 μm, the etching angle is 88.8°, and the P-type epitaxial filling concentration is 4.2e15 cm -2 .

7. The method for manufacturing a MOS device according to claim 4, wherein: The thickness of the thin pre-oxidation layer in step S4 is 200 angstroms, and the injection condition of the P-body region is 6e13cm -2 / 60keV, annealing condition is 1100℃, annealing time is 180min.

8. The method for manufacturing a MOS device according to claim 4, wherein: In step S5, the ambient temperature of the surface thermal deposition is 980°C, the thickness of the field oxide layer is 8000 angstroms; the growth temperature of the gate oxide layer is 1050°C, the growth thickness is 1000 angstroms, and the growth time is 90 minutes; the self-doping concentration of the polysilicon deposition is 4.3e20cm -3 , with a thickness of 4000 angstroms; the polysilicon gate area in the middle of each cell in the gate area is etched 1.6μm for Dummy design; the oxide layer deposition thickness before general injection is 2000 angstroms to facilitate the isolation of the ESD polysilicon in the gate PAD area; the ESD polysilicon thickness of the gate PAD area is 6000 angstroms, and the general injection condition is 1e14cm -2 / 80keV.

9. The method for manufacturing a MOS device according to claim 4, wherein: The remaining thickness of the oxide layer after etching in step S6 is 200 angstroms; the injection activation condition of the source region and the ESD protection zone is 5e15cm of arsenic ions. -2 / 50keV, annealing temperature is 950℃, annealing time is 30min; ILD interlayer dielectric thickness is 11200 angstroms, dense reflow temperature is 900℃, dense reflow time is 30min; the opening size before metal deposition etching is 3μm, and the hole injection condition is 1.25e15cm of boron difluoride. -2 / 40keV, 3.5e15cm for boron -2 / 80keV, and perform rapid annealing for 15s; deposit 4μm aluminum-copper alloy front metal electrode and back metal electrode.

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