Semiconductor device, manufacturing method thereof and electronic equipment
By filling the second through holes in the second dielectric layer of the semiconductor device, the accuracy and damage problems during the etching process are solved, the process is simplified, the cost and parasitic capacitance are reduced, and the yield and performance are improved.
Patent Information
- Application Number
- CN202311770127.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-20
- Publication Date
- 2025-06-27
AI Technical Summary
During the production process of semiconductor devices, the etching of the second dielectric layer requires high accuracy to avoid adverse effects on the gate, and it is prone to over-etching, resulting in damage to the barrier layer, increasing production difficulty and reducing yield.
By filling the second through holes in the second dielectric layer, grooves are naturally formed without etching, the production process is simplified and the production difficulty and cost are reduced.
This method simplifies the production process of semiconductor devices, reduces production difficulty and cost, improves production yield, and reduces parasitic capacitance by naturally forming sinking parts, and improves device performance.
Smart Images
Figure CN120224760A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art
[0002] A transistor as a semiconductor device generally includes: a substrate, a channel layer, a barrier layer, a first dielectric layer, a second dielectric layer, and a third dielectric layer that are sequentially located on the substrate. Among them, a first through hole is provided in the first dielectric layer, and a gate disposed between the second dielectric layer and the barrier layer is connected to the barrier layer through the first through hole; a second through hole is provided in the second dielectric layer, and a field plate disposed between the second dielectric layer and the third dielectric layer fills the second through hole, so that a part of the field plate filled in the second through hole is called a sinking portion. The transistor further includes: a third through hole and a fourth through hole that respectively penetrate the third dielectric layer, the second dielectric layer, and the first dielectric layer. The source electrode is connected to the source region in the barrier layer through the third through hole, the drain electrode is connected to the drain region in the barrier layer through the fourth through hole, the sinking portion is disposed between the gate and the drain electrode, and the field plate is connected to the source electrode; the electric field distribution between the gate and the drain electrode can be adjusted through the sinking portion, thereby reducing the parasitic capacitance between the gate and the drain electrode and improving the performance of the transistor.
[0003] However, in order to form the second through hole in the second dielectric layer to form the sinking portion, it is necessary to etch the second dielectric layer. At this time, the etching needs to avoid the position of the first through hole to avoid adverse effects on the gate, which requires high etching accuracy during etching. And when the etching selectivity ratio of the manufacturing materials of the first dielectric layer and the second dielectric layer is similar, over-etching is likely to occur during the etching of the second dielectric layer, which may damage the barrier layer and thus damage the performance of the transistor, increasing the manufacturing difficulty of the transistor and reducing the manufacturing yield. Summary of the Invention
[0004] This application provides a semiconductor device, a manufacturing method thereof, and an electronic device, which are used to reduce the manufacturing difficulty and cost of the semiconductor device and improve the manufacturing yield of the semiconductor device.
[0005] In a first aspect, an embodiment of this application provides a semiconductor device, which may include: a channel layer, a barrier layer, a first dielectric layer, and a second dielectric layer that are sequentially stacked. A first through hole and a second through hole that penetrate are provided in the first dielectric layer; the semiconductor device further includes a gate and a field plate. The gate is disposed between the barrier layer and the second dielectric layer, the gate is connected to the barrier layer through the first through hole, the second dielectric layer fills the second through hole, so that a groove is formed at a position corresponding to the second through hole on the surface of the second dielectric layer, and the field plate is disposed on a surface of the second dielectric layer facing away from the first dielectric layer, and the field plate fills the groove.
[0006] Thus, when the second dielectric layer fills the second through-hole, a groove will be correspondingly formed on the surface of the second dielectric layer facing away from the substrate. Therefore, the groove is arranged corresponding to the second through-hole, and the shape of the groove is similar to that of the second through-hole. Furthermore, when forming the groove, there is no need to etch the second dielectric layer, and the groove can be naturally formed by filling the second through-hole. In this way, the manufacturing process of the semiconductor device can be simplified, the manufacturing difficulty can be reduced, and thus the manufacturing cost can be reduced, which is beneficial to improving the manufacturing yield of the semiconductor device.
[0007] Moreover, when the field plate fills the groove, the part of the field plate filled in the groove can be called the sinking part, and the part of the field plate arranged outside the groove can be called the body, so that the body and the sinking part constitute the field plate. At this time, by filling the groove, the sinking part can be naturally formed in the field plate, which is beneficial to reducing the parasitic capacitance of the semiconductor device through the sinking part, and further beneficial to improving the performance of the semiconductor device.
[0008] Optionally, since the shape of the groove is similar to that of the second through-hole, and the field plate filled in the groove forms the sinking part, the shape of the sinking part is the same as that of the groove. Furthermore, the shape of the sinking part is similar to that of the second through-hole. The shape of the second through-hole can be set according to actual needs, such as but not limited to: circular or quadrilateral and other shapes, which are not specifically limited here.
[0009] Optionally, the field plate extends along the first direction, and there are multiple sinking parts arranged at intervals, and each sinking part is arranged along the first direction. In this way, when the semiconductor device includes a drain electrode, and the sinking part is arranged in the space between the gate electrode and the drain electrode, there are multiple sinking parts arranged between the gate electrode and the drain electrode. Through these sinking parts, the electric field distribution between the gate electrode and the drain electrode can be adjusted, so that the parasitic capacitance between the gate electrode and the drain electrode can be reduced. Moreover, there can be multiple grooves arranged at intervals, and the number of grooves arranged can be the same as the number of sinking parts arranged. At this time, the sinking part and the groove can be arranged in one-to-one correspondence, so that each sinking part can be naturally formed when filling the groove, which can reduce the manufacturing difficulty of the sinking part and simplify the manufacturing process.
[0010] Alternatively, the field plate extends along a first direction, there is one groove and it extends along the first direction, and the sunken portion completely fills the groove, so that the number of grooves can be reduced, and further the number of second through-holes can be reduced; since when forming the first through-hole and the second through-hole, the first dielectric layer needs to be patterned first and then etched, the simplified structure of the second through-hole can simplify the difficulty of the patterning process, thereby reducing the manufacturing difficulty of the semiconductor device. Moreover, the sunken portion extends to opposite ends of the body (or the field plate) arranged along the first direction, that is, the length of the body in the first direction is equal to the length of the sunken portion in the first direction, so that the sunken portion can be arranged between the gate and the drain by making full use of the field plate, further reducing the parasitic capacitance between the gate and the drain, and thus further improving the performance of the semiconductor device.
[0011] Optionally, the semiconductor device may further include a source electrode and a drain electrode. The semiconductor device may further include: a third through-hole and a fourth through-hole respectively penetrating through the second dielectric layer, the first dielectric layer and the barrier layer. The source electrode is connected to the source region in the channel layer through the third through-hole, and the drain electrode is connected to the drain region in the channel layer through the fourth through-hole; the source electrode, the drain electrode and the field plate are arranged on the same layer, and the source electrode, the drain electrode and the field plate can be made of the same material. In this way, the source electrode, the drain electrode and the field plate can be formed simultaneously by using one manufacturing process, and further the source electrode, the drain electrode and the field plate are located on the same dielectric layer (i.e., the second dielectric layer). Compared with the prior art in which the source electrode, the drain electrode and the field plate are formed by different manufacturing processes and are located on different dielectric layers, the manufacturing difficulty of the semiconductor device can be further simplified, the manufacturing process can be further simplified, and thus the manufacturing cost of the semiconductor device can be further reduced.
[0012] Wherein, the field plate and the source electrode are electrically connected through a connecting portion, so that the sunken portion in the field plate has the same potential as the source electrode. When the sunken portion is arranged between the gate and the drain, the existence of the sunken portion can adjust the electric field distribution between the gate and the drain, thereby reducing the parasitic capacitance between the gate and the drain and improving the stability of the semiconductor device.
[0013] Optionally, the distance between the bottom of the groove and the barrier layer can be defined as the first distance, that is, the distance between the surface of the sinking part facing the substrate and the barrier layer can be defined as the first distance, and the distance between the surface of the gate facing away from the barrier layer and the barrier layer can be defined as the second distance. The first distance can be set to be not greater than the second distance. When the surface of the gate facing away from the barrier layer is called the upper surface, compared with the upper surface, the bottom of the groove is closer to the barrier layer. Therefore, the sinking part can be located between the regions directly opposite to each other in the second direction between the gate and the drain, so as to effectively adjust the electric field distribution between the gate and the drain, and further reduce the parasitic capacitance between the gate and the drain. Among them, the first distance can be designed according to actual needs and is not specifically limited here. The second direction can be understood as: the direction perpendicular to the first direction and parallel to the substrate surface.
[0014] Moreover, since the groove is naturally formed by filling the second through-hole, the second dielectric layer does not need to be etched. Therefore, the thickness difference of the second dielectric layer at different positions is not greater than 500 nm, that is, the thicknesses of the second dielectric layer at different positions are relatively close. And generally, the second dielectric layer is set to be thicker and the first dielectric layer is set to be thinner. Therefore, the thickness of the second dielectric layer at any position is greater than the thickness of the first dielectric layer. In this way, the withstand voltage ability of the end of the field plate close to the drain can be improved, and the breakdown of the second dielectric layer when it is thinner, resulting in a short circuit between the end of the field plate close to the drain and the drain, can be avoided, thereby improving the reliability and safety of the semiconductor device. Among them, the thickness of the second dielectric layer can be set to 300 nm, and the thickness of the first dielectric layer can be set to 50 nm.
[0015] Optionally, the manufacturing materials of each structure in the semiconductor device can be set in the following ways but are not limited to them:
[0016] The manufacturing materials of the channel layer can include but are not limited to: GaN, etc.;
[0017] The manufacturing materials of the barrier layer can include but are not limited to semiconductor materials such as AlGaN, AlN, InGaN, ScAlN, etc.;
[0018] The manufacturing materials of the first dielectric layer can include but are not limited to dielectric materials such as AlN, SiN, Al2O3, SiO2, etc.;
[0019] The manufacturing materials of the second dielectric layer can include but are not limited to dielectric materials such as AlN, SiN, Al2O3, SiO2, etc., and the manufacturing materials of the first dielectric layer and the second dielectric layer can be the same or different;
[0020] The manufacturing materials of the gate can include but are not limited to at least one of conductive materials such as Ni, TiN, W, Pt, etc.;
[0021] The manufacturing materials of the source, drain, and field plate can include, but are not limited to, at least one of conductive materials such as Ti, Au, Al, TiN, etc.
[0022] Among them, the gate, source, drain, and field plate can be of a multi-layer composite structure; taking the source as an example, the source can be set to the following structures: a composite structure formed by stacking a Ti layer and an Au layer, or a composite structure formed by stacking a Ti layer, an Al layer, and a Ti layer in sequence, or a composite structure formed by stacking a TiN layer, an Al layer, and a TiN layer in sequence, or other composite structures such as a composite structure formed by stacking a TiN layer, a Ti layer, an Al layer, a Ti layer, and a TiN layer in sequence, etc., which will not be listed one by one here.
[0023] In a second aspect, the embodiments of the present application further provide a manufacturing method of a semiconductor device. This manufacturing method is used to manufacture the semiconductor device described in the first aspect and any one of the embodiments in the first aspect. This manufacturing method may include: forming a channel layer on a substrate; forming a barrier layer on the channel layer; forming a first dielectric layer on the barrier layer; forming a first through hole and a second through hole penetrating the first dielectric layer; forming a gate on the first dielectric layer, and the gate is connected to the barrier layer through the first through hole; forming a second dielectric layer on the first dielectric layer with the gate formed thereon, and the second dielectric layer fills the second through hole, so that a groove is formed at the position corresponding to the second through hole on the surface of the second dielectric layer; forming a field plate on the second dielectric layer, and the field plate fills the groove. In this way, when the second dielectric layer fills the second through hole, a groove will be correspondingly formed on the surface of the second dielectric layer facing away from the substrate. Therefore, the groove is correspondingly arranged with the second through hole, and the shape of the groove is similar to the shape of the second through hole. Furthermore, when forming the groove, it is not necessary to etch the second dielectric layer, and the groove can be naturally formed by filling the second through hole. In this way, the manufacturing process of the semiconductor device can be simplified, the manufacturing difficulty can be reduced, and thus the manufacturing cost can be reduced, which is beneficial to improving the manufacturing yield of the semiconductor device.
[0024] Optionally, this manufacturing method may further include: after forming the second dielectric layer and before forming the field plate, etching the second dielectric layer, the first dielectric layer, and the barrier layer respectively to form a third through hole and a fourth through hole, and the third through hole exposes the source region in the channel layer, and the fourth through hole exposes the drain region in the channel layer. Based on this, forming the field plate may specifically include: simultaneously forming the source, drain, and field plate on the second dielectric layer, the source is connected to the source region through the third through hole, and the drain is connected to the drain region through the fourth through hole. In this way, the source, drain, and field plate can be formed by using one manufacturing process, and further, the source, drain, and field plate are located on the same dielectric layer (i.e., the second dielectric layer). Compared with the prior art in which the source, drain, and field plate are formed by different manufacturing processes and the source, drain, and field plate are located on different dielectric layers, the manufacturing difficulty of the semiconductor device can be further simplified, the manufacturing process can be further simplified, and thus the manufacturing cost of the semiconductor device can be further reduced.
[0025] It should be understood that since the principle of the semiconductor device fabricated by this fabrication method for solving problems is similar to that of the aforementioned semiconductor device for solving problems, the implementation and technical effects of this fabrication method can be referred to those of the aforementioned semiconductor device, and the repeated parts will not be elaborated again.
[0026] In a third aspect, an embodiment of the present application further provides an electronic device, which may include: a housing, and a semiconductor device as introduced in the first aspect and any one of the embodiments of the first aspect, and the semiconductor device is disposed inside the housing. Thus, on the basis that the fabrication process of the semiconductor device is simplified, and the fabrication difficulty and cost are reduced, the fabrication process of the electronic device can also be simplified, and the fabrication difficulty and cost can also be reduced.
[0027] It should be understood that since the principle of the electronic device for solving problems is similar to that of the aforementioned semiconductor device for solving problems, the implementation and technical effects of this electronic device can be referred to those of the aforementioned semiconductor device, and the repeated parts will not be elaborated again. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 is a schematic structural diagram of the electronic device provided by an embodiment of the present application;
[0029] Figure 2 is a schematic structural diagram of a semiconductor device in the prior art;
[0030] Figure 3 is a schematic structural diagram of the semiconductor device provided by an embodiment of the present application;
[0031] Figure 4 is along Figure 3 a cross-sectional view taken along the x1 - x2 direction in;
[0032] Figure 5 is along Figure 3 a cross-sectional view taken along the x3 - x4 direction in;
[0033] Figure 6 is along Figure 3 another cross-sectional view taken along the x3 - x4 direction in;
[0034] Figure 7 is a fabrication flow chart of the semiconductor device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0035] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.
[0036] It should be noted that the same reference numerals in the drawings of the present application denote the same or similar structures, and thus repeated descriptions thereof will be omitted. The words expressing positions and directions described in the present application are illustrative with reference to the drawings, but can be changed as needed, and all such changes are included within the scope of protection of the present application. The drawings of the present application are only used to schematically show the relative positional relationship and do not represent the true scale.
[0037] To facilitate the understanding of the technical solutions provided by the embodiments of the present application, the application scenarios thereof will be described first below.
[0038] The semiconductor devices provided by the embodiments of the present application can be widely applied in various electronic devices. The electronic devices provided by the embodiments of the present application can include various terminal devices and electronic components. Among them, the terminal devices can include, but are not limited to: smart phones, smart TVs, smart TV set-top boxes, smart watches, personal computers (PCs), wearable devices, smart broadband and other devices. The electronic components can include, but are not limited to: telecommunications devices such as wireless networks, fixed networks, servers, and components such as chip modules and memories, which will not be listed one by one here.
[0039] Figure 1 An exemplary structural schematic diagram of the semiconductor device applied in the electronic device is shown. Refer to Figure 1 As shown, the electronic device includes a housing 100 and a circuit board 200 disposed within the housing 100, and the semiconductor device 300 is disposed on the circuit board 200. The semiconductor device 300 is the core of the electronic device. With the continuous development of technology, higher requirements are put forward for the energy consumption, power, efficiency, and miniaturization of the semiconductor device 300. Among them, materials such as GaN, GaAs, SiC, Ga2O3, AlN, and diamond have a wide bandgap and have significant advantages in applications such as high power and high frequency. When using these materials to fabricate the semiconductor device 300, the semiconductor device 300 can meet the performance requirements. However, taking the semiconductor device 300 as a transistor as an example, there is a parasitic capacitance between the gate and the drain in the transistor, and the existence of the parasitic capacitance may limit the performance of the transistor such as output power, gain, and efficiency, making it impossible to effectively improve the performance of the transistor.
[0040] To solve this problem, a sinking portion can be provided in the field plate, and the sinking portion is disposed between the gate and the drain, thereby reducing the parasitic capacitance between the gate and the drain and improving the performance of the transistor. Exemplarily, refer to Figure 2As shown, the transistor includes: a substrate, a GaN layer, an AlGaN layer, a first dielectric layer 41, a second dielectric layer 42, and a third dielectric layer 43 that are sequentially located on the substrate. The transistor further includes: a gate 51, a source 52, a drain 53, and a field plate 54. A first through hole T1 is provided in the first dielectric layer 41. The gate 51 disposed between the second dielectric layer 42 and the AlGaN layer is connected to the AlGaN layer through the first through hole T1. A second through hole T2 is provided in the second dielectric layer 42. The field plate 54 disposed between the second dielectric layer 42 and the third dielectric layer 43 fills the second through hole T2, so that a part of the field plate 54 filled in the second through hole T2 is called a sinking portion 54a. The transistor further includes: a third through hole ( Figure 2 not shown in the figure) and a fourth through hole ( Figure 2 not shown in the figure) that respectively penetrate the third dielectric layer 43, the second dielectric layer 42, and the first dielectric layer 41. The source 52 is connected to the source region 61 in the AlGaN layer through the third through hole, and the drain 53 is connected to the drain region 62 in the AlGaN layer through the fourth through hole. The sinking portion 54a is disposed between the gate 51 and the drain 53, and the field plate 54 is connected to the source 52, Figure 2 not shown in the figure; the electric field distribution between the gate 51 and the drain 53 can be adjusted through the sinking portion 54a, so that the parasitic capacitance between the gate 51 and the drain 53 can be reduced. However, in order to form the second through hole T2 in the second dielectric layer 42 to form the sinking portion 54a, the second dielectric layer 42 needs to be etched. At this time, the etching needs to avoid the position of the first through hole T1 in order to avoid adverse effects on the gate 51, which requires high etching accuracy during etching. And when the etching selectivity of the manufacturing materials of the first dielectric layer 41 and the second dielectric layer 42 is similar, over-etching is likely to occur during the etching of the second dielectric layer 42, and it is very likely to damage the AlGaN layer, thereby damaging the performance of the transistor, increasing the manufacturing difficulty of the transistor, and reducing the manufacturing yield.
[0041] The embodiment of the present application provides a semiconductor device for reducing the manufacturing difficulty and cost of the semiconductor device and improving the manufacturing yield of the semiconductor device. The following will be described in conjunction with specific embodiments.
[0042] Figures 3 to 5 An exemplary structural schematic diagram of a semiconductor device provided by the present application is shown. Refer to Figures 3 to 5 as shown, Figure 4 is a cross-sectional view taken along the Figure 3 x1-x2 direction in the figure, Figure 5 is a cross-sectional view taken along the Figure 3A cross-sectional view taken in the x3-x4 direction as shown, the semiconductor device includes: a substrate 10, and a channel layer 20, a barrier layer 30, a first dielectric layer 41, and a second dielectric layer 42 stacked in sequence on the substrate 10. A first through hole T1 and a second through hole T2 penetrating through the first dielectric layer 41 along its thickness direction are provided in the first dielectric layer 41; the semiconductor device may further include a gate 51 and a field plate 54. The gate 51 is disposed between the barrier layer 30 and the second dielectric layer 42, and the gate 51 is connected to the barrier layer 30 through the first through hole T1; the second dielectric layer 42 fills the second through hole T2, so that a groove T0 is formed at a position corresponding to the second through hole T2 on the surface of the second dielectric layer 42. In other words, when the second dielectric layer 42 fills the second through hole T2, a groove T0 will be correspondingly formed on the surface of the second dielectric layer 42 facing away from the substrate 10. Therefore, the groove T0 is correspondingly arranged with the second through hole T2, and the shape of the groove T0 is similar to the shape of the second through hole T2. Furthermore, when forming the groove T0, there is no need to etch the second dielectric layer 42, and the groove T0 can be naturally formed by filling the second through hole T2. In this way, the manufacturing process of the semiconductor device can be simplified, the manufacturing difficulty can be reduced, and thus the manufacturing cost can be reduced, which is beneficial to improving the manufacturing yield of the semiconductor device. The field plate 54 is disposed on the surface of the second dielectric layer 42 facing away from the first dielectric layer 41, and the field plate 54 fills the groove T0. At this time, the part of the field plate 54 filled in the groove T0 can be called a sinking part 54a. At this time, by filling the groove T0, a sinking part 54a can be naturally formed in the field plate 54, so that the parasitic capacitance of the semiconductor device can be reduced through the sinking part 54a, and further the performance of the semiconductor device can be improved.
[0043] Wherein, since the shape of the groove T0 is similar to the shape of the second through hole T2, and the field plate 54 filled in the groove T0 forms a sinking part 54a, the shape of the sinking part 54a is the same as the shape of the groove T0. Furthermore, the shape of the sinking part 54a is similar to the shape of the second through hole T2. The shape of the second through hole T2 can be set according to actual needs, such as but not limited to: circular or quadrilateral and other shapes, which are not specifically limited herein.
[0044] And, referring to Figure 4 as shown, the semiconductor device may further include a source electrode 52 and a drain electrode 53. The semiconductor device may further include: a third through hole ([ Figure 4 not shown in the figure) and a fourth through hole ([ Figure 4(not shown in the figure), the source electrode 52 is connected to the source region 61 in the channel layer 20 through a third through-hole, and the drain electrode 53 is connected to the drain region 62 in the channel layer 20 through a fourth through-hole; the source electrode 52, the drain electrode 53, and the field plate 54 are arranged on the same layer, and the source electrode 52, the drain electrode 53, and the field plate 54 can be made of the same material. In this way, the source electrode 52, the drain electrode 53, and the field plate 54 can be formed simultaneously by one manufacturing process, and then the source electrode 52, the drain electrode 53, and the field plate 54 are located on the same dielectric layer (i.e., the second dielectric layer 42). Compared with the prior art in which the source electrode 52, the drain electrode 53, and the field plate 54 are formed by different manufacturing processes and are located on different dielectric layers, the manufacturing difficulty of the semiconductor device can be further simplified, the manufacturing process can be further simplified, and thus the manufacturing cost of the semiconductor device can be further reduced.
[0045] In addition, referring to Figure 3 shown in the figure, the field plate 54 and the source electrode 52 are electrically connected through a connecting portion 55, so that the sinking portion 54a in the field plate 54 has the same potential as the source electrode 52. When the sinking portion 54a is arranged between the gate electrode 51 and the drain electrode 53, the presence of the sinking portion 54a can adjust the electric field distribution between the gate electrode 51 and the drain electrode 53, thereby reducing the parasitic capacitance between the gate electrode 51 and the drain electrode 53 and improving the stability of the semiconductor device.
[0046] Furthermore, the distance between the bottom of the groove T0 and the barrier layer 30 can be defined as a first distance d1, that is, the distance between the surface of the sinking portion 54a facing the substrate 10 and the barrier layer 30 can be defined as the first distance d1, and the distance between the surface of the gate electrode 51 facing away from the barrier layer 30 and the barrier layer 30 can be defined as a second distance d2. The first distance d1 can be set to be not greater than the second distance d2; if the surface of the gate electrode 51 facing away from the barrier layer 30 is called the upper surface, the bottom of the groove is closer to the barrier layer 30 than the upper surface. Therefore, the sinking portion 54a can be located between the regions directly opposite to each other in the x direction of the gate electrode 51 and the drain electrode 53, thereby effectively adjusting the electric field distribution between the gate electrode 51 and the drain electrode 53 and further reducing the parasitic capacitance between the gate electrode 51 and the drain electrode 53. Among them, the first distance d1 can be designed according to actual needs and is not specifically limited here.
[0047] Referring to Figure 3 and Figure 5As shown, the field plate 54, source electrode 52, drain electrode 53, and gate electrode 51 all extend along the first direction (i.e., the y direction). The field plate 54 includes a connected body 54b and a sunken portion 54a. The sunken portion 54a is located within the groove T0, and the body 54b is located in the area outside the groove T0. The sunken portion 54a and the body 54b can be integrally formed. There are multiple sunken portions 54a and they are arranged at intervals. Each sunken portion 54a is arranged along the first direction. In this way, multiple sunken portions 54a are provided between the gate electrode 51 and the drain electrode 53. Through these sunken portions 54a, the electric field distribution between the gate electrode 51 and the drain electrode 53 can be reduced, thereby reducing the parasitic capacitance between the gate electrode 51 and the drain electrode 53. Moreover, multiple grooves T0 can be provided and arranged at intervals. The number of grooves T0 provided can be the same as the number of sunken portions 54a provided. At this time, the sunken portions 54a and the grooves T0 can be arranged in one-to-one correspondence, so that each sunken portion 54a can be naturally formed when filling the groove T0, thereby reducing the manufacturing difficulty of the sunken portion 54a and simplifying the manufacturing process.
[0048] Continue to refer to Figure 4 As shown, since the groove T0 is naturally formed by filling the second through hole T2, the second dielectric layer 42 does not need to be etched. Therefore, the thickness difference of the second dielectric layer 42 at different positions is not greater than 500 nm, that is, the thicknesses of the second dielectric layer 42 at different positions are relatively close. And the second dielectric layer 42 is generally set to be thicker, and the first dielectric layer 41 is generally set to be thinner. Therefore, the thickness of the second dielectric layer 42 at any position is greater than the thickness of the first dielectric layer 41. In this way, the breakdown voltage withstand ability of the end of the field plate 54 close to the drain electrode 53 (as shown within the virtual coil p1 in Figure 4 ) can be improved, avoiding short-circuiting between the end of the field plate 54 close to the drain electrode 53 and the drain electrode 53 due to breakdown when the second dielectric layer 42 is thinner, thereby improving the reliability and safety of the semiconductor device. Among them, the thickness d3 of the second dielectric layer 42 can be set to 300 nm, and the thickness d4 of the first dielectric layer 41 can be set to 50 nm.
[0049] It should be understood that, combined with Figure 4 As shown, in the x direction, the distance between the right end of the field plate 54 and the drain electrode 53 is generally in the micron level, while the thicknesses of the second dielectric layer 42 and the first dielectric layer 41 are generally in the nanometer level. Therefore, the position circled by the virtual coil p1 in the field plate 54 is closer to the drain electrode 53; if the second dielectric layer 42 is set to be thinner, it will result in a lower breakdown voltage withstand ability of the second dielectric layer 42, and further lead to short-circuiting between the position circled by the virtual coil p1 in the field plate 54 and the drain electrode 53. Therefore, setting the second dielectric layer 42 thicker can increase the breakdown voltage withstand ability of the second dielectric layer 42, thereby improving the reliability and safety of the semiconductor device.
[0050] Exemplarily, the manufacturing materials for each structure in the semiconductor device may but are not limited to be set in the following manner:
[0051] The manufacturing materials for the channel layer 20 may but are not limited to include: GaN, etc.;
[0052] The manufacturing materials for the barrier layer 30 may but are not limited to include semiconductor materials such as AlGaN, AlN, InGaN, ScAlN, etc.;
[0053] The manufacturing materials for the first dielectric layer 41 may but are not limited to include dielectric materials such as AlN, SiN, Al2O3, SiO2, etc.;
[0054] The manufacturing materials for the second dielectric layer 42 may but are not limited to include dielectric materials such as AlN, SiN, Al2O3, SiO2, etc., and the manufacturing materials for the first dielectric layer 41 and the second dielectric layer 42 may be the same or different;
[0055] The manufacturing materials for the gate 51 may but are not limited to include at least one of conductive materials such as Ni, TiN, W, Pt, etc.;
[0056] The manufacturing materials for the source 52, drain 53, and field plate 54 may but are not limited to include at least one of conductive materials such as Ti, Au, Al, TiN, etc.
[0057] Among them, the gate 51, source 52, drain 53, and field plate 54 may be multi-layer composite structures; taking the source 52 as an example, the source 52 may be set to the following structures: a composite structure formed by stacking a Ti layer and an Au layer, or a composite structure formed by stacking a Ti layer, an Al layer, and a Ti layer in sequence, or a composite structure formed by stacking a TiN layer, an Al layer, and a TiN layer in sequence, or other composite structures such as a composite structure formed by stacking a TiN layer, a Ti layer, an Al layer, a Ti layer, and a TiN layer in sequence, which are not listed one by one here.
[0058] Figure 6 Exemplarily shows a schematic structural diagram of a semiconductor device provided by the present application. Referring to Figure 6 As shown, the structure of the semiconductor device in this embodiment is the same as that in the previous embodiment Figures 3 to 5The structures of the semiconductor devices shown are basically similar, except that: there is one sinking portion 54a and one groove T0. Exemplarily, when the field plate 54 extends along the first direction (i.e., the y direction), there is one groove T0 and it extends along the y direction, and the sinking portion 54a completely fills the groove T0, so that the part of the field plate 54 filled in the groove T0 forms the sinking portion 54a, and the part of the field plate 54 outside the groove T0 forms the body 54b. In this way, the number of grooves T0 can be reduced, and then the number of second through-holes can be reduced; since when forming the first through-hole and the second through-hole, the first dielectric layer needs to be patterned first and then etched, the simplification of the structure of the second through-hole can simplify the difficulty of the patterning process, thereby reducing the manufacturing difficulty of the semiconductor device. Moreover, the sinking portion 54a extends to the opposite ends of the body 54a arranged along the y direction, that is, the length of the body 54b in the y direction is equal to the length of the sinking portion 54a in the y direction. In this way, the sinking portion 54a can be fully utilized between the gate 51 and the drain 53 of the field plate 54, further reducing the parasitic capacitance between the gate 51 and the drain 53, thereby further improving the performance of the semiconductor device.
[0059] It should be understood that the similarity between the structure of the semiconductor device in this embodiment and the Figures 3 to 5 structure of the semiconductor device shown in the foregoing embodiment can be referred to the relevant introduction of the semiconductor device shown in the foregoing embodiment, and the repeated parts will not be elaborated. Figures 3 to 5 shown in the foregoing embodiment, and the repeated parts will not be elaborated.
[0060] Figure 7 Exemplarily shown is a schematic diagram of a manufacturing method of a semiconductor device provided by the present application. Referring to Figure 7 shown, the manufacturing method of the semiconductor device may include:
[0061] Step S1, as Figure 7 shown in (a) of
[0062] shown, using but not limited to physical vapor deposition method, using but not limited to GaN, epitaxially grow a GaN layer on the substrate, and this GaN layer can be used as a channel layer; then, using but not limited to physical vapor deposition method, using but not limited to AlGaN, epitaxially grow an AlGaN layer on the GaN layer, and this AlGaN layer can be used as a barrier layer 30; Figure 7 shown in (a) of
[0063] Step S2, as Figure 7is not shown in (a); however, since the ion implantation positions in the AlGaN layer will be etched away subsequently to expose the source region 61 and the drain region 62, the ion implantation positions in the AlGaN layer have less impact on the source region 61 and the drain region 62 in the GaN layer.
[0064] Step S3, as Figure 7 shown in (a), use but not limited to physical vapor deposition method, use but not limited to SiO2, to form a SiO2 layer on the barrier layer 30, and this SiO2 layer serves as the first dielectric layer 41;
[0065] Step S4, as Figure 7 shown in (b), etch the SiO2 layer to etch out the first via hole T1 and the second via hole T2. Both the first via hole T1 and the second via hole T2 penetrate the SiO2 layer to expose the barrier layer 30;
[0066] Of course, when forming the first via hole T1 and the second via hole T2, they can be obtained simultaneously through a single etching process, or can be obtained separately through two etching processes.
[0067] Step S5, as Figure 7 shown in (c), use but not limited to physical vapor deposition method, use but not limited to Ni and Au, deposit a Ni layer and an Au layer in sequence on the SiO2 layer, so that the Ni layer and the Au layer form a first composite layer; and perform patterning and etching processes on the first composite layer in sequence, so that the remaining structure fills the first via hole T1 and contacts the barrier layer 30, while the second via hole T2 is exposed. At this time, the remaining structure can serve as the gate 51;
[0068] Step S6, as Figure 7 shown in (d), use but not limited to physical vapor deposition method, use but not limited to SiN, to form a SiN layer. This SiN layer covers the gate 51 and the first dielectric layer 41, and fills the second via hole T2. At this time, a groove T0 is formed at the position of the SiN layer surface corresponding to the second via hole T2 due to filling the second via hole T2, and this groove T0 is formed naturally without the need for etching; and this SiN layer serves as the second dielectric layer 42;
[0069] Step S7, as Figure 7 shown in (e), perform patterning and etching processes on the SiN layer, the SiO2 layer and the AlGaN layer to form a third via hole T3 and a fourth via hole T4 that sequentially penetrate the SiN layer, the SiO2 layer and the AlGaN layer, and both the gate 51 and the second via hole T2 are disposed between the third via hole T3 and the fourth via hole T4. The third via hole T3 exposes the source region 61 in the GaN layer, and the fourth via hole T4 exposes the drain region 62 in the GaN layer;
[0070] Step S8, asFigure 7 As shown in (f) therein, by using but not limited to physical vapor deposition method, and using but not limited to Ti and Au, a Ti layer and an Au layer are sequentially deposited on the SiN layer, so that the Ti layer and the Au layer form a second composite layer; and the second composite layer is sequentially subjected to patterning treatment and etching treatment, so that the filled groove T0 and the structure located on a part of the SiN layer are field plates 54, the structure filling the third through hole T3 is a source electrode 52, the source electrode 52 is in contact with the source region 61 through the third through hole T3, the structure filling the fourth through hole T4 is a drain electrode 53, the drain electrode 53 is in contact with the drain region 62 through the fourth through hole T4, and the source electrode 52 is connected to the field plate 54, thereby forming a semiconductor device.
[0071] Thus, first, since the groove T0 in the second dielectric layer 42 is formed naturally rather than by etching, one etching process can be reduced, so as to simplify the manufacturing steps of the semiconductor device, reduce the manufacturing cost, and avoid the problem of reduced manufacturing yield caused by etching deviation when forming the groove T0 by etching, and improve the manufacturing yield of the semiconductor device and the stability of the manufacturing process. Second, when etching the SiO2 layer to form the first through hole T1 and the second through hole T2, due to the large difference in etching selectivity between the AlGaN layer and the SiO2 layer, the AlGaN layer can be used as an etching stop layer, with strong controllability, avoiding over-etching during etching and damaging the GaN layer. In this way, the manufacturing yield of the semiconductor device can also be improved, and the stability of the manufacturing process can also be improved. Third, the source electrode 52, the drain electrode 53 and the field plate 54 are formed simultaneously. Compared with forming the source electrode 52, the drain electrode 53 and the field plate 54 separately, the manufacturing process of the semiconductor device can be simplified and the manufacturing cost can be reduced. Fourth, a part of the field plate 54 filled in the groove T0 is a sinking part, and the sinking part can reduce the parasitic capacitance between the gate 51 and the drain electrode 53, thereby improving the performance of the semiconductor device.
[0072] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these changes and modifications.
Claims
1. A semiconductor device, characterized in that, Comprising: A channel layer, a barrier layer, a first dielectric layer, and a second dielectric layer that are sequentially stacked, and a through first via hole and a second via hole are provided in the first dielectric layer; The semiconductor device further includes a gate and a field plate. The gate is disposed between the barrier layer and the second dielectric layer. The gate is connected to the barrier layer through the first via hole. The second dielectric layer fills the second via hole, so that a groove is formed at a position corresponding to the second via hole on the surface of the second dielectric layer. The field plate is disposed on a surface of the second dielectric layer facing away from the first dielectric layer, and the field plate fills the groove.
2. The semiconductor device according to claim 1, wherein, The field plate extends along a first direction; A portion of the field plate filled in the groove is a sinking portion; There are a plurality of the sinking portions and they are arranged at intervals, and each of the sinking portions is arranged along the first direction.
3. The semiconductor device according to claim 2, wherein, There are a plurality of the grooves, and the grooves are arranged at intervals.
4. The semiconductor device according to claim 1, wherein The field plate extends along a first direction; A portion of the field plate filled in the groove is a sinking portion; There is one groove and it extends along the first direction, and the sinking portion completely fills the groove.
5. The semiconductor device according to claim 4, wherein, The sinking portion extends to opposite ends of the field plate arranged along the first direction.
6. The semiconductor device according to any one of claims 1-5, characterized in that, The semiconductor device further includes a source electrode and a drain electrode; The semiconductor device further includes: a third via hole and a fourth via hole that respectively penetrate the second dielectric layer, the first dielectric layer, and the barrier layer. The source electrode is connected to a source region in the channel layer through the third via hole, and the drain electrode is connected to a drain region in the channel layer through the fourth via hole; The source electrode, the drain electrode, and the field plate are arranged in the same layer.
7. The semiconductor device according to any one of claims 1-6, characterized in that, The distance between the bottom of the groove and the barrier layer is a first distance, and the distance between a surface of the gate facing away from the barrier layer and the barrier layer is a second distance, and the first distance is not greater than the second distance.
8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The thickness difference of the second dielectric layer at different positions is not greater than 500 nm.
9. The semiconductor device according to any one of claims 1-8, characterized in that, The thickness of the second dielectric layer at any position is greater than the thickness of the first dielectric layer.
10. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a channel layer on a substrate; Forming a barrier layer on the channel layer; Forming a first dielectric layer on the barrier layer; Forming a through first via hole and a second via hole in the first dielectric layer; Forming a gate on the first dielectric layer, and the gate is connected to the barrier layer through the first via hole; Forming a second dielectric layer on the first dielectric layer on which the gate is formed, and the second dielectric layer fills the second via hole, so that a groove is formed at a position corresponding to the second via hole in the surface of the second dielectric layer; Forming a field plate on the second dielectric layer, and the field plate fills the groove.
11. The manufacturing method according to claim 10, wherein Further comprising: After forming the second dielectric layer and before forming the field plate, etching the second dielectric layer, the first dielectric layer, and the barrier layer respectively to form a third via hole and a fourth via hole, and the third via hole exposes the source region in the channel layer, and the fourth via hole exposes the drain region in the channel layer; Forming the field plate specifically includes: simultaneously forming a source electrode, a drain electrode, and the field plate on the second dielectric layer, where the source electrode is connected to the source region through the third through hole, and the drain electrode is connected to the drain region through the fourth through hole.
12. An electronic device, characterized in that, It includes: a housing and the semiconductor device according to any one of claims 1-9, where the semiconductor device is disposed within the housing.
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