Preparation method of integrated circuit chip

Abstract

The invention discloses a preparation method of an integrated circuit chip. The integrated circuit chip comprises a first device region and a second device region, the preparation method comprises the steps of forming a semiconductor substrate; forming a first dielectric layer on one side of the semiconductor substrate; the first dielectric layer comprises a first dielectric branch located in the first device region and a second dielectric branch located in the second device region; at least performing first patterning processing on the first dielectric layer to form a protection groove; the protection groove is located between the first device in the first device region and the second device in the second device region; and performing second patterning processing on the first dielectric layer to enable the thickness of the first dielectric subsection to be different from the thickness of the second dielectric subsection. According to the technical scheme provided by the embodiment of the invention, the process accuracy and the process stability can be improved while the same dielectric layer in different device regions has different thicknesses.

Description

Technical Field

[0001] The present invention relates to the technical field of chip manufacturing, and particularly to a method for preparing an integrated circuit chip. Background Art

[0002] In the process of preparing an integrated circuit chip, it is usually necessary to prepare a dielectric layer. Since multiple devices are integrated inside the integrated circuit chip and different devices may have different requirements for the thickness of the same dielectric layer, when preparing the dielectric layer in the integrated circuit chip, usually after preparing a whole layer of dielectric layer with equal thickness, local thinning or even local complete removal of the dielectric layer is performed through patterning processes (common processes are photolithography and etching processes) to meet the different thickness requirements of different devices for the same dielectric layer.

[0003] However, when any two adjacent devices have different thickness requirements for the same dielectric layer, using the existing patterning method, the photoresist can only cover and protect the upper surface of the part of the dielectric layer with a larger required thickness. As a result, when locally etching the dielectric layer, the etching substance (gas or liquid) will etch the part of the dielectric layer that originally does not need to be etched (i.e., the part with a larger required thickness mentioned above) in the horizontal direction, affecting the process accuracy and process stability of the patterning process, and even possibly affecting the performance of the device. Summary of the Invention

[0004] The present invention provides a method for preparing an integrated circuit chip to improve process accuracy and process stability while achieving different thicknesses of the same dielectric layer in different device regions.

[0005] In a first aspect, the present invention provides a method for preparing an integrated circuit chip. The integrated circuit chip includes a first device region and a second device region. The preparation method includes:

[0006] Forming a semiconductor substrate;

[0007] Forming a first dielectric layer on one side of the semiconductor substrate. The first dielectric layer includes a first dielectric sub - part located in the first device region and a second dielectric sub - part located in the second device region;

[0008] Performing at least a first patterning process on the first dielectric layer to form a protection groove. The protection groove is located between the first device in the first device region and the second device in the second device region;

[0009] Performing a second patterning process on the first dielectric layer to make the thickness of the first dielectric sub - part different from the thickness of the second dielectric sub - part.

[0010] Optionally, the depth of the protection groove is less than or equal to the thickness of the first dielectric layer.

[0011] Optionally, the thickness of the first dielectric sub - portion is greater than the thickness of the second dielectric sub - portion;

[0012] Performing a second patterning process on the first dielectric layer, including:

[0013] Forming a photoresist on the side of the first dielectric layer away from the semiconductor substrate; the photoresist covers the first dielectric sub - portion on the side of the protection groove close to the first device region and the side wall of the protection groove on the side close to the first device region;

[0014] Removing at least a portion of the thickness of the second dielectric sub - portion by an etching process.

[0015] In a second aspect, the present invention also provides a method for manufacturing an integrated circuit chip, the integrated circuit chip including a first active device region and a first passive device region; the manufacturing method includes:

[0016] Forming a semiconductor substrate;

[0017] Forming a first capacitor plate on one side of the semiconductor substrate; the first capacitor plate is located in the first passive device region;

[0018] Forming a first dielectric layer on the side of the first capacitor plate away from the semiconductor substrate; the first dielectric layer includes a first dielectric sub - portion located in the first active device region and a second dielectric sub - portion located in the first passive device region;

[0019] Removing at least a portion of the thickness of the first dielectric sub - portion along the direction from the first capacitor plate towards the semiconductor substrate and forming an etching interface, while retaining the second dielectric sub - portion;

[0020] Forming a gate electrode at the etching interface on the semiconductor substrate; the gate electrode is located in the first active device region; the gate electrode includes a first gate sub - portion and a second gate sub - portion, the first gate sub - portion is located on the side of the second gate sub - portion away from the semiconductor substrate, and the orthographic projection of the first gate sub - portion on the semiconductor substrate covers the orthographic projection of the second gate sub - portion on the semiconductor substrate; the first gate sub - portion includes a first surface connected to the second gate sub - portion, the first surface faces the etching interface and there is an air gap between them; along the direction perpendicular to the plane of the semiconductor substrate, the height of the air gap is less than or equal to the distance between the first surface and the etching interface.

[0021] Optionally, before removing at least a portion of the thickness of the first dielectric sub - portion, the manufacturing method further includes:

[0022] At least patterning the first dielectric layer to form a protection groove; the protection groove is located between the first active device in the first active device region and the first passive device in the first passive device region.

[0023] Optionally, before forming the first dielectric layer on one side of the semiconductor substrate, the manufacturing method further includes:

[0024] A second dielectric layer is formed on the semiconductor substrate; the second dielectric layer covers the semiconductor substrate;

[0025] Part of the first dielectric layer and the second dielectric layer are in direct contact, and the protection groove is located in the area where the first dielectric layer and the second dielectric layer are in direct contact;

[0026] In the same etching process, the etching rate of the second dielectric layer is less than that of the first dielectric layer.

[0027] Optionally, the protection groove penetrates at least the first dielectric layer.

[0028] Optionally, the distance between the protection groove and the first passive device is less than the distance between the protection groove and the first active device.

[0029] Optionally, removing at least part of the thickness of the first dielectric segment includes:

[0030] A photoresist is formed on the side of the first dielectric layer away from the semiconductor substrate; the photoresist covers the second dielectric segment on the side of the protection groove close to the first passive device region and the sidewall of the protection groove on the side close to the first passive device region;

[0031] An etching process is used to remove at least part of the thickness of the first dielectric segment.

[0032] Optionally, after forming the gate electrode at the etching interface on the semiconductor substrate, the preparation method further includes:

[0033] A source electrode and a drain electrode are formed on the semiconductor substrate; the source electrode and the drain electrode are located in the first active device region and are respectively located on opposite sides of the gate electrode;

[0034] A third dielectric layer is formed on the side of the second dielectric segment away from the first capacitor plate; the third dielectric layer covers the first active device region and the first passive device region;

[0035] A second capacitor plate is formed on the side of the third dielectric layer away from the first capacitor plate; the second capacitor plate is located in the first passive device region and is arranged to overlap the first capacitor plate in a direction perpendicular to the plane where the semiconductor substrate is located.

[0036] Before achieving the design goal of making the thickness of the first dielectric section different from that of the second dielectric section by performing a second patterning process on the first dielectric layer, a first patterning process is first performed on the first dielectric layer to form a protection groove, so that when performing the second patterning process, the upper surface of the part in the first dielectric layer that requires a greater thickness (such as the first dielectric section or the second dielectric section) and the side surface exposed by the protection groove can be covered by a photoresist, providing all-round protection for the part in the first dielectric layer that requires a greater thickness, further improving the protection effect of the photoresist, and improving the process accuracy and process stability.

[0037] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0039] Figure 1 is a schematic flowchart of a method for manufacturing an integrated circuit chip provided by an embodiment of the present invention;

[0040] Figures 2 - 5 is related to Figure 1 corresponding schematic diagram of the main manufacturing process of the integrated circuit chip;

[0041] Figure 6 is a schematic structural diagram of an existing integrated circuit chip;

[0042] Figure 7 is a schematic flowchart of another method for manufacturing an integrated circuit chip provided by an embodiment of the present invention;

[0043] Figures 8 - 13 is related to Figure 7 corresponding schematic diagram of the main manufacturing process of the integrated circuit chip;

[0044] Figure 14 is a schematic structural diagram of an integrated circuit chip provided by an embodiment of the present invention;

[0045] Figure 15 is a schematic flowchart of another method for manufacturing an integrated circuit chip provided by an embodiment of the present invention;

[0046] Figure 16 is using Figure 15Schematic diagram of the structure of an integrated circuit chip prepared by the preparation method shown;

[0047] Figure 17 It is a schematic flow chart of another preparation method of an integrated circuit chip provided by an embodiment of the present invention;

[0048] Figure 18 and Figure 19 are respectively Figure 17 Schematic diagrams of the structures of two integrated circuit chips prepared by the preparation method shown;

[0049] Figure 20 It is a schematic flow chart of another preparation method of an integrated circuit chip provided by an embodiment of the present invention;

[0050] Figure 21 and Figure 22 is Figure 20 The partial preparation flow chart of the corresponding integrated circuit chip;

[0051] Figure 23 It is a schematic flow chart of another preparation method of an integrated circuit chip provided by an embodiment of the present invention;

[0052] Figure 24 is Figure 23 Schematic diagram of the structure of an integrated circuit chip prepared by the preparation method shown. Detailed implementation manners

[0053] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0054] Without departing from the spirit or scope of the present application, various modifications and changes can be made in the present application, which will be obvious to those skilled in the art. Therefore, the present application is intended to cover the modifications and changes of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without conflict.

[0055] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily describe a specific order, quantity or importance. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process or method including a series of steps does not have to be limited to those clearly listed steps, but may include other steps not clearly listed or inherent to these processes or methods; again, a product including various elements, components or structures does not have to be limited to those clearly listed elements, components or structures, but may include other elements, components or structures not clearly listed or inherent to these products. Additionally, the shapes and sizes of the components in the drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present invention.

[0056] Figure 1 is a flowchart illustration of a method for manufacturing an integrated circuit chip provided by an embodiment of the present invention Figures 2 - 5 is related to Figure 1 corresponding main manufacturing process schematic diagram of the integrated circuit chip, as Figure 1 shown, the method for manufacturing an integrated circuit chip provided by an embodiment of the present invention includes the following steps:

[0057] S1001. Form a semiconductor substrate.

[0058] Among them, the semiconductor substrate can be a single-crystal semiconductor such as silicon or germanium, or it can also be a compound semiconductor such as silicon nitride, silicon carbide, gallium arsenide, or gallium nitride. It can also be an epitaxial semiconductor substrate formed by multiple semiconductor layers including gallium nitride, aluminum nitride, aluminum gallium nitride, etc.; the semiconductor substrate of the present invention can be a multi-semiconductor layer including a heterostructure and can be prepared through a series of epitaxial processes. Those skilled in the art can design a suitable semiconductor substrate and its manufacturing process according to the actual product, and the embodiments of the present invention do not limit this.

[0059] S1002. Form a first dielectric layer on one side of the semiconductor substrate; the first dielectric layer includes a first dielectric part located in the first device area and a second dielectric part located in the second device area.

[0060] As Figure 2 shown, the integrated circuit chip includes a first device area X and a second device area Y. A first dielectric layer 32 is formed on one side of the semiconductor substrate 1. The first dielectric layer 32 includes a first dielectric part 321 located in the first device area X and a second dielectric part 322 located in the second device area Y.

[0061] Specifically, multiple devices can be integrated inside an integrated circuit chip, and each device occupies a certain area. In this embodiment, the first device area X can be understood as the area where the first device is located, and the second device area Y can be understood as the area where the second device is located. Refer to Figure 2 , Figure 2 Use the identifier S1 to represent the area actually occupied by the first device, and use the identifier S2 to represent the area actually occupied by the second device. The range of the first device area X can be slightly larger than the area S1 actually occupied by the first device, and the range of the second device area Y can be slightly larger than the area S2 actually occupied by the second device.

[0062] Furthermore, the devices inside the integrated circuit chip can include at least one of active devices and passive devices. Taking the case where the integrated circuit chip integrates both active devices and passive devices as an example, the first device area X and the second device area Y can both be areas where passive devices are located (i.e., both the first device and the second device are passive devices), or both of them can be areas where active devices are located (i.e., both the first device and the second device are active devices), or one of them is an area where active devices are located and the other is an area where passive devices are located (i.e., the first device and the second device are an active device and a passive device respectively). The embodiments of the present invention do not limit this.

[0063] Furthermore, the first dielectric layer can be understood as any dielectric layer in the integrated circuit chip with the following characteristics: the first device and the second device have different requirements for the thickness of the first dielectric layer. For example, for the first device, it is required that the thickness of the corresponding first dielectric layer is relatively thick, and for the second device, it is required that the thickness of the corresponding first dielectric layer is relatively thin, or vice versa. Therefore, after the first dielectric layer is fabricated, it needs to be patterned so that the thickness of the first dielectric layer corresponding to the first device is different from the thickness of the second dielectric layer corresponding to the second device.

[0064] It should be noted that the embodiments of the present invention do not limit the specific materials of the semiconductor substrate and the first dielectric layer, and appropriate materials can be selected according to actual products.

[0065] S1003. At least perform a first patterning process on the first dielectric layer to form a protection groove; the protection groove is located between the first device in the first device area and the second device in the second device area.

[0066] As Figure 3 shown, a protection groove 5 is formed in the first dielectric layer 32, and the protection groove 5 is located between the first device (the area indicated by S1 in the figure) in the first device area X and the second device (the area indicated by S2 in the figure) in the second device area Y.

[0067] Among them, the first patterning process can be carried out by means of photolithography and etching processes. Specifically, by forming a photoresist with a certain pattern, using the photoresist to cover the first dielectric layer outside the area where the protection groove is to be set, and then etching the exposed first dielectric layer to form the protection groove 5.

[0068] Among them, at least performing the first patterning process on the first dielectric layer to form the protection groove may be only performing the first patterning process on the first dielectric layer, or may be performing the first patterning process on the first dielectric layer and other dielectric layers in contact therewith below it simultaneously. Specifically, it can be determined according to the actual situation of dielectric layers with different designed thicknesses as needed. The embodiments of the present invention do not limit this, and only an example is given here where the first dielectric layer is designed to have different thicknesses in the first device area and the second device area. At this time, only the first patterning process needs to be performed on the first dielectric layer to form the protection groove. When only performing the first patterning process on the first dielectric layer, the depth of the optional protection groove is less than or equal to the thickness of the first dielectric layer. Figure 3 Only taking the depth of the protection groove 5 being less than the thickness of the first dielectric layer 32 as an example for illustration. Exemplarily, in actual implementation, the depth of the protection groove 5 can be determined according to the thickness difference between the first dielectric part 321 and the second dielectric part 322 after the second patterning process of the first dielectric layer 32.

[0069] It should be noted that in this embodiment, as long as it is ensured that the protection groove 5 is located between the first device (the area indicated by S1 in the figure) and the second device (the area indicated by S2 in the figure). Exemplarily, Figure 3 Only taking a part of the orthographic projection of the protection groove 5 on the semiconductor substrate 1 being located in the first device area X and another part being located in the second device area Y as an example for illustration. In other embodiments, the orthographic projection of the protection groove 5 on the semiconductor substrate 1 may be entirely located in the first device area X, or may also be entirely located in the second device area Y. The embodiments of the present invention do not limit this. In addition, the position of the dividing line between the first device area X and the second device area Y shown in the drawings is only for illustration and is not a limitation.

[0070] S1004. Perform a second patterning process on the first dielectric layer to make the thickness of the first dielectric part different from the thickness of the second dielectric part.

[0071] Among them, the second patterning process can also be carried out by means of photolithography and etching processes. The difference between the second patterning process and the first patterning process lies in the different coverage ranges of the photoresist, or rather, the different positions in the first dielectric layer that need to be etched. In addition, the objectives of the first patterning process and the second patterning process and the results after processing (the morphology of the first dielectric layer) are different.

[0072] Specifically, the portion in the first dielectric layer that needs to be etched can be determined according to the thickness of the first dielectric portion and the thickness of the second dielectric portion. Exemplarily, in specific implementation, a first dielectric layer with a uniform thickness can be prepared first according to the thickness requirement of the device with a larger thickness of the first dielectric layer; then, a protective groove is formed in the first dielectric layer through a first patterning process; then, a second patterning process is performed. Specifically, the first dielectric layer in the device area with a larger thickness requirement is protected by a photoresist, and then the first dielectric layer in the exposed state in the other device area is etched (thinned or even completely removed), so that the thicknesses of the first dielectric layers in the two device areas are different, that is, the thicknesses of the first dielectric portion and the second dielectric portion are different, achieving the design goal.

[0073] Exemplarily, referring to Figure 4 and Figure 5 , taking the design goal that the thickness of the first dielectric portion 321 is greater than the thickness of the second dielectric portion 322 as an example, the process of performing the second patterning process on the first dielectric layer can include the following steps:

[0074] As Figure 4 shown, first, a photoresist 4 is formed on the side of the first dielectric layer 32 away from the semiconductor substrate 1; the photoresist 4 is made to cover the first dielectric portion 321 on the side of the protective groove 5 close to the first device area X and the sidewall of the protective groove 5 close to the first device area X; then, as Figure 5 shown, an etching process is used to remove at least part of the thickness of the second dielectric portion 322 and remove the photoresist 4, so that the design goal that the thickness of the first dielectric portion 321 is greater than the thickness of the second dielectric portion 322 can be achieved.

[0075] Furthermore, before forming the first dielectric layer 32, a second dielectric layer is first formed on the semiconductor substrate 1, so that the second dielectric layer covers the semiconductor substrate 1, and part of the first dielectric layer 32 and the second dielectric layer are in direct contact. Preferably, the protective groove 5 is located in the area where the first dielectric layer 32 and the second dielectric layer are in contact.

[0076] Optionally, in the same etching process, the etching rate of the second dielectric layer is less than the etching rate of the first dielectric layer 32. In this way, when using the etching process to remove part of the first dielectric layer 32, the influence on the film quality of the second dielectric layer under the first dielectric layer can be reduced, and the phenomenon of uneven thickness or a large amount of damage of the second dielectric layer can be avoided.

[0077] Exemplarily, the etching rate of the second dielectric layer can be made less than the etching rate of the first dielectric layer 32 by selecting different materials or by preparing the same material with different process parameters.

[0078] Different from the conventional solution of directly thinning or completely removing the dielectric layer in a local area through photolithography and etching processes to make the thicknesses of the dielectric layers in different areas different, before achieving the design goal of making the thickness of the first dielectric part different from that of the second dielectric part by performing a second patterning process on the first dielectric layer in this embodiment, a first patterning process is first performed on the first dielectric layer to form a protection groove. In this way, when performing the second patterning process, the upper surface of the part of the first dielectric layer that requires a greater thickness (such as the first dielectric part) and the side surface exposed by the protection groove can be covered with photoresist to provide all-round protection for the part of the first dielectric layer that requires a greater thickness (such as the first dielectric part), further improving the protection effect of the photoresist and improving the process accuracy and process stability.

[0079] Referring to Figure 5 , it should be noted that the thickness of the above-mentioned first dielectric part 321 can be understood as the thickness of the first dielectric layer corresponding to the position of the first device (the area indicated by S1 in the figure). The thickness of the first dielectric layer at the remaining positions in the first device area X except for the area S1 can be the same as or different from it (such as Figure 5 ); similarly, the thickness of the above-mentioned second dielectric part 322 can be understood as the thickness of the first dielectric layer corresponding to the position of the second device (the area indicated by S2 in the figure). The thickness of the first dielectric layer at the remaining positions in the second device area Y except for the area S2 can be the same as (such as Figure 5 ) or different from it. In short, in this embodiment, by performing a second patterning process on the first dielectric layer, it is at least necessary to make the thickness of the first dielectric layer corresponding to the first device different from the thickness of the first dielectric layer corresponding to the second device.

[0080] Next, based on the same design goal and design concept, taking an integrated circuit chip integrated with passive devices (such as capacitors) and active devices (such as transistors), such as a MMIC (Monolithic Microwave Integrated Circuit) chip as an example, and taking the first dielectric layer specifically referring to the film layer where the dielectric layer of the capacitor is located as an example, a method for manufacturing an integrated circuit chip is correspondingly provided.

[0081] With the further development of the microelectronics industry, the operating frequency of electronic products is getting higher and higher, and it is necessary to reduce the parasitic capacitance in the design process of transistors. To achieve this goal, many novel structures are adopted in transistor devices, such as the air-gate dielectric structure.

[0082] For an integrated circuit chip integrated with passive devices (such as capacitors) and active devices (such as transistors), such as an MMIC (Monolithic Microwave Integrated Circuit) chip, the dielectric layer (i.e., the first dielectric layer) of the capacitor is usually prepared as a whole layer within the entire chip area, and only the part corresponding to the capacitor plates in the first dielectric layer functions as the capacitor dielectric. However, when the transistor adopts an air-gate dielectric structure, the thickness requirements for the first dielectric layer in the passive device area and the active device area are different. Specifically, to enable the capacitor to have a larger breakdown voltage, the design of the integrated circuit chip usually requires a thicker first dielectric layer corresponding to the capacitor device, while to implement a transistor with an air-gate dielectric structure, a thinner first dielectric layer corresponding to the transistor is required. Moreover, the traditional manufacturing process will cause the air dielectric under the gate to be backfilled by the first dielectric layer, resulting in the failure of manufacturing a transistor with an air-gate dielectric structure and unable to achieve the goal of reducing parasitic capacitance.

[0083] Exemplarily, Figure 6 is a schematic structural diagram of an existing integrated circuit chip. Referring to Figure 6 , the integrated circuit chip includes a substrate 01, a transistor 02, and a capacitor 03 located on the substrate 01. The transistor 02 is located in the active device area, and the capacitor is located in the passive device area. The traditional manufacturing process usually first prepares the transistor 02 on the substrate 01. After the gate 021, source 022, and drain 023 of the transistor 02 are fabricated, the lower plate 031, dielectric layer 032, and upper plate 033 of the capacitor 03 are then fabricated. In this way, the dielectric layer 032 of the capacitor 03 can play a role in protecting the integrated circuit. Additionally, in view of this, using the traditional manufacturing process will cause the air dielectric under the gate to be backfilled by the dielectric layer of the capacitor (as shown by the area within the dashed box Q in Figure 6 . Before fabricating the capacitor 03, this area is air dielectric, and after fabricating the capacitor 03, this area is filled with the dielectric layer 032 of the capacitor 03), unable to form an air-gate dielectric structure and unable to achieve the goal of reducing parasitic capacitance. To solve this problem and meet the different thickness requirements of the capacitor and the transistor for the first dielectric layer, the embodiments of the present invention propose the following solutions.

[0084] Figure 7 is a schematic flowchart of another method for fabricating an integrated circuit chip provided by an embodiment of the present invention. The integrated circuit chip includes a first active device area (such as the area where the transistor is located) and a first passive device area (such as the area where the capacitor is located). Figures 8 - 13 is corresponding to Figure 7 The main manufacturing process schematic diagram of the integrated circuit chip, as shown in Figure 7 , the method for fabricating the integrated circuit chip includes the following steps:

[0085] S101. Form a semiconductor substrate.

[0086] The semiconductor substrate may be a single-crystal semiconductor such as silicon or germanium, or may be a compound semiconductor such as silicon nitride, silicon carbide, gallium arsenide, or gallium nitride, or may also be an epitaxial semiconductor substrate formed by multiple semiconductor layers including gallium nitride, aluminum nitride, aluminum gallium nitride, etc.; the semiconductor substrate of the present invention may be a multi-layer semiconductor layer including a heterostructure and can be prepared by a series of epitaxial processes. Those skilled in the art can design a suitable semiconductor substrate and its preparation process according to the actual product, and the embodiments of the present invention do not limit this.

[0087] S102. Form a first capacitor plate on one side of the semiconductor substrate; the first capacitor plate is located in the first passive device region.

[0088] As Figure 8 shown, a first capacitor plate 31 is formed on one side of the semiconductor substrate 1, and the first capacitor plate 31 is located in the first passive device region na. Among them, the first capacitor plate 31 can be understood as the lower plate of the capacitor. Exemplarily, the first capacitor plate 31 can be formed of a metal such as titanium, platinum, or gold, or can be formed by laminating metals such as titanium, platinum, and gold. Of course, the first capacitor plate can also be formed of other metals, and the embodiments of the present invention do not limit this.

[0089] S103. Form a first dielectric layer on the side of the first capacitor plate away from the semiconductor substrate; the first dielectric layer includes a first dielectric part located in the first active device region and a second dielectric part located in the first passive device region.

[0090] As Figure 9 shown, the first dielectric layer 32 is formed on the side of the first capacitor plate 31 away from the semiconductor substrate 1 and covers the semiconductor substrate 1, and specifically includes a first dielectric part 321 located in the first active device region aa and a second dielectric part 322 located in the first passive device region na.

[0091] Among them, the first dielectric layer is the dielectric layer between the upper and lower plates of the capacitor. Exemplarily, the forming materials of the first dielectric layer include, but are not limited to, dielectric materials such as silicon nitride, silicon oxide, and aluminum oxide.

[0092] S104. Remove at least part of the thickness of the first dielectric part along the direction from the first capacitor plate to the semiconductor substrate to form an etching interface, and retain the second dielectric part.

[0093] Among them, at least part of the etching interface is located in the first active device region aa. Refer to Figures 9 - 12, in the direction from the first capacitor plate 31 towards the semiconductor substrate 1, removing at least a part of the thickness of the first dielectric section 321 can be understood as removing a part of the thickness of the first dielectric section 321 from top to bottom to form an etching interface F2, that is, thinning the first dielectric section 321 to form the etching interface F2. At this time, the etching interface F2 is the interface of the first dielectric layer 32 after etching; or, all the thickness of the first dielectric section 321 can also be removed from top to bottom, that is, completely removing the first dielectric section 321 to form the etching interface F2. At this time, the etching interface F2 is the interface of the film layer below the first dielectric layer 32, which can be specifically understood as the interface of the uppermost surface of all the film layers located below the film layer where the first dielectric layer 32 is located in the first active device region aa.

[0094] Exemplarily, Figures 10 - 12 Taking the complete removal of the first dielectric section as an example, an implementation manner of removing the first dielectric section is shown. Combining Figure 9 and Figure 10 as shown, a photoresist 4 can be first formed on the side of the first dielectric layer 32 away from the semiconductor substrate, so that the photoresist 4 covers the first passive device region na, and the second dielectric section 322 in the first passive device region na is protected by the photoresist 4. Next, combining Figure 9 and Figure 11 as shown, the first dielectric section 321 can be removed by an etching process. Optionally, the etching process can be a dry etching process, a wet etching process, or a process combining dry etching and wet etching. Finally, combining Figure 11 and Figure 12 as shown, the photoresist 4 is removed to expose the second dielectric section 322. By adopting the above method, the first dielectric section 321 in the first active device region aa is removed, and the second dielectric section 322 in the first passive device region na is retained.

[0095] S105. Form a gate electrode at the etching interface on the semiconductor substrate; the gate electrode is located in the first active device region.

[0096] As Figure 13 shown, a gate electrode 21 is formed at the etching interface on the semiconductor substrate 1, and the gate electrode 21 is located in the first active device region aa. Optionally, a Schottky contact is formed between the gate electrode 21 and the semiconductor substrate 1. In addition, as Figure 13 shown, after forming the gate electrode, the source electrode 22 and the drain electrode 23 are prepared, and the second capacitor plate 33 is prepared, so that a transistor 2 can be formed in the first active device region aa and a capacitor 3 can be formed in the first passive device region na.

[0097] Continue to refer to Figure 13, in the embodiment of the present invention, the gate electrode 21 includes a first gate segment 211 and a second gate segment 212. The first gate segment 211 is located on the side of the second gate segment 212 away from the semiconductor substrate 1, and the orthographic projection of the first gate segment 211 on the semiconductor substrate 1 covers the orthographic projection of the second gate segment 212 on the semiconductor substrate 1; the first gate segment 211 includes a first surface F1 connected to the second gate segment 212. The first surface F1 faces the etching interface F2 and there is an air gap between the two; along the direction perpendicular to the plane where the semiconductor substrate 1 is located, the height h of the air gap is less than or equal to the distance d between the first surface F1 and the etching interface F2.

[0098] Among them, the region where the air gap is located is the region where the above-mentioned air gate dielectric is located. The higher the height h of the air gap, the more beneficial it is to reduce the parasitic capacitance of the transistor.

[0099] Combined with Figures 8 - 13 , based on the above preparation method, in this embodiment, before preparing the gate electrode 21 of the first active device region aa, the first capacitor plate 31 and the first dielectric layer 32 are prepared first, and then at least part of the thickness of the first dielectric layer (i.e., the first dielectric segment 321) of the first active device region aa is removed, so that the thickness of the first dielectric segment 321 is less than the thickness of the second dielectric segment 322, and then the gate electrode 21 is prepared. In this way, it can not only solve the problem that the traditional preparation process causes the failure of manufacturing a transistor with an air gate dielectric structure, form a transistor with an air gate dielectric structure in the first active device region, and achieve the design goal of reducing the parasitic capacitance, but also make the capacitor in the first passive device region have a thicker dielectric layer, ensure the reliability of the capacitor under high operating voltage, meet the design requirements of the device for high capacitance density and high breakdown voltage, and take into account the performance requirements of the devices in the first passive device region and the first active device region of the integrated circuit chip.

[0100] In addition, since the traditional preparation process protects the integrated circuit through the dielectric layer of the capacitor, such as Figure 6The gate 021, source 022, and drain 023 are protected by the dielectric layer 032 of the capacitor 03 as shown. Therefore, based on the design concept of the traditional manufacturing process, there is no need and no reason to remove the dielectric layer 032 of the capacitor located in the first active device region aa at all. Moreover, adopting the traditional manufacturing process, due to the relatively complex structure of the gate 021 of the transistor in the first active device region aa, even if it is necessary to remove the dielectric layer 032 under the gate, the process implementation difficulty is very high. Compared with the traditional manufacturing process, in this embodiment, a new manufacturing method is designed. Before manufacturing the gate electrode 21 of the first active device region aa, the first dielectric layer 32 is manufactured first, and then at least part of the thickness of the first dielectric layer 32 in the first active device region aa is removed, so that the thickness of the first dielectric layer 32 in the first active device region aa can be made thinner (even zero), while the thickness of the first dielectric layer 32 in the first passive device region na is thicker. This not only simplifies the process, but also is beneficial to forming a transistor with an air-gate dielectric structure in the first active device region aa, and at the same time makes the first dielectric layer corresponding to the capacitor thicker, taking into account the performance requirements of the devices in the first passive device region and the first active device region of the integrated circuit chip.

[0101] It should be noted that Figure 13 Only taking the example that the first dielectric layer (i.e., the first dielectric sub-portion) located in the first active device region aa is removed, at this time, the etching interface F2 is the interface where the uppermost surface of the film layer under the first dielectric layer 32 (such as the upper surface of the semiconductor substrate 1) is located, and the height h of the air gap is equal to the distance d between the first surface F1 and the etching interface F2. This implementation manner is not limited. Exemplarily, Figure 14 is a schematic structural diagram of an integrated circuit chip provided by an embodiment of the present invention. Comparing 4 and Figure 14 , in some embodiments, optionally, the first dielectric sub-portion 321 located in the first active device region aa is not completely removed, but only thinned. At this time, the interface of the etched first dielectric layer 32 forms the etching interface F2, and the height h of the air gap is equal to the distance d between the first surface F1 and the etching interface F2. Adopting this solution, while taking into account the performance requirements of the devices in the first passive device region na and the first active device region aa of the integrated circuit chip, the surface of the first active device region aa can also be protected by the thinned first dielectric layer in the first active device region aa, improving the defect problem of the first active device region aa, and further improving the performance of the transistor. In the subsequent embodiments, only the example that the first dielectric layer (i.e., the first dielectric sub-portion) located in the first active device region aa is removed will be used for description.

[0102] It should also be noted that the position of the boundary line between the first active device region aa and the first passive device region na shown in the accompanying drawings of the embodiments of the present invention is only for illustration and not an absolute position. Specifically, the boundary line can be in the active region or the passive region. The first passive device region na can be understood as the region where the passive device is located, and this region can include part of the active region; the first active device region aa can be understood as the region where the active device is located, and this region can include part of the passive region.

[0103] Figure 15 FIG. is a schematic flowchart of another method for manufacturing an integrated circuit chip provided by an embodiment of the present invention. On the basis of the above embodiments, the method for manufacturing an integrated circuit chip is further supplemented and optimized. The same parts as those in the above Embodiment 1 will not be described in detail herein. As Figure 15 shown, the method for manufacturing an integrated circuit chip may include the following steps:

[0104] S201. Form a semiconductor substrate.

[0105] S202. Form a second dielectric layer on the semiconductor substrate; the second dielectric layer covers the semiconductor substrate.

[0106] Figure 16 is a schematic structural diagram of an integrated circuit chip prepared by using the Figure 15 shown manufacturing method. Referring to Figure 16 shown, in this embodiment, before forming the first capacitor plate 31, a second dielectric layer 20 is first formed on the semiconductor substrate 1 so that the second dielectric layer 20 covers the semiconductor substrate 1. Such a setting can avoid direct contact between the first capacitor plate 31 and the semiconductor substrate 1, improve the leakage situation of the capacitor 3, and enhance the device performance.

[0107] Exemplarily, the forming material of the second dielectric layer includes, but is not limited to, dielectric materials such as silicon nitride, silicon oxide, and aluminum oxide.

[0108] S203. Form a first capacitor plate on the side of the second dielectric layer away from the semiconductor substrate; the first capacitor plate is located in the first passive device region.

[0109] S204. Form a first dielectric layer on the side of the first capacitor plate away from the semiconductor substrate; the first dielectric layer includes a first dielectric part located in the first active device region and a second dielectric part located in the first passive device region.

[0110] S205. Remove the first dielectric part along the direction from the first capacitor plate to the semiconductor substrate, and retain the second dielectric part.

[0111] Referring to Figure 16, in this embodiment, the first dielectric layer 32 (i.e., the first dielectric sub-portion) of the first active device region aa is removed, and the second dielectric layer 20 below it is not processed. At this time, the etching interface F2 refers to the interface where the uppermost surface of the second dielectric layer 20 is located, and the height h of the air gap is equal to the distance between the first surface F1 and the etching interface F2.

[0112] S206. Form a gate electrode at the etching interface on the semiconductor substrate; the gate electrode is located in the first active device region.

[0113] S207. Form a source electrode and a drain electrode on the semiconductor substrate; the source electrode and the drain electrode are located in the first active device region and are respectively located on opposite sides of the gate electrode.

[0114] As Figure 16 shown, an active electrode 22 and a drain electrode 23 are formed on the semiconductor substrate 1. The source electrode 22 and the drain electrode 23 are both located in the first active device region aa and are respectively located on opposite sides of the gate electrode 21. Optionally, the source electrode 22 and the drain electrode 23 form an ohmic contact with the semiconductor substrate 1.

[0115] S208. Form a second capacitor plate on the side of the second dielectric sub-portion away from the first capacitor plate; the second capacitor plate is located in the first passive device region and is arranged to overlap with the first capacitor plate in a direction perpendicular to the plane where the semiconductor substrate is located.

[0116] As Figure 16 shown, the first dielectric layer in the first active device region aa is removed, and only the second dielectric sub-portion 322 of the first passive device region na is retained. The second capacitor plate 33 is formed on the side of the second dielectric sub-portion 322 away from the first capacitor plate 31 and is arranged to overlap with the first capacitor plate 31 in a direction perpendicular to the plane where the semiconductor substrate 1 is located.

[0117] As Figure 16 shown, in the technical solution of this embodiment, before forming the first dielectric layer 32 (specifically, before forming the first capacitor plate 31), the second dielectric layer 20 is first formed on the semiconductor substrate 1 so that the second dielectric layer 20 covers the semiconductor substrate 1 and part of the first dielectric layer 32 and the second dielectric layer 20 are in direct contact. On the one hand, it can improve the leakage situation of the capacitor 3, and on the other hand, it can also protect the surface of the first active device region aa through the second dielectric layer 20, improve the defect problem of the first active device region aa, and thus improve the performance of the transistor 2.

[0118] Optionally, in the same etching process, the etching rate of the second dielectric layer 20 is less than the etching rate of the first dielectric layer 32. In this way, when the first dielectric layer of the first active device region aa is removed by the etching process, the influence on the film quality of the second dielectric layer 20 can be reduced, and the phenomenon of uneven thickness or a large amount of damage of the second dielectric layer 20 can be avoided.

[0119] Exemplarily, by selecting different materials or adopting different process parameters for the same material, the etching rate of the second dielectric layer 20 can be made less than that of the first dielectric layer 32.

[0120] Figure 17 FIG. is a schematic flow chart of another method for manufacturing an integrated circuit chip provided by an embodiment of the present invention. Figure 18 and Figure 19 are respectively schematic structural diagrams of two integrated circuit chips manufactured by using the manufacturing method shown in Figure 17 . Referring to Figure 16 , the second dielectric layer 20 includes a third dielectric sub-portion 201 located in the first active device region aa and a fourth dielectric sub-portion 202 located in the first passive device region na. Comparing Figure 18 ( Figure 19 ) and Figure 16 , the difference between this embodiment and the second embodiment is that in this embodiment, at least a portion of the thickness of the third dielectric sub-portion 201 is removed, so that the height h of the air gap can be increased, and the parasitic capacitance of the transistor can be further reduced.

[0121] As Figure 17 shown, in this embodiment, the method for manufacturing an integrated circuit chip may include the following steps (the same parts as the above embodiment will not be explained in detail):

[0122] S301. Form a semiconductor substrate.

[0123] S302. Form a second dielectric layer on the semiconductor substrate; the second dielectric layer covers the semiconductor substrate.

[0124] S303. Form a first capacitor plate on a side of the second dielectric layer away from the semiconductor substrate; the first capacitor plate is located in the first passive device region.

[0125] S304. Form a first dielectric layer on a side of the first capacitor plate away from the semiconductor substrate; the first dielectric layer includes a first dielectric sub-portion located in the first active device region and a second dielectric sub-portion located in the first passive device region.

[0126] S305. Remove the first dielectric sub-portion along the direction from the first capacitor plate to the semiconductor substrate, and retain the second dielectric sub-portion.

[0127] S306. Remove at least a portion of the thickness of the third dielectric sub-portion along the direction from the first capacitor plate to the semiconductor substrate.

[0128] Exemplarily, comparing Figure 16 , Figure 18Taking the thinning of the second dielectric layer 20 of the first active device region aa, that is, the removal of the third dielectric sub-portion 201 with a partial thickness as an example for illustration. At this time, the etching interface F2 refers to the interface where the uppermost surface of the etched second dielectric layer 20 is located, and the height h of the air gap is equal to the distance d between the first surface F1 and the etching interface F2. In this way, the height h of the air gap can be increased to a certain extent, the parasitic capacitance of the transistor can be reduced, and the surface of the first active device region aa can be protected by the remaining second dielectric layer in the first active device region aa to improve the performance of the transistor. The leakage of the capacitance can be improved by the second dielectric layer (i.e., the fourth dielectric sub-portion) of the first passive device region na.

[0129] Exemplarily, for comparison Figure 16 , Figure 19 Taking the complete removal of the second dielectric layer of the first active device region aa, that is, the removal of the third dielectric sub-portion 201 with the entire thickness as an example for illustration. At this time, the etching interface F2 refers to the interface where the uppermost surface of the film layer below the first dielectric layer 32 (such as the upper surface of the semiconductor substrate 1) is located, and the height h of the air gap is equal to the distance d between the first surface F1 and the etching interface F2. In this way, the height h of the air gap can be increased to a greater extent, and the effect of reducing the parasitic capacitance is better. Those skilled in the art can select a suitable preparation method according to the actual situation, and the embodiments of the present invention do not limit this.

[0130] Exemplarily, the third dielectric sub-portion can be processed by dry etching, wet etching, or a combination of dry etching and wet etching. It should be noted that in this embodiment, after removing the first dielectric layer (i.e., the first dielectric sub-portion) of the first active device region, at least a partial thickness of the third dielectric sub-portion is removed along the direction from the first capacitor plate to the semiconductor substrate. Therefore, when adopting the technical solution of this embodiment, the magnitude relationship between the etching rates of the second dielectric layer and the first dielectric layer can be not limited.

[0131] S307. Form a gate electrode at the etching interface on the semiconductor substrate; the gate electrode is located in the first active device region.

[0132] S308. Form a source electrode and a drain electrode on the semiconductor substrate; the source electrode and the drain electrode are located in the first active device region and are respectively located on opposite sides of the gate electrode.

[0133] S309. Form a second capacitor plate on the side of the second dielectric sub-portion away from the first capacitor plate; the second capacitor plate is located in the first passive device region and is overlapped with the first capacitor plate in a direction perpendicular to the plane where the semiconductor substrate is located.

[0134] Figure 20It is a schematic flow chart of another method for manufacturing an integrated circuit chip provided by an embodiment of the present invention. Based on any of the above embodiments, the method for removing at least a part of the thickness of the first dielectric section in the first active device region is further optimized, and the same parts will not be described in detail here. Figure 21 and Figure 22 is the partial manufacturing flow chart of the integrated circuit chip corresponding to Figure 20 Combined with Figures 20 - 22 shown, in this embodiment, the method for manufacturing an integrated circuit chip may include the following steps:

[0135] S401. Form a semiconductor substrate.

[0136] S402. Form a first capacitor plate on one side of the semiconductor substrate; the first capacitor plate is located in the first passive device region.

[0137] Exemplarily, referring to Figure 21 , in this embodiment, an example is given in which a second dielectric layer 20 is first formed on the semiconductor substrate 1 and then the first capacitor plate 31 is formed. At this time, the first capacitor plate 31 is specifically located on the side of the second dielectric layer 20 away from the semiconductor substrate 1.

[0138] S403. Form a first dielectric layer on the side of the first capacitor plate away from the semiconductor substrate; the first dielectric layer includes a first dielectric section located in the first active device region and a second dielectric section located in the first passive device region.

[0139] S404. At least perform patterning on the first dielectric layer to form a protection groove; the protection groove is located between the first active device in the first active device region and the first passive device in the first passive device region.

[0140] In this embodiment, the first passive device specifically refers to a capacitor, and the first active device specifically refers to a transistor.

[0141] Among them, the patterning method can be carried out by dry etching, wet etching or a combination of dry etching and wet etching. Specifically, a photoresist can be first formed in the area outside the setting area of the protection groove, and the structure outside the setting area of the protection groove is protected by the photoresist, and then the protection groove is formed by an etching method, and finally the photoresist is removed.

[0142] Among them, the protection groove is located between the first active device in the first active device region aa and the first passive device in the first passive device region na. It can be that the position of the protection groove overlaps with the position of the boundary line between the first active device region aa and the first passive device region na, or the protection groove is located in the first active device region aa, or the protection groove is located in the first passive device region na, as long as it is ensured that the protection groove is located between the first active device (such as a transistor) and the second active device (such as a capacitor).

[0143] Among them, patterning at least the first dielectric layer can be understood as that only the first dielectric layer can be patterned, or the first dielectric layer and the film layer below it can be patterned. Specifically, the film layer to be patterned can be determined according to the depth design requirements of the protection groove.

[0144] Exemplarily, Figure 21 Taking the case where only the first dielectric layer 32 is patterned to form the protection groove 5 as an example for illustration. At this time, the depth of the protection groove 5 can be less than or equal to the thickness of the first dielectric layer 32. Figure 21 Only taking the case where the depth of the protection groove 5 is equal to the thickness of the first dielectric layer 32, that is, the protection groove 5 penetrates the first dielectric layer 32 as an example for illustration. In other embodiments, when only the first dielectric layer 32 is patterned, the protection groove 5 can also be designed not to penetrate the first dielectric layer 32. In addition, referring to Figure 21 , in other embodiments, the first dielectric layer 32 and the second dielectric layer 20 can also be patterned so that the depth of the protection groove 5 is greater than the thickness of the first dielectric layer 32 and less than or equal to the sum of the thicknesses of the first dielectric layer 32 and the second dielectric layer 20. Preferably, the protection groove 5 is located in the area where the first dielectric layer 32 and the second dielectric layer 20 are in contact.

[0145] S405. A photoresist is formed on the side of the first dielectric layer away from the semiconductor substrate; the photoresist covers the second dielectric sub-portion on the side of the protection groove close to the first passive device region and the sidewall of the protection groove on the side close to the first passive device region.

[0146] As Figure 22 shown, the photoresist 4 is formed on the side of the first dielectric layer 32 away from the semiconductor substrate 1, covering the second dielectric sub-portion on the side of the protection groove 5 close to the first passive device region na and the sidewall of the protection groove 5 on the side close to the first passive device region na. It should be noted that the photoresist 4 can completely fill the protection groove 5, or as Figure 22 shown, only fill a part of the protection groove 5. The embodiments of the present invention do not limit this, as long as it is ensured that the photoresist 4 does not cover the first dielectric layer on the side of the protection groove 5 close to the first active device region aa. It should also be noted that Figure 22 only taking the case where the protection groove 5 is located in the first passive device region na and is closer to the first passive device for illustration. At this time, the photoresist 4 covers the part of the second dielectric sub-portion on the side of the protection groove 5 close to the first passive device region na and covers the sidewall of the protection groove 5 close to the first passive device region na, protecting the sidewall of the second dielectric sub-portion exposed by the protection groove 5. The first dielectric sub-portion and the part of the second dielectric sub-portion on the side of the protection groove 5 close to the first active device region aa will be thinned or completely removed due to the lack of protection of the photoresist.

[0147] Specifically, referring to Figure 22 , in this embodiment, by first forming the protection groove 5 and then forming the photoresist 4, so that part of the photoresist 4 fills the protection groove 5, the upper surface and at least part of the side surface of the film layer structure (such as the first dielectric layer) of the first passive device region na can be protected by the photoresist 4. In this way, when etching the first dielectric layer 32 of the first active device region aa, damage to the first dielectric layer 32 of the first passive device region na can be avoided, and the quality of the capacitor can be prevented from being affected. Exemplarily, when wet etching is used, since the photoresist 4 protects the side surface of the first dielectric layer 32 of the first passive device region na, the quality of the capacitor can be prevented from being affected by the lateral corrosion of the etching solution.

[0148] It can be understood that the depth of the protection groove affects the coverage range of the side surface of the film layer structure of the first passive device region by the photoresist. Therefore, according to the actual design situation, that is, according to the thickness of the dielectric layer to be removed in the first active device region, the depth of the protection groove can be determined to protect the side surface of the corresponding film layer structure of the first passive device region by the photoresist in the protection groove. In specific implementation, optionally, the protection groove at least penetrates the first dielectric layer. In this way, at least the side surface of the first dielectric layer of the first passive device region na can be completely protected by the photoresist, the influence on the capacitor quality can be reduced, and it is also beneficial to ensure the height of the air gate dielectric (the above-mentioned air gap) of the first active device region aa and reduce the parasitic capacitance of the transistor.

[0149] In addition, referring to Figure 22 , in this embodiment, since the formation of the protection groove 5 enables the photoresist 4 to protect the upper surface and the side surface of the first dielectric layer 32 of the first passive device region na, the distance between the protection groove and the first passive device can be optionally less than the distance between the protection groove and the first active device, so that the position of the protection groove 5 is as close as possible to the first passive device (as close as possible to the first capacitor plate 31). In this way, neither the quality of the first passive device will be affected, nor will it be beneficial to reduce the area occupied by the first passive device, thereby reducing the size of the integrated circuit chip and being beneficial to the miniaturized design of the integrated circuit chip.

[0150] S406. Along the direction from the first capacitor plate to the semiconductor substrate, use an etching process to remove at least part of the thickness of the first dielectric sub-part and form an etching interface, and retain the second dielectric sub-part.

[0151] S407. Form a gate electrode at the etching interface on the semiconductor substrate; the gate electrode is located in the first active device region.

[0152] S408. Form a source electrode and a drain electrode on the semiconductor substrate; the source electrode and the drain electrode are located in the first active device region and are respectively located on opposite sides of the gate electrode.

[0153] S409. Form a second capacitor plate on a side of the second dielectric section away from the first capacitor plate; the second capacitor plate is located in the first passive device region and is disposed overlapping with the first capacitor plate in a direction perpendicular to the plane of the semiconductor substrate.

[0154] Figure 23 is a schematic flow chart of a preparation method of another integrated circuit chip provided by an embodiment of the present invention. On the basis of any of the above embodiments, the preparation method is further supplemented and optimized, and the same parts will not be explained in detail here. As Figure 23 shown, in this embodiment, the preparation method of the integrated circuit chip may include the following steps:

[0155] S501. Form a semiconductor substrate.

[0156] S502. Form a first capacitor plate on one side of the semiconductor substrate; the first capacitor plate is located in the first passive device region.

[0157] S503. Form a first dielectric layer on a side of the first capacitor plate away from the semiconductor substrate; the first dielectric layer includes a first dielectric section located in the first active device region and a second dielectric section located in the first passive device region.

[0158] S504. Remove at least a part of the thickness of the first dielectric section along the direction from the first capacitor plate to the semiconductor substrate to form an etching interface, and retain the second dielectric section.

[0159] S505. Form a gate electrode at the etching interface on the semiconductor substrate; the gate electrode is located in the first active device region.

[0160] S506. Form a source electrode and a drain electrode on the semiconductor substrate; the source electrode and the drain electrode are located in the first active device region and are respectively located on opposite sides of the gate electrode.

[0161] S507. Form a third dielectric layer on a side of the second dielectric section away from the first capacitor plate; the third dielectric layer covers the first active device region and the first passive device region.

[0162] S508. Form a second capacitor plate on a side of the third dielectric layer away from the first capacitor plate; the second capacitor plate is located in the first passive device region and is disposed overlapping with the first capacitor plate in a direction perpendicular to the plane of the semiconductor substrate.

[0163] Specifically, Figure 24 is Figure 23 a schematic structural diagram of an integrated circuit chip prepared by the preparation method shown, with reference to Figure 24, the difference between this embodiment and other embodiments is that after forming the source electrode 22 and the drain electrode 23 (S506) on the semiconductor substrate 1, and before forming the second capacitor plate 33 (S508) on the side of the second dielectric portion 322 away from the first capacitor plate 31, in this embodiment, a third dielectric layer 6 is first formed on the side of the second dielectric portion 322 away from the first capacitor plate 31, and the third dielectric layer 6 is used to cover the first active device region aa and the first passive device region na, that is, to cover the film layer structure between the third dielectric layer 6 and the semiconductor substrate 1, such as Figure 24 part of the surfaces of the second dielectric portion 322, the gate electrode 21, the source electrode 22, the drain electrode 23, and the second dielectric layer 20 in

[0164] Referring to Figure 24 , in this embodiment, the third dielectric layer 6 wraps and covers structures such as the gate electrode 21. Therefore, the height h of the air gap between the first surface F1 and the etching interface F2 is less than the distance d between the first surface F1 and the etching interface F2.

[0165] Exemplarily, the forming material of the third dielectric layer includes, but is not limited to, dielectric materials such as silicon nitride, silicon oxide, and aluminum oxide. Exemplarily, the third dielectric layer 6 can be prepared by a CVD (Chemical Vapor Deposition) process.

[0166] Based on the same inventive concept, an embodiment of the present invention provides an integrated circuit chip, which integrates a capacitor and a transistor and can be obtained by using the preparation method provided in any of the above related embodiments. Exemplarily, referring to Figure 13, the integrated circuit chip includes a first active device region aa and a first passive device region na, and further includes a semiconductor substrate 1, a first capacitor plate 31, a first dielectric layer, and a gate electrode 21; the first capacitor plate 31 is located on one side of the semiconductor substrate 1 and is located in the first passive device region na; the first dielectric layer at least includes a second dielectric sub-portion 322, and the second dielectric sub-portion 322 is located on the side of the first capacitor plate 31 away from the semiconductor substrate 1 and is located in the first passive device region na; the gate electrode 21 is located on the semiconductor substrate 1 and is located in the first active device region aa; the gate electrode 21 includes a first gate sub-portion 211 and a second gate sub-portion 212, the first gate sub-portion 211 is located on the side of the second gate sub-portion 212 away from the semiconductor substrate 1, and the orthographic projection of the first gate sub-portion 211 on the semiconductor substrate 1 covers the orthographic projection of the second gate sub-portion 212 on the semiconductor substrate 1; the first gate sub-portion 211 includes a first surface F1 connected to the second gate sub-portion 212, a part of the thickness of the first dielectric sub-portion 321 is removed to form an etching interface F2, the first surface F1 is opposite to the etching interface F2 and there is an air gap between them; along the direction perpendicular to the plane where the semiconductor substrate 1 is located, the height h of the air gap is less than or equal to the distance d between the first surface F1 and the etching interface F2.

[0167] It should be noted that Figure 13 only the example where the first dielectric layer only includes the second dielectric sub-portion 322 located in the first passive device region na is shown for illustration. In other embodiments, such as Figure 14 shown, optionally, the first dielectric layer 32 covers the first active device region aa and the first passive device region na, and the thickness of the first dielectric layer located in the first passive device region na is greater than the thickness of the first dielectric layer located in the first active device region aa.

[0168] In addition, as Figure 16 shown, optionally, the integrated circuit chip further includes a second dielectric layer 20, the second dielectric layer 20 is located between the first capacitor plate 31 and the semiconductor substrate 1, and covers the first active device region aa and the first passive device region na.

[0169] As Figure 18 shown, optionally, the thickness of the second dielectric layer located in the first passive device region na is greater than the thickness of the second dielectric layer located in the first active device region aa.

[0170] As Figure 19 shown, optionally, the second dielectric layer only includes a fourth dielectric sub-portion 202 located in the first passive device region na.

[0171] As Figure 24As shown, optionally, the integrated circuit chip further includes a third dielectric layer 6, which is located between the film layer where the second dielectric segment 322 is located and the film layer where the second capacitor plate 33 is located, covers the first active device region aa and the first passive device region na, and wraps the surfaces of the gate electrode 21, the source electrode 22, and the drain electrode 23. When the integrated circuit chip includes the third dielectric layer 6, in the direction perpendicular to the plane of the semiconductor substrate 1, the height h of the air gap is less than the distance d between the first surface F1 and the etching interface F2.

[0172] The above specific embodiments do not limit the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing an integrated circuit chip, the integrated circuit chip including a first device region and a second device region; characterized in that, The preparation method includes: Forming a semiconductor substrate; Forming a first dielectric layer on one side of the semiconductor substrate; the first dielectric layer includes a first dielectric sub-portion located in the first device region and a second dielectric sub-portion located in the second device region; Performing at least a first patterning process on the first dielectric layer to form a protection groove; the protection groove is located between a first device in the first device region and a second device in the second device region; Performing a second patterning process on the first dielectric layer to make the thickness of the first dielectric sub-portion different from the thickness of the second dielectric sub-portion.

2. The preparation method according to claim 1, wherein, The depth of the protection groove is less than or equal to the thickness of the first dielectric layer.

3. The preparation method according to claim 1, characterized in that, The thickness of the first dielectric sub-portion is greater than the thickness of the second dielectric sub-portion; Performing the second patterning process on the first dielectric layer includes: Forming a photoresist on the side of the first dielectric layer away from the semiconductor substrate; the photoresist covers the first dielectric sub-portion on the side of the protection groove close to the first device region and the sidewall of the protection groove on the side close to the first device region; Removing at least part of the thickness of the second dielectric sub-portion by an etching process.

4. A method for manufacturing an integrated circuit chip, the integrated circuit chip including a first active device region and a first passive device region; characterized in that, The preparation method includes: Forming a semiconductor substrate; Forming a first capacitor plate on one side of the semiconductor substrate; the first capacitor plate is located in the first passive device region; Forming a first dielectric layer on the side of the first capacitor plate away from the semiconductor substrate; the first dielectric layer includes a first dielectric sub-portion located in the first active device region and a second dielectric sub-portion located in the first passive device region; Removing at least part of the thickness of the first dielectric sub-portion along the direction from the first capacitor plate to the semiconductor substrate to form an etching interface, and retaining the second dielectric sub-portion; Forming a gate electrode at the etching interface on the semiconductor substrate; the gate electrode is located in the first active device region; the gate electrode includes a first gate sub-portion and a second gate sub-portion, the first gate sub-portion is located on the side of the second gate sub-portion away from the semiconductor substrate, and the orthographic projection of the first gate sub-portion on the semiconductor substrate covers the orthographic projection of the second gate sub-portion on the semiconductor substrate; the first gate sub-portion includes a first surface connected to the second gate sub-portion, the first surface faces the etching interface and there is an air gap between them; along the direction perpendicular to the plane where the semiconductor substrate is located, the height of the air gap is less than or equal to the distance between the first surface and the etching interface.

5. The preparation method according to claim 4, characterized in that, Before removing at least part of the thickness of the first dielectric sub-portion, the preparation method further includes: Performing at least a patterning process on the first dielectric layer to form a protection groove; the protection groove is located between a first active device in the first active device region and a first passive device in the first passive device region.

6. The preparation method according to claim 1 or 5, characterized in that, Before forming the first dielectric layer on one side of the semiconductor substrate, the preparation method further includes: Forming a second dielectric layer on the semiconductor substrate; the second dielectric layer covers the semiconductor substrate; The first dielectric layer and the second dielectric layer in the part are in direct contact, and the protection groove is located in the area where the first dielectric layer and the second dielectric layer are in direct contact; Under the same etching process, the etching rate of the second dielectric layer is less than that of the first dielectric layer.

7. The preparation method according to claim 5, characterized in that, The protection groove penetrates at least the first dielectric layer.

8. The preparation method according to claim 5, characterized in that, The distance between the protection groove and the first passive device is less than the distance between the protection groove and the first active device.

9. The preparation method according to claim 5, characterized in that, The removing at least part of the thickness of the first dielectric sub - part includes: Forming a photoresist on the side of the first dielectric layer away from the semiconductor substrate; the photoresist covers the second dielectric sub - part on the side of the protection groove close to the first passive device area and the side wall of the protection groove on the side close to the first passive device area; Removing at least part of the thickness of the first dielectric sub - part by an etching process.

10. The preparation method according to claim 4, characterized in that, After forming the gate electrode on the semiconductor substrate, the preparation method further includes: Forming a source electrode and a drain electrode on the semiconductor substrate; the source electrode and the drain electrode are located in the first active device area and are respectively on opposite sides of the gate electrode; Forming a third dielectric layer on the side of the second dielectric sub - part away from the first capacitor plate; the third dielectric layer covers the first active device area and the first passive device area; Forming a second capacitor plate on the side of the third dielectric layer away from the first capacitor plate; the second capacitor plate is located in the first passive device area and is arranged to overlap with the first capacitor plate in a direction perpendicular to the plane of the semiconductor substrate.

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