Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate; the epitaxial structure is positioned on one side of the substrate; two-dimensional electron gas is arranged in the epitaxial structure; the gate electrode structure comprises a gate electrode and a gate power supply electrode, and the gate electrode and the gate power supply electrode are independently arranged; the first odd-mode resistor comprises a first resistor electrode and a second resistor electrode, the first resistor electrode and the second resistor electrode are both in ohmic contact with the two-dimensional electron gas, and a two-dimensional electron gas conducting channel exists between the first resistor electrode and the second resistor electrode in the arrangement direction of the first resistor electrode and the second resistor electrode; for the gate electrodes and the gate power supply electrode which are independently arranged, the first resistor electrode in the same first odd-mode resistor is electrically connected with at least one gate electrode, and the second resistor electrode is electrically connected with the gate power supply electrode. By adopting the technical means, the odd film oscillation can be inhibited by arranging the first odd film resistor, and the stability of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, and particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Gallium nitride high electron mobility transistors (HEMTs) have excellent characteristics such as a high bandgap width and high mobility, and are suitable for fabricating devices with high temperature, high frequency, high voltage, and high power. They can be widely used in the fields of radio frequency and microwave, as well as power electronics, and are one of the research hotspots in the field of semiconductor devices currently.

[0003] Currently, 5G communication has increasingly high requirements for the bandwidth and operating frequency of semiconductor chips. Gallium nitride high electron mobility transistors are a type of high electron mobility device formed by the two-dimensional electron gas at the heterojunction in the epitaxial structure, and can be better applied to the fields of high frequency, high voltage, and high power, and are naturally favored by the 5G communication field.

[0004] For gallium nitride radio frequency power amplifiers, achieving higher power, gain, and efficiency of the device has always been pursued for gallium nitride chips. However, in order to achieve higher power, multiple gate fingers need to be designed, which easily forms a long feedback loop between different gate fingers and the drain, resulting in oscillation. This oscillation is odd-mode oscillation, which in turn affects the stability of the device. Therefore, how to improve the stability of semiconductor devices is an urgent problem to be solved currently. Summary of the Invention

[0005] The present invention provides a semiconductor device and a method for manufacturing the same to suppress odd-mode oscillation and improve the stability of the semiconductor device.

[0006] In a first aspect, an embodiment of the present invention provides a semiconductor device, including:

[0007] A substrate;

[0008] An epitaxial structure located on one side of the substrate; a two-dimensional electron gas is provided in the epitaxial structure;

[0009] A gate electrode structure located on the side of the epitaxial structure away from the substrate. The gate electrode structure includes a gate electrode and a gate power supply electrode, and the gate electrode and the gate power supply electrode are independently provided.

[0010] The first odd-mode resistor includes a first resistor electrode and a second resistor electrode. Both the first resistor electrode and the second resistor electrode form ohmic contacts with the two-dimensional electron gas, and there is a two-dimensional electron gas conduction channel between the first resistor electrode and the second resistor electrode along the arrangement direction of the first resistor electrode and the second resistor electrode. For the independently provided gate electrode and gate power supply electrode, the first resistor electrode in the same first odd-mode resistor is electrically connected to at least one of the gate electrodes, and the second resistor electrode is electrically connected to the gate power supply electrode.

[0011] Optionally, the semiconductor device includes a plurality of the gate electrodes. Any one of the gate electrodes is independently provided with the gate power supply electrode, and the first odd-mode resistor is provided between any one of the gate electrodes and the gate power supply electrode.

[0012] Optionally, the semiconductor device includes a plurality of the gate electrodes. The plurality of gate electrodes extend along a first direction and are arranged along a second direction. The first direction and the second direction intersect and are both parallel to the plane of the substrate.

[0013] For the independently provided gate electrode and gate power supply electrode, the first resistor electrode in the same first odd-mode resistor is electrically connected to at least two of the gate electrodes adjacent along the second direction, and the second resistor electrode is electrically connected to the gate power supply electrode.

[0014] Optionally, the semiconductor device further includes a source electrode. Along the second direction, the source electrode is located between two adjacent gate electrodes.

[0015] For the independently provided gate electrode and gate power supply electrode, the first resistor electrode in the same first odd-mode resistor is electrically connected to two gate electrodes adjacent to the source electrode, and the second resistor electrode is electrically connected to the gate power supply electrode.

[0016] Optionally, the plurality of gate electrodes extend along a first direction and are arranged along a second direction, and any two adjacent gate electrodes along the second direction are symmetrically arranged with respect to a symmetry axis. The symmetry axis extends along the first direction. The first direction and the second direction intersect and are both parallel to the plane of the substrate.

[0017] The first odd-mode resistor electrically connected to the two symmetrically arranged gate electrodes is symmetrically arranged with respect to the symmetry axis.

[0018] Optionally, the gate electrode includes a connected gate body portion and a gate tail portion. The gate tail portion is located on a side of the gate body portion close to the gate power supply electrode, and in a second direction, an extended width of the gate tail portion is greater than an extended width of the gate body portion; the second direction intersects with an extending direction of the gate electrode.

[0019] The first resistance electrode is electrically connected to the gate tail portion, and a part of the two-dimensional electron gas is reserved in the semiconductor structure at a position corresponding to the gate tail portion.

[0020] Optionally, the gate power supply electrode includes a connected power supply body portion and a power supply protruding portion. The power supply protruding portion is located on a side of the power supply body portion close to the gate electrode.

[0021] The second resistance electrode is electrically connected to the power supply protruding portion.

[0022] Optionally, in the same first odd-mode resistor, the first resistance electrode and the second resistance electrode are arranged along a first direction and extend along a second direction; the first direction and the second direction intersect and are both parallel to a plane where the substrate is located, and the first direction is parallel to an extending direction of the gate electrode.

[0023] Optionally, in the same first odd-mode resistor, a distance between the first resistance electrode and the second resistance electrode is d, and extended lengths of the first resistance electrode and the second resistance electrode are both w.

[0024] A contact resistance between the first resistance electrode and the gate electrode is Rc1, connection resistances between the second resistance electrode and the gate power supply electrode are both Rc2, and a sheet resistance of the two-dimensional electron gas is Rsh.

[0025] The

[0026] Optionally, the semiconductor device further includes an ohmic electrode.

[0027] The first resistance electrode and the second resistance electrode are both arranged in the same layer as the ohmic electrode, and the first resistance electrode is in contact electrical connection with the gate electrode, and the second resistance electrode is in contact electrical connection with the gate power supply electrode.

[0028] Optionally, the semiconductor device further includes an ohmic electrode structure. The ohmic electrode structure includes a connected ohmic electrode and an ohmic power supply electrode.

[0029] The gate power supply electrode and / or the ohmic power supply electrode includes at least two independently arranged power supply sub-portions.

[0030] The semiconductor device further includes a second odd-mode resistor, which includes a third resistor electrode and a fourth resistor electrode. Both the third resistor electrode and the fourth resistor electrode form ohmic contacts with the two-dimensional electron gas, and along the arrangement direction of the third resistor electrode and the fourth resistor electrode, there is a two-dimensional electron gas conductive channel between the third resistor electrode and the fourth resistor electrode. There are two adjacent power supply branches. The third resistor electrode in the same second odd-mode resistor is electrically connected to one of the power supply branches, and the fourth resistor electrode is electrically connected to the other power supply branch.

[0031] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, including:

[0032] Providing a substrate and preparing an epitaxial structure on one side of the substrate; a two-dimensional electron gas is provided in the epitaxial structure;

[0033] Preparing a first odd-mode resistor and a gate electrode structure on the side of the epitaxial structure away from the substrate; the first odd-mode resistor includes a first resistor electrode and a second resistor electrode. Both the first resistor electrode and the second resistor electrode form ohmic contacts with the two-dimensional electron gas, and along the arrangement direction of the first resistor electrode and the second resistor electrode, there is a two-dimensional electron gas conductive channel between the first resistor electrode and the second resistor electrode. The gate electrode structure includes a gate electrode and a gate power supply electrode, and the gate electrode and the gate power supply electrode are independently arranged. For the independently arranged gate electrode and gate power supply electrode, the first resistor electrode in the same first odd-mode resistor is electrically connected to at least one of the gate electrodes, and the second resistor electrode is electrically connected to the gate power supply electrode.

[0034] Optionally, preparing the first odd-mode resistor and the gate electrode structure on the side of the epitaxial structure away from the substrate includes:

[0035] Using the same mask process to prepare a first resistor electrode, a second resistor electrode, and an ohmic electrode on the side of the epitaxial structure away from the substrate;

[0036] Preparing a gate electrode in the area outside the ohmic electrode, and the gate electrode is in electrical contact with the first resistor electrode;

[0037] Preparing a gate power supply electrode, the gate power supply electrode is in electrical contact with the gate electrode and in electrical contact with the second resistor electrode.

[0038] In the technical solution of the embodiment of the present invention, by providing a first odd-film resistor, the first odd-film resistor includes a first resistor electrode and a second resistor electrode. Both the first resistor electrode and the second resistor electrode form ohmic contacts with the two-dimensional electron gas, and there is a two-dimensional electron gas conductive channel between the first resistor electrode and the second resistor electrode. Thus, the first resistor electrode and the second resistor electrode can conduct through the channel. Further, for the independently provided gate electrode and gate power supply electrode, the first resistor electrode in the same first odd-mode resistor is electrically connected to at least one gate electrode, and the second resistor electrode is electrically connected to the gate power supply electrode. That is, the first resistor electrode and the second resistor electrode are connected in ohmic contact with the two-dimensional electron gas and are electrically connected to the gate electrode and the gate power supply electrode. Thus, the first odd-film resistor can dissipate the energy of the odd-film signal, suppress the generation of odd-film oscillation, and improve the stability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 FIG. is a top view schematic diagram of a semiconductor device provided by an embodiment of the present invention;

[0040] Figure 2 is Figure 1 a schematic cross-sectional structure diagram of a semiconductor device provided along the section line A-A';

[0041] Figure 3 FIG. is a top view schematic diagram of another semiconductor device provided by an embodiment of the present invention;

[0042] Figure 4 FIG. is a top view schematic diagram of yet another semiconductor device provided by an embodiment of the present invention;

[0043] Figure 5 FIG. is a top view schematic diagram of yet another semiconductor device provided by an embodiment of the present invention;

[0044] Figure 6 FIG. is a flow schematic diagram of a preparation method of a semiconductor device provided by an embodiment of the present invention;

[0045] Figure 7 FIG. is a flow schematic diagram of another preparation method of a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0047] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of the present invention are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0048] Figure 1 A top view schematic diagram of a semiconductor device provided by an embodiment of the present invention; Figure 2 For Figure 1 A schematic cross-sectional structure diagram of a semiconductor device along the section line A-A'; the semiconductor device includes: a substrate 10; an epitaxial structure 20 located on one side of the substrate 10; a two-dimensional electron gas (Two Dimensional Electron Gas, 2DEG) is provided in the epitaxial structure 20; a gate electrode structure 30 is located on the side of the epitaxial structure 20 away from the substrate 10, the gate electrode structure 30 includes a gate electrode 301 and a gate power supply electrode 302, and the gate electrode 301 and the gate power supply electrode 302 are independently arranged; a first odd-mode resistor 40 includes a first resistor electrode 401 and a second resistor electrode 402, both the first resistor electrode 401 and the second resistor electrode 402 form an ohmic contact with the two-dimensional electron gas, and along the arrangement direction of the first resistor electrode 401 and the second resistor electrode 402, there is a two-dimensional electron gas conduction channel between the first resistor electrode 401 and the second resistor electrode 402, that is, the first resistor electrode 401 and the second resistor electrode 402 are electrically connected through the two-dimensional electron gas; for the independently arranged gate electrode 301 and the gate power supply electrode 302, the first resistor electrode 401 in the same first odd-mode resistor 40 is electrically connected to at least one gate electrode 301, and the second resistor electrode 402 is electrically connected to the gate power supply electrode 302.

[0049] Specifically, the gate electrode structure 30 includes a gate electrode 301 and a gate power supply electrode 302. The gate power supply electrode 302 can be understood as a gate pad. The gate electrode 301 and the gate power supply electrode 302 are independently arranged, that is, the gate electrode 301 and the gate power supply electrode 302 are not in electrical contact, but there is a gap between the two.

[0050] Specifically, the first odd-mode resistor 40 includes a first resistor electrode 401 and a second resistor electrode 402. Both the first resistor electrode 401 and the second resistor electrode 402 form ohmic contacts with the two-dimensional electron gas. Usually, the two-dimensional electron gas in the passive region bb will be consumed by means such as ion implantation. In the embodiment of the present invention, the odd-mode resistor 40 is disposed in the passive region bb, and the two-dimensional electron gas in the region where the odd-mode resistor 40 is disposed in the passive region bb is retained, so that the odd-mode resistor 40 forms an ohmic contact with the two-dimensional electron gas. It should be noted that both the gate electrode 301 and the gate power supply electrode 302 are in zero contact with the two-dimensional electron gas in the region of the odd-mode resistor 40. That is to say, when preparing the gate electrode 301 and the gate power supply electrode 302, the first resistor electrode 401 and the second resistor electrode 402 cannot be completely wrapped, and at least two adjacent side surfaces of the first resistor electrode 401 and the second resistor electrode 402 are exposed to ensure that the first resistor electrode 401 and the second resistor electrode 402 form complete contact with the two-dimensional electron gas while preventing the gate electrode and the gate power supply electrode from contacting the two-dimensional electron gas. Further, along the arrangement direction of the first resistor electrode 401 and the second resistor electrode 402, there is a two-dimensional electron gas conductive channel between the first resistor electrode 401 and the second resistor electrode 402, so that the first resistor electrode 401 and the second resistor electrode 402 can conduct through the channel. For the independently disposed gate electrode 301 and the gate power supply electrode 302, the first resistor electrode 401 in the same first odd-mode resistor 40 is electrically connected to at least one gate electrode 301, and the second resistor electrode 402 is electrically connected to the gate power supply electrode 302. Thus, by electrically connecting the first resistor electrode 401 and the second resistor electrode 402 to the gate electrode 301 and the gate power supply electrode 302 respectively, that is, the first odd-mode resistor 40 is disposed between the gate electrode 301 and the gate power supply electrode 302, and then the energy of the odd-mode signal is consumed through the first odd-mode resistor 40, that is, the odd-mode oscillation is suppressed, and the stability of the semiconductor device can be improved.

[0051] It should be noted that the first resistor electrode 401 can be located at the end position of the gate electrode 301 close to the gate power supply electrode 302, and the second resistor electrode 402 can be located at the end position of the gate power supply electrode 302 close to the gate electrode 301, so as to improve the freedom of setting the first odd-mode resistor 40.

[0052] It can be understood that the semiconductor device may further include a source electrode 101 and a source power supply electrode electrically connected to the source electrode 101. The semiconductor device may further include a drain electrode 501 and a drain power supply electrode 502 electrically connected to the drain electrode 501. The source electrode 101 may serve as the input terminal of the semiconductor device, and the drain electrode 501 may serve as the output terminal of the semiconductor device. The drain power supply electrode 502 can be understood as a drain pad. The drain electrode 501 in the active region aa can be connected to the drain power supply electrode 502 located in the passive region bb, and the drain electrode 501 can receive a voltage signal through the drain power supply electrode 502 to ensure the normal operation of the semiconductor device.

[0053] Exemplarily, the substrate 10 may be formed of one of the materials such as silicon, sapphire, silicon carbide, and gallium arsenide. The epitaxial structure 20 located on one side of the substrate 10 may be formed of one or more of group III-V nitrides such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride.

[0054] Exemplarily, continuing to refer to Figure 2 , the epitaxial structure 20 may include a nucleation layer 202, a buffer layer 203, a channel layer 204, and a barrier layer 205; the channel layer 204 and the barrier layer 205 may form a heterojunction structure.

[0055] Exemplarily, continuing to refer to Figure 2 , the material of the nucleation layer 202 may be aluminum nitride, which is located between the substrate 10 and the buffer layer 203 and serves to bond the next semiconductor material layer to be grown.

[0056] Exemplarily, continuing to refer to Figure 2 , the buffer layer 203 is located on one side of the substrate 10. The material of the buffer layer 203 may be gallium nitride, and the buffer layer 203 may include iron atoms, which is beneficial to achieving the high-resistance performance of the buffer layer 203, ensuring the blocking of vertical leakage and improving the pinch-off performance of the semiconductor device.

[0057] Exemplarily, continuing to refer to Figure 2 , the channel layer 204 may be a group III nitride, such as Al x Ga 1－x N, where 0 ≤ x < 1, that is, at the interface between the channel layer 204 and the barrier layer 205, that is, the energy of the conduction band edge of the channel layer 204 is less than the energy of the conduction band edge of the barrier layer 205. Exemplarily, x = 0 indicates that the channel layer 204 is GaN. The channel layer 204 may also be other group III nitrides, such as InGaN or AlInGaN. The channel layer 204 may be undoped or unintentionally doped. The channel layer 204 may also be a multilayer structure, such as a combination of superlattice, GaN, or AlGaN.

[0058] Exemplarily, continuing to refer to Figure 2 , the barrier layer 205 can be AlN, AlInN, AlGaN or AlInGaN. The barrier layer 205 has a sufficient thickness and a sufficiently high Al component to form a significant carrier concentration at the interface between the channel layer 204 and the barrier layer 205.

[0059] Exemplarily, continuing to refer to Figure 2 , the channel layer 204 can include GaN, and the barrier layer 205 can include AlGaN, that is, the material of the barrier layer 205 has a higher bandgap than the material of the channel layer 204, and the channel layer 204 can also have a greater electron affinity than the barrier layer 205. Due to the bandgap difference between the barrier layer 205 and the channel layer 204 and the piezoelectric polarization effect at the interface between the barrier layer 205 and the channel layer 204, a two-dimensional electron gas is formed at the channel layer 204 and the barrier layer 205.

[0060] It can be understood that the epitaxial structure 20 can further include a cap layer, and the cap layer is located on the surface of the barrier layer 205 away from the substrate 10. The cap layer can reduce surface states, reduce surface leakage of subsequent semiconductor devices, and suppress current collapse, thereby improving the stability and reliability of the epitaxial structure 20 and the semiconductor device.

[0061] The semiconductor device provided by the embodiment of the present invention, by providing a first odd-mode film resistor, the first odd-mode film resistor includes a first resistor electrode and a second resistor electrode, both the first resistor electrode and the second resistor electrode form an ohmic contact with the two-dimensional electron gas, and there is a two-dimensional electron gas conduction channel between the first resistor electrode and the second resistor electrode, so that the first resistor electrode and the second resistor electrode can be electrically connected through the channel conduction. Further, for the independently provided gate electrode and gate power supply electrode, the first resistor electrode in the same first odd-mode resistor is electrically connected to at least one gate electrode, and the second resistor electrode is electrically connected to the gate power supply electrode, that is, the first resistor electrode and the second resistor electrode are ohmically contacted and connected to the two-dimensional electron gas, and are electrically connected to the gate electrode and the gate power supply electrode. In this way, the odd-mode signal in the gate electrode 301 can be dissipated through the first odd-mode film resistor, the generation of odd-mode oscillation can be suppressed, and the stability of the semiconductor device can be improved.

[0062] Optionally, continuing to refer to Figure 1 , the semiconductor device includes a plurality of gate electrodes 301, any gate electrode 301 is independently provided with the gate power supply electrode 302, and a first odd-mode resistor 40 is provided between any gate electrode 301 and the gate power supply electrode 302.

[0063] Specifically, a first resistance electrode 401 is provided at the end position of each gate electrode 301 close to the gate power supply electrode 302, and at least two second resistance electrodes 402 are provided at the position of the gate power supply electrode 302 close to the gate electrode 301, and the first resistance electrode 401 and the second resistance electrode 402 are arranged in correspondence, that is, the number of the first odd-mode resistors 40 is the same as the number of the gate electrodes 301. In this way, the odd-mode oscillation can be further suppressed by the first odd-mode resistor 40, thereby improving the stability of the semiconductor device.

[0064] Optionally, continue to refer to Figure 1 , the semiconductor device includes a plurality of gate electrodes 301, the plurality of gate electrodes 301 extend along a first direction (the Y direction shown in the figure), are arranged along a second direction (the X direction shown in the figure), and any two adjacent gate electrodes 301 along the second direction X are symmetrically arranged with respect to a symmetry axis M, and the symmetry axis M extends along the first direction Y; the first direction Y and the second direction X intersect and are both parallel to the plane where the substrate 10 is located; the first odd-mode resistor 40 electrically connected to the two symmetrically arranged gate electrodes 301 is symmetrically arranged with respect to the symmetry axis M.

[0065] Specifically, the first odd-mode resistor 40 electrically connected to the two symmetrically arranged gate electrodes 301 is symmetrically arranged with respect to the symmetry axis M. In this way, the phase balance of each gate electrode 301 can be ensured, and odd-mode oscillation is not likely to occur. In addition, by setting the symmetry of the two first odd-mode resistors 40 to be consistent with the symmetry of the two gate electrodes 301, the possibility of generating odd-mode signal oscillation in the semiconductor device can be further reduced, and it is also beneficial to ensure the stability of the radio frequency signal.

[0066] Optionally, Figure 3 is a top view schematic diagram of another semiconductor device provided by an embodiment of the present invention. As Figure 3 shown, the semiconductor device includes a plurality of gate electrodes 301, the plurality of gate electrodes 301 extend along a first direction Y and are arranged along a second direction X; the first direction Y and the second direction X intersect and are both parallel to the plane where the substrate 10 is located; for the independently arranged gate electrode 301 and the gate power supply electrode 302, the first resistance electrode 401 in the same first odd-mode resistor 40 is electrically connected to at least two adjacent gate electrodes 301 along the second direction X, and the second resistance electrode 402 is electrically connected to the gate power supply electrode 302.

[0067] Specifically, the first resistance electrode 401 in the same first odd-mode resistor 40 is electrically connected to at least two gate electrodes 301 arranged adjacent to each other along the second direction X. That is, at least two adjacent gate electrodes 301 share the same first resistance electrode 401. In other words, at least two gate electrodes 301 are connected to the gate power supply electrode 302 through the same first odd-mode resistor 40. In this way, on the one hand, it can ensure that the odd-mode signals in each gate electrode 301 are suppressed, which is beneficial to achieving the phase balance of each gate electrode 301. On the other hand, it can also increase the resistance value of the first odd-mode resistor 40 and save the area of the semiconductor device, realizing the miniaturized design of the semiconductor device. Preferably, the two adjacent gate electrodes are the gate electrodes 301 on both sides of the same source electrode 501.

[0068] It can be understood that Figure 2 Only the technical solution in which the first resistance electrode 401 in the same first odd-mode resistor 40 is electrically connected to at least two gate electrodes 301 arranged adjacent to each other along the second direction X is shown. Exemplarily, it can also be that three or more gate electrodes 301 share the same resistance electrode 401.

[0069] Furthermore, multiple gate electrodes 301 extend along the first direction Y, are arranged along the second direction X, and any two adjacent gate electrodes 301 along the second direction X are symmetrically arranged with respect to the symmetry axis M, and the symmetry axis M extends along the first direction Y; the first direction Y and the second direction X intersect and are both parallel to the plane where the substrate 10 is located; the two first odd-mode resistors 40 electrically connected to the two symmetrically arranged gate electrodes 301 are symmetrically arranged with respect to the symmetry axis M.

[0070] Optionally, Figure 4 This is a top view schematic diagram of another semiconductor device provided by an embodiment of the present invention. As Figure 4 shown, the semiconductor device further includes a source electrode 101. Along the second direction X, the source electrode 101 is located between two adjacent gate electrodes 301; for the independently arranged gate electrode 301 and the gate power supply electrode 302, the first resistance electrode 401 in the same first odd-mode resistor 40 is electrically connected to the two gate electrodes 301 adjacent to the source electrode 101, and the second resistance electrode 402 is electrically connected to the gate power supply electrode 302.

[0071] Specifically, the first resistance electrode 401 in the same first odd-mode resistor 40 is electrically connected to the two gate electrodes 301 adjacent to the source electrode 101, and the second resistance electrode 402 is electrically connected to the gate power supply electrode 302. That is, along the second direction X, the gate electrodes 301 located on both sides of the source electrode 101 are electrically connected to the same first resistance electrode 401, and the second resistance electrode 402 is correspondingly arranged with respect to the first resistance electrode 401.

[0072] Continue to refer toFigure 3 , in the same first odd-mode resistor 40, the first resistor electrode 401 is electrically connected to two gate electrodes 301 adjacent to the drain electrode 501, and the second resistor electrode 402 is electrically connected to the gate power supply electrode 302, that is, the two gate electrodes on both sides of the drain electrode 501 are connected to the same first resistor electrode 401, so as to realize the diversity of the semiconductor device setting.

[0073] Optionally, continue to refer to Figure 1 , the gate electrode 301 includes a connected gate main body 3011 and a gate tail 3012. The gate tail 3012 is located on the side of the gate main body 3011 close to the gate power supply electrode 302, and along the second direction X, the extension width of the gate tail 3012 is greater than the extension width of the gate main body 3011; the second direction X intersects with the extension direction of the gate electrode 301; the first resistor electrode 401 is electrically connected to the gate tail 3012, and a part of the two-dimensional electron gas is reserved in the semiconductor structure at the position corresponding to the gate tail 3012.

[0074] Specifically, along the second direction X, the extension width of the gate tail 3012 is greater than the extension width of the gate main body 3011, that is, along the second direction X, the width of the gate electrode 301 in the passive region bb is greater than the width of the gate electrode 301 in the active region aa, which is beneficial to improving the reliability. In addition, the curvature radius corresponding to the gate tail 3012 in the passive region bb along the second direction X can be greater than the width of the gate main body 3011 in the active region aa along the second direction X, so that the difficulty of the developer penetrating from the end of the gate electrode 301 to the middle can be reduced, the display difficulty can be reduced, and the gate electrode 301 corresponding to the corner positions at both ends of the source and drain can be moderately compensated to make up for or completely eliminate the problem of the reduction of the width of the gate electrode 301 caused by the diffraction of light. Further, the first resistor electrode 401 is electrically connected to the gate tail 3012, that is, the first resistor electrode 401 is electrically connected to the region with a larger width in the gate electrode 301. In this way, on the one hand, the connection stability is ensured, and on the other hand, it is beneficial to have a smaller contact resistance between the first resistor electrode 401 and the gate electrode 301, and to avoid the problems of poor contact or large signal loss between the gate electrode 301 and the first resistor electrode 104.

[0075] Further, a part of the two-dimensional electron gas under the gate tail 3012 in the passive region bb is reserved, and the gate tail 3012 is in zero contact with the two-dimensional electron gas, so as to ensure that the first resistor electrode 401 forms an ohmic contact with the two-dimensional electron gas while being electrically connected to the gate tail 3012, and to avoid the gate tail 3012 from forming contact with the two-dimensional electron gas.

[0076] Optionally, continue to refer to Figure 1, the gate power supply electrode 302 includes a connected power supply main body portion 3021 and a power supply protruding portion 3022, and the power supply protruding portion 3022 is located on the side of the power supply main body portion 3021 close to the gate electrode 301; the second resistance electrode 402 is electrically connected to the power supply protruding portion 3022.

[0077] Specifically, the power supply protruding portion 3022 is located on the side of the power supply main body portion 3021 close to the gate electrode 301, and the second resistance electrode 402 is electrically connected to the power supply protruding portion 3022. The power supply main body portion 3021, as the main power supply pad, does not affect the working characteristics of the gate power supply electrode 302. In addition, by adjusting the shape of the power supply protruding portion 3022, the contact effect between the gate power supply electrode 302 and the second resistance electrode 402 can be ensured, which is conducive to ensuring the stability of the contact between the gate power supply electrode 302 and the second resistance electrode 402; by adjusting the length of the power supply protruding portion 3022, the distance between the two resistance electrodes can be adjusted, which is convenient for adjusting the resistance value of the first odd-mode resistance 40, so that the resistance value of the odd-mode resistance 40 is adjustable and the adjustment method is simple to meet the requirements of various different scenarios.

[0078] Optionally, continue to refer to Figure 1 , in the same first odd-mode resistance 40, the first resistance electrode 401 and the second resistance electrode 402 are arranged along the first direction Y and extend along the second direction X; the first direction Y and the second direction X intersect and are both parallel to the plane where the substrate 10 is located, and the first direction Y is parallel to the extending direction of the gate electrode 301.

[0079] Specifically, since the presence of the odd-mode signal in the gate electrode 301 will affect the stability of the semiconductor device, by setting the arrangement direction of the first resistance electrode 401 and the second resistance electrode 402 to be the same as the extending direction of the gate electrode 301, it is beneficial to dissipate the odd-mode signal in the gate electrode 301 through the first odd-mode resistance 40, thereby suppressing the odd-mode oscillation and ensuring the stability of the semiconductor device.

[0080] Optionally, continue to refer to Figure 1 , in the same first odd-mode resistance 40, the distance between the first resistance electrode 401 and the second resistance electrode 402 is d, and the extending lengths of the first resistance electrode 401 and the second resistance electrode 402 are both w; the contact resistance between the first resistance electrode 401 and the gate electrode 301 is Rc1, and the connection resistances between the second resistance electrode 402 and the gate power supply electrode 302 are both Rc2, and the sheet resistance of the two-dimensional electron gas is Rsh;

[0081] Specifically, the contact resistance Rc1 between the first resistance electrode 401 and the gate electrode 301, the connection resistance Rc2 between the second resistance electrode 402 and the gate power supply electrode 302, and the sheet resistance Rsh of the two-dimensional electron gas are all fixed. Therefore, the resistance value of the first odd-mode resistor 40 can be changed by adjusting the distance d between the first resistance electrode 401 and the second resistance electrode 402 and / or adjusting the extension length w of the first resistance electrode 401 and the second resistance electrode 402. In this way, by adjusting the resistance value of the first odd-mode resistor 40, a diversified design of the resistance value of the odd-mode resistor 40 can be achieved, so as to achieve different suppression effects and meet the requirements in various different scenarios.

[0082] It can be understood that, compared with the thin-film resistor in the prior art, the odd-mode resistor provided by the embodiment of the present invention is arranged on the same layer as the ohmic electrode, without adding a new film layer, and the resistance value of the odd-mode resistor can be adjusted by adjusting the distance between the first resistance electrode and the second resistance electrode, and / or adjusting the extension length of the first resistance electrode and the second resistance electrode, thereby improving the flexibility of adjusting the resistance value of the odd-mode resistor.

[0083] Optionally, continue to refer to Figure 1 and Figure 2 , the electrodes of the semiconductor device may include an ohmic electrode and a Schottky electrode. The ohmic electrode includes a source electrode 101 and / or a drain electrode 501, and the Schottky electrode includes a gate electrode 301. It can be understood that the ohmic electrode forms an ohmic contact with the epitaxial structure 20, and the Schottky electrode forms a Schottky contact with the epitaxial structure 20.

[0084] Both the first resistance electrode 401 and the second resistance electrode 402 are arranged on the same layer as the ohmic electrode, and the gate electrode 301 covers the first resistance electrode 401 and is in electrical contact, and the second resistance electrode 402 is in electrical contact with the gate power supply electrode 302. To ensure that the odd-mode resistor forms an ohmic contact with the two-dimensional electron gas and suppresses the odd-mode signal during the signal transmission of each gate.

[0085] Specifically, taking the drain electrode 501 as an example in this embodiment, both the first resistance electrode 401 and the second resistance electrode 402 are arranged on the same layer as the drain electrode 501, that is, the first resistance electrode 401, the second resistance electrode 402, and the drain electrode 501 are prepared by the same mask process. That is, the resistance electrodes in the first odd-mode resistor 40 are all arranged in the ohmic contact metal layer, and the first resistance electrode 401, the second resistance electrode 402, and the drain electrode 501 are arranged on the same layer. In this way, on the one hand, while ensuring a good ohmic contact effect between the resistance electrode and the two-dimensional electron gas, the thinning of the semiconductor device can be realized, and on the other hand, the process flow can be simplified.

[0086] Optionally, Figure 5A top view schematic diagram of another semiconductor device provided by an embodiment of the present invention is shown as Figure 5 shown. The semiconductor device further includes an ohmic electrode structure. Exemplarily, the ohmic electrode structure may be a drain electrode structure 50, and the drain electrode structure 50 includes a connected drain electrode 501 and a drain power supply electrode 502; the gate power supply electrode 302 and / or the drain power supply electrode 502 includes at least two independently arranged power supply parts 100; the semiconductor device further includes a second odd-mode resistor 60, and the second odd-mode resistor 60 includes a third resistor electrode 601 and a fourth resistor electrode 602. Both the third resistor electrode 601 and the fourth resistor electrode 602 form an ohmic contact with the two-dimensional electron gas, and along the arrangement direction of the third resistor electrode 601 and the fourth resistor electrode 602, there is a two-dimensional electron gas conductive channel between the third resistor electrode 601 and the fourth resistor electrode 602; there are two adjacent power supply parts 100 arranged adjacent to each other. The third resistor electrode 601 in the same second odd-mode resistor 60 is electrically connected to one of the power supply parts 100, and the fourth resistor electrode 602 is electrically connected to the other power supply part 100.

[0087] Specifically, the gate power supply electrode 302 and / or the drain power supply electrode 502 includes at least two independently arranged power supply parts 100, and two adjacent power supply parts 100 are independently arranged. That is to say, the gate power supply electrode 302 and / or the drain power supply electrode 502 is not a whole, but is arranged in a disconnected manner. In this way, the semiconductor device can be divided into at least two cell units, and the isolation degree between two adjacent cell units can be increased by increasing the disconnection distance between two adjacent power supply parts 100 arranged adjacent to each other.

[0088] As a feasible implementation manner, the gate power supply electrode 302 includes at least two independently arranged power supply sub - parts 100. There are two adjacent power supply sub - parts 100. The third resistance electrode 601 in the same second odd - mode resistor 60 is electrically connected to one of the power supply sub - parts 100, and the fourth resistance electrode 602 is electrically connected to the other power supply sub - part 100. Both the third resistance electrode 601 and the fourth resistance electrode 602 form ohmic contacts with the two - dimensional electron gas. Usually, the two - dimensional electron gas in the passive region bb will be consumed by means such as ion implantation. In the embodiment of the present invention, the second odd - mode resistor 60 is arranged in the passive region bb. By retaining the two - dimensional electron gas in the region where the second odd - mode resistor 60 is arranged in the passive region bb, thus the second odd - mode resistor 60 forms an ohmic contact with the two - dimensional electron gas. In addition, along the arrangement direction of the third resistance electrode 601 and the fourth resistance electrode 602, there is a two - dimensional electron gas conduction channel between the third resistance electrode 601 and the fourth resistance electrode 602, that is, the channel between the third resistance electrode 601 and the fourth resistance electrode 602 is conducting. Further, the third resistance electrode 601 is electrically connected to one of the power supply sub - parts 100, and the fourth resistance electrode 602 is electrically connected to the other power supply sub - part 100. In this way, the third resistance electrode 601 and the fourth resistance electrode 602 can be electrically connected to the power supply sub - part 100, that is, there is a second odd - mode resistor 60 between two adjacent power supply sub - parts 100. Furthermore, the energy of the odd - mode signal is consumed through the second odd - mode resistor 60, that is, the odd - mode oscillation in the feedback loop formed by the gate electrode 301 and the drain electrode 501 can be further suppressed, and thus the stability of the semiconductor device can be improved.

[0089] As another feasible implementation manner, the drain power supply electrode 502 includes at least two independently arranged power supply sub - parts 100. The third resistance electrode 601 in the same second odd - mode resistor 60 is electrically connected to one of the power supply sub - parts 100, and the fourth resistance electrode 602 is electrically connected to the other power supply sub - part 100. In this way, the third resistance electrode 601 and the fourth resistance electrode 602 can be electrically connected to the power supply sub - part 100, that is, there is a second odd - mode resistor 60 between two adjacent power supply sub - parts 100. Furthermore, the energy of the odd - mode signal is consumed through the second odd - mode resistor 60, that is, the odd - mode oscillation in the feedback loop formed by the gate electrode 301 and the drain electrode 501 can be further suppressed, and thus the stability of the semiconductor device can be improved.

[0090] It can be understood that Figure 5The shown drain power supply electrode 502 includes two independently arranged power supply sub - parts 100. The power supply sub - part 100 includes a power supply main body part 101 and at least one power supply finger part 102 electrically connected to the power supply main body part. Along the first direction Y, the power supply finger part 102 is located on one side of the power supply main body part 101, and the power supply finger part 102 extends along the first direction Y. The power supply finger parts 102 of two adjacent power supply sub - parts 100 arranged along the first direction Y are alternately arranged along the second direction X. The second direction Y is parallel to the plane of the substrate 10 and intersects with the first direction X. Exemplarily, the number of the power supply finger parts 102 can be at least two, so that at least two second odd - mode resistors 60 can be connected in parallel, and thus the diversity of the resistance values of the second odd - mode resistors 60 can be realized, so as to achieve different suppression effects and meet the requirements in various different scenarios.

[0091] As another feasible implementation manner, the gate power supply electrode 302 and the drain power supply electrode 502 include at least two independently arranged power supply sub - parts 100. That is to say, the second odd - mode resistors 60 are arranged in the power supply sub - parts 100 of both the drain power supply electrode 302 and the gate power supply electrode 302. In this way, on the one hand, the odd - mode oscillation in the feedback loop formed by the gate electrode 301 and the drain electrode 501 can be further suppressed, which can improve the stability of the semiconductor device. On the other hand, it is beneficial to realize the diversified setting of the semiconductor device.

[0092] It should be noted that Figure 5 Only the technical solution in which the semiconductor device includes two cell units is shown. It can be understood that the semiconductor device can also include three or more cell units. In addition, the number of gate electrodes in each cell unit can be the same or different, and the embodiments of the present invention do not specifically limit the number of gate electrodes in each cell unit.

[0093] It should be understood that from the perspective of semiconductor device design, the embodiments of the present invention can suppress odd-mode oscillation by setting an odd-mode resistor, thereby improving the stability of semiconductor devices. Semiconductor devices include but are not limited to: high-power high-electron mobility transistors operating in high-voltage and high-current environments, transistors with a Silicon-On-Insulator (SOI) structure, gallium arsenide (GaAs)-based transistors, and Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), Metal-Semiconductor Field-Effect Transistors (MISFETs), Double Heterojunction Field-Effect Transistors (DHFETs), Junction Field-Effect Transistors (JFETs), Metal-Semiconductor Field-Effect Transistors (MESFETs), Metal-Semiconductor Heterojunction Field-Effect Transistors (MISHFETs), or other field-effect transistors. The odd-mode resistors provided in the semiconductor devices according to the embodiments of the present invention can be widely used in the manufacturing fields of semiconductor devices such as radio frequency microwave and power electronics. In particular, for gallium nitride electronic devices with a large bandgap, high electron mobility, high breakdown field strength, and good thermal conductivity, the advantages are more obvious, and they can better meet the high-performance requirements of rapidly developing fields such as electronic communication.

[0094] Based on the same inventive concept, the embodiments of the present invention also provide a method for manufacturing a semiconductor device. Figure 6 As a schematic flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention, as Figure 6 shown, the method for manufacturing the semiconductor device includes:

[0095] S101. Provide a substrate and prepare an epitaxial structure on one side of the substrate; a two-dimensional electron gas is formed in the epitaxial structure.

[0096] Specifically, a heterojunction structure is included between the channel layer and the barrier layer of the epitaxial structure, and the heterojunction structure can be a two-dimensional electron gas.

[0097] S102. Prepare a first odd-mode resistor and a gate electrode structure on the side of the epitaxial structure away from the substrate; the first odd-mode resistor includes a first resistor electrode and a second resistor electrode. Both the first resistor electrode and the second resistor electrode form ohmic contacts with the two-dimensional electron gas, and along the arrangement direction of the first resistor electrode and the second resistor electrode, there is a two-dimensional electron gas conduction channel between the first resistor electrode and the second resistor electrode; the gate electrode structure includes a gate electrode and a gate power supply electrode, and the gate electrode and the gate power supply electrode are independently arranged; and for the independently arranged gate electrode and gate power supply electrode, the first resistor electrode in the same first odd-mode resistor is electrically connected to at least one gate electrode, and the second resistor electrode is electrically connected to the gate power supply electrode.

[0098] Specifically, continue to refer to Figure 1 and Figure 2 , prepare a first odd-mode resistor 40 and a gate electrode structure 30 on the side of the epitaxial structure 20 away from the substrate 10. The gate electrode structure 30 can be understood as a gate electrode 301 and a gate power supply electrode 302. The gate electrode 301 and the gate power supply electrode 302 are independently arranged, that is, the gate electrode 301 and the gate power supply electrode 302 are not in electrical contact, but there is a gap between them.

[0099] Optionally, when the odd-mode resistor 40 is arranged in the passive region bb, the following steps are further included:

[0100] Before preparing the electrode structure, first eliminate the two-dimensional electron gas in the passive region while retaining the two-dimensional electron gas in the odd-mode resistor region.

[0101] Generally, the two-dimensional electron gas in the passive region bb will be completely consumed by ion implantation or other methods after the epitaxial structure is formed. In the embodiment of the present invention, when the odd-mode resistor 40 is arranged in the passive region bb, it is necessary to retain the two-dimensional electron gas in the region of the odd-mode resistor 40 in the passive region bb, so that the odd-mode resistor 40 forms an ohmic contact with the two-dimensional electron gas.

[0102] Specifically, the first odd-mode resistor 40 includes a first resistor electrode 401 and a second resistor electrode 402. Both the first resistor electrode 401 and the second resistor electrode 402 form ohmic contacts with the two-dimensional electron gas. Usually, the two-dimensional electron gas in the passive region bb is consumed by means such as ion implantation. In the embodiment of the present invention, the odd-mode resistor 40 is arranged in the passive region bb, and the two-dimensional electron gas in the region where the odd-mode resistor 40 is arranged in the passive region bb is retained, so that the odd-mode resistor 40 forms an ohmic contact with the two-dimensional electron gas. In the embodiment of the present invention, both the gate electrode 301 and the gate power supply electrode 302 are in zero contact with the two-dimensional electron gas in the region of the odd-mode resistor 40, that is, when preparing the gate electrode 301 and the gate power supply electrode 302, the first resistor electrode 401 and the second resistor electrode 402 cannot be completely wrapped, and at least two adjacent side surfaces of the first resistor electrode 401 and the second resistor electrode 402 are exposed. Further, along the arrangement direction of the first resistor electrode 401 and the second resistor electrode 402, there is a two-dimensional electron gas conduction channel between the first resistor electrode 401 and the second resistor electrode 402, so that the first resistor electrode 401 and the second resistor electrode 402 can conduct through the channel. For the independently arranged gate electrode 301 and gate power supply electrode 302, the first resistor electrode 401 in the same first odd-mode resistor 40 is electrically connected to at least one gate electrode 301, and the second resistor electrode 402 is electrically connected to the gate power supply electrode 302. In this way, by electrically connecting the first resistor electrode 401 and the second resistor electrode 402 to the gate electrode 301 and the gate power supply electrode 302 respectively, that is, a first odd-mode resistor 40 is arranged between the gate electrode 301 and the gate power supply electrode 302, and then the energy of the odd-mode signal is consumed through the first odd-mode resistor 40, that is, the odd-mode oscillation is suppressed, and the stability of the semiconductor device can be improved.

[0103] In the manufacturing method of the semiconductor device provided by the embodiment of the present invention, the gate electrode and the gate power supply electrode are independently arranged. By setting the first odd-mode resistor, the first resistor electrode in the same first odd-mode resistor is electrically connected to at least one gate electrode, and the second resistor electrode is electrically connected to the gate power supply electrode. In this way, the energy of the odd-mode signal can be dissipated through the first odd-mode resistor, the generation of the odd-mode oscillation can be suppressed, and further the stability of the semiconductor device can be improved.

[0104] Optionally, Figure 7 is a schematic flowchart of another manufacturing method of the semiconductor device provided by the embodiment of the present invention. Figure 7 On the basis of the above embodiment, the specific operation of preparing the first odd-mode resistor and the gate electrode structure on the side of the epitaxial structure away from the substrate is elaborated in detail, as Figure 7 shown, the manufacturing method of the semiconductor device includes:

[0105] S201. Provide a substrate and prepare an epitaxial structure on one side of the substrate; a two-dimensional electron gas is formed in the epitaxial structure.

[0106] S202. Using the same mask process, prepare a first resistance electrode, a second resistance electrode, and an ohmic electrode on the side of the epitaxial structure away from the substrate; both the first resistance electrode and the second resistance electrode form ohmic contacts with the two-dimensional electron gas, and along the arrangement direction of the first resistance electrode and the second resistance electrode, there is a two-dimensional electron gas conduction channel between the first resistance electrode and the second resistance electrode.

[0107] Specifically, continue to refer to Figure 1 and Figure 2 , the electrodes of the semiconductor device of the present invention may include an ohmic electrode and a Schottky electrode, and the ohmic electrode includes a source electrode 101 and / or a drain electrode 501. In this embodiment, taking the drain electrode 501 as an example, the first resistance electrode 401, the second resistance electrode 402, and the drain electrode 501 are prepared by using the same mask process, that is, the resistance electrodes in the first odd-mode resistor 40 are all arranged in the ohmic contact metal layer. In this way, on the one hand, it can ensure that the first resistance electrode 401, the second resistance electrode 402, and the drain electrode 501 are set in the same layer and the same process, and while ensuring a good ohmic contact effect between the resistance electrode and the two-dimensional electron gas, the thinning of the semiconductor device can be realized. On the other hand, the process flow can be simplified.

[0108] S203. Prepare a gate electrode in the area outside the ohmic electrode, and the gate electrode is in electrical connection with the first resistance electrode.

[0109] Specifically, continue to refer to Figure 1 and Figure 2 , in the active region aa, the semiconductor device includes a source electrode 101 belonging to the ohmic electrode, a drain electrode 501, and a gate electrode 301 belonging to the Schottky electrode; the gate electrode 301 is in electrical connection with the first resistance electrode 401, so that an ohmic contact connection is formed with the two-dimensional electron gas through the first resistance electrode 401.

[0110] S204. Prepare a gate power supply electrode, and the gate power supply electrode is in electrical connection with the gate electrode and in electrical connection with the second resistance electrode.

[0111] Specifically, continue to refer to Figure 1 and Figure 2 , the gate power supply electrode 302 is in electrical connection with the gate electrode 301 and in electrical connection with the second resistance electrode 402. That is to say, an ohmic contact connection is formed with the two-dimensional electron gas through the second resistance electrode 402. At the same time, both the gate power supply electrode 302 and the gate electrode 301 are in electrical connection with the second resistance electrode 402. In this way, the first resistance electrode 401 and the second resistance electrode 402 can form the first odd-mode resistor 40, thereby suppressing the odd-mode oscillation and improving the stability of the semiconductor device.

[0112] The manufacturing method of the semiconductor device provided by the embodiment of the present invention can, by adopting the same masking process, fabricate a first resistance electrode, a second resistance electrode, and an ohmic electrode on the side of the epitaxial structure away from the substrate, ensuring that the first resistance electrode, the second resistance electrode, and the source electrode 101 or the drain electrode 501 of the ohmic electrode are arranged on the same layer. While ensuring a good ohmic contact effect between the resistance electrode and the two-dimensional electron gas, the semiconductor device can be made thinner, and on the other hand, the process flow can be simplified.

[0113] Note that the above is only the preferred embodiment of the present invention and the applied technical principle. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; An epitaxial structure located on one side of the substrate; A two-dimensional electron gas is provided in the epitaxial structure; A gate electrode structure located on the side of the epitaxial structure away from the substrate, the gate electrode structure includes a gate electrode and a gate power supply electrode, and there is a case where the gate electrode and the gate power supply electrode are independently provided; A first odd-mode resistor includes a first resistor electrode and a second resistor electrode, both the first resistor electrode and the second resistor electrode form an ohmic contact with the two-dimensional electron gas, and along the arrangement direction of the first resistor electrode and the second resistor electrode, there is a two-dimensional electron gas conductive channel between the first resistor electrode and the second resistor electrode; For the independently provided gate electrode and the gate power supply electrode, the first resistor electrode in the same first odd-mode resistor is electrically connected to at least one of the gate electrodes, and the second resistor electrode is electrically connected to the gate power supply electrode.

2. The semiconductor device according to claim 1, wherein The semiconductor device includes a plurality of the gate electrodes, any one of the gate electrodes is independently provided with the gate power supply electrode, and the first odd-mode resistor is provided between any one of the gate electrodes and the gate power supply electrode.

3. The semiconductor device according to claim 1, wherein, The semiconductor device includes a plurality of the gate electrodes, the plurality of gate electrodes extend along a first direction and are arranged along a second direction; the first direction and the second direction intersect and are both parallel to the plane where the substrate is located; For the independently provided gate electrode and the gate power supply electrode, the first resistor electrode in the same first odd-mode resistor is electrically connected to at least two of the gate electrodes adjacent to each other along the second direction, and the second resistor electrode is electrically connected to the gate power supply electrode.

4. The semiconductor device according to claim 3, wherein The semiconductor device further includes a source electrode, along the second direction, the source electrode is located between two adjacent gate electrodes; For the independently provided gate electrode and the gate power supply electrode, the first resistor electrode in the same first odd-mode resistor is electrically connected to two gate electrodes adjacent to the source electrode, and the second resistor electrode is electrically connected to the gate power supply electrode.

5. The semiconductor device according to claim 2 or 3, characterized in that, The plurality of gate electrodes extend along a first direction and are arranged along a second direction, and any two adjacent gate electrodes along the second direction are symmetrically arranged with respect to a symmetry axis; the symmetry axis extends along the first direction; the first direction and the second direction intersect and are both parallel to the plane where the substrate is located; The first odd-mode resistor electrically connected to the two symmetrically arranged gate electrodes is symmetrically arranged with respect to the symmetry axis.

6. The semiconductor device according to claim 1, wherein The gate electrode includes a connected gate main body portion and a gate tail portion, the gate tail portion is located on the side of the gate main body portion close to the gate power supply electrode, and along the second direction, the extension width of the gate tail portion is greater than the extension width of the gate main body portion; the second direction intersects with the extension direction of the gate electrode; The first resistor electrode is electrically connected to the gate tail portion, and a part of the two-dimensional electron gas is reserved in the semiconductor structure at the position corresponding to the gate tail portion.

7. The semiconductor device according to claim 1, characterized in that, The gate power supply electrode includes a connected power supply main body portion and a power supply protruding portion, and the power supply protruding portion is located on a side of the power supply main body portion close to the gate electrode; The second resistance electrode is electrically connected to the power supply protruding portion.

8. The semiconductor device according to claim 1, characterized in that, In the same first odd-mode resistor, the first resistance electrode and the second resistance electrode are arranged along a first direction and extend along a second direction; the first direction and the second direction intersect and are both parallel to the plane where the substrate is located, and the first direction is parallel to the extending direction of the gate electrode.

9. The semiconductor device according to claim 1, wherein In the same first odd-mode resistor, the distance between the first resistance electrode and the second resistance electrode is d, and the extending lengths of the first resistance electrode and the second resistance electrode are both w; The contact resistance between the first resistance electrode and the gate electrode is Rc1, the connection resistances between the second resistance electrode and the gate power supply electrode are both Rc2, and the sheet resistance of the two-dimensional electron gas is Rsh; 10. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes an ohmic electrode; The first resistance electrode and the second resistance electrode are both arranged in the same layer as the ohmic electrode, and the first resistance electrode is in contact electrical connection with the gate electrode, and the second resistance electrode is in contact electrical connection with the gate power supply electrode.

11. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes an ohmic electrode structure, and the ohmic electrode structure includes a connected ohmic electrode and an ohmic power supply electrode; The gate power supply electrode and / or the ohmic power supply electrode includes at least two independently arranged power supply sub-portions; The semiconductor device further includes a second odd-mode resistor, and the second odd-mode resistor includes a third resistance electrode and a fourth resistance electrode. The third resistance electrode and the fourth resistance electrode both form ohmic contacts with the two-dimensional electron gas, and there is a two-dimensional electron gas conduction channel between the third resistance electrode and the fourth resistance electrode along the arrangement direction of the third resistance electrode and the fourth resistance electrode; There are two adjacent power supply sub-portions. The third resistance electrode in the same second odd-mode resistor is electrically connected to one of the power supply sub-portions, and the fourth resistance electrode is electrically connected to the other power supply sub-portions.

12. A method for manufacturing a semiconductor device, characterized in that, Including: Providing a substrate and preparing an epitaxial structure on one side of the substrate; a two-dimensional electron gas is formed in the epitaxial structure; Preparing a first odd-mode resistor and a gate electrode structure on a side of the epitaxial structure away from the substrate; the first odd-mode resistor includes a first resistance electrode and a second resistance electrode. The first resistance electrode and the second resistance electrode both form ohmic contacts with the two-dimensional electron gas, and there is a two-dimensional electron gas conduction channel between the first resistance electrode and the second resistance electrode along the arrangement direction of the first resistance electrode and the second resistance electrode; The gate electrode structure includes a gate electrode and a gate power supply electrode, and the gate electrode and the gate power supply electrode are independently arranged; and for the independently arranged gate electrode and gate power supply electrode, the first resistance electrode in the same first odd-mode resistor is electrically connected to at least one of the gate electrodes, and the second resistance electrode is electrically connected to the gate power supply electrode.

13. The preparation method according to claim 12, characterized in that, Fabricate a first odd-mode resistor and a gate electrode structure on the side of the epitaxial structure away from the substrate, including: Using the same mask process, fabricate a first resistor electrode, a second resistor electrode, and an ohmic electrode on the side of the epitaxial structure away from the substrate; Fabricate a gate electrode in the region outside the ohmic electrode, and the gate electrode is in electrical contact with the first resistor electrode; Fabricate a gate power supply electrode, and the gate power supply electrode is in electrical contact with the gate electrode and is also in electrical contact with the second resistor electrode.

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