Liquid crystal on silicon display device with stacked integrated circuit substrates

Abstract

An example liquid crystal display device includes a reflective display backplane and one or more integrated circuit substrates arranged in a stacked configuration. The reflective display backplane includes an array of reflective pixel mirrors and a corresponding array of data latches. A top surface of an integrated circuit substrate is connected to a back surface of the reflective display backplane and is configured as a display driver, and a set of through-silicon vias is used to provide control signals to the reflective display backplane. Optionally, another integrated circuit substrate (front-to-back) is connected to the one integrated circuit substrate and is configured to provide virtual reality, augmented reality, and / or other video processing support to the display driver. Exemplary embodiments are provided with a chip scale package structure formed on a stacked bottom integrated circuit substrate.

Description

Technical Field

[0001] The present invention generally relates to a display device, and more particularly to a liquid crystal on silicon (LCoS) display device. Background Art

[0002] Liquid crystal on silicon (LCoS) display devices are currently incorporated into various host devices, including but not limited to augmented reality (AR) glasses, virtual reality (VR) glasses, automotive applications, etc.

[0003] In such applications, it is important for an LCoS display device to be designed with a high form factor to relax the design constraints imposed on the host device by the module. For example, in AR and VR glasses applications, such LCoS display devices are typically designed to be as small as possible to minimize the space occupied by the module on the host glasses. To maximize the runtime between charges in a battery-powered host device, it is also important for the LCoS display device to consume as little power as possible during operation.

[0004] Current LCoS display devices typically have a poor form factor and high power consumption, inadvertently imposing undesirable design constraints and low performance characteristics on the host device.

[0005] Therefore, what is needed is an LCoS display device with an improved form factor and reduced power consumption during operation. Summary of the Invention

[0006] The present invention overcomes problems associated with the prior art by providing a liquid crystal on silicon (LCoS) display device that has a smaller size and footprint than prior art LCoS devices. Exemplary embodiments of the present invention demonstrate more efficient energy use by combining circuit substrates having different voltage requirements and synergistic functionality in a stacked relationship.

[0007] An integrated circuit substrate (or simply a circuit substrate) is formed by doping regions of a semiconductor substrate (e.g., a silicon wafer, a bulk substrate) to form semiconductor devices (e.g., diodes, transistors, etc.), and forming a metal interconnect layer on the semiconductor substrate to interconnect the semiconductor devices to form a circuit. Thus, the circuit substrate includes the semiconductor substrate and the circuit formed in and on the semiconductor substrate. In certain embodiments, the semiconductor substrate may correspond to one or more epitaxially grown semiconductor layers (e.g., P-type or N-type doped silicon) formed on a carrier wafer, where the carrier layer may be removed during the manufacturing process (e.g., during chemical mechanical polishing).

[0008] An exemplary liquid crystal display device includes: a first circuit substrate, a second circuit substrate, and a first set of conductive vias. The first circuit substrate has a first surface, a second surface opposite the first surface, and a first set of integrated circuits. The first set of integrated circuits is formed in and on the second surface of the first circuit substrate and includes a first set of metal interconnect layers. The first circuit substrate further includes an array of conductive pixel mirrors, the array of conductive pixel mirrors being formed above the first set of metal interconnect layers and being electrically coupled via the first set of metal interconnect layers to the circuits of the first set of integrated circuits. The second circuit substrate has a first surface; a second surface opposite the first surface; and a second set of integrated circuits, the second set of integrated circuits being formed in and on the second surface of the second circuit substrate. The second set of integrated circuits includes a second set of metal interconnect layers. The first set of conductive vias passes through the first circuit substrate and electrically connects the first set of metal interconnect layers to the second set of metal interconnect layers.

[0009] The exemplary liquid crystal display device may further include: a liquid crystal material layer and a transparent electrode. The liquid crystal material layer is disposed above the array of conductive pixel mirrors. The transparent electrode is disposed above the liquid crystal material layer.

[0010] In a particular exemplary liquid crystal display device, the first set of metal interconnect layers includes at least one bondpad. The (one or more) bondpads are exposed on the first surface of the first circuit substrate. The (one or more) bondpads facilitate electrical connection to the first set of metal interconnect layers.

[0011] Alternatively, other exemplary liquid crystal display devices may include: a chip-scale package structure and a second set of conductive vias. The chip-scale package (CSP) structure may have a first surface and a second surface opposite the first surface. The CSP structure may include a first set of contacts formed on the first surface of the CSP structure and a second set of contacts formed on the second surface of the CSP structure. The conductive vias of the second set of conductive vias pass through the second circuit substrate and electrically connect the second set of metal interconnect layers to the first set of contacts of the CSP structure.

[0012] Another exemplary liquid crystal display device further includes: a third circuit substrate and a second set of conductive vias. The third circuit substrate has a first surface, a second surface opposite the first surface, and a third integrated circuit, the third integrated circuit being formed in and on the second surface of the third circuit substrate. The third set of integrated circuits includes a third set of metal interconnect layers. The conductive vias of the second set of conductive vias pass through the second circuit substrate and electrically connect the second set of metal interconnect layers to the third set of metal interconnect layers.

[0013] The exemplary liquid crystal display device may further include: a chip scale package (CSP) structure and a third set of conductive vias. The CSP structure has a first surface and a second surface opposite to the first surface. The CSP structure may include: a first set of contacts formed on the first surface of the CSP structure and a second set of contacts formed on the second surface of the CSP structure. The third set of conductive vias passes through the third circuit board and electrically connects the third set of metal interconnect layers to the first set of contacts of the CSP structure.

[0014] In the exemplary liquid crystal display device, the first circuit board may be a reflective display backplane including a data input and a control signal input. The second set of integrated circuits may include a video data buffer and a control signal generator. The control signal generator may be configured to generate a control signal based on the data stored in the data buffer and provide the control signal to the control signal input of the reflective display backplane. The third set of integrated circuits may include a video processing circuit. As an optional, non-limiting example, the video processing circuit may include a circuit configured to receive video data in a first format and further include a circuit configured to convert the video data in the first format into video data in a second format.

[0015] In another exemplary liquid crystal display device, the first set of integrated circuits may include a plurality of pixel latches. Each pixel latch in the array of pixel latches may be electrically coupled to an associated conductive pixel mirror in the conductive pixel mirrors. The second set of integrated circuits may include a frame buffer configured to store at least one frame of pixel data. Optionally, the frame buffer may have a capacity sufficient to store multiple frames of pixel data (e.g., ping-pong frame buffer, dual frame buffer, triple frame buffer, etc.).

[0016] In another exemplary liquid crystal display device, the first set of integrated circuits may operate at a first voltage. The second set of integrated circuits may operate at a second voltage different from the first voltage. The first voltage may be higher than the second voltage. The exemplary liquid crystal display device may further include an interface circuit, and digital video data may be transmitted from the second set of integrated circuits operating at the second voltage to the first set of integrated circuits operating at the first voltage through the interface circuit.

[0017] In another exemplary liquid crystal display device, the first circuit board and the second circuit board may be fabricated or processed at different technology nodes to save costs. The second circuit board is fabricated or processed at a second technology node, and the first circuit board may be processed at a first technology node that is not as advanced as the second technology node. For example, the first circuit board may be processed at a technology node of at least 65 nm. The second circuit board may be processed at a technology node of 28 nm or less. In a specific exemplary liquid crystal display device, the first circuit board may have a technology node of at least 130 nm. The second circuit board may have a technology node of 22 nm or less.

[0018] In a particular example liquid crystal display device, the second set of integrated circuits may include a display driver circuit. The display driver circuit may include a control circuit and a memory. The control circuit may be configured to generate control signals based on video data stored in the memory, the control signals being defined to drive an array of conductive pixel mirrors of a first circuit substrate.

[0019] Certain example liquid crystal display devices further include: a liquid crystal material layer and dams. The liquid crystal layer is disposed above the pixel mirrors, and the dams surround and contain the liquid crystal layer. The first set of integrated circuits, the first set of metal interconnect layers, the second set of integrated circuits, and the second set of metal interconnect layers are all included within a space defined by a perimeter of the dams projected along an axis perpendicular to a first surface of the first circuit substrate. In other words, all of the circuits of the liquid crystal display device are disposed below and within an occupied area of the liquid crystal display layer elements.

[0020] Another example liquid crystal display device includes: a first circuit substrate, a liquid crystal layer, a transparent electrode, and a second circuit substrate. The first circuit substrate has: a top surface; an opposite bottom surface; an array of pixel mirrors formed on the top surface; a first set of integrated circuits configured to apply pixel data to the pixel mirrors; and a plurality of electrical contacts formed on the bottom surface. The electrical contacts are connected to the first set of integrated circuits. The liquid crystal layer is disposed above the pixel mirrors, and the transparent electrode is disposed above the liquid crystal layer.

[0021] The second circuit substrate includes: a top surface; a bottom surface opposite the top surface; a second set of electrical contacts formed on the top surface; and a second set of integrated circuits electrically coupled to the second set of electrical contacts. The second set of integrated circuits includes, but is not limited to, a frame buffer configured to store digital video data and a control circuit configured to generate control signals based at least in part on the digital video data. The electrical contacts of the first set are firmly connected to the electrical contacts of the second set, thereby providing a mechanical bond between the first circuit substrate and the second circuit substrate and providing an electrical connection for transferring the control signals from the second set of integrated circuits to the first set of integrated circuits.

[0022] An example method of manufacturing a liquid crystal display device is also disclosed. The example method includes: providing a reflective display backplane including an array of pixel mirrors and forming vias through the reflective display backplane. The example method further includes: providing one or more circuit substrates, forming vias in the one or more circuit substrates, and assembling the reflective display backplane and the one or more circuit substrates in a stacked relationship with the reflective display backplane on top. The circuits of the reflective display backplane are electrically connected to the one or more integrated circuit substrates through the vias. A chip-scale package may be formed on one of the circuit substrates located at the bottom. The example method further includes: assembling liquid crystal display elements above the array of pixel mirrors. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be described with reference to the following drawings, in which like reference numerals generally represent like elements.

[0024] Figure 1 is a perspective view of a pair of augmented reality (AR) glasses equipped with a projection system including an LCoS display device (not shown);

[0025] Figure 2 is a perspective view of a virtual reality (VR) goggle equipped with a projection system including an LCoS display device (not shown);

[0026] Figure 3 is a cross-sectional view of a first exemplary LCoS display device, which may be included, for example, in the projection systems of Figure 1 and Figure 2 ;

[0027] Figure 4A Shows the first step in a first exemplary method of manufacturing an LCoS display device Figure 3 ;

[0028] Figure 4B Shows the second step in a first exemplary method of manufacturing an LCoS display device Figure 3 ;

[0029] Figure 4C Shows the third step in a first exemplary method of manufacturing an LCoS display device Figure 3 ;

[0030] Figure 4D Shows the fourth step in a first exemplary method of manufacturing an LCoS display device Figure 3 ;

[0031] Figure 4E Shows the fifth step in a first exemplary method of manufacturing an LCoS display device Figure 3 ;

[0032] Figure 4F Shows the sixth step in a first exemplary method of manufacturing an LCoS display device Figure 3 ;

[0033] Figure 4G Shows the seventh step in a first exemplary method of manufacturing an LCoS display device Figure 3 ;

[0034] Figure 4H Shows the eighth step in a first exemplary method of manufacturing an LCoS display device Figure 3 ;

[0035] Figure 5A Display manufacturing Figure 3 The first step in the second exemplary method of an LCoS display device;

[0036] Figure 5B Display manufacturing Figure 3 The second step in the second exemplary method of an LCoS display device;

[0037] Figure 5C Display manufacturing Figure 3 The third step in the second exemplary method of an LCoS display device;

[0038] Figure 5D Display manufacturing Figure 3 The fourth step in the second exemplary method of an LCoS display device;

[0039] Figure 5E Display manufacturing Figure 3 The fifth step in the second exemplary method of an LCoS display device;

[0040] Figure 5F Display manufacturing Figure 3 The sixth step in the second exemplary method of an LCoS display device;

[0041] Figure 5G Display manufacturing Figure 3 The seventh step in the second exemplary method of an LCoS display device;

[0042] Figure 5H Display manufacturing Figure 3 The eighth step in the second exemplary method of an LCoS display device;

[0043] Figure 6 Is a cross-sectional view of a second exemplary LCoS display device, which display device may for example be included in a Figure 1 and Figure 2 projection system;

[0044] Figure 7A Display manufacturing Figure 6 The first step in the exemplary method of a second exemplary LCoS display device;

[0045] Figure 7B Display manufacturing Figure 6 The second step in the exemplary method of a second exemplary LCoS display device;

[0046] Figure 7C Display manufacturing Figure 6 The third step in the exemplary method of a second exemplary LCoS display device;

[0047] Figure 7D Display manufacturingFigure 6 The fourth step in the exemplary method of the second exemplary LCoS display device;

[0048] Figure 7E Display manufacturing Figure 6 The fifth step in the exemplary method of the second exemplary LCoS display device;

[0049] Figure 7F Display manufacturing Figure 6 The sixth step in the exemplary method of the second exemplary LCoS display device;

[0050] Figure 8 is a cross-sectional view of a third exemplary LCoS display device, which may include, for example, in Figure 1 and Figure 2 the projection system;

[0051] Figure 9A Display manufacturing Figure 8 The first step in the first exemplary method of the third exemplary LCoS display device;

[0052] Figure 9B Display manufacturing Figure 8 The second step in the first exemplary method of the third exemplary LCoS display device;

[0053] Figure 9C Display manufacturing Figure 8 The third step in the first exemplary method of the third exemplary LCoS display device;

[0054] Figure 9D Display manufacturing Figure 8 The fourth step in the first exemplary method of the third exemplary LCoS display device;

[0055] Figure 9E Display manufacturing Figure 8 The fifth step in the first exemplary method of the third exemplary LCoS display device;

[0056] Figure 9F Display manufacturing Figure 8 The sixth step in the first exemplary method of the third exemplary LCoS display device;

[0057] Figure 9G Display manufacturing Figure 8 The seventh step in the first exemplary method of the third exemplary LCoS display device;

[0058] Figure 9H Display manufacturing Figure 8 The eighth step in the first exemplary method of the third exemplary LCoS display device;

[0059] Figure 9I Display manufacturing Figure 8 The ninth step in the first exemplary method of the third exemplary LCoS display device for display manufacturing;

[0060] Figure 9J Display manufacturing Figure 8 The tenth step in the first exemplary method of the third exemplary LCoS display device for display manufacturing;

[0061] Figure 9K Display manufacturing Figure 8 The eleventh step in the first exemplary method of the third exemplary LCoS display device for display manufacturing;

[0062] Figure 10A Display manufacturing Figure 8 The first step in the second exemplary method of the third exemplary LCoS display device for display manufacturing;

[0063] Figure 10B Display manufacturing Figure 8 The second step in the second exemplary method of the third exemplary LCoS display device for display manufacturing;

[0064] Figure 10C Display manufacturing Figure 8 The third step in the second exemplary method of the third exemplary LCoS display device for display manufacturing;

[0065] Figure 10D Display manufacturing Figure 8 The fourth step in the second exemplary method of the third exemplary LCoS display device for display manufacturing;

[0066] Figure 10E Display manufacturing Figure 8 The fifth step in the second exemplary method of the third exemplary LCoS display device for display manufacturing;

[0067] Figure 10F Display manufacturing Figure 8 The sixth step in the second exemplary method of the third exemplary LCoS display device for display manufacturing;

[0068] Figure 10G Display manufacturing Figure 8 The seventh step in the second exemplary method of the third exemplary LCoS display device for display manufacturing;

[0069] Figure 10H Display manufacturing Figure 8 The eighth step in the second exemplary method of the third exemplary LCoS display device for display manufacturing;

[0070] Figure 10I Display manufacturing Figure 8 The ninth step in the second exemplary method of the third exemplary LCoS display device for display manufacturing;

[0071] Figure 10J Display manufacturing Figure 8 The tenth step in the second example method of the third example LCoS display device shown;

[0072] Figure 11 is a flowchart outlining an example method of manufacturing an LCoS display device, which display device can for example be included in a Figure 1 and Figure 2 projection system;

[0073] Figure 12A is an outline of Figure 11 the example method of performing step 1112 in the method of;

[0074] Figure 12B is an outline of Figure 11 another example method of performing step 1112 in the method of; and

[0075] Figure 12C is an outline of Figure 11 yet another example method of performing step 1112 in the method of. DETAILED DESCRIPTION

[0076] The present invention overcomes problems associated with the prior art by providing an LCoS display device that includes a plurality of stacked circuit substrate layers, the circuit substrate layers having semiconductor circuit layers and metal interconnect layers formed therein or thereon. The present invention also provides a method of manufacturing an LCoS display device. In the following description, numerous specific details (e.g., circuit configurations, number of stacked layers, electrical bonding techniques, etc.) are set forth in order to provide a thorough understanding of the present invention. However, those skilled in the art will understand that the present invention may be practiced without these specific details. In other instances, well-known electronics manufacturing practices (e.g., wire bonding, semiconductor doping, etching, back grinding, etc.) and details of components are omitted so as not to unnecessarily obscure the present invention.

[0077] For ease of description, spatial relative terms may be used herein, such as "below", "under", "above", "beneath", "on", "over", "top", "bottom", "left", "right", "center", "middle", etc., to describe the relationship between one element or feature shown in the drawings relative to other elements or features. It should be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation other than the orientation shown in the drawings. For example, if the device in the drawings is rotated or flipped, an element described as "under" or "beneath" or "below" another element or feature will be oriented "above" or "over" that other element or feature. Thus, the exemplary terms "under" and "beneath" can cover both the upper and lower orientations. The device may also be in other orientations (e.g., rotated 90 degrees or other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. In addition, it should be understood that when an element is described as being "between" two other elements, it may be the only element between the two elements, or there may be one or more intermediate elements.

[0078] Figure 1 Representatively shown is a liquid crystal on silicon (LCoS) display device 100 included in a projection system 102. The projection system 102 is integrated with a host device, which is described by way of non-limiting example as a pair of augmented reality (AR) glasses 104. Specifically, the projection system 102 is fixed to the inner side of the temple 106 of the AR glasses 104. The projection system 102 projects an image directly onto the lens 108 of the AR glasses 104, and a person wearing the AR glasses 104 can see the image.

[0079] Figure 2 Another example host device is shown, which is described by way of non-limiting example as a pair of virtual reality (VR) goggles 200. The VR goggles 200 include an image system 202 that includes one or more display devices 100. The VR goggles 200 include various other electronic components (e.g., PCB, battery, etc.) (not shown) disposed in a housing 204. The VR goggles 200 also include a headband 206 and a head strap 208 for fixing the housing 204 above the eyes of a user's head.

[0080] The AR glasses 104 and the goggles 200 are intended to illustrate an example environment. However, the display device 100 can be incorporated into other environments, such as, for example, a head-up display (HUD) in an automotive application, a medical device, an optical instrument, etc.

[0081] Figure 3is a cross-sectional view of an LCoS display device 100, which includes: a display component 300, a first circuit board 302, a second circuit board 304, a first group of through-silicon vias (TSVs) 306 (first group of conductive vias), a second group of TSVs 308 (second group of conductive vias), and a chip-scale package (CSP) structure 310. The display component 300 is formed above the top surface 301 of the first circuit board 302. The opposite bottom surface 303 of the first circuit board 302 is joined to the top surface 305 of the second circuit board 304. The CSP structure 310 is coupled to the bottom surface 307 of the second circuit board 304. The first group of TSVs 306 electrically connects the circuits disposed on the second circuit board 304 to the circuits disposed on the first circuit board 302, and the second group of TSVs 308 electrically connects the circuits of the CSP structure 310 to the circuits of the second circuit board 304.

[0082] As will be described in more detail below, a TSV generally includes an opening formed through a silicon substrate. The opening itself is sometimes referred to as a via or a through hole, but a TSV also includes other structures. Specifically, a TSV generally includes: an insulating liner formed on the wall of the via, and a conductive core that connects the circuit on the top side of the silicon substrate to the circuit on the bottom side of the silicon substrate. The insulating liner provides insulation between the conductive core and the silicon substrate.

[0083] The display component 300 includes: a cover glass (transparent layer) 312, a transparent electrode 314, a first liquid crystal alignment layer 316, a liquid crystal layer 318, a second liquid crystal alignment layer 320, and a dam portion 322. The transparent electrode 314 is formed on the bottom surface of the cover glass 312, and, for example, the transparent electrode 314 is thin enough to be transparent and is a conductive material layer (e.g., indium tin oxide) that serves as a common electrode across the liquid crystal layer 318. The alignment layers 316 and 320 assist in the alignment of the liquid crystal molecules of the liquid crystal layer 318. The alignment layer 316 is formed on the bottom surface of the transparent electrode 314, and the alignment layer 320 is formed above the first circuit board 302. The alignment layers 316 and 320 can be formed of any suitable material, such as, for example, polyimide, SiO2, etc. The transparent electrode 314, the first liquid crystal alignment layer 316, the liquid crystal layer 318, the second liquid crystal alignment layer 320 are disposed or otherwise arranged between the cover glass 312 and the first circuit board 302. The dam portion 322 is disposed around the periphery of the liquid crystal layer 318 and serves as a gasket to encapsulate and hold the liquid crystal layer 318 between the alignment layers 316 and 320.

[0084] The first circuit board 302 includes an LCoS circuit configured to drive a plurality of pixel mirrors 324. The LCoS circuit includes various semiconductor circuit elements (i.e., latches, row / column decoders, line registers, transistors, etc.) (not shown) formed in and on a semiconductor material layer (e.g., in and on a silicon substrate 326). The various circuit elements formed in and on the silicon substrate 326 are electrically connected to each other and to the pixel mirrors 324 through a metal interconnect layer 328, which includes various conductive metal elements 330 and an electrically insulating material 332. In an embodiment, the metal interconnect layer 328 may include one or more metal layers embedded in the electrically insulating material 332, and the plurality of pixel mirrors 324 are formed by the topmost metal layer in the one or more metal layers. The pixel mirrors 324 are highly reflective electrodes (e.g., aluminum, silver-plated aluminum, etc.) formed in and on the top surface of the interconnect layer 328. The pixel mirrors 324 may be arranged in an array form.

[0085] As a non-limiting example, the second circuit board 304 includes, but is not limited to, an application specific integrated circuit (ASIC), which also includes various logic circuit elements (not shown) formed in and on a silicon substrate 334. In this example, the circuit of the second circuit board 304 will be configured as a display driver. Examples of such display driver circuits include, but are not limited to: timing circuits, display data conversion circuits, display data buffers, frame buffers, display control signal generators, etc. The various circuit elements formed in and on the silicon substrate 334 are electrically connected to each other through a metal interconnect layer 336, which includes a plurality of interconnect layers of various conductive metal elements 338 separated by an electrically insulating material 340. The top surface of the interconnect layer 336 is joined to the bottom surface of the silicon substrate 326 in a stacked configuration.

[0086] A first set of TSVs 306 is formed through the silicon substrate 326, which has a first dielectric liner layer (e.g., formed of an oxide-based material) and is filled with a conductive material (e.g., copper, aluminum, etc.) to electrically connect the interconnect layer 336 to the interconnect layer 328. The first dielectric liner layer insulates the conductive material from the silicon substrate 326. Similarly, a second set of TSVs 308 is formed through the silicon substrate 334, which has a second dielectric liner layer (e.g., formed of an oxide-based material), such as an insulating layer 341, and is filled with or lined with a conductive material (e.g., copper) to electrically connect the CSP structure 310 to the interconnect layer 336.

[0087] In this exemplary embodiment, the first circuit board 302 is an LCoS chip (e.g., a reflective display backplane) operating at a first voltage, while the second circuit board 304 is an ASIC chip operating at a second voltage, which is a different voltage lower than the first voltage. In particular, the voltage of the circuit driving the first circuit board 302 and of the plurality of pixel mirrors 324 included in the first circuit board 302 is higher than the voltage required for the logic circuit driving the second circuit board 304.

[0088] The first circuit board 302 and the second circuit board 304 may be fabricated at different technology nodes. The first circuit board 302 may be fabricated or processed at a node of 65 nm or 130 nm. The second circuit board 304 may use a node of 22 nm or 28 nm, such nodes being more advanced processing and integrated circuit formation technologies.

[0089] The CSP structure 310 is coupled to / formed on the bottom surface of the silicon substrate 334 and is configured to electrically connect the LCoS display device 100 to the circuitry of the host device. The CSP structure 310 includes: an insulating layer 341, a plurality of metal contacts (conductive structures) 342, a plurality of solder bumps 344, and an interposer layer 346 (e.g., a solder mask). The insulating layer 341 is deposited after a hole (or via) is formed through the silicon substrate 334 but before depositing a conductive material (e.g., metal) to form the second set of TSVs 308. The metal contacts 342 are electrically connected to the second set of TSVs 308, and the solder bumps 344 are electrically connected to the metal contacts 342. Further, the solder bumps 344 are configured to provide an electrical connection for an external signal path (e.g., a power connection, a control signal, or a data signal). For example, the solder bumps 344 are configured to be electrically connected to the contact pads of the host device by some suitable process (such as, for example, reflow soldering, ultrasonic bonding, etc.) to establish a signal connection. The interposer layer 346 is disposed around and between the metal contacts 342.

[0090] Even if not shown in the drawings, an insulating layer similar to the insulating layer 341 may be disposed between the first circuit board 302 and the second circuit board 304 and enter the holes (or vias) through the silicon substrate 326 to form the second set of TSVs 308.

[0091] A summary of the exemplary operation of the LCoS display device 100 is as follows. As Figure 3As shown, the incident light 348 is polarized in a first predetermined polarization state and enters through the top surface of the glass 312, passes through the layers 314, 316, 318, and 320, is reflected by a plurality of pixel mirrors 324, and then passes through the layers 320, 318, 316, 314, and 312 again in the opposite direction, and then leaves the LCoS display device 100. Depending on the electric field applied to the liquid crystal layer 318 (i.e., the voltage difference between the pixel mirror 324 and the transparent electrode 314), the polarization of the light is changed by the liquid crystal layer 318. When the transparent electrode 314 is maintained at a specific voltage, the electric field on the liquid crystal layer 318 is controlled by the voltage applied to the individual pixel mirrors 324. Therefore, the polarization of the incident light 348 undergoes spatial modulation according to the image signal applied to the pixel mirrors 324, and the incident light 348 is output as a spatially modulated light beam 350. The modulated light beam 350 is then analyzed by an analyzer (not shown) having a predetermined polarization state to generate a displayable image. Therefore, in response to a specific signal applied to each pixel mirror 324, the intensity of the light displayed by each pixel depends on the polarization imparted by the liquid crystals in the liquid crystal layer 318.

[0092] Figures 4A to 4H FIG. shows a first exemplary method of manufacturing the LCoS display device 100. As Figure 4A shown, the carrier wafer substrate 400, the first circuit substrate 302, and the second circuit substrate 304 are provided as separate elements. Then, as Figure 4B shown, the top surface 301 of the interconnect layer 328 of the first circuit substrate 302 is thermally bonded to the bottom surface 404 of the carrier wafer substrate 400. In the illustrated embodiment, the first circuit substrate 302 may be pre-treated to have one or more integrated circuits (e.g., including pixel latches) and a plurality of metal elements formed thereon. Similarly, the second circuit substrate 304 may be pre-treated to have one or more integrated circuits (e.g., including a display driver circuit and memory cells) formed thereon.

[0093] Next, as Figure 4C shown, first, material is removed from the bottom surface (also referred to as the back surface or rear surface) 303 of the silicon substrate 326 by some suitable method (such as, for example, back grinding, back lapping, chemical etching, etc.) to thin the silicon substrate 326. Once the silicon substrate 326 is thinned by a predetermined amount, a first set of TSVs 306 is formed through the silicon substrate 326. During the formation of the first set of TSVs 306, the TSVs 306 are electrically connected to specific metal elements 330, and the TSVs 306 are exposed on the bottom surface 303 of the silicon substrate 326.

[0094] Then, as Figure 4DAs shown, the top surface 305 of the interconnect layer 336 is bonded to the thinned bottom surface 303 of the silicon substrate 326. The bonding of the interconnect layer 336 to the silicon substrate 326 includes: the physical bonding of the interconnect layer 336 to the silicon substrate 326, and the electrical connection of the specific metal elements 338 of the interconnect layer 336 to the TSVs 306. Once the first circuit substrate 302 and the second circuit substrate 304 are electrically and physically bonded to each other, the carrier wafer 400 is removed from the interconnect layer 328 of the first circuit substrate 302.

[0095] Next, as Figure 4E shown, a pixel mirror 324 is formed on the top surface 301 of the interconnect layer 328 of the first circuit substrate 302. During the formation of the pixel mirror 324, each pixel mirror 324 is electrically connected to a specific one of the metal elements 338 of the interconnect layer 328, thereby providing a dedicated connection between each pixel mirror 324 and the corresponding circuit (such as a pixel latch circuit) of the silicon substrate 326.

[0096] Then, as Figure 4F shown, a display assembly 300 is formed on the top surface 301 of the interconnect layer 328, above the pixel mirrors 324. That is, an alignment layer 316 is formed on the bottom surface 410 of the cover glass 312. An alignment layer 320 is formed on the top surface 301 of the interconnect layer 328 and above the pixel mirrors 324. The alignment layers 316 and 320 are disposed between the cover glass 312 and the metal interconnect layer 328. The dam 322 is sandwiched between the bottom surface 410 of the cover glass 312 and the top surface 301 of the interconnect layer 328. A liquid crystal material is deposited in the space defined by the dam 322 and the alignment layers 316 and 320 to form a liquid crystal layer 318. The liquid crystal layer 318 is formed or otherwise disposed between the cover glass 312 and the silicon substrate 326.

[0097] Next, as Figure 4G shown, material is removed from the bottom surface 307 of the silicon substrate 334 by some suitable method (such as, for example, back grinding, back lapping, chemical etching, etc.) to thin the silicon substrate 334. Then, as Figure 4HAs shown, an insulating layer 341 is formed on the bottom surface 307 (e.g., via material deposition techniques), and TSVs 308 and the CSP structure 310 are formed. A second set of TSVs 308 is formed through the silicon substrate 334. In one example, a plurality of openings or trenches corresponding to the positions of the TSVs 308 are formed through the silicon substrate 334. After forming the openings (or trenches) through the silicon substrate 334 but before depositing the conductive material (e.g., a metal material such as copper or aluminum) of the second set of TSVs 308, an insulating layer 341 is deposited on the lining sidewall surfaces of the openings or trenches, such that the insulating layer 341 provides electrical insulation between the conductive material and the silicon substrate 334. During the formation of the second set of TSVs 308, the TSVs 308 are electrically connected to specific metal elements 338, and the TSVs 308 are exposed on the bottom surface of the insulating layer 341. The bottom surface of the insulating layer 341 may be the surface of the insulating layer 341 that is away from the bottom surface 307 of the silicon substrate 334. Subsequently, metal contacts 342 are formed and electrically connected to the second set of TSVs 308 to electrically connect to the corresponding metal elements 338, and solder bumps 344 are formed on the bottom surface 307 of the silicon substrate 334 to contact the metal contacts 342. An interlayer 346 (e.g., a solder mask) is disposed between and around the metal contacts 342. In an embodiment, the interlayer 346 may surround the metal contacts 342. The interlayer 346 may also be disposed to surround the solder bumps 344.

[0098] Figures 5A to 5H A second exemplary method of manufacturing the LCoS display device 100 is shown. Initially, as Figure 5A shown, the carrier wafer substrate 400, the first circuit substrate 302, and the second circuit substrate 304 are provided as separate elements. In this particular method, first, the first circuit substrate 302 is provided with the pixel mirrors 324 formed on the top surface 301 of the interconnect layer 328. Subsequently, as Figure 5B shown, the carrier wafer substrate 400 is bonded (e.g., thermally bonded) to the top surface 301 of the interconnect layer 328.

[0099] Next, as Figure 5C shown, first, material is removed from the bottom surface 303 of the silicon substrate 326 by some suitable method (such as, for example, back grinding, back lapping, chemical etching, etc.) to thin the silicon substrate 326. Once the silicon substrate 326 is thinned, a first set of TSVs 306 is formed through the silicon substrate 326. During the formation of the first set of TSVs 306, the TSVs 306 are electrically connected to specific metal elements 330, and the TSVs 306 are exposed on the bottom surface 303 of the silicon substrate 326.

[0100] Subsequently, as Figure 5DAs shown, the top surface 305 of the interconnect layer 336 is bonded to the thinned bottom surface 303 of the silicon substrate 326. The bonding of the interconnect layer 336 of the second circuit substrate 304 to the silicon substrate 326 of the first circuit substrate 302 includes: physical bonding of the interconnect layer 336 to the silicon substrate 326, and electrical connection of the metal elements 338 of the interconnect layer 336 to the TSVs 306.

[0101] Next, as Figure 5E shown, the silicon substrate 334 is thinned, an insulating layer 341 is formed, a second set of TSVs 308 is formed, and the remainder of the CSP structure 310 is formed on the bottom surface of the silicon substrate 334. Material is removed from the bottom surface 307 of the silicon substrate 334 by some suitable method (such as, for example, back grinding, back lapping, chemical etching, etc.) to thin the silicon substrate 334. A second set of TSVs 308 is formed through the silicon substrate 334. In one example, a plurality of openings or trenches corresponding to the positions of the TSVs 308 are formed through the silicon substrate 334 or formed on the silicon substrate 334. After the openings are formed through the silicon substrate 334 and before depositing the conductive material (such as, for example, a metal material such as copper or aluminum) of the TSVs 308, the insulating layer 341 is deposited on the lining sidewall surfaces of the openings or trenches, and the insulating layer 341 provides electrical insulation between the conductive material and the silicon substrate 334. During the formation of the TSVs 308, the TSVs 308 are electrically connected to specific metal elements 338, and the TSVs 308 are exposed on the bottom surface of the insulating layer 341. The bottom surface of the insulating layer 341 can be the surface of the insulating layer 341 that is away from the bottom surface 307 of the silicon substrate 334. Then, metal contacts 342 are formed, and optionally, the interposer 346 is partially formed with openings corresponding to the positions of the metal contacts 342.

[0102] Next, as Figure 5F shown, a second carrier wafer substrate 500 is provided and bonded to the bottom surface 502 of the CSP structure 310, and the first carrier wafer substrate 400 is peeled off and removed from the top surface 301 of the interconnect layer 328. Then, as Figure 5G shown, a display assembly 300 is formed on the top surface 301 of the interconnect layer 328, above the pixel mirror 324. That is, an alignment layer 316 is formed on the bottom surface 410 of the cover glass 312, an alignment layer 320 is formed above the top surface 301 of the interconnect layer 328 and the pixel mirror 324, the dam portion 322 is sandwiched between the bottom surface 410 of the cover glass 312 and the top surface 301 of the interconnect layer 328, and a liquid crystal material is deposited in the space defined by the dam portion 322 and the alignment layers 316 and 320 to form a liquid crystal layer 318.

[0103] Finally, as Figure 5HAs shown, the second carrier wafer substrate 500 is peeled off and removed from the CSP structure 310, thereby exposing the metal contacts 342. Subsequently, solder balls 344 can be formed on the metal contacts 342, and the interposer 346 can be thickened to complete the CSP structure 310. In this process, the CSP structure 310 can be formed without being restricted by the temperature of the liquid crystal material (e.g., 100 degrees Celsius), because the liquid crystal layer 318 is formed after the CSP structure 310 is formed.

[0104] Figure 6 FIG. 4 is a cross-sectional view of a second exemplary LCoS display device 600, which includes: a display assembly 602, a first circuit board 604, a second circuit board 606, a set of TSVs 608, and a set of contact pads 610. The display assembly 602 is formed above the top surface 601 of the first circuit board 604, and the opposite bottom surface 603 of the first circuit board 604 is bonded to the top surface 605 of the second circuit board 606. The set of TSVs 608 electrically connects the circuits of the second circuit board 606 to the circuits of the first circuit board 604. The contact pads 610 are formed on the top surface 601 of the first circuit board 604 and facilitate wire bonding of the circuits of the LCoS display device 600 to an external device (e.g., a host device). The contact pads 610 can be arranged and disposed adjacent to the display assembly 602. The contact pads 610 can be arranged in rows and / or columns.

[0105] The display assembly 602 includes: a cover glass 612 (transparent layer), a transparent electrode 614, a first liquid crystal alignment layer 616, a liquid crystal layer 618, a second liquid crystal alignment layer 620, and dams 622. The transparent electrode 614 is formed on the bottom surface of the cover glass 612, and, for example, the transparent electrode 614 is thin enough to be transparent and is a conductive material layer (e.g., indium tin oxide) that serves as a common electrode across the liquid crystal layer 618. The alignment layers 616 and 620 contribute to the alignment of the liquid crystal molecules in the liquid crystal layer 618. The alignment layer 616 is formed on the bottom surface of the transparent electrode 614, and the alignment layer 620 is formed above the first circuit board 604. The alignment layers 616 and 620 can be formed of any suitable material, such as, for example, polyimide and / or SiO2. The dams 622 are disposed around the periphery of the liquid crystal layer 618 and serve as gaskets to encapsulate the liquid crystal layer 618 between the alignment layers 616 and 620. The cover glass 612 does not cover the contact pads 610.

[0106] The first circuit board 604 includes an LCoS circuit configured to drive a plurality of pixel mirrors 624. The LCoS circuit includes various semiconductor circuit elements formed in and on a silicon substrate 626 for use in a reflective display backplane. For example, the LCoS circuit may include, but is not limited to: pixel latches, row / column decoders, line registers, address registers, data memories, and / or any other useful circuits in the reflective display backplane ( Figure 6 not shown). The various circuit elements formed in and on the silicon substrate 626 are electrically connected to each other and to the pixel mirrors 624 through a metal interconnect layer 628, which includes various conductive metal elements 630 (e.g., wires, leads, etc.) and an electrically insulating material 632. The pixel mirror 624 is a highly reflective aluminum electrode formed in and on the top surface 601 of the interconnect layer 628.

[0107] The second circuit board 606 includes control circuitry, such as an application specific integrated circuit (ASIC), which also includes various logic circuit elements (not shown) formed in and on a silicon substrate 634. The various logic circuit elements may operate at different operating voltages that are lower than the operating voltage of the LCoS circuit. In this example, the circuitry of the second circuit board 606 will be configured as a display driver. Examples of such display driver circuits include, but are not limited to: timing circuits, display data conversion circuits, display data buffers, frame buffers, display control signal generators, etc. The various circuit elements formed in and on the silicon substrate 634 are electrically connected to each other through a metal interconnect layer 636, which includes multiple interconnect layers of various conductive metal elements 638 separated by an electrically insulating material 640. The top surface 605 of the interconnect layer 636 is joined to the bottom surface 603 of the silicon substrate 626 in a stacked configuration.

[0108] The set of TSVs 608 are through-silicon vias formed through the silicon substrate 626 and filled with or lined with a conductive material (e.g., copper, aluminum, etc.) to electrically connect the conductive metal elements 638 of the interconnect layer 636 to the conductive metal elements 630 of the interconnect layer 628. Thus, the set of TSVs 608 interconnects the circuitry of the first circuit board 604 with the circuitry of the second circuit board 606. Even though not shown in the drawings, an insulating layer similar to insulating layer 341 ( Figure 3 ) may be provided between the first circuit board 604 and the second circuit board 606 and between each individual TSV of the set of TSVs 608.

[0109] Contact pads 610 are formed by removing (e.g., etching) a portion of the insulating material 632 from the top surface 601 of the interconnect layer 628 to expose a predetermined portion of the conductive metal elements 630.

[0110] In this exemplary embodiment, the first circuit substrate 604 is an LCoS chip (reflective display backplane) operating at a first voltage, and the second circuit substrate 606 is an ASIC chip having one or more circuits operating at a different second voltage. The second voltage is lower than the first voltage. In particular, the voltage required to drive the integrated circuit on the silicon substrate 626 that controls the operation of the pixel mirror 624 is higher than the voltage required to drive the logic circuits of the second circuit substrate 606.

[0111] Figures 7A to 7F A method of manufacturing a second exemplary LCoS display device 600 is shown. As Figure 7A shown, the carrier wafer substrate 700, the first circuit substrate 604, and the second circuit substrate 606 are provided as separate elements. Then, as Figure 7B shown, the top surface 601 of the interconnect layer 628 of the first circuit substrate 604 is bonded (e.g., thermally bonded) to the carrier wafer substrate 700. Then, as Figure 7C shown, material is removed from the bottom surface 603 of the silicon substrate 626 by some suitable method (such as, for example, back grinding, back lapping, chemical etching, etc.) to thin the silicon substrate 626 to a predetermined thickness. Once the silicon substrate 626 is thinned, the set of TSVs 608 is formed through the bottom surface 603 and the silicon substrate 626. During the formation of the set of TSVs 608, the TSVs 608 are electrically connected to the conductive metal elements 630 that form the electrical connection, and the TSVs 608 are exposed on the bottom surface 603 of the silicon substrate 626.

[0112] Next, as Figure 7D shown, the bottom surface 603 of the silicon substrate 626 is bonded to the top surface 605 of the interconnect layer 636 of the second circuit substrate 606, and the carrier wafer substrate 700 is peeled off and removed from the top surface 601 of the interconnect layer 628 of the first circuit substrate 604. Then, as Figure 7E shown, contact pads 610 and pixel mirrors 624 are formed on the top surface 601 of the first circuit substrate 604. The contact pads 610 are formed by removing (e.g., etching) a portion of the electrical insulating material 632 from the top surface 601 of the interconnect layer 628, thereby exposing a portion of the conductive metal elements 630. The pixel mirrors 624 are formed by patterning the reflective metal on the interconnect layer 628, wherein each individual pixel mirror is in electrical contact with at least one of the conductive metal elements 630.

[0113] Finally, as Figure 7FAs shown, a display component 602 is formed on the top surface 601 of the interconnect layer 628, above the pixel mirror 624. That is, an alignment layer 616 is formed on the bottom surface 710 of the cover glass 612 on the transparent electrode 614, and an alignment layer 620 is formed above the top surface 601 of the interconnect layer 628 and the pixel mirror 624, such that the dam portion 622 is sandwiched between the bottom surface 710 of the cover glass 612 and the top surface 601 of the interconnect layer 628, and a liquid crystal material is deposited in the space defined by the dam portion 622 and the alignment layers 616 and 620 to form a liquid crystal layer 618.

[0114] Figure 8 FIG. 4 is a cross-sectional view of a third exemplary LCoS display device 800, which includes: a display component 802, a first circuit board 804, a second circuit board 806, a third circuit board 808, a first group of TSVs 810 (first group of conductive vias), a second group of TSVs 812 (second group of conductive vias), a third group of TSVs 814 (third group of conductive vias), and a CSP structure 816. The display component 802 is formed above the top surface 801 of the first circuit board 804, and the opposite bottom surface 803 of the first circuit board 804 is bonded to the top surface 805 of the second circuit board 806. The bottom surface 807 of the second circuit board 806 is bonded to the top surface 809 of the third circuit board 808, and the CSP structure 816 is formed on the bottom surface 811 of the third circuit board 808. The first group of TSVs 810 electrically connects the circuit of the second circuit board 806 to the circuit of the first circuit board 804. The second group of TSVs 812 electrically connects the circuit of the third circuit board 808 to the circuit of the second circuit board 806. The third group of TSVs 814 electrically connects the circuit of the CSP structure 816 to the circuit of the third circuit board 808.

[0115] The display component 802 includes: a cover glass 818, a transparent electrode 820, a first liquid crystal alignment layer 822, a liquid crystal layer 824, a second liquid crystal alignment layer 826, and a dam portion 828. The transparent electrode 820 is formed on the bottom surface of the cover glass 818, and, for example, the transparent electrode 820 is thin enough to be transparent and is a conductive material layer (e.g., indium tin oxide) that serves as a common electrode across the liquid crystal layer 824. The alignment layers 822 and 826 assist in the alignment of the liquid crystal molecules of the liquid crystal layer 824. The alignment layer 822 is formed on the bottom surface of the transparent electrode 820, and the alignment layer 826 is formed above the first circuit board 804. The alignment layers 822 and 826 can be formed of any suitable material, such as, for example: polyimide and / or SiO2. The dam portion 828 is disposed around the periphery of the liquid crystal layer 824 and serves as a gasket to encapsulate the liquid crystal layer 824 between the alignment layers 822 and 826.

[0116] The first circuit board 804 includes an LCoS circuit configured to drive a plurality of pixel mirrors 830. Specifically, the first circuit board 804 is a reflective display backplane, which, as a non-limiting example, includes: pixel data latches, data input lines, control signal lines, row and / or column decoders, address registers, data line buffers, etc. These functional elements are implemented as various semiconductor circuit elements formed in and on a silicon substrate 832. The various circuit elements formed in and on the silicon substrate 832 are electrically connected to each other through a metal interconnect layer 834, and are electrically connected to the pixel mirrors 830. The metal interconnect layer 834 includes multiple layers of various conductive metal elements 836 separated by an electrically insulating material 838. In an embodiment, the plurality of pixel mirrors 830 are electrodes of highly reflective aluminum or silver-plated aluminum formed in and on the top surface 801 of the interconnect layer 834.

[0117] The second circuit board 806 includes an application-specific integrated circuit (ASIC), which also includes various logic circuit elements (not shown) formed in and on a silicon substrate 840. As described with reference to other example devices, the circuits of the second circuit board 806 function as display drivers. The various circuit elements formed in and on the silicon substrate 840 are electrically connected to each other through a metal interconnect layer 842, and the metal interconnect layer 842 includes multiple layers of various conductive metal elements 844 separated by an electrically insulating material 846. The top surface 805 of the interconnect layer 842 is joined to the bottom surface 803 of the silicon substrate 832 of the first circuit board 804 in a stacked configuration.

[0118] The third circuit board 808 includes various logic circuit elements (not shown) formed in and on a silicon substrate 848. The various circuit elements formed in and on the silicon substrate 848 are electrically connected to each other through a metal interconnect layer 850, and the metal interconnect layer 842 includes multiple layers of various conductive metal elements 852 separated by an electrically insulating material 854. The top surface 809 of the interconnect layer 850 is joined to the bottom surface 807 of the silicon substrate 840 of the second circuit board 806 in a stacked configuration.

[0119] The circuitry of the third circuit board 808 can provide many and various functions that have a synergistic relationship with the display driver circuitry of the second circuit board 806 and / or the reflective display backplane circuitry of the first circuit board 804. For example, the circuitry of the third circuit board 808 can include additional data storage for video data. As another example, the circuitry of the third circuit board 808 can be configured to receive video data in a first format (e.g., 24-bit RGB data) and convert the video data to another format, such as data having a combination of binary weighted bits and other equally weighted bits. As another example, the circuitry of the third circuit board 808 can include a processing unit and storage for executable code. The code can include AR or VR applications, video processing and / or enhancement applications, configuration routines, etc. Alternatively, such functions can be provided by a pre-configured controller or logic array. The above examples are not intended to be limiting, but rather to provide a small sample of the types of display synergistic functions that can be integrated into the third circuit board 808.

[0120] The TSVs included in the first group of TSVs 810 are through-silicon vias formed through the silicon substrate 832 and filled or coated with a conductive material (e.g., copper, aluminum, etc.) to electrically connect the circuitry of the interconnect layer 842 to the circuitry of the interconnect layer 834. The TSVs included in the second group of TSVs 812 are through-silicon vias formed through the silicon substrate 840 and filled or coated with a conductive material (e.g., copper, aluminum, etc.) to electrically connect the circuitry of the interconnect layer 850 to the circuitry of the interconnect layer 842. The TSVs included in the third group of TSVs 814 are through-silicon vias formed through the silicon substrate 848 and filled or coated with a conductive material (e.g., copper, aluminum, etc.) to electrically connect the circuitry of the CSP structure 816 to the circuitry of the interconnect layer 850.

[0121] The first circuit board 804 is an LCoS chip operating at a first voltage, while the second circuit board 806 is an ASIC chip operating at a second voltage, which is a different voltage lower than the first voltage. In particular, the voltage of the integrated circuit (e.g., the LCoS driver circuitry) driving the first circuit board 804 and the pixel mirror 830 is higher than the voltage of the logic circuitry driving the second circuit board 806. The voltage driving the third circuit board 808 can be the same as the voltage of the integrated circuit driving the second circuit board 806, can be the same as the voltage of the circuitry driving the first circuit board 804, or can be a third voltage different from the former two.

[0122] The CSP structure 816 is coupled to the bottom surface 811 of the silicon substrate 848 and is configured to electrically connect the circuit of the LCoS display device 800 to the circuit of the host device. The CSP structure 816 includes: an insulating layer 817, a plurality of metal contacts 856, a plurality of solder bumps 858, and an interposer layer 860 (e.g., a solder mask). The insulating layer 817 is formed after forming vias through the silicon substrate 848 but before depositing the conductive material (e.g., a metal material such as copper or aluminum) of the TSV 814. The contacts 856 are electrically connected to the corresponding TSVs in the third group of TSVs 814, and the solder bumps 858 are electrically connected to the contacts 856. The solder bumps 858 facilitate electrical connection to the contact pads of an external device (such as a host device) through some suitable processes (such as, for example, reflow soldering, ultrasonic bonding, etc.) to provide control signals and / or display image data thereto. The interposer layer 860 is disposed around and between the contacts 856.

[0123] Even if not shown in the drawings, an insulating layer similar to the insulating layer 817 may be disposed between the first circuit substrate 804 and the second circuit substrate 806, and between the individual TSVs included in the first group of TSVs 810 and the silicon substrate 832. Similarly, an insulating layer is disposed between the second circuit substrate 806 and the third circuit substrate 808, and between the individual TSVs included in the second group of TSVs 812 and the silicon substrate 840.

[0124] Although the LCoS display device 800 includes three stacked circuit substrates, it should be understood that alternative devices may include any desired number of circuit substrates connected in a stacked configuration.

[0125] Figures 9A to 9K Show a first exemplary method of manufacturing an LCoS display device 800. As Figure 9A shown, the carrier wafer substrate 900, the first circuit substrate 804, the second circuit substrate 806, and the third circuit substrate 808 are provided as separate elements. Then, as Figure 9B shown, the carrier wafer substrate 900 is bonded (e.g., thermally bonded) to the top surface 801 of the interconnect layer 834. Next, as Figure 9C shown, material is removed from the bottom surface 803 of the silicon substrate 832 by some suitable method (such as, for example, back grinding, back lapping, chemical etching, etc.) to thin the silicon substrate 832. After the silicon substrate 832 is thinned, TSVs 810 are formed through the bottom surface 803 and the silicon substrate 832. During the formation of the first group of TSVs 810, the first group of TSVs 810 are electrically connected to specific metal elements 836, and the first group of TSVs 810 are exposed on the bottom surface 803 of the silicon substrate 832.

[0126] Then, as Figure 9DAs shown, the top surface 805 of the interconnect layer 842 is bonded to the thinned bottom surface 803 of the silicon substrate 832. The bonding of the interconnect layer 842 to the silicon substrate 832 includes: physical bonding of the interconnect layer 842 to the silicon substrate 832, and electrical connection of specific metal elements 844 of the interconnect layer 842 to corresponding TSVs included in the first group of TSVs 810. Next, as Figure 9E shown, material is removed from the bottom surface 807 of the silicon substrate 840 by some suitable method (such as, for example, back grinding, back lapping, chemical etching, etc.) to thin the silicon substrate 840. After the silicon substrate 840 is thinned, TSVs forming the second group of TSVs 812 are formed through the bottom surface 807 and the silicon substrate 840. During the formation of the second group of TSVs 812, the second group of TSVs 812 is electrically connected to the specific metal elements 844, and the second group of TSVs 812 is exposed on the bottom surface 807 of the silicon substrate 840.

[0127] Then, as Figure 9F shown, the top surface 809 of the interconnect layer 850 is bonded to the thinned bottom surface 807 of the silicon substrate 840. The bonding of the interconnect layer 850 to the silicon substrate 840 includes: physical bonding of the interconnect layer 850 to the silicon substrate 840, and electrical connection of specific metal elements in the metal elements 852 of the interconnect layer 850 to corresponding TSVs included in the second group of TSVs 812.

[0128] Next, as Figure 9G shown, the carrier wafer substrate 900 is removed from the top surface 801 of the interconnect layer 834. Then, as Figure 9H shown, a pixel mirror 830 is formed on the top surface 801 of the interconnect layer 834 of the first circuit substrate 804. During the formation of the pixel mirror 830, each pixel mirror 830 is electrically connected to a specific one of the metal elements 836 of the interconnect layer 834.

[0129] Next, as Figure 9I shown, a display component 802 is formed on the top surface 801 of the interconnect layer 834, above the pixel mirror 830. That is, an alignment layer 822 is formed on the bottom surface 912 of the cover glass 818 on the transparent electrode 820, an alignment layer 826 is formed above the top surface 801 of the interconnect layer 834 and the pixel mirror 830, the dam portion 828 is sandwiched between the bottom surface 912 of the cover glass 818 and the top surface 801 of the interconnect layer 834, and a liquid crystal material is deposited in the space defined by the dam portion 828 and the alignment layers 822 and 826 to form a liquid crystal layer 824. Then, as Figure 9J shown, material is removed from the bottom surface 811 of the silicon substrate 848 by some suitable method (such as, for example, back grinding, back lapping, chemical etching, etc.) to thin the silicon substrate 848.

[0130] Finally, as Figure 9K shown, a third group of TSVs 814 and CSP structures 816 are formed. The CSP structure 816 includes an insulating layer 817 formed on the bottom surface 811 of the silicon substrate 848. TSVs of the third group of TSVs 814 are formed through the bottom surface 811 and the silicon substrate 848. In one example, a plurality of openings or trenches are formed through the silicon substrate 848 or at positions corresponding to the positions of the TSVs of the third group of TSVs 814 on the silicon substrate 848. After forming the openings (or trenches) through the silicon substrate 848 but before depositing the conductive material (e.g., a metallic material such as copper or aluminum) for forming the individual TSVs included in the third group of TSVs 814, the insulating layer 817 is deposited on the liner sidewall surfaces of the openings or trenches such that the insulating layer 817 provides electrical insulation between the conductive material of each individual TSV included in the third group of TSVs 814 and the silicon substrate 848. During the formation of the third group of TSVs 814, the third group of TSVs 814 is electrically connected to the corresponding metal elements 852 and the third group of TSVs 814 is exposed on the bottom surface 916 of the insulating layer 817. The bottom surface 916 of the insulating layer 817 may be the surface of the insulating layer 817 that is away from the bottom surface 811 of the silicon substrate 848. Then, metal contacts 856 are formed in electrical contact with the corresponding TSVs included in the third group of TSVs 814, and solder bumps 858 are formed on the bottom surface 811 of the silicon substrate 848 to contact the metal contacts 856. An interposer 860 (solder mask) is disposed around and between the metal contacts 856. In an embodiment, the interposer 860 may enclose the metal contacts 856. The interposer 860 may also be disposed to surround the solder bumps 858.

[0131] Figures 10A to 10J Shows a second method of manufacturing the third exemplary LCoS display device 800.

[0132] As Figure 10A shown, the carrier wafer substrate 900, the first circuit substrate 804, the second circuit substrate 806, and the third circuit substrate 808 are provided as separate elements. In this particular method, the first circuit substrate 804 includes a plurality of pixel mirrors 830 formed on the top surface 801 of the interconnect layer 834. Then, as Figure 10B shown, the carrier wafer substrate 900 is bonded (e.g., thermally bonded) to the top surface 801 of the interconnect layer 834.

[0133] Next, as Figure 10CAs shown, material is removed from the bottom surface 803 of the silicon substrate 832 by some suitable method (such as, for example, back grinding, back lapping, chemical etching, etc.) to thin the silicon substrate 832. After the silicon substrate 832 is thinned, a first set of TSVs 810 is formed through the bottom surface 803 and the silicon substrate 832. During the formation of the conductive TSVs included in the first set of TSVs 810, the TSVs included in the first set of TSVs 810 are electrically connected to a specific metal element 836, and the TSVs included in the first set of TSVs 810 are exposed on the bottom surface 803 of the silicon substrate 832.

[0134] Next, as Figure 10D shown, the top surface 805 of the interconnect layer 842 is bonded to the thinned bottom surface 803 of the silicon substrate 832. The bonding of the interconnect layer 842 to the silicon substrate 832 includes: physical bonding of the interconnect layer 842 to the silicon substrate 832, and electrical connection of a specific metal element 844 of the interconnect layer 842 to the corresponding TSVs included in the first set of TSVs 810.

[0135] Next, as Figure 10E shown, material is removed from the bottom surface 807 of the silicon substrate 840 to thin the silicon substrate 840. Once the silicon substrate 840 is thinned, a second set of TSVs 812 is formed through the bottom surface 807 and the silicon substrate 840. During the formation of the conductive TSVs included in the second set of TSVs 812, the TSVs included in the second set of TSVs 812 are electrically connected to a specific metal element among the metal elements 844, and the TSVs included in the second set of TSVs 812 are exposed on the bottom surface 807 of the silicon substrate 840. Next, as Figure 10F shown, the top surface 809 of the interconnect layer 850 is bonded to the thinned bottom surface 807 of the silicon substrate 840. The bonding of the interconnect layer 850 to the silicon substrate 840 includes: physical bonding of the interconnect layer 850 to the silicon substrate 840, and electrical connection of a specific metal element among the metal elements 852 of the interconnect layer 850 to the TSVs 812.

[0136] Next, as Figure 10GAs shown, the silicon substrate 848 is thinned to form an insulating layer 817, a third group of TSVs 814, and part of the CSP structure 816. The silicon substrate 848 is thinned by removing material from the bottom surface 811 of the silicon substrate 848. A third group of TSVs 814 is formed through the bottom surface 811 and the silicon substrate 848. The insulating layer 817 is deposited after forming the via openings through the silicon substrate 848 but before depositing the conductive material (e.g., metal) of the TSVs included in the third group of TSVs 814. During the formation of the third group of TSVs 814 and the contact pads 856, the TSVs included in the third group of TSVs 814 are electrically connected to specific metal elements 852, and the contact pads 856 are exposed on the bottom surface of the insulating layer 817. Then, an interposer 860 is partially formed between and around the contact pads 856.

[0137] Next, as Figure 10H shown, a second carrier wafer substrate 1000 is provided and bonded to the bottom surface 1002 of the CSP structure 816, and the first carrier wafer substrate 900 is peeled off and removed from the top surface 801 of the interconnect layer 834.

[0138] Next, as Figure 10I shown, a display component 802 is formed on the top surface 801 of the interconnect layer 834 and above the pixel mirror 830. That is, an alignment layer 822 is formed on the bottom surface 912 of the cover glass 818, an alignment layer 826 is formed above the top surface 801 of the interconnect layer 834 and the pixel mirror 830, the dam 828 is sandwiched between the bottom surface 912 of the cover glass 818 and the top surface 801 of the interconnect layer 834, and a liquid crystal material is deposited in the space defined by the dam 828 and the alignment layers 822 and 826 to form a liquid crystal layer 824.

[0139] Finally, as Figure 10J shown, the second carrier wafer substrate 1000 is peeled off and removed from the CSP structure 816, thereby exposing the metal contacts 856. Solder balls 858 are formed on each metal contact 856, and the remaining part of the interposer 860 can be formed.

[0140] Figure 11is a flowchart outlining an example method 1100 of manufacturing an LCoS display device. In a first step 1102, a reflective display backplane (RDB) is set up. Circuit substrates 302, 604, and 804 are non-limiting examples of a reflective display backplane. Next, in a second step 1104, TSVs are formed in the RDB. Next, in a third step 1106, a liquid crystal display element is assembled on the RDB according to a first selection. Next, in a fourth step 1108, one or more circuit substrates are set up. Next, in a fifth step 1110, any desired TSVs are formed in the one or more circuit substrates. Next, in a sixth step 1112, the RDB and the one or more circuit substrates are assembled in a stacked configuration and electrically interconnected. Next, in an optional seventh step 1114, a CSP structure is formed on the bottom circuit substrate. Finally, in an eighth step 1116, a liquid crystal display element is assembled on the RDB according to a second selection that replaces the first selection of step 1106.

[0141] Figure 12A is a flowchart outlining an example method 1200A of performing the sixth step 1112 in method 1100. In a first step 1202A, a carrier substrate is set up. Next, in a second step 1204A, the carrier substrate is attached to the top side of the RDB. Next, in a third step 1206A, a portion of the bottom side of the RDB is removed to thin the RDB. Next, in a fourth step 1208A, the bottom side of the RDB is attached to the top side of the circuit substrate. Next, in a fifth step 1210A, a portion of the bottom side of the circuit substrate is removed to thin the circuit substrate. Finally, in a sixth step 1212A, the carrier substrate is removed from the RDB.

[0142] Figure 12B is a flowchart outlining another example method 1200B of performing the sixth step 1112 in method 1100. In a first step 1202B, a carrier substrate is set up. Next, in a second step 1204B, the carrier substrate is attached to the top side of the RDB. Next, in a third step 1206B, a portion of the bottom side of the RDB is removed to thin the RDB. Next, in a fourth step 1208B, the bottom side of the RDB is attached to the top side of the circuit substrate. Finally, in a fifth step 1210B, the carrier substrate is removed from the RDB.

[0143] Figure 12CIt is a flowchart of another method that outlines step 1112 of method 1100. In a first step 1202C, a carrier substrate is set. Next, in a second step 1204C, the carrier substrate is attached to the top side of the RDB. Next, in a third step 1206C, the RDB is thinned by removing a portion of the bottom side of the RDB. Next, in a fourth step 1208C, the bottom side of the RDB is attached to the top side of a first circuit substrate. Next, in a fifth step 1210C, the first circuit substrate is thinned by removing a portion of the bottom side of the first circuit substrate. Next, in a sixth step 1212C, the bottom side of the first circuit substrate is attached to the top side of a second circuit substrate. Next, in a seventh step 1214C, the second circuit substrate is thinned by removing a portion of the bottom side of the second circuit substrate. Finally, in an eighth step 1216C, the carrier substrate is removed from the RDB.

[0144] Prior to proceeding to the eighth step 1216C, any number of circuit substrates can be added to the stack by repeating the sixth step 1212C and the seventh step 1214C for each subsequent (third, fourth, fifth, …) substrate.

[0145] The description of specific embodiments of the present invention has now been completed. Many of the described features can be substituted, altered, or omitted without departing from the scope of the present invention. For example, the LCoS display device disclosed herein can be used in host devices different from the AR glasses and VR goggles exemplified herein, including but not limited to mobile phones, medical devices, optical systems, etc. As another example, the solder balls exemplified herein can be replaced with alternative electrical connections (e.g., columnar bumps). As another example, the liquid crystal display device of the present invention is not limited to a stacked configuration of only two or three circuit substrates, but can include any number (i.e., four or more) of circuit substrates configured in a stacked relationship. These and other variations from the specific embodiments shown will be apparent to those skilled in the art, particularly in view of the foregoing disclosure.

Claims

1. A liquid crystal display device, comprising: A first circuit substrate having: a first surface; and a second surface opposite to the first surface; a first set of integrated circuits formed in and on the second surface of the first circuit substrate and including a first set of metal interconnect layers; and an array of conductive pixel mirrors formed over the first set of metal interconnect layers and electrically coupled to circuits of the first set of integrated circuits via the first set of metal interconnect layers; The second circuit substrate has: a first surface; and a second surface opposite to the first surface; and a second set of integrated circuits formed in and on the second surface of the second circuit substrate and including a second set of metal interconnect layers; as well as A first set of conductive vias passes through the first circuit substrate and electrically connects the first set of metal interconnect layers to the second set of metal interconnect layers.

2. The liquid crystal display device according to claim 1, further comprising: a layer of liquid crystal material disposed above the array of conductive pixel mirrors; as well as A transparent electrode is disposed above the liquid crystal material layer.

3. The liquid crystal display device according to claim 1, wherein: The first set of metal interconnect layers includes at least one bonding pad exposed on the first substrate of the first circuit substrate.

4. The liquid crystal display device according to claim 1, further comprising: a chip scale package (CSP) structure having a first surface and a second surface opposite the first surface, the CSP structure including a first set of contacts formed on the first surface of the CSP structure and a second set of contacts formed on the second surface of the CSP structure; as well as A second set of conductive vias passes through the second circuit substrate and electrically connects the second set of metal interconnect layers to the first set of contacts.

5. The liquid crystal display device according to claim 1, further comprising: A third circuit substrate has: a first surface; and a second surface opposite to the first surface; and a third set of integrated circuits formed in and on the second surface of the third circuit substrate and including a third set of metal interconnect layers; as well as A second set of conductive vias passes through the second circuit substrate and electrically connects the second set of metal interconnect layers to the third set of metal interconnect layers.

6. The liquid crystal display device according to claim 5, further comprising: a chip scale package (CSP) structure having a first surface and a second surface opposite the first surface, the CSP structure including a first set of contacts formed on the first surface of the CSP structure and a second set of contacts formed on the second surface of the CSP structure; as well as A third set of conductive vias passes through the third circuit substrate and electrically connects the third set of metal interconnect layers to the first set of contacts.

7. The liquid crystal display device according to claim 5, wherein: The first circuit substrate is a reflective display backplane including a data input and a control signal input; the second set of integrated circuits comprising a video data buffer and a control signal generator, the control signal generator being configured to generate a control signal based on data stored in the video data buffer and to provide the control signal to the control signal input of the reflective display backplane; and The third group of integrated circuits includes video processing circuits.

8. The liquid crystal display device according to claim 7, wherein: The video processing circuit comprises: Circuitry configured to receive video data in a first format; and Circuitry configured to convert the video data in the first format to video data in a second format.

9. The liquid crystal display device according to claim 1, wherein: The first set of integrated circuits includes a plurality of pixel latches, each pixel latch in an array of pixel latches being electrically coupled to an associated one of the conductive pixel mirrors; as well as The second group of integrated circuits includes a frame buffer configured to store at least one frame of pixel data.

10. The liquid crystal display device according to claim 9, wherein: The frame buffer has a capacity sufficient to store multiple frames of pixel data.

11. The liquid crystal display device according to claim 1, wherein: The first set of integrated circuits operates at a first voltage; The second set of integrated circuits operates at a second voltage; and The first voltage is higher than the second voltage.

12. The liquid crystal display device according to claim 11, further comprising an interface circuit, wherein: Digital video data is transmitted from the second group of integrated circuits operating at the second voltage to the first group of integrated circuits operating at the first voltage through the interface circuit.

13. The liquid crystal display device according to claim 1, wherein: The first circuit substrate has a technology node of at least 65 nm; and The second circuit substrate has a technology node of 28 nm or less.

14. The liquid crystal display device according to claim 13, wherein: The first circuit substrate has a technology node of at least 130 nm.

15. The liquid crystal display device according to claim 13, wherein: The second circuit substrate has a technology node of 22 nm or less.

16. The liquid crystal display device according to claim 1, wherein: The second group of integrated circuits includes display driver circuits.

17. The liquid crystal display device according to claim 16, wherein: The display driving circuit includes a control circuit and a memory.

18. The liquid crystal display device according to claim 1, further comprising: a liquid crystal layer, the liquid crystal layer being disposed above the conductive pixel mirror; as well as a dam portion, the dam portion surrounding the liquid crystal layer; and in The first group of integrated circuits, the first group of metal interconnect layers, the second group of integrated circuits, and the second group of metal interconnect layers are all contained within a space defined by a periphery of the dam projected along an axis perpendicular to the first surface of the first circuit substrate.

19. A liquid crystal display device, comprising: a first circuit substrate comprising: a top surface; an opposing bottom surface; an array of pixel mirrors formed on the top surface; a first set of integrated circuits configured to apply pixel data on the pixel mirrors; and a plurality of electrical contacts formed on the bottom surface, the electrical contacts connected to the first set of integrated circuits; A liquid crystal layer, the liquid crystal layer is disposed above the pixel mirror; a transparent electrode disposed above the liquid crystal layer; and a second circuit substrate, comprising: a top surface; a bottom surface opposite the top surface; a second set of electrical contacts, the second set of electrical contacts being formed on the top surface; and a second set of integrated circuits, the second set of integrated circuits being electrically coupled to the second set of electrical contacts, the second set of integrated circuits comprising: a frame buffer configured to store digital video data, and a control circuit configured to generate a control signal based at least in part on the digital video data; and wherein The first set of electrical contacts are securely connected to the second set of electrical contacts, thereby providing a mechanical bond between the first and second circuit substrates and providing an electrical connection through which the control signals are passed from the second set of integrated circuits to the first set of integrated circuits.

20. A method for manufacturing a liquid crystal display device, the method comprising: Providing a reflective display backplane including an array of pixel mirrors; forming a through hole passing through the reflective display backplane; providing one or more integrated circuit substrates; forming a through hole in the one or more integrated circuit substrates; Assembling the reflective display backplane and the one or more integrated circuit substrates in a stacked relationship, wherein the reflective display backplane is disposed between the cover glass and the one or more integrated circuit substrates; electrically connecting the circuit of the reflective display backplane to the one or more integrated circuit substrates through the through holes; forming a chip scale packaging structure on a bottom one of the integrated circuit substrates; and A liquid crystal display element is assembled over the array of pixel mirrors.

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