Display panel

Abstract

A display panel is provided. The display panel includes: a (1-1) th sub-pixel and a (1-2) th sub-pixel disposed over the substrate so as to be in a main display area, the main display area being located outside the component area in a plan view; a (2-1) th sub-pixel and a (2-2) th sub-pixel, the (2-1) th sub-pixel and the (2-2) th sub-pixel being arranged over the substrate so as to be in the feature region, the (2-1) th sub-pixel and the (2-2) th sub-pixel including thin film transistors, each of which has a semiconductor layer; and a conductive layer disposed between the semiconductor layer and the substrate, the conductive layer including, in plan view, an opening having a polygonal shape in the feature region, at least one interior angle of the opening being an obtuse angle.

Description

[0001] This application is a divisional application of a Chinese patent application with an application number of 202110068411.4 and an invention title of "Display Panel and Display Device Including the Same" filed on January 19, 2021.

[0002] Cross - reference to related applications

[0003] This application claims the priority of Korean Patent Application No. 10 - 2020 - 0007378, filed with the Korean Intellectual Property Office on January 20, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0004] One or more exemplary embodiments of the present inventive concept relate to a display panel and a display device including the display panel, and more particularly, to a display panel having an extended display area for displaying an image and a display device including the display panel. Background art

[0005] A display panel generally includes sub - pixels arranged uniformly to display various images. The display panel is widely used in various electronic devices because of its thinness and light weight.

[0006] Since display devices are used in various different electronic devices, various methods can be applied to design the shape of the display device.

[0007] However, in existing display panels, when the display panel includes components as electronic elements, the area of the display region for displaying an image is limited. Summary of the invention

[0008] One or more exemplary embodiments include a display panel and a display device including the display panel, the display panel having an extended display area so as to display an image even in an area where components as electronic elements are arranged. However, it should be understood that the exemplary embodiments described herein should be considered only in a descriptive sense and not for limiting the present invention.

[0009] Additional aspects will be set forth in part in the following detailed description, and in part will be obvious from the description, or may be learned by practicing the embodiments of the present disclosure.

[0010] According to one or more exemplary embodiments, a display panel includes a first-1 sub-pixel and a first-2 sub-pixel arranged in a first row. A second-1 sub-pixel is arranged in a second row. A third-1 sub-pixel and a third-2 sub-pixel are arranged in a third row. A first data line is configured to electrically connect the pixel circuits of the first-1 sub-pixel, the second-1 sub-pixel, and the third-1 sub-pixel. A second-1 data line is configured to electrically connect to the pixel circuit of the first-2 sub-pixel. A second-2 data line is configured to electrically connect to the pixel circuit of the third-2 sub-pixel. A first bridge wire is arranged on a layer different from the first data line, the second-1 data line, and the second-2 data line. The first bridge wire has a first side in contact with the second-1 data line and a second side in contact with the second-2 data line. The first bridge wire has a portion extending along at least a part of the first data line.

[0011] The first-1 sub-pixel, the first-2 sub-pixel, the second-1 sub-pixel, the third-1 sub-pixel, and the third-2 sub-pixel may be arranged on a substrate, wherein an orthographic projection image on the top surface of the substrate of the portion of the first bridge wire extending along at least a part of the first data line may overlap with the orthographic projection image on the top surface of the substrate of the first data line.

[0012] The display panel may further include: a first-3 sub-pixel and a first-4 sub-pixel in the first row, wherein the first-3 sub-pixel is located in a direction opposite to the first-2 sub-pixel with respect to the first-1 sub-pixel, and the first-4 sub-pixel is located between the first-1 sub-pixel and the first-2 sub-pixel; a second-2 sub-pixel in the second row; a third-3 sub-pixel and a 3-4 sub-pixel in the third row, wherein the third-3 sub-pixel is located in a direction opposite to the third-2 sub-pixel with respect to the third-1 sub-pixel, and the third-4 sub-pixel is located between the third-1 sub-pixel and the third-2 sub-pixel; a third data line configured to electrically connect the pixel circuits of the first-3 sub-pixel, the second-2 sub-pixel, and the third-3 sub-pixel; a fourth-1 data line configured to electrically connect to the pixel circuit of the first-4 sub-pixel; a fourth-2 data line configured to electrically connect to the pixel circuit of the third-4 sub-pixel; and a second bridge wire, wherein the second bridge wire is located on a layer different from the third data line, the fourth-1 data line, and the fourth-2 data line, the second bridge wire has a side in contact with the fourth-1 data line and another side in contact with the fourth-2 data line, and the second bridge wire has a portion extending along at least a part of the third data line.

[0013] The first-3 sub-pixel, the first-4 sub-pixel, the second-2 sub-pixel, the third-3 sub-pixel, and the third-4 sub-pixel may be located on the substrate, wherein an orthographic projection image on the top surface of the substrate of the portion of the second bridge wire extending along at least a part of the third data line may overlap with the orthographic projection image on the top surface of the substrate of the third data line.

[0014] The third data line, the 4-1 data line, and the 4-2 data line may be located on the same layer as the first data line, the 2-1 data line, and the 2-2 data line, and the second bridging line may be located on the same layer as the first bridging line.

[0015] The first bridging line and the second bridging line may be located on an insulating layer covering the first data line, the 2-1 data line, the 2-2 data line, the third data line, the 4-1 data line, and the 4-2 data line.

[0016] The display panel may include a component area and a main display area surrounding the component area, where the 1-1 sub-pixels, the 1-2 sub-pixels, the 3-1 sub-pixels, and the 3-2 sub-pixels may be located in the main display area, and the 2-1 sub-pixel may be located in the component area.

[0017] The component area may include a transmissive area outside the 2-1 sub-pixel.

[0018] The display panel may further include an additional data line electrically connected to the pixel circuit of one sub-pixel in the component area, where the additional data line may extend along the edge of the transmissive area.

[0019] The resolution of the component area may be 1 / 2 or less than 1 / 2 of the resolution of the main display area.

[0020] The display panel may further include an auxiliary driving voltage line electrically connected to the pixel circuit of the 2-1 sub-pixel to apply a driving voltage to the pixel circuit of the 2-1 sub-pixel, where the auxiliary driving voltage line may be located in the component area, and is located on a layer different from the first data line and the first bridging line and overlaps with the first data line and the first bridging line.

[0021] The auxiliary driving voltage line may be located below the first data line and the first bridging line.

[0022] The display panel may further include: a driving voltage line in the main display area, the driving voltage line being electrically connected to the pixel circuit of the 1-1 sub-pixel to apply a driving voltage to the pixel circuit of the 1-1 sub-pixel.

[0023] The driving voltage line may be located on the layer where the first data line is located.

[0024] The width of the auxiliary driving voltage line may be greater than the width of the driving voltage line.

[0025] The display panel may further include: the 1st - 5th sub - pixels in the first row; the 3rd - 5th sub - pixels in the third row; and a fifth data line that electrically connects the pixel circuits of the 1st - 5th sub - pixels and the pixel circuits of the 3rd - 5th sub - pixels. The display panel may include a component area and a main display area surrounding the component area. The 1st - 1st sub - pixel, the 1st - 2nd sub - pixel, the 1st - 5th sub - pixel, the 3rd - 1st sub - pixel, the 3rd - 2nd sub - pixel, and the 3rd - 5th sub - pixel may be located in the main display area, and the 2nd - 1st sub - pixel may be located in the component area. The fifth data line may cross the component area but may not be connected to the pixel circuits of the sub - pixels in the component area.

[0026] The display panel may further include: the 1st - 6th sub - pixels in the first row; the 3rd - 6th sub - pixels in the third row; a 6 - 1 data line electrically connected to the 1st - 6th sub - pixel; a 6 - 2 data line electrically connected to the 3rd - 6th sub - pixel; and a third bridging line on a layer different from the 6 - 1 data line and the 6 - 2 data line. The third bridging line has one side in contact with the 6 - 1 data line and the other side in contact with the 6 - 2 data line. The third bridging line has a portion extending along at least a part of the fifth data line.

[0027] The 6 - 1 data line and the 6 - 2 data line may be located on the layer where the first data line, the 2 - 1 data line, and the 2 - 2 data line are located, and the third bridging line may be located on the layer where the first bridging line is located.

[0028] The first bridging line and the third bridging line may be located on an insulating layer covering the first data line, the 2 - 1 data line, the 2 - 2 data line, the 6 - 1 data line, and the 6 - 2 data line.

[0029] According to one or more exemplary embodiments, a display device includes: a display panel including a component area and a main display area surrounding the component area, and electronic components arranged to correspond to the component area of the display panel. The display panel includes the 1st - 1st sub - pixel and the 1st - 2nd sub - pixel arranged in the first row. The 2nd - 1st sub - pixel is arranged in the second row. The 3rd - 1st sub - pixel and the 3rd - 2nd sub - pixel are arranged in the third row. The first data line is configured to electrically connect the pixel circuits of the 1st - 1st sub - pixel, the pixel circuit of the 2nd - 1st sub - pixel, and the pixel circuit of the 3rd - 1st sub - pixel. The 2 - 1 data line is configured to electrically connect to the pixel circuit of the 1st - 2nd sub - pixel. The 2 - 2 data line is configured to electrically connect to the pixel circuit of the 3rd - 2nd sub - pixel. The first bridging line is arranged on a layer different from the first data line, the 2 - 1 data line, and the 2 - 2 data line. The first bridging line has a first side in contact with the 2 - 1 data line and a second side in contact with the 2 - 2 data line. The first bridging line has a portion extending along at least a part of the first data line.

[0030] The electronic components may include an imaging device.

[0031] According to an exemplary embodiment of the present invention concept, a display panel includes a component area surrounded by a main display area. The component area has a plurality of auxiliary sub-pixels and a transmissive area surrounding the plurality of auxiliary sub-pixels. The transmissive area is configured such that light is transmitted through the transmissive area. The main display area has a first plurality of main sub-pixels arranged in a lower row adjacent to the lower side of the component area and a second plurality of main sub-pixels arranged in an upper row adjacent to the upper side of the component area. At least one first data line extends from the lower row across the component area to the upper row. Each of the at least one first data lines is configured to electrically connect the sub-pixels in the lower row and the upper row to a first auxiliary sub-pixel. At least one lower second data line is configured to electrically connect to the sub-pixels in the lower row. At least one upper second data line is configured to electrically connect to the sub-pixels in the upper row. Each of the at least one bridge lines has a first end connected to one of the at least one lower second data lines and a second end connected to one of the at least one upper second data lines. The at least one bridge line is arranged on a layer different from the at least one first data line, and each of the at least one bridge lines has an overlapping portion extending along at least a part of one of the at least one first data lines.

[0032] According to one or more exemplary embodiments, a display panel includes: a first-1 sub-pixel and a first-2 sub-pixel, the first-1 sub-pixel and the first-2 sub-pixel are arranged in a main display area above a substrate, and the main display area is located outside a component area in a plan view; a second-1 sub-pixel and a second-2 sub-pixel, the second-1 sub-pixel and the second-2 sub-pixel are arranged in the component area above the substrate, the second-1 sub-pixel and the second-2 sub-pixel include thin film transistors, and each of the thin film transistors has a semiconductor layer; and a conductive layer, the conductive layer is arranged between the semiconductor layer and the substrate, and the conductive layer includes an opening having a polygonal shape in the component area in a plan view, and at least one inner angle of the opening is an obtuse angle.

[0033] In a plan view, the conductive layer overlaps with the thin film transistors of the second-1 sub-pixel and the second-2 sub-pixel.

[0034] In a plan view, the conductive layer overlaps with all the thin film transistors included in the second-1 sub-pixel and the second-2 sub-pixel.

[0035] In a plan view, the conductive layer overlaps with the pixel electrodes included in the second-1 sub-pixel and the second-2 sub-pixel.

[0036] The display panel further includes a metal layer, and the metal layer is arranged between the substrate and the thin film transistor included in the first-1 sub-pixel.

[0037] The metal layer overlaps with a part of the semiconductor layer of the thin film transistor of the first sub-pixel 1-1, and this part of the semiconductor layer overlaps with the gate electrode of the thin film transistor of the first sub-pixel 1-1.

[0038] The conductive layer and the metal layer are arranged on the same layer.

[0039] The opening of the conductive layer defines a transmissive area in the component area.

[0040] The light transmittance in the component area is different from that in the main display area.

[0041] The display panel further includes an organic insulating layer, which is arranged between the substrate and the pixel electrodes included in the second sub-pixel 2-1 and the second sub-pixel 2-2, and the organic insulating layer includes holes corresponding to the openings of the conductive layer.

[0042] The holes of the organic insulating layer overlap with the openings of the conductive layer in a plan view.

[0043] The group including the first sub-pixel 1-1 and the first sub-pixel 1-2 appears repeatedly in the main display area, and the group including the second sub-pixel 2-1 and the second sub-pixel 2-2 appears repeatedly in the component area.

[0044] The group including the second sub-pixel 2-1 and the second sub-pixel 2-2 is arranged above the conductive layer.

[0045] The group including the second sub-pixel 2-1 and the second sub-pixel 2-2 overlaps with the conductive layer in a plan view.

[0046] The opening of the conductive layer has an octagonal shape.

[0047] The display panel further includes a bridge wire, which transmits signals to the sub-pixels arranged beside the component area in the main display area.

[0048] The bridge wire overlaps with the conductive layer in the component area in a plan view.

[0049] The display panel further includes a driving voltage line, which is in the main display area, and the driving voltage line is electrically connected to the first sub-pixel 1-1 to apply a driving voltage to the first sub-pixel 1-1, wherein the conductive layer is electrically connected to the driving voltage line.

[0050] The driving voltage line is arranged on a layer different from the layer where the conductive layer is arranged.

[0051] The component area has a circular shape in a plan view.

[0052] According to one or more exemplary embodiments, a display panel includes: a first-1 sub-pixel and a first-2 sub-pixel, the first-1 sub-pixel and the first-2 sub-pixel are disposed in a main display area above a substrate, and the main display area is located outside a component area in a plan view; a second-1 sub-pixel and a second-2 sub-pixel, the second-1 sub-pixel and the second-2 sub-pixel are disposed in the component area above the substrate, the second-1 sub-pixel and the second-2 sub-pixel include thin film transistors, and each of the thin film transistors has a semiconductor layer; and a conductive layer, the conductive layer is disposed between the semiconductor layer and the substrate, the conductive layer includes an opening having a polygonal shape in the component area in a plan view, and the conductive layer overlaps with the thin film transistors of the second-1 sub-pixel and the second-2 sub-pixel in a plan view.

[0053] Other aspects, features, and advantages in addition to the above aspects, features, and advantages will be apparent from the detailed description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The above and other aspects, features, and advantages of exemplary embodiments of the inventive concept will become more apparent from the following description in conjunction with the drawings, in which:

[0055] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the inventive concept;

[0056] Figure 2 is a cross-sectional view of the display device taken along line A-A' according to an exemplary embodiment of the inventive concept; Figure 1 of;

[0057] Figure 3 is a plan view of a display panel that may be included in the display device according to an exemplary embodiment of the inventive concept; Figure 1 of;

[0058] Figure 4 is a plan view showing a pixel arrangement structure in a main display area of a display panel according to an exemplary embodiment of the inventive concept; Figure 3 of;

[0059] Figure 5 and Figure 6 is a plan view showing a pixel arrangement structure in a component area of a display panel according to an exemplary embodiment of the inventive concept; Figure 3 of;

[0060] Figure 7 and Figure 8 is an equivalent circuit diagram of a pixel circuit of a sub-pixel in a display panel according to an exemplary embodiment of the inventive concept; Figure 3 of;

[0061] Figure 9 is a cross-sectional view of a pixel arrangement structure taken along line I-I' of an exemplary embodiment according to the inventive concept and Figure 4 line II-II'; Figure 6 ;

[0062] Figure 10 and Figure 11 is a plan view showing an arrangement of sub-pixels and wiring lines of a display panel of an exemplary embodiment according to the inventive concept; Figure 3 ;

[0063] Figure 12 is a cross-sectional view of an arrangement of sub-pixels and wiring lines taken along line III-III' of an exemplary embodiment according to the inventive concept and Figure 10 ; Figure 11 ;

[0064] Figure 13 is a plan view showing an arrangement of driving voltage lines and auxiliary driving voltage lines of a display panel of an exemplary embodiment according to the inventive concept; Figure 3 ;

[0065] Figure 14 and Figure 15 are plan views showing an arrangement of sub-pixels and wiring lines of a display panel of an exemplary embodiment according to the inventive concept; and

[0066] Figure 16 and Figure 17 are plan views showing an arrangement of sub-pixels and wiring lines of a display panel of an exemplary embodiment according to the inventive concept. DETAILED DESCRIPTION

[0067] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the exemplary embodiments of the inventive concept may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the aspects of the inventive concept will be described only by referring to the accompanying drawings to explain the aspects of the inventive concept. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, or c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variants thereof.

[0068] Although exemplary embodiments of the inventive concept are shown in the drawings and described in the detailed description thereof, the exemplary embodiments of the inventive concept may have different modified embodiments. When referring to the exemplary embodiments described with reference to the drawings, the effects and features of the inventive concept and methods for achieving these will be apparent. However, the inventive concept may be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein.

[0069] Hereinafter, one or more exemplary embodiments of the inventive concept will be described in more detail with reference to the drawings. Irrespective of the reference numerals, those components that are the same or corresponding are denoted by the same reference numerals, and redundant explanations are omitted for convenience of explanation.

[0070] It will be understood that when a layer, region, or component is referred to as being "formed on" or "arranged on" another layer, region, or component, it may be directly or indirectly formed on the other layer, region, or component. For example, there may be an intermediate layer, region, or component. However, when a layer, region, or component is referred to as being "directly formed on" or "directly arranged on" another layer, region, or component, there may be no intermediate layer, region, or component. For convenience of explanation, the sizes of the elements in the drawings may be exaggerated. For example, since the sizes and thicknesses of the components in the drawings are arbitrarily shown for convenience of explanation, the following embodiments are not limited thereto.

[0071] In the following exemplary embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0072] Figure 1 is a schematic perspective view of a display device 1 according to an exemplary embodiment of the inventive concept.

[0073] Referring to Figure 1 the exemplary embodiment of, the display device 1 includes a display area DA and a peripheral area PA outside the display area DA. The display area DA includes a component area CA and a main display area MDA that at least partially surrounds the component area CA. In the exemplary embodiment, the component area CA and the main display area MDA may display an image separately or together. The peripheral area PA may be a non-display area in which no display elements are arranged. The display area DA may be completely surrounded by the peripheral area PA. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the display area DA may extend to at least one edge of the display device 1 and may not be surrounded by the peripheral area PA on at least one side.

[0074] Figure 1A component area CA is shown to be located in the main display area MDA. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the display device 1 may have a plurality of component areas CA. The shape and size of each of the plurality of component areas CA may be the same, or the shape and size of at least one of the plurality of component areas CA may be different from each other. The plurality of component areas CA may be arranged in various different arrangements in the display area DA.

[0075] Hereinafter, the organic light emitting display device will be described as the display device 1 according to an exemplary embodiment of the inventive concept. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the display device 1 may be an inorganic light emitting display device (or an inorganic electroluminescence (EL) display device), a quantum dot light emitting display device, etc. For example, the emission layer of the display element of the display device 1 may include an organic material, an inorganic material, quantum dots, an organic material and quantum dots, or an inorganic material and quantum dots.

[0076] In Figure 1 the exemplary embodiment, the component area CA is shown to have a substantially circular shape. However, the exemplary embodiments of the inventive concept are not limited thereto, and when viewed in a direction substantially perpendicular to the upper surface of the substrate (e.g., in a plan view in the plane defined by the x-direction and the y-direction), the component area CA may have one of various shapes including an ellipse, a polygon (such as a square, a star, and a rhombus), an irregular shape, etc.

[0077] In Figure 1 the exemplary embodiment, when viewed in a direction substantially perpendicular to the upper surface of the substrate (e.g., in a plan view in the plane defined by the x-direction and the y-direction), the component area CA is arranged at the center (e.g., in the x-direction) on the upper side (+y direction) of the main display area MDA having a substantially rectangular shape. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, the component area CA may be arranged in various different areas of the main display area MDA, such as on one side in the x-direction (e.g., the upper right side or the upper left side) of the main display area MDA having a substantially rectangular shape. Although the main display area MDA is Figure 1 shown to have a substantially rectangular shape in the exemplary embodiment, the exemplary embodiments of the inventive concept are not limited thereto. In other exemplary embodiments, the main display area MDA may have various different shapes including a spherical shape, a polygon, and an irregular shape.

[0078] The display device 1 can provide an image by using a plurality of main sub-pixels Pm arranged in the main display area MDA and a plurality of auxiliary sub-pixels Pa arranged in the component area CA.

[0079] As described in the exemplary embodiments with reference to Figure 2 below, the component 20 as an electronic component can be arranged below the component area CA. In the exemplary embodiment, the component 20 is a camera using infrared light or visible light and can include an imaging device. Alternatively, the component 20 can have a function of receiving sound. In order to reduce the functional limitations of the component 20, the component area CA can include a transmission area TA for transmitting light and / or sound output from the component 20 to the outside and / or transmitting light and / or sound from the outside to the component 20. The transmission area TA may not include pixels or sub-pixels. Through the display panel 10 according to an exemplary embodiment of the present invention concept and the display device 1 having the display panel 10 according to an exemplary embodiment of the present invention concept, when infrared light passes through the component area CA, the light transmittance can be about 10% or more, for example, about 20% or more, about 25% or more, about 50% or more, about 85% or more, or about 90% or more.

[0080] A plurality of auxiliary sub-pixels Pa can be arranged in the component area CA. The plurality of auxiliary sub-pixels Pa can emit light to generate an image. The image displayed in the component area CA is an auxiliary image and can have a lower resolution than the image displayed in the main display area MDA. Since the component area CA includes a transmission area TA capable of transmitting light and sound and no sub-pixels are arranged in the transmission area TA, the number of auxiliary sub-pixels Pa that can be arranged per unit area can be less than the number of main sub-pixels Pm arranged per unit area in the main display area MDA.

[0081] Figure 2 is a schematic cross-sectional view of a part of the display device 1 taken along the Figure 1 line A-A' according to an exemplary embodiment of the present invention concept.

[0082] Referring to Figure 2 the exemplary embodiment of, the display device 1 can include a display panel 10 and a component 20, where the display panel 10 includes display elements, and the component 20 is located below the display panel 10 (for example, in the -z direction) and is an electronic component corresponding to the component area CA.

[0083] The display panel 10 can include a substrate 100, a display element layer 200 arranged on the substrate 100, and a thin film encapsulation layer 300 for sealing the display element layer 200. The display panel 10 can also include various components. For example, as Figure 2As shown in the exemplary embodiment, the display panel 10 may further include a lower protective film 175 and the like disposed under the substrate 100.

[0084] In the exemplary embodiment, the substrate 100 may include glass or a polymer resin. For example, the substrate 100 may include a polymer resin such as at least one compound selected from polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate. The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer containing the aforementioned polymer resin and an inorganic layer. For example, the substrate 100 may include two layers including the aforementioned polymer resin and an inorganic barrier layer interposed therebetween. However, the exemplary embodiment of the inventive concept is not limited thereto.

[0085] The display element layer 200 may include a circuit layer including a thin film transistor (TFT), an organic light emitting diode (OLED) as a display element, and an insulating layer (IL) disposed between the circuit layer and the organic light emitting diode (OLED).

[0086] The main sub-pixels Pm are arranged in the main display area (MDA). The main sub-pixels Pm include a pixel circuit including a thin film transistor (TFT) and an organic light emitting diode (OLED) electrically connected to the pixel circuit. In addition, the wiring lines electrically connected to the main sub-pixels Pm and the auxiliary sub-pixels Pa may be arranged in the main display area (MDA).

[0087] In the component area (CA), the auxiliary sub-pixels Pa are arranged. The auxiliary sub-pixels Pa include a pixel circuit including a thin film transistor (TFT) and an organic light emitting diode (OLED) electrically connected to the pixel circuit. In addition, the component area (CA) may have a transmissive area (TA) that does not include a thin film transistor (TFT) and in which no sub-pixels are arranged. The transmissive area (TA) is an area through which at least part of the light / sound / signal emitted from the component 20 or the light / sound / signal incident on the component 20 (e.g., from the external environment) may pass.

[0088] A component 20 located below the display panel 10 (e.g., in the -z direction) may be positioned corresponding to the component area CA. The component 20 may be an electronic component using light or sound. For example, the component 20 may be an imaging device such as a camera, a sensor that receives and uses light (such as an infrared sensor), a sensor that outputs and senses light or sound to measure distance or identify fingerprints or the like, a small lamp that outputs light, or a speaker that outputs sound. However, the exemplary embodiments of the inventive concept are not limited thereto. The electronic component using light may use light in different wavelength bands, such as visible light, infrared light, and ultraviolet light. In the component area CA, one component 20 may be arranged or multiple components 20 may be arranged. For example, a first component (such as a light-emitting element) and a second component (such as a light-receiving element) may be arranged corresponding to one component area CA. Alternatively, one component 20 may include a light-emitting portion and a light-receiving portion, and may be arranged corresponding to one component area CA.

[0089] In an exemplary embodiment, the thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 2 As an example, it is shown that the thin film encapsulation layer 300 (e.g., in the z direction) includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 therebetween. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0090] In an exemplary embodiment, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulating materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may include a polymer material. For example, the polymer material may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, an acrylic resin (e.g., polymethyl methacrylate or polyacrylic acid), or any combination thereof.

[0091] The lower protective film 175 may be attached to the lower surface of the substrate 100 and may support and protect the substrate 100. For example, as shown in the exemplary embodiment of Figure 2 , the upper surface of the lower protective film 175 may directly contact the lower surface of the substrate 100. The lower protective film 175 may have an opening 175OP corresponding to the component area CA. Since the lower protective film 175 has the opening 175OP, light / sound passing through the component area CA may be guided to the component 20, or light / sound from the component 20 may enter the component area CA. In an exemplary embodiment, the lower protective film 175 may include polyethylene terephthalate or polyimide.

[0092] The area of the component region CA (e.g., the area in the x and y directions) may be larger than the area where the components 20 are arranged. Although in Figure 2 the component region CA and the opening 175OP in the lower protective film 175 have the same area, this is only an example. The area of the opening 175OP in the lower protective film 175 may not be equal to the area of the component region CA. For example, the area of the opening 175OP may be smaller than the area of the component region CA.

[0093] Although Figure 2 not shown in

[0094] In Figure 2 as described above, the thin film encapsulation layer 300 serves as an encapsulation member for sealing the display element layer 200. However, the exemplary embodiments of the present inventive concept are not limited thereto. For example, an encapsulation substrate coupled to the substrate 100 by a sealant or frit may be used as a member for sealing the display element layer 200.

[0095] Figure 3 is a schematic plan view of a display panel 10 that may be included in Figure 1 a display device 1 according to an exemplary embodiment of the present inventive concept.

[0096] Referring to Figure 3 the exemplary embodiment of

[0097] various components constituting the display panel 10 are arranged on the substrate 100. The substrate 100 includes a display area DA and a peripheral area PA (e.g., in the x and y directions) surrounding the display area DA. The display area DA includes a main display area MDA and a component area CA, where a main image is displayed on the main display area MDA, the component area CA includes a transmissive area TA, and an auxiliary image is displayed on the component area CA. In the exemplary embodiment, the auxiliary image may form an integral image together with the main image, and the auxiliary image may be an image independent of the main image. Figure 2 As described above with reference to

[0098] The component area CA may be arranged within the main display area MDA, and a plurality of auxiliary sub-pixels Pa are arranged in the component area CA. Each of the plurality of auxiliary sub-pixels Pa may include a display element such as an organic light emitting diode. Each of the plurality of auxiliary sub-pixels Pa may emit, for example, red light, green light, blue light, or white light. However, the exemplary embodiments of the inventive concept are not limited thereto. As described above with reference to Figure 2 As described, the thin film encapsulation layer 300 may cover the component area CA to protect it from ambient air or moisture.

[0099] The component area CA may include a transmissive area TA. The transmissive area TA may be arranged to surround the plurality of auxiliary sub-pixels Pa. Alternatively, the transmissive area TA may be arranged in a lattice shape with the plurality of auxiliary sub-pixels Pa (see Figure 10 ).

[0100] Since the component area CA includes the transmissive area TA, the resolution of the component area CA may be lower than the resolution of the main display area MDA. For example, in an exemplary embodiment, the resolution of the component area CA may be about 1 / 2, about 3 / 8, about 1 / 3, about 1 / 4, about 2 / 9, about 1 / 8, about 1 / 9, about 1 / 16, or a similar value of the resolution of the main display area MDA. For example, in an exemplary embodiment, the resolution of the main display area MDA may be about 400 ppi or more, and the resolution of the component area CA may be about 200 ppi or about 100 ppi.

[0101] Each of the main sub-pixels Pm and the auxiliary sub-pixels Pa may be electrically connected to an external circuit arranged in the peripheral area PA. A first scan driving circuit 110, a second scan driving circuit 120, a terminal 140, a first power supply line 160, and a second power supply line 170 may be arranged in the peripheral area PA.

[0102] The first scan driving circuit 110 may apply a scan signal to each of the main sub-pixels Pm and the auxiliary sub-pixels Pa through the scan lines SL. In addition, the first scan driving circuit 110 may apply an emission control signal to each pixel through the emission control line EL. The second scan driving circuit 120 may be located on the opposite side of the first scan driving circuit 110 with respect to the main display area MDA (e.g., in the +x direction), and may be substantially parallel to the first scan driving circuit 110. The first plurality of main sub-pixels Pm in the main display area MDA may be electrically connected to the first scan driving circuit 110, and the remaining main sub-pixels Pm (e.g., the second plurality of main sub-pixels Pm) may be electrically connected to the second scan driving circuit 120. The second scan driving circuit 120 may apply a scan signal and an emission control signal to the main sub-pixels Pm in the main display area MDA that are electrically connected to the second scan driving circuit 120 via the scan lines SL and the emission control line EL. The first plurality of auxiliary sub-pixels Pa in the component area CA may be electrically connected to the first scan driving circuit 110, and the remaining auxiliary sub-pixels Pa (e.g., the second plurality of auxiliary sub-pixels Pa) may be electrically connected to the second scan driving circuit 120. The second scan driving circuit 120 may apply a scan signal and an emission control signal to the auxiliary sub-pixels Pa in the component area CA that are electrically connected to the second scan driving circuit 120 via the scan lines SL and the emission control line EL.

[0103] Alternatively, each of the main sub-pixels Pm in the main display area MDA may be electrically connected to both the first scan driving circuit 110 and the second scan driving circuit 120, and thus may receive a scan signal via the scan line SL connected to both the first scan driving circuit 110 and the second scan driving circuit 120 and receive an emission control signal via the emission control line EL connected to both the first scan driving circuit 110 and the second scan driving circuit 120. Each of the auxiliary sub-pixels Pa in the component area CA may also be electrically connected to both the first scan driving circuit 110 and the second scan driving circuit 120, and thus may receive a scan signal via the scan line SL connected to both the first scan driving circuit 110 and the second scan driving circuit 120 and receive an emission control signal via the emission control line EL connected to both the first scan driving circuit 110 and the second scan driving circuit 120.

[0104] However, the exemplary embodiments of the inventive concept are not limited thereto, and in some exemplary embodiments, the second scan driving circuit 120 may be omitted. In such an embodiment, all of the main sub-pixels Pm in the main display area MDA may be electrically connected to the first scan driving circuit 110, and similarly, all of the auxiliary sub-pixels Pa in the component area CA may be electrically connected to the first scan driving circuit 110.

[0105] As a reference, although the first scan driving circuit 110 is shown as one component in Figure 3 , exemplary embodiments of the inventive concept are not limited thereto. For example, the first scan driving circuit 110 may include a first scan signal driving circuit and a first emission control driving circuit separated from each other (e.g., in the x-direction and / or y-direction). In this embodiment, the first scan signal driving circuit may be electrically connected to the scan line SL, and the first emission control driving circuit may be electrically connected to the emission control line EL. The second scan driving circuit 120 may also include a second scan signal driving circuit and a second emission control driving circuit separated from each other. In this embodiment, the second scan signal driving circuit may be electrically connected to the scan line SL, and the second emission control driving circuit may be electrically connected to the emission control line EL.

[0106] The terminals 140 may be arranged on one side of the substrate 100. For example, as shown in an exemplary embodiment of Figure 3 , the terminals 140 may be arranged on the lower side (e.g., in the -y direction) of the substrate 100. The terminals 140 may be exposed without being covered by an insulating layer and electrically connected to the printed circuit board PCB. The terminals PCB-P of the printed circuit board PCB may be electrically connected to the terminals 140 of the display panel 10. The printed circuit board PCB transmits signals or power of the controller to the display panel 10. The control signal generated by the controller may be transmitted to each of the first scan driving circuit 110 and the second scan driving circuit 120 through the printed circuit board PCB. The controller may provide the first power voltage ELVDD (see Figure 7 and Figure 8 ) to the first power line 160 through the first connection line 161, and may provide the second power voltage ELVSS (see Figure 7 and Figure 8 ) to the second power line 170 through the second connection line 171. The first power voltage ELVDD may be applied to each of the main sub-pixels Pm and the auxiliary sub-pixels Pa through the driving voltage line PL connected to the first power line 160, and the second power voltage ELVSS may be applied to the opposite electrodes of each of the main sub-pixels Pm and the auxiliary sub-pixels Pa connected to the second power line 170. The first power voltage ELVDD may be referred to as a driving voltage. Hereinafter, for convenience, the first power voltage ELVDD will be referred to as a driving voltage.

[0107] The data driving circuit 150 is electrically connected to the data line DL. The data signals of the data driving circuit 150 may be applied to the main sub-pixels Pm and the auxiliary sub-pixels Pa through the connection line 151 connected to the terminals 140 and the data line DL connected to the connection line 151. Although Figure 3Exemplary embodiments show the data driving circuit 150 arranged on a printed circuit board (PCB), but exemplary embodiments of the inventive concept are not limited thereto, and in other exemplary embodiments, the data driving circuit 150 may be arranged on the substrate 100. For example, the data driving circuit 150 may be arranged (e.g., in the y direction) between the terminal 140 and the first power line 160.

[0108] The first power line 160 may include a first sub-line 162 extending in the x-axis direction and spaced apart from the first power line 160 in the y direction, and a second sub-line 163, wherein the main display area (MDA) is located between the first sub-line 162 and the second sub-line 163. The second sub-line 163 located in the +y direction of the main display area MDA may be electrically connected to the first sub-line 162 located in the -y direction of the main display area MDA via some of the driving voltage lines (PL) extending along the y-axis, so as to span the main display area MDA, as Figure 3 shown. For example, some of the driving voltage lines (PL) may be electrically connected only to the first sub-line 162, some of the driving voltage lines (PL) may be electrically connected only to the second sub-line 163, and some of the driving voltage lines (PL) may be electrically connected to both the first sub-line 162 and the second sub-line 163. Alternatively, the line may be located in the peripheral area (PA) such that the line may electrically connect the second sub-line 163 to the first sub-line 162.

[0109] The second power line 170 may have an annular shape, where the annular shape has an open side (e.g., the lower side in the y direction) and partially surrounds the main display area (MDA).

[0110] Figure 4 is a schematic plan view showing the pixel arrangement structure in the main display area (MDA) of the display panel 10, and Figure 3 and Figure 5 and Figure 6 is a schematic plan view showing the pixel arrangement structure in the component area (CA) of the display panel 10 according to an exemplary embodiment of the inventive concept. Figure 3

[0111] As Figure 4 shown in the exemplary embodiment, a plurality of main sub-pixels (Pm) may be arranged in the main display area (MDA). Each of the plurality of main sub-pixels (Pm) may include a display element such as an organic light-emitting diode. Each of the plurality of main sub-pixels (Pm) may emit one of red light, green light, blue light, and white light. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, the plurality of main sub-pixels (Pm) may include a main sub-pixel (Pr) emitting red light, a main sub-pixel (Pg) emitting green light, and a main sub-pixel (Pb) emitting blue light. In Figure 4 ​In an exemplary embodiment, a plurality of main sub-pixels Pm are arranged in a pentile type. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the plurality of main sub-pixels Pm may be arranged in a stripe shape or various other shapes.

[0112] As Figure 5 As shown in an exemplary embodiment, a plurality of auxiliary sub-pixels Pa may be arranged in the component area CA. Each of the plurality of auxiliary sub-pixels Pa may include a display element such as an organic light emitting diode. Each of the plurality of auxiliary sub-pixels Pa may emit one of red light, green light, blue light, and white light. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0113] The component area CA may include a pixel group PG including at least one auxiliary sub-pixel Pa and a transmissive area TA. As Figure 5 As shown in an exemplary embodiment, the pixel group PG and the transmissive area TA may be alternately arranged in the x-axis direction and the y-axis direction, and for example, may be arranged in a lattice shape. However, the exemplary embodiments of the inventive concept are not limited thereto. As Figure 5 As shown in an exemplary embodiment, the component area CA may include a plurality of pixel groups PG and a plurality of transmissive areas TA.

[0114] The pixel group PG may be defined as a set of sub-pixels in which a plurality of auxiliary sub-pixels Pa or main sub-pixels Pm are grouped in a preset unit. In Figure 5 and Figure 6 In an exemplary embodiment, one pixel group PG includes eight auxiliary sub-pixels Pa. In other words, in Figure 5 and Figure 6 , one pixel group PG includes a red sub-pixel Pr, a green sub-pixel Pg, a blue sub-pixel Pb, and a green sub-pixel Pg arranged in the x-axis direction in the first row and a blue sub-pixel Pb, a green sub-pixel Pg, a red sub-pixel Pr, and a green sub-pixel Pg arranged in parallel in the x-axis direction in a second row different from the first row. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, the number or arrangement of the auxiliary sub-pixels Pa included in the pixel group PG may be modified according to the resolution of the component area CA. In addition, it can be understood that Figure 5 One pixel group PG shown in Figure 4As shown in the exemplary embodiments, for the main sub-pixels Pm in the main display area MDA, the pixel group PG can be defined in the same manner. The description of the pixel group PG of the auxiliary sub-pixels Pa, which will be described later, can also be applied to the pixel group PG of the main sub-pixels Pm. However, the exemplary embodiments of the inventive concept are not limited thereto, and in some exemplary embodiments, the pixel group PG for the main sub-pixels Pm may have a different number of sub-pixels or a different sub-pixel arrangement from the pixel group PG for the auxiliary sub-pixels Pa.

[0115] As described above, the pixel group PG may include eight auxiliary sub-pixels Pa, and Figure 5 shows that the auxiliary sub-pixels Pa are arranged in a pentile type. However, the auxiliary sub-pixels Pa may be arranged in a stripe shape or various other shapes.

[0116] The transmissive area TA may be arranged on one side of the pixel group PG. For example, as Figure 5 shown in the exemplary embodiments, a plurality of transmissive areas TA and a plurality of pixel groups PG are alternately arranged in a lattice shape. However, as Figure 6 shown, a plurality of transmissive areas TA may be arranged to surround one pixel group PG. In this embodiment, the plurality of transmissive areas TA may be adjacent to each other in the x direction and / or the y direction, and the transmissive areas TA and the pixel group PG are not arranged in a lattice shape.

[0117] The transmissive area TA is a part of the component area CA where at least some of the components included in the auxiliary sub-pixels Pa are not arranged. For example, in the transmissive area TA, at least some of the pixel electrodes included in the organic light-emitting diode OLED, the intermediate layer including the emission layer, and the counter electrode may not be arranged, or at least a part of the pixel circuit electrically connected to the organic light-emitting diode OLED may not be arranged. Some signal lines among the data line DL, the scan line SL, and the emission control line EL (see Figure 3 ) that are connected to provide signals to some of the auxiliary sub-pixels Pa located in the component area CA may be arranged to cross the transmissive area TA. However, even in this embodiment, the data line DL, the scan line SL, and the emission control line EL may be arranged to be biased toward the edge of the transmissive area TA rather than toward the center of the transmissive area TA to increase light / sound transmission in the transmissive area TA.

[0118] Although Figure 5 and Figure 6 are not shown in the exemplary embodiments, a metal layer may be arranged on the substrate 100 corresponding to the pixel group PG of the component area CA. For example, the metal layer may be arranged (e.g., in the z direction) between the thin-film transistor TFT of the auxiliary sub-pixel Pa and the substrate 100. The metal layer may block the light emitted from the component 20 or the external light guided to the component 20 from entering the pixel circuit PC of the auxiliary sub-pixel Pa (seeFigure 7 and Figure 8 ). Further, the metal layer can prevent light diffraction caused by minute gaps between one line route and another line route, or reduce the degree of light diffraction. A constant voltage or signal can be applied to the metal layer to prevent damage to the pixel circuit PC due to electrostatic discharge. In an exemplary embodiment, multiple metal layers can be arranged in the component area CA, and in some cases, different voltages can be applied to at least one of the multiple metal layers. A single metal layer in a lattice form can be located in the component area CA.

[0119] Figure 7 and Figure 8 is of an exemplary embodiment according to the inventive concept Figure 3 equivalent circuit diagram of the pixel circuit PC of a sub-pixel in the display panel 10.

[0120] Referring to Figure 7 the exemplary embodiment of

[0121] each main sub-pixel Pm or auxiliary sub-pixel Pa includes a pixel circuit PC electrically connected to a scan line SL and a data line DL, and an organic light-emitting diode OLED electrically connected to the pixel circuit PC.

[0122] The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 is electrically connected to the scan line SL and the data line DL, and is configured to transmit a data signal Dm received via the data line DL to the driving thin-film transistor T1 according to a scan signal Sn received via the scan line SL.

[0123] The storage capacitor Cst is electrically connected to the switching thin-film transistor T2 and a driving voltage line PL. The storage capacitor Cst stores a voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the driving voltage ELVDD provided to the driving voltage line PL.

[0124] Although the pixel circuit PC shown in the exemplary embodiment of Figure 7 includes two thin-film transistors and one storage capacitor, the exemplary embodiment of the inventive concept is not limited thereto. For example, as shown in the exemplary embodiment of Figure 8 the pixel circuit PC can include seven thin-film transistors and one storage capacitor. Although Figure 7In the exemplary embodiment shown, the pixel circuit PC includes a storage capacitor. However, in other exemplary embodiments, the pixel circuit PC may include two or more storage capacitors. Further, although in Figure 7 the exemplary embodiment shown, both the driving thin film transistor T1 and the switching thin film transistor T2 have single gate electrodes, in other exemplary embodiments, at least one of the transistors may have a double gate electrode or the like.

[0125] Referring to Figure 8 the exemplary embodiment, each main sub-pixel Pm or auxiliary sub-pixel Pa includes a pixel circuit PC and an organic light emitting diode OLED electrically connected to the pixel circuit PC. The pixel circuit PC may include a plurality of thin film transistors and a storage capacitor Cst. The thin film transistors and the storage capacitor Cst may be electrically connected to signal lines such as a scan line SL, a previous scan line SL-1, an emission control line EL, and a data line DL. The thin film transistors and the storage capacitor Cst may also be electrically connected to an initialization voltage line VL and a driving voltage line PL.

[0126] Although in Figure 8 the exemplary embodiment, each main sub-pixel Pm or auxiliary sub-pixel Pa is electrically connected to the signal lines, the initialization voltage line VL, and the driving voltage line PL, the exemplary embodiments of the inventive concept are not limited thereto. For example, at least one of the signal lines, the initialization voltage line VL, and the driving voltage line PL may be shared by adjacent sub-pixels.

[0127] The signal lines include a scan line SL configured to transmit a scan signal Sn, a previous scan line SL-1 that transmits a previous scan signal Sn-1 to a first initialization thin film transistor T4 and a second initialization thin film transistor T7, an emission control line EL that transmits an emission control signal En to an operation control thin film transistor T5 and an emission control thin film transistor T6, and a data line DL that intersects the scan line SL and transmits a data signal Dm. The driving voltage line PL is configured to transmit a driving voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VL transmits an initialization voltage Vint to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, where the initialization voltage Vint initializes the pixel electrode of the driving thin film transistor T1 and the organic light emitting diode OLED.

[0128] The driving thin film transistor T1 includes a driving gate electrode G1 connected to a lower electrode CE1 of the storage capacitor Cst, a driving source electrode S1 connected to the driving voltage line PL via the operation control thin film transistor T5, and a driving drain electrode D1 electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2, and outputs a driving current IOLED Provided to the organic light emitting diode (OLED).

[0129] The switching thin film transistor T2 includes a switching gate electrode G2 connected to the scan line SL, a switching source electrode S2 connected to the data line DL, and a switching drain electrode D2. The switching drain electrode D2 is connected to the driving source electrode S1 of the driving thin film transistor T1 and is also connected to the driving voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on according to the scan signal Sn received via the scan line SL, and performs a switching operation of transmitting the data signal Dm received from the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0130] The compensation thin film transistor T3 includes a compensation gate electrode G3 connected to the scan line SL, a compensation source electrode S3 connected to the driving drain electrode D1 of the driving thin film transistor T1 and also connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6, and a compensation drain electrode D3 connected to the lower electrode CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on according to the scan signal Sn received via the scan line SL, and electrically connects the driving gate electrode G1 and the driving drain electrode D1 of the driving thin film transistor T1 to each other, so that the driving thin film transistor T1 is diode-connected. As Figure 8 shown in the exemplary embodiment of, the compensation gate electrode G3 may be a double gate electrode.

[0131] The first initialization thin film transistor T4 includes a first initialization gate electrode G4 connected to the previous scan line SL-1, a first initialization source electrode S4 connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL, and a first initialization drain electrode D4 connected to the lower electrode CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on according to the previous scan signal Sn-1 received via the previous scan line SL-1, and is configured to transmit the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1, thereby initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1. As Figure 8 shown in the exemplary embodiment of, the first initialization thin film transistor T4 may be a double gate electrode.

[0132] The operation control thin film transistor T5 includes an operation control gate electrode G5 connected to the emission control line EL, an operation control source electrode S5 connected to the driving voltage line PL, and an operation control drain electrode D5, where the operation control drain electrode D5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0133] The emission control thin film transistor T6 includes an emission control gate electrode G6 connected to the emission control line EL, an emission control source electrode S6 connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and an emission control drain electrode D6, where the emission control drain electrode D6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0134] The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on according to the emission control signal En received via the emission control line EL, and thus the driving voltage ELVDD is transmitted to the organic light emitting diode OLED so that the driving current I OLED can flow in the organic light emitting diode OLED.

[0135] The second initialization thin film transistor T7 includes a second initialization gate electrode G7 connected to the previous scan line SL-1, a second initialization source electrode S7 connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and a second initialization drain electrode D7 connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 is turned on according to the previous scan signal Sn-1 received via the previous scan line SL-1 and initializes the pixel electrode of the organic light emitting diode OLED.

[0136] Although in Figure 8 the exemplary embodiment the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the previous scan line SL-1, the exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, the first initialization thin film transistor T4 may be connected to the previous scan line SL-1 and operate according to the previous scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to a separate signal line (e.g., the next scan line, etc.) and operate according to the signal transmitted from the separate signal line.

[0137] The upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL, and the opposite electrode of the organic light-emitting diode OLED is connected to the second power supply voltage ELVSS. Thus, the organic light-emitting diode OLED can receive the driving current I from the driving thin film transistor T1 OLED and emit light, thereby displaying an image.

[0138] Although in Figure 8 the exemplary embodiments of, each of the compensation thin film transistor T3 and the first initialization thin film transistor T4 has a double gate electrode, in other exemplary embodiments, at least one of the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have a single gate electrode.

[0139] Figure 9 is a schematic cross-sectional view of a pixel arrangement structure taken along line I-I' of Figure 4 and line II-II' of Figure 6 according to an exemplary embodiment of the inventive concept.

[0140] As described above, the display panel 10 includes a main display area MDA and a component area CA. A plurality of main sub-pixels Pm are arranged in the main display area MDA, and a plurality of auxiliary sub-pixels Pa are arranged in the component area CA. The component area CA includes a transmissive area TA.

[0141] The main sub-pixel Pm may include a main thin film transistor TFT, a main storage capacitor Cst, and an organic light-emitting diode OLED. The auxiliary sub-pixel Pa may include an auxiliary thin film transistor TFT', an auxiliary storage capacitor Cst', and an organic light-emitting diode OLED'. The display panel 10 may have a transmissive hole TAH corresponding to the transmissive area TA.

[0142] The first metal layer BSM1 may be arranged below (e.g., in the -z direction) the main thin film transistor TFT of the main sub-pixel Pm to overlap with the main thin film transistor TFT. The second metal layer BSM2 may be arranged below (e.g., in the -z direction) the auxiliary thin film transistor TFT' of the auxiliary sub-pixel Pa to overlap with the auxiliary thin film transistor TFT'. However, the exemplary embodiments of the inventive concept are not limited thereto, and the display panel 10 may have various modifications. For example, the first metal layer BSM1 arranged to overlap with the main thin film transistor TFT may be omitted.

[0143] Hereinafter, the stacked structure of the display panel 10 will be described.

[0144] As described above, the substrate 100 may include a polymer resin. As Figure 9As shown in the exemplary embodiments, the substrate 100 includes, for example, in the z direction, a first base layer 101, a first inorganic layer 102, a second base layer 103, and a second inorganic layer 104 that are sequentially stacked. Each of the first base layer 101 and the second base layer 103 may include a polymer resin as described above. Each of the first inorganic layer 102 and the second inorganic layer 104 is a barrier layer that prevents impurities from penetrating from the outside. In the exemplary embodiments, the first inorganic layer 102 and the second inorganic layer 104 may include inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON), and may have a single-layer structure or a multi-layer structure.

[0145] A buffer layer 111 may be disposed on the substrate 100 to prevent or reduce the penetration of impurities from the bottom of the substrate 100, and may also be used to provide a flat surface on the substrate 100 to planarize it. In the exemplary embodiments, the buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic compound. The buffer layer 111 may have a single-layer structure or may have a multi-layer structure.

[0146] As described above, the first metal layer BSM1 and the second metal layer BSM2 may be disposed, for example, in the z direction, between the substrate 100 and the buffer layer 111. For example, the first metal layer BSM1 and the second metal layer BSM2 may be directly disposed between the second inorganic layer 104 and the buffer layer 111. However, the exemplary embodiments of the inventive concept are not limited thereto, and in other exemplary embodiments, the first metal layer BSM1 and the second metal layer BSM2 may be disposed below the second inorganic layer 104. For example, the first metal layer BSM1 and the second metal layer BSM2 may be directly disposed between the second base layer 103 and the second inorganic layer 104. Alternatively, the first metal layer BSM1 and the second metal layer BSM2 may be arranged on different layers.

[0147] Each of the first metal layer BSM1 and the second metal layer BSM2 may be connected to a conductive line CL arranged on another layer through a contact hole. In the exemplary embodiments, a constant voltage or signal may be applied to the first metal layer BSM1 and the second metal layer BSM2 from the conductive line CL. For example, a driving voltage ELVDD or a scan signal may be applied to the first metal layer BSM1 and the second metal layer BSM2. By applying a constant voltage or signal to the first metal layer BSM1 and the second metal layer BSM2, the probability that the pixel circuit PC is damaged due to electrostatic discharge can be significantly reduced. However, the exemplary embodiments of the inventive concept are not limited thereto, and in other exemplary embodiments, an electrical signal may not be applied to the first metal layer BSM1 and the second metal layer BSM2. In another exemplary embodiment, one of the first metal layer BSM1 and the second metal layer BSM2 may be electrically floating, and an electrical signal may be applied to the other metal layer.

[0148] In an exemplary embodiment, each of the first metal layer BSM1 and the second metal layer BSM2 may include at least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). Additionally, the first metal layer BSM1 and the second metal layer BSM2 may each have a single-layer structure or a multi-layer structure.

[0149] The main thin film transistor TFT and the auxiliary thin film transistor TFT' may be disposed on the buffer layer 111. For example, as Figure 9 shown in an exemplary embodiment, the main thin film transistor TFT and the auxiliary thin film transistor TFT' are directly disposed on the buffer layer 111. The main thin film transistor TFT includes a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The auxiliary thin film transistor TFT' includes a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The main thin film transistor TFT may be electrically connected to the organic light-emitting diode OLED of the main sub-pixel Pm in the main display area MDA to drive the organic light-emitting diode OLED. The auxiliary thin film transistor TFT' may be electrically connected to the organic light-emitting diode OLED' of the auxiliary sub-pixel Pa in the component area CA to drive the organic light-emitting diode OLED'.

[0150] In an exemplary embodiment, the first semiconductor layer A1 and the second semiconductor layer A2 may be disposed on the buffer layer 111 and may each include polysilicon or amorphous silicon. However, the exemplary embodiments of the present inventive concept are not limited thereto. For example, in another exemplary embodiment, each of the first semiconductor layer A1 and the second semiconductor layer A2 may include an oxide of at least one material selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). Each of the first semiconductor layer A1 and the second semiconductor layer A2 may include a channel region and source and drain regions doped with impurities.

[0151] The first semiconductor layer A1 may overlap with the first metal layer BSM1 (e.g., in the z direction), while the buffer layer 111 is located therebetween. The area of the first semiconductor layer A1 (e.g., in the plane defined by the x direction and the y direction) may be smaller than the area of the first metal layer BSM1, and thus, when viewed in a direction perpendicular to the substrate 100 (e.g., the -z direction), the entire portion of the first semiconductor layer A1 may overlap with the first metal layer BSM1.

[0152] The second semiconductor layer A2 may overlap with the second metal layer BSM2 (e.g., in the z direction), while the buffer layer 111 is located therebetween. The area of the second semiconductor layer A2 (e.g., in the plane defined by the x and y directions) may be smaller than the area of the second metal layer BSM2, and thus, when viewed in a direction perpendicular to the substrate 100 (e.g., the -z direction), the entire portion of the second semiconductor layer A2 may overlap with the second metal layer BSM2.

[0153] The first gate insulating layer 112 covers the first semiconductor layer A1 and the second semiconductor layer A2. For example, as shown in the exemplary embodiment of Figure 9 , the lower surface of the first gate insulating layer 112 may be directly disposed on the upper surfaces of the buffer layer 111, the first semiconductor layer A1, and the second semiconductor layer A2. In an exemplary embodiment, the first gate insulating layer 112 may include an inorganic insulating material such as at least one compound selected from silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The first gate insulating layer 112 may have a single-layer structure or may have a multi-layer structure.

[0154] The first gate electrode G1 and the second gate electrode G2 are arranged on the first gate insulating layer 112 to overlap the first semiconductor layer A1 and the second semiconductor layer A2, respectively (e.g., in the z direction). In an exemplary embodiment, each of the first gate electrode G1 and the second gate electrode G2 may include elements such as Mo, Al, Cu, Ti, and the like, and may have a single-layer structure or a multi-layer structure. For example, each of the first gate electrode G1 and the second gate electrode G2 may have a single-layer structure including Mo.

[0155] The second gate insulating layer 113 covers the first gate electrode G1 and the second gate electrode G2. For example, as shown in the exemplary embodiment of Figure 9 , the lower surface of the second gate insulating layer 113 may directly contact the upper surfaces of the first gate insulating layer 112, the first gate electrode G1, and the second gate electrode G2. In an exemplary embodiment, the second gate insulating layer 113 may include an inorganic insulating material such as at least one compound selected from SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, and ZnO2. The second gate insulating layer 113 may have a single-layer structure or a multi-layer structure.

[0156] The first upper electrode CE2 of the main storage capacitor Cst and the second upper electrode CE2' of the auxiliary storage capacitor Cst' may be disposed on the second gate insulating layer 113. For example, as shown in the exemplary embodiment of Figure 9As shown in the exemplary embodiment, the lower surfaces of the first upper electrode CE2 and the second upper electrode CE2' may directly contact the upper surface of the second gate insulating layer 113.

[0157] In the main display area MDA, the first upper electrode CE2 may overlap with the first gate electrode G1 below it (e.g., in the z direction). The first gate electrode G1 and the first upper electrode CE2 that overlap each other may form the main storage capacitor Cst, where the second gate insulating layer 113 is located between the first gate electrode G1 and the first upper electrode CE2. As Figure 9 shown in the exemplary embodiment, the first gate electrode G1 may be the first lower electrode CE1 of the main storage capacitor Cst. In the component area CA, the second upper electrode CE2' may overlap with the second gate electrode G2 below it (e.g., in the z direction). The second gate electrode G2 and the second upper electrode CE2' that overlap each other may form the auxiliary storage capacitor Cst', where the second gate insulating layer 113 is located between the second gate electrode G2 and the second upper electrode CE2'. As Figure 9 shown in the exemplary embodiment, the first gate electrode G1 may be the second lower electrode CE1' of the auxiliary storage capacitor Cst'.

[0158] In the exemplary embodiment, each of the first upper electrode CE2 and the second upper electrode CE2' may include at least one compound selected from Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu, and may have a single-layer structure or a multi-layer structure.

[0159] The interlayer insulating layer 115 may be formed to cover the first upper electrode CE2 and the second upper electrode CE2'. For example, as Figure 9 shown in the exemplary embodiment, the lower surface of the interlayer insulating layer 115 may directly contact the upper surfaces of the first upper electrode CE2, the second upper electrode CE2', and the second gate insulating layer 113. In the exemplary embodiment, the interlayer insulating layer 115 may include at least one compound selected from SiO2, SiN X , SiON, Al2O3, TiO2, Ta2O5, HfO2, ZnO2, and the like.

[0160] The first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 are collectively referred to as the inorganic insulating layer IL. The inorganic insulating layer IL may have a first hole H1 corresponding to the transmission region TA. The first hole H1 may expose a part of the buffer layer 111 or the upper surface of the substrate 100. The first hole H1 may be formed by overlapping an opening of the first gate insulating layer 112, an opening of the second gate insulating layer 113, and an opening of the interlayer insulating layer 115 formed corresponding to the transmission region TA. The openings may be formed separately by separate processes or may be formed simultaneously by the same process. When the openings are formed by separate processes, the inner surface of the first hole H1 is not smooth and may have stepped steps.

[0161] However, in other exemplary embodiments, the inorganic insulating layer IL may have a groove instead of the first hole H1 exposing the buffer layer 111. Alternatively, the inorganic insulating layer IL may not have the first hole H1 or the groove corresponding to the transmission region TA. The inorganic insulating layer IL includes an inorganic insulating material that generally has excellent light transmittance, and thus, even if it does not have a hole or a groove corresponding to the transmission region TA, it has sufficient transmittance. Therefore, even in embodiments where the first hole H1 or the groove is not included in the inorganic insulating layer IL, the component 20 (see Figure 2 ) can transmit / receive a sufficient amount of light.

[0162] The first source electrode S1 and the second source electrode S2, and the first drain electrode D1 and the second drain electrode D2 are arranged on the interlayer insulating layer 115. Each of the first source electrode S1 and the second source electrode S2 and each of the first drain electrode D1 and the second drain electrode D2 may include a conductive material containing elements such as Mo, Al, Cu, Ti, and the like, and may have a multilayer structure or a single-layer structure. For example, each of the first source electrode S1 and the second source electrode S2 and each of the first drain electrode D1 and the second drain electrode D2 may have a multilayer structure of Ti / Al / Ti.

[0163] The first planarization layer 117 covers the first source electrode S1 and the second source electrode S2, and the first drain electrode D1 and the second drain electrode D2. For example, as Figure 9As shown in the exemplary embodiment, the lower surface of the first planarization layer 117 may directly contact the upper surfaces of the first source electrode S1 and the second source electrode S2 and the interlayer insulating layer 115. The first planarization layer 117 may have an upper surface with a substantially flat shape (e.g., extending substantially along the x direction). The second planarization layer 118 may be disposed on the first planarization layer 117 (e.g., directly on the first planarization layer 117 in the z direction). A plurality of contact metal layers CM and CM' may be arranged between the first planarization layer 117 and the second planarization layer 118 (e.g., in the z direction). The plurality of contact metal layers CM and CM' may electrically connect the first pixel electrode 221 and the second pixel electrode 221' to the corresponding first drain electrode D1 and second drain electrode D2 through contact holes formed in the first planarization layer 117 and the second planarization layer 118, respectively.

[0164] In an exemplary embodiment, each of the first planarization layer 117 and the second planarization layer 118 may include an organic material or an inorganic material and may have a single-layer structure or a multi-layer structure. For example, each of the first planarization layer 117 and the second planarization layer 118 may include a commercial polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a parylene polymer, a vinyl alcohol polymer, a blend thereof, or the like. In an exemplary embodiment, each of the first planarization layer 117 and the second planarization layer 118 may include at least one compound selected from SiO2, SiN X , SiON, Al2O3, TiO2, Ta2O5, HfO2, ZnO2, and the like. In an exemplary embodiment, when forming the first planarization layer 117 and the second planarization layer 118, chemical mechanical polishing may be performed on the top surface of each layer to provide a flat top surface after the formation of each layer.

[0165] The first planarization layer 117 and the second planarization layer 118 may have a second hole H2 corresponding to the transmission region TA. The second hole H2 may overlap the first hole H1 (e.g., in the z direction). In Figure 9In an exemplary embodiment, the area of the second hole H2 is larger than the area of the first hole H1 (e.g., in a plane defined by the x - direction and the y - direction). However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the first planarization layer 117 and the second planarization layer 118 may be disposed on side edges of the first hole H1 of the inorganic insulating layer IL to cover the edges of the first hole H1, and thus, the area of the second hole H2 may be smaller than the area of the first hole H1.

[0166] The first planarization layer 117 and the second planarization layer 118 may have an opening exposing one of the first source electrode S1 and the first drain electrode D1 of the main thin - film transistor TFT, and the first pixel electrode 221 may be electrically connected to the main thin - film transistor TFT through the opening by contacting the first source electrode S1 or the first drain electrode D1. Additionally, the first planarization layer 117 and the second planarization layer 118 may have an opening exposing one of the second source electrode S2 and the second drain electrode D2 of the auxiliary thin - film transistor TFT', and the second pixel electrode 221' may be electrically connected to the auxiliary thin - film transistor TFT' through the opening by contacting the second source electrode S2 or the second drain electrode D2.

[0167] In an exemplary embodiment, each of the first pixel electrode 221 and the second pixel electrode 221' may include a conductive oxide, such as at least one compound selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). Each of the first pixel electrode 221 and the second pixel electrode 221' may include a reflective layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof. For example, each of the first pixel electrode 221 and the second pixel electrode 221' may have the following structure: including a layer containing ITO, IZO, ZnO, or In2O3 above or below the reflective layer. In this embodiment, each of the first pixel electrode 221 and the second pixel electrode 221' may have a stacked structure of ITO / Ag / ITO.

[0168] The pixel defining layer 119 may cover side edges of each of the first pixel electrode 221 and the second pixel electrode 221'. The pixel defining layer 119 has a first opening OP1 and a second opening OP2 that respectively overlap with the first pixel electrode 221 and the second pixel electrode 221', and defines an emission region of the sub-pixel. The pixel defining layer 119 increases a distance between edges of the first pixel electrode 221 and the second pixel electrode 221 and a counter electrode 223 thereabove, thereby preventing arcing from occurring at edges of the first pixel electrode 221 and the second pixel electrode 221. In an exemplary embodiment, the pixel defining layer 119 may include an organic insulating material such as at least one compound selected from polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be formed by spin coating or the like.

[0169] The pixel defining layer 119 may have a third hole H3 located in the transmissive region TA. The third hole H3 may overlap with the first hole H1 and the second hole H2. As Figure 9 shown in an exemplary embodiment of, an area of the third hole H3 (e.g., in a plane defined in the x direction and the y direction) may be larger than an area of the second hole H2. However, the exemplary embodiment of the inventive concept is not limited thereto. The light transmittance in the transmissive region TA may be increased through the first hole H1 to the third hole H3. A part of the counter electrode 223 to be described later may be arranged on inner surfaces of the first hole H1 to the third hole H3.

[0170] The first intermediate layer 222a is arranged to cover the pixel defining layer 119. The first intermediate layer 222a may have a single-layer structure or a multi-layer structure. The first intermediate layer 222a may include a hole transport layer (HTL) having a single-layer structure. Alternatively, the first intermediate layer 222a may include a hole injection layer (HIL) and an HTL. The first intermediate layer 222a may be integrally formed in main sub-pixels Pm and auxiliary sub-pixels Pa included in a main display area MDA and a component area CA, respectively.

[0171] A first emission layer 222b and a second emission layer 222b' corresponding to the first pixel electrode 221 and the second pixel electrode 221' respectively are arranged on the first intermediate layer 222a. In an exemplary embodiment, each of the first emission layer 222b and the second emission layer 222b' may include a polymer material or a low molecular material and may emit red light, green light, blue light, or white light.

[0172] The second intermediate layer 222c may be disposed on the first emission layer 222b and the second emission layer 222b'. The second intermediate layer 222c may have a single-layer structure or a multi-layer structure. The second intermediate layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second intermediate layer 222c may be integrally formed in the main sub-pixels Pm and the auxiliary sub-pixels Pa included in the main display area MDA and the component area CA, respectively. However, the exemplary embodiments of the present inventive concept are not limited thereto, and in some exemplary embodiments, the display panel 10 may not include at least one of the first intermediate layer 222a and the second intermediate layer 222c.

[0173] The opposite electrode 223 is disposed on the second intermediate layer 222c. The opposite electrode 223 may include a conductive material having a low work function. For example, in an exemplary embodiment, the opposite electrode 223 may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. Alternatively, the opposite electrode 223 may further include a layer including ITO, IZO, ZnO, or In2O3 on the (semi) transparent layer including the above materials. The opposite electrode 223 may be integrally formed to correspond to the main sub-pixels Pm and the auxiliary sub-pixels Pa arranged in the main display area MDA and the component area CA, respectively.

[0174] The layer from the first pixel electrode 221 to the opposite electrode 223 formed in the main display area MDA may form a main organic light-emitting diode OLED. The layer from the second pixel electrode 221' to the opposite electrode 223 formed in the component area CA may form an organic light-emitting diode OLED'.

[0175] The cover layer 250 may be disposed on the opposite electrode 223 (e.g., directly disposed thereon in the z direction). In an exemplary embodiment, the cover layer 250 may include LiF. Alternatively, the cover layer 250 may include an inorganic insulating material such as silicon nitride and / or an organic insulating material. However, the exemplary embodiments of the present inventive concept are not limited thereto, and in some exemplary embodiments, the display panel 10 may not include the cover layer 250.

[0176] The first intermediate layer 222a, the second intermediate layer 222c, the counter electrode 223, and the cover layer 250 may have a transmissive hole TAH corresponding to the transmissive region TA. For example, the first intermediate layer 222a, the second intermediate layer 222c, the counter electrode 223, and the cover layer 250 may respectively have an opening corresponding to the transmissive region TA, and the openings together form the transmissive hole TAH. In an exemplary embodiment, the areas of the openings of the first intermediate layer 222a, the second intermediate layer 222c, the counter electrode 223, and the cover layer 250 may be substantially the same. The area of the opening of the counter electrode 223 may be substantially the same as the area of the transmissive hole TAH. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the area of the opening of the first intermediate layer 222a (e.g., in a plane defined by the x-direction and the y-direction), the area of the opening of the second intermediate layer 222c, the area of the opening of the counter electrode 223, and the area of the opening of the cover layer 250 may not be the same, and the area of any one of the openings may be smaller than or larger than the areas of some of the other openings. For example, the inner surface of the opening of the first intermediate layer 222a may be located in the transmissive hole TAH, and thus, the portion defining the opening of the first intermediate layer 222a may have a shape protruding into the transmissive hole TAH.

[0177] The correspondence between the transmissive hole TAH and the transmissive region TA means that the transmissive hole TAH overlaps with the transmissive region TA. In an exemplary embodiment, the area of the transmissive hole TAH may be smaller than the area of the first hole H1 formed in the inorganic insulating layer IL. For example, as Figure 9 shown in the exemplary embodiment of, the width Wt of the transmissive hole TAH (e.g., the length in the x-direction) is smaller than the width W1 of the first hole H1 (e.g., the length in the x-direction). In this embodiment, the area of the transmissive hole TAH may be defined by the opening having the smallest size among the overlapping openings of the layers located in the transmissive portion among the layers of the panel. The area of the first hole H1 may also be defined as the area of the opening having the smallest area among the openings constituting the first hole H1.

[0178] Due to the transmissive hole TAH, a part of the counter electrode 223 does not exist in the transmissive region TA, and thus, the light transmittance in the transmissive region TA can be significantly increased. The counter electrode 223 may be formed in various ways. For example, by forming a layer of the material for the counter electrode 223 and then removing the portion corresponding to the transmissive region TA by laser lift-off, the counter electrode 223 having an opening may be formed. Alternatively, the counter electrode 223 having an opening may be formed by fine metal mask patterning. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0179] The organic light-emitting diode (OLED) in the main display area (MDA) and the organic light-emitting diode (OLED') in the component area (CA) can be sealed by a thin-film encapsulation layer 300. The thin-film encapsulation layer 300 can be disposed on the cover layer 250. For example, as Figure 9 shown in the exemplary embodiment of

[0180] Figure 9 Figure 9 shown, the lower surface of the thin-film encapsulation layer 300 can directly contact the upper surface of the cover layer 250. The thin-film encapsulation layer 300 can prevent external moisture or foreign substances from penetrating into the organic light-emitting diode (OLED) and the organic light-emitting diode (OLED').

[0181] The thin-film encapsulation layer 300 can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In the exemplary embodiment

[0182] Figure 9 Figure 9As shown in the exemplary embodiment, the lower surface of the first inorganic encapsulation layer 310 may directly contact the upper surface of the buffer layer 111 in the transmissive hole TAH, and the organic encapsulation layer 320 and the second inorganic encapsulation layer 330 are continuously stacked thereon. However, the exemplary embodiment of the inventive concept is not limited thereto. For example, in some exemplary embodiments, the organic encapsulation layer 320 may be integrally formed to cover the main display area MDA and the component area CA, but may not be disposed in the transmissive area TA. For example, the organic encapsulation layer 320 may have an opening corresponding to the transmissive area TA. In this embodiment, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may directly contact each other in the transmissive hole TAH.

[0183] Figure 10 and Figure 11 is a schematic plan view showing the arrangement of sub-pixels and wiring lines of the display panel 10 according to an exemplary embodiment of the inventive concept. Since the plan view only shows a part of the display panel 10, many sub-pixels are omitted. Moreover, since the plan view only shows the wiring lines required for description, many wiring lines are omitted for convenience of explanation. The plan view shows a part of the component area CA and a part of the main display area MDA outside the component area CA. Figure 3 The arrangement of sub-pixels and wiring lines shown in the exemplary embodiment of includes a first data line D1, a 2-1 data line D Figure 10 among the wiring lines. 2-1 and a 2-2 data line D 2-2 and a third data line D3, a 4-1 data line D 4-1 and a 4-2 data line D 4-2 . Figure 11 The arrangement of sub-pixels shown in the exemplary embodiment of shows a first bridge line B1 and a second bridge line B2 among the wiring lines. In Figure 10 and Figure 11 of the exemplary embodiment, for convenience of explanation, the first data line D1, the 2-1 data line D 2-1 and a 2-2 data line D 2-2 and a third data line D3, a 4-1 data line D 4-1 and a 4-2 data line D 4-2 , the first bridge line B1 and the second bridge line B2 are shown as passing through the center of the sub-pixel. However, the wiring lines can be modified in various ways, such as passing through the edge of the sub-pixel, etc. The wiring lines shown in the drawings in combination with the exemplary embodiments and their modifications described below can also be modified in various ways and are not limited by their illustrations.

[0184] As Figure 10 and Figure 11As shown in the exemplary embodiment, the sub-pixels are arranged in multiple rows extending in the x-axis direction. The 1-1 sub-pixel Sub 1-1 and the 1-2 sub-pixel Sub 1-2 are located in the first row R1, where the first row R1 is positioned adjacent to the lower side of the component area CA (e.g., in the y-direction). The first row R1 is adjacent to the lower side of the component area CA in the -y direction. The 2-1 sub-pixel Sub 2-1 is located in the second row R2, where the second row R2 is located in the component area CA (e.g., below the central part of the component area CA in the -y direction) and is spaced apart from the first row R1 in the +y direction. The 3-1 sub-pixel Sub 3-1 and the 3-2 sub-pixel Sub 3-2 are located in the third row R3, where the third row R3 is positioned adjacent to the upper side of the component area CA (e.g., in the y-direction). The third row R3 is adjacent to the upper side of the component area CA in the +y direction and is spaced apart from the second row R2 in the +y direction.

[0185] In Figure 10 the exemplary embodiment, each of the first row R1, the second row R2, and the third row R3 is shown as including two rows extending in the x-axis direction and spaced apart in the y-direction. For example, in the case of the third row R3, the red sub-pixel Pr shown in the upper left corner of the exemplary embodiment of Figure 10 , the green sub-pixel Pg shown in the +x direction from the red sub-pixel Pr, the blue sub-pixel Pb shown in the -y direction from the red sub-pixel Pr, and the green sub-pixel Pg shown in the +x direction from the blue sub-pixel Pb can form a pixel. Therefore, in Figure 10 the exemplary embodiment, the third row R3 is shown as including two rows extending in the x-axis direction. This also applies to the first row R1 or the second row R2. However, the exemplary embodiments of the present inventive concept are not limited thereto. For example, in another exemplary embodiment, each of the first row R1, the second row R2, and the third row R3 may include one row extending in the x-axis direction, and the red sub-pixel Pr, the green sub-pixel Pg located in the +x direction from the red sub-pixel Pr, and the blue sub-pixel Pb located in the +x direction from the green sub-pixel Pg may be repeatedly arranged in one row. In this exemplary embodiment, the red sub-pixel Pr, the green sub-pixel Pg located in the +x direction from the red sub-pixel Pr, and the blue sub-pixel Pb located in the +x direction from the green sub-pixel Pg can form a pixel. In other exemplary embodiments, the arrangement of the sub-pixels forming a pixel may be changed. Hereinafter, for the convenience of explanation, the case of the sub-pixel arrangement shown in Figure 10 will be described.

[0186] The 1-1 sub-pixel Sub 1-1, the 1-2nd sub-pixel Sub 1-2 , the 3-1st sub-pixel Sub 3-1 and the 3-2nd sub-pixel Sub 3-2 can be located in the main display area MDA, and the 2-1st sub-pixel Sub 2-1 can be located in the component area CA. In this exemplary embodiment, when the component area CA is at the center, the 1-1st sub-pixel Sub 1-1 and the 1-2nd sub-pixel Sub 1-2 are located in the first row R1 adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction). The 3-1st sub-pixel Sub 3-1 and the 3-2nd sub-pixel Sub 3-2 are located in the third row R3 adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). Therefore, the component area CA has a transmissive area TA between the first row R1 and the second row R2 and between the second row R2 and the third row R3. Therefore, the component area CA has a transmissive area TA arranged outside the 2-1st sub-pixel Sub 2-1 (e.g., outside in the -y direction, +y direction, -x direction, and +x direction).

[0187] The first data line D1 extends substantially in the +y direction from the first row R1 across the component area CA to the third row R3, and electrically connects the pixel circuits of the 1-1st sub-pixel Sub 1-1 in the main display area MDA, the pixel circuits of the 2-1st sub-pixel Sub 2-1 in the component area CA, and the pixel circuits of the 3-1st sub-pixel Sub 3-1 in the main display area MDA.

[0188] The 2-1st data line D 2-1 also extends in the +y direction and is electrically connected to the pixel circuit of the 1-2nd sub-pixel Sub 1-2 in the main display area MDA. However, the 2-1st data line D 2-1 is not connected to the auxiliary sub-pixel Pa in the component area CA. For example, the 2-1st data line D 2-1 can terminate at or in a part of the main display area MDA adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction). The 2-1st data line D 2-1 may not extend to the second row R2 and the third row R3.

[0189] The 2-2nd data line D 2-2 extends in the -y direction and is electrically connected to the pixel circuit of the 3-2nd sub-pixel Sub 3-2is electrically connected to the pixel circuit. The second - second data line D 2-2 is not connected to the auxiliary sub - pixel Pa located in the component area CA. For example, the second - second data line D 2-2 may terminate in a part of the main display area MDA adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction) or located in the component area CA. The second - second data line D 2-2 may not extend to the first row R1 and the second row R2.

[0190] As described above with reference to Figure 3 the exemplary embodiment of, the data line DL transmits the data signal Dm from the data driving circuit 150 located outside the main display area MDA (e.g., in the -y direction) to the main sub - pixel Pm and the auxiliary sub - pixel Pa.

[0191] The first - first sub - pixel Sub in the main display area MDA 1-1 the second - first sub - pixel Sub in the component area CA 2-1 and the third - first sub - pixel Sub in the main display area MDA 3-1 are electrically connected to the first data line D1 extending across the component area CA in the +y direction, and thus can receive the data signal Dm from the data driving circuit 150. The first - second sub - pixel Sub in a part of the main display area MDA adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction) 1-2 is electrically connected to the second - first data line D 2-1 and thus can receive the data signal Dm from the data driving circuit 150. However, the third - second sub - pixel Sub in a part of the main display area MDA adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction) 3-2 is electrically connected to the second - second data line D 2-2 However, the second - second data line D 2-2 extends in the -y direction towards the component area CA, but does not extend across the component area CA to the main display area MDA adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction). Thus, in this configuration, the data signal Dm is not applied to the third - second sub - pixel Sub in a part of the main display area MDA adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction) through the data line. 3-2

[0192] However, since the display device 1 according to the inventive concept includes as Figure 11In the exemplary embodiment, the data signal Dm can also be applied to the 3-2nd sub-pixel Sub located in a part of the main display area MDA adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). 3-2 For example, the first side of the first bridge wiring B1 contacts the 2-1st data line D in the first row R1 adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction). 2-1 And the second side of the first bridge wiring B1 contacts the 2-2nd data line D in the third row R3 adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). 2-2 Therefore, the 2-2nd data line D 2-2 is electrically connected to the 2-1st data line D 2-1 . Thus, the data signal Dm can be applied to the 3-2nd sub-pixel Sub through the 2-2nd data line D 2-2 . 3-2 .

[0193] The first bridge wiring B1 is located on a layer different from the first data line D1, the 2-1st data line D 2-1 and the 2-2nd data line D 2-2 . For example, in the exemplary embodiment, the first data line D1, the 2-1st data line D 2-1 and the 2-2nd data line D 2-2 can be arranged on the interlayer insulating layer 115 as shown in the exemplary embodiment of Figure 9 , and the first bridge wiring B1 can be arranged on the first planarization layer 117 covering the first data line D1, the 2-1st data line D 2-1 and the 2-2nd data line D 2-2 (see Figure 9 ). In this exemplary embodiment, the first data line D1, the 2-1st data line D 2-1 and the 2-2nd data line D 2-2 can be formed of the same material as the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 and formed simultaneously with the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2, and the first bridge wiring B1 can be formed of the same material as the plurality of contact metal layers CM and CM' and formed simultaneously with the plurality of contact metal layers CM and CM'. The first bridge wiring B1 can be electrically connected to each of the 2-1st data line D 2-1 and the 2-2nd data line D 2-2 located below the first planarization layer 117 through contact holes formed in the first planarization layer 117.

[0194] The display device 1 according to the present exemplary embodiment may display a high-resolution image in a part of the main display area MDA that is adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction), and may also display a high-resolution image in a part of the main display area MDA that is adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction).

[0195] The first bridge wiring B1 may have a part (e.g., an overlapping part) extending along at least a part of the first data line D1. Therefore, the orthogonal projection image of the part of the first bridge wiring B1 extending along at least a part of the first data line D1 in a direction perpendicular to the top surface of the substrate 100 (e.g., in the z direction) overlaps with the orthogonal projection image of the first data line D1 in a direction perpendicular to the top surface of the substrate 100 (z direction). This is possible because the first bridge wiring B1 is located on a layer different from the layer where the first data line D1 is located. Referring to Figure 10 and Figure 11 In the exemplary embodiment, the first bridge wiring B1 overlaps with the first data line D1 (e.g., in the z direction) in substantially all areas except for the areas adjacent to the upper edge of the component area CA and the areas adjacent to the lower edge of the component area CA.

[0196] With this configuration, the display device 1 according to the present exemplary embodiment can even display a high-resolution image in a part of the main display area MDA that is adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). In the component area CA, the light transmission area of the transmission area TA may have a large area (e.g., in the plane defined by the x direction and the y direction) because the first bridge wiring B1 does not cause loss in the light transmission area of the transmission area TA.

[0197] As Figure 10 and Figure 11 shown in the exemplary embodiment of, the 1st - 3rd sub-pixels Sub 1-3 and the 1st - 4th sub-pixels Sub 1-4 may be located in the first row R1, the 2nd - 2nd sub-pixels Sub 2-2 may be located in the second row R2, and the 3rd - 3rd sub-pixels Sub 3-3 and the 3rd - 4th sub-pixels Sub 3-4 may be located in the third row R3. The 1st - 3rd sub-pixels Sub 1-3 are adjacent to the 1st - 1st sub-pixels Sub 1-1 in the -x direction, where the -x direction is the direction opposite to the direction (e.g., +x direction) in which the 1st - 2nd sub-pixels Sub 1-1 are arranged with respect to the 1st - 1st sub-pixels Sub 1-2 . The 1st - 4th sub-pixels Sub 1-4Located at the 1-1 sub-pixel Sub 1-1 and the 1-2 sub-pixel Sub 1-2 therebetween. The 3-3 sub-pixel Sub 3-3 is positioned adjacent to the 3-1 sub-pixel Sub 3-1 in the -x direction, where the -x direction is the direction opposite to the direction (e.g., the +x direction) in which the 3-2 sub-pixel Sub 3-1 is arranged with respect to the 3-1 sub-pixel Sub 3-2 . The 3-4 sub-pixel Sub 3-4 is located between the 3-1 sub-pixel Sub 3-1 and the 3-2 sub-pixel Sub 3-2 .

[0198] Therefore, the 1-3 sub-pixel Sub 1-3 , the 1-4 sub-pixel Sub 1-4 , the 3-3 sub-pixel Sub 3-3 and the 3-4 sub-pixel Sub 3-4 can be located in the main display area MDA. The 2-2 sub-pixel Sub 2-2 can be located in the component area CA. Additionally, when the component area CA is centered, the 1-3 sub-pixel Sub 1-3 and the 1-4 sub-pixel Sub 1-4 are positioned adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction), and the 3-3 sub-pixel Sub 3-3 and the 3-4 sub-pixel Sub 3-4 are positioned adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). The component area CA has a transmissive area TA arranged outside the 2-2 sub-pixel Sub 2-2 .

[0199] The third data line D3 extends substantially in the +y direction from the first row R1 across the component area CA to the third row R3, and electrically connects the pixel circuits of the 1-3 sub-pixel Sub 1-3 in the main display area MDA, the pixel circuit of the 2-2 sub-pixel Sub 2-2 in the component area CA, and the pixel circuit of the 3-3 sub-pixel Sub 3-3 in the main display area MDA.

[0200] The 4-1 data line D 4-1 also extends in the +y direction and is electrically connected to the pixel circuit of the 1-4 sub-pixel Sub 1-4 located in the main display area MDA. However, the 4-1 data line D 4-1Not connected to the auxiliary sub-pixel Pa located in the component area CA. For example, the 4-1 data line D 4-1 may terminate at a part adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction) in the main display area MDA or in a part located in the component area CA. The 4-1 data line D 4-1 may not extend to the second row R2 and the third row R3.

[0201] The 4-2 data line D 4-2 extends in the -y direction and is electrically connected to the pixel circuit of the 3-4 sub-pixel Sub 3-4 located in the main display area MDA. The 4-2 data line D 4-2 is not connected to the auxiliary sub-pixel Pa located in the component area CA. For example, the 4-2 data line D 4-2 may terminate at a part adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction) in the main display area MDA or in a part located in the component area CA. The 4-2 data line D 4-2 may not extend to the first row R1 and the second row R2.

[0202] The 1-3 sub-pixel Sub 1-3 in the main display area MDA, the 2-2 sub-pixel Sub 2-2 in the component area CA, and the 3-3 sub-pixel Sub 3-3 in the main display area MDA are electrically connected to the third data line D3 extending in the +y direction, and thus, can receive the data signal Dm from the data driving circuit 150. The 1-4 sub-pixel Sub 1-4 in a part of the main display area MDA adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction) is electrically connected to the 4-1 data line D 4-1 and thus, can receive the data signal Dm from the data driving circuit 150. However, the 3-4 sub-pixel Sub 3-4 in a part of the main display area MDA adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction) is electrically connected to the 4-2 data line D 4-2 However, the 4-2 data line D 4-2 extends toward the component area CA in the -y direction but does not extend across the component area CA to the main display area MDA adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction). Therefore, in this configuration, the data signal Dm is not applied to the 3-4 sub-pixel Sub 3-4 in a part of the main display area MDA adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction) through the data line.

[0203] However, since the display device 1 according to the inventive concept includes the second bridge wiring B2 as shown in the exemplary embodiment such as Figure 11 the data signal Dm can also be applied to the 3-4th sub-pixel Sub in a part of the main display area MDA adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). 3-4 . For example, the first side of the second bridge wiring B2 contacts the 4-1st data line D in the first row R1 adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction). 4-1 and the second side of the second bridge wiring B2 contacts the 4-2nd data line D in the third row R3 adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). 4-2 . Therefore, the 4-2nd data line D 4-2 is electrically connected to the 4-1st data line D 4-1 . Thus, the data signal Dm can be applied to the 3-4th sub-pixel Sub through the 4-2nd data line D 4-2 . 3-4 .

[0204] The second bridge wiring B2, the third data line D3, the 4-1st data line D 4-1 and the 4-2nd data line D 4-2 are located on different layers. For example, in the exemplary embodiment, the third data line D3, the 4-1st data line D 4-1 and the 4-2nd data line D 4-2 can be arranged on the interlayer insulating layer 115 as shown in the exemplary embodiment such as Figure 9 , and the second bridge wiring B2 can be arranged on the first planarization layer 117 as shown in the exemplary embodiment such as Figure 9 . In this exemplary embodiment, the third data line D3, the 4-1st data line D 4-1 and the 4-2nd data line D 4-2 can be formed of the same material as the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 and formed simultaneously, and the second bridge wiring B2 can be formed of the same material as the plurality of contact metal layers CM and CM' and formed simultaneously. The second bridge wiring B2 can be electrically connected to each of the 4-1st data line D 4-1 and the 4-2nd data line D 4-2 located below the first planarization layer 117 through contact holes formed in the first planarization layer 117.

[0205] The display device 1 according to this exemplary embodiment can display a high-resolution image in a portion of the main display area MDA that is positioned adjacent to the lower side of the component area CA (for example, adjacent in the -y direction), and can also display a high-resolution image in a portion of the main display area MDA that is adjacent to the upper side of the component area CA (for example, adjacent in the +y direction).

[0206] The second bridge line B2 may have a portion (e.g., an overlapping portion) extending along at least a portion of the third data line D3. Therefore, an orthogonal projection image of the portion of the second bridge line B2 extending along at least a portion of the third data line D3 in a direction perpendicular to the top surface of the substrate 100 (z direction) overlaps with an orthogonal projection image of the third data line D3 in a direction perpendicular to the top surface of the substrate 100 (z direction). This is possible because the second bridge line B2 is arranged on a layer different from the layer on which the third data line D3 is arranged. Figure 10 and Figure 11 In the exemplary embodiment, the second bridge line B2 substantially overlaps the third data line D3 (eg, in the z direction) in all regions except a region adjacent to an edge of an upper side of the component area CA and a region adjacent to an edge of a lower side of the component area CA.

[0207] By this configuration, the display device 1 according to the present exemplary embodiment can display a high-resolution image even in a portion of the main display area MDA that is located adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). In the component area CA, the light transmission area of ​​the transmission area TA can have a large area because the second bridging line B2 does not cause a loss in the light transmission area of ​​the transmission area TA.

[0208] Figure 12 is an exemplary embodiment according to the present inventive concept. Figure 10 and Figure 11 A schematic cross-sectional view of the arrangement of sub-pixels and line lines taken along line III-III'. Figure 12 As shown in the exemplary embodiment of FIG. 1 , the third data line D3 is arranged on the same layer as the first data line D1 (for example, arranged on the interlayer insulating layer 115), and the second bridge line B2 is arranged on the same layer as the first bridge line B1 (for example, arranged on the first planarization layer 117). The first data line D1 and the third data line D3 may also be located at the same layer as the second-first data line D1. 2-1 , 2-2 data line D 2-2 , 4-1 data line D 4-1 and 4-2 data line D 4-2 On the same layer. Figure 12As shown in the exemplary embodiment, the first bridge wiring B1 and the second bridge wiring B2 may have portions overlapping with the first data line D1 and the third data line D3 (e.g., in the z direction), respectively, thereby reducing losses in the light transmission region of the transmission region TA.

[0209] The display panel 10 may include an additional data line Da electrically connected to a pixel circuit of a sub-pixel adjacent to the 1-3 sub-pixels Sub in the -x direction in the first row R1. 1-3 The additional data line Da may extend substantially in the +y direction and may extend into the component region CA. The additional data line Da may have a shape substantially parallel to the first data line D1. In this exemplary embodiment, the additional data line Da is electrically connected to a pixel circuit of a sub-pixel in the component region CA, and then may extend substantially in the +y direction along the edge of the transmission region TA on the outer side in the -x direction of the 2-1 sub-pixel Sub. 2-1 The additional data line Da may be electrically connected to a pixel circuit of a main sub-pixel Pm in a part of the main display region MDA adjacent to the upper side (e.g., adjacent in the +y direction) of the component region CA. For example, as shown in the exemplary embodiment of Figure 10 The additional data line Da may be electrically connected to a sub-pixel adjacent to the 3-3 sub-pixels Sub in the -x direction in the third row R3. 3-3 As described above, the driving voltage ELVDD is applied to the pixel circuit of each sub-pixel.

[0210] FIG. is a schematic plan view showing the arrangement of a plurality of driving voltage lines PL1, PL2, PL3, PL4, and PL5 and the auxiliary driving voltage line PLca of the display panel 10 according to an exemplary embodiment of the inventive concept. Figure 13 FIG. Figure 3 The driving voltages from the plurality of driving voltage lines PL2 and PL5 electrically connected to the first sub-line 162 (see

[0211] ) are applied to the main sub-pixels Pm in a part of the main display region MDA adjacent to the lower side (e.g., adjacent in the -y direction) of the component region CA. The driving voltages from the plurality of driving voltage lines PL3 and PL4 electrically connected to the second sub-line 163 (see Figure 3 ) are applied to the main sub-pixels Pm in a part of the main display region MDA adjacent to the upper side (e.g., adjacent in the +y direction) of the component region CA. The driving voltage from the driving voltage line PL1 electrically connected to the first sub-line 162 and / or the second sub-line 163 is applied to the main sub-pixels Pm in the remaining part of the main display region MDA. Figure 3 FIG.

[0212] In an exemplary embodiment, the driving voltages from the plurality of driving voltage lines PL4 and PL5 electrically connected to the first sub-line 162 and / or the second sub-line 163 may also be applied to the auxiliary sub-pixels Pa in the component area CA. However, in another exemplary embodiment as shown in Figure 13 , the driving voltage may be applied to the auxiliary sub-pixels Pa in the component area CA through an auxiliary driving voltage line PLca located in the component area CA.

[0213] The auxiliary driving voltage line PLca is arranged on a layer different from the first data line D1 and the first bridge line B1. For example, in an exemplary embodiment, the auxiliary driving voltage line PLca may be arranged on the same layer as the first metal layer BSM1 and the second metal layer BSM2 as shown in an exemplary embodiment such as Figure 9 , and is formed of the same material as the first metal layer BSM1 and the second metal layer BSM2. For example, the auxiliary driving voltage line PLca may be directly arranged on the second inorganic layer 104 ( Figure 9 ). In this exemplary embodiment, the auxiliary driving voltage line PLca is located below the first data line D1 and the first bridge line B1. The plurality of driving voltage lines PL1, PL2, PL3, PL4, and PL5 may be located on the same layer as the first data line D1 and the third data line D3.

[0214] In addition, the auxiliary driving voltage line PLca may (e.g., in the z direction) overlap with the first data line D1, the third data line D3, the first bridge line B1, and the second bridge line B2, and may be electrically connected to the pixel circuit of the 2-1 sub-pixel Sub 2-1 which is the auxiliary sub-pixel Pa located in the component area CA to apply the driving voltage to the pixel circuit. Contact holes may be formed in the buffer layer 111 or a similar layer so that the pixel circuit of the 2-1 sub-pixel Sub 2-1 is electrically connected to the auxiliary driving voltage line PLca. In addition, the auxiliary driving voltage line PLca may be electrically connected to the plurality of driving voltage lines PL4 and PL5 located on a layer different from the auxiliary driving voltage line PLca through contact holes at the edge of the component area CA.

[0215] The auxiliary driving voltage line PLca may protect the pixel circuit PC in the component area CA from external light or from the component 20 (see Figure 2) of light. In addition, since the auxiliary driving voltage line PLca overlaps with the first data line D1, the third data line D3, the first bridge line B1, and the second bridge line B2, the auxiliary driving voltage line PLca can prevent or reduce light diffraction occurring due to small gaps between various line lines (such as the first data line D1, the third data line D3, the first bridge line B1, and the second bridge line B2), and this light diffraction can cause noise in the data collected by the component 20 (such as an imaging device). As Figure 13 As shown in the exemplary embodiment of, the width of the auxiliary driving voltage line PLca (e.g., the length in the x direction) can be greater than the width of each of the plurality of driving voltage lines PL1, PL2, PL3, PL4, and PL5.

[0216] In Figure 10 and Figure 11 In the exemplary embodiment of, the auxiliary sub-pixels Pa in the component area CA are shown arranged in a zigzag pattern along the y-axis direction. However, the exemplary embodiment of the present inventive concept is not limited thereto. For example, as Figure 14 and Figure 15 As shown in the exemplary embodiment of ( Figure 14 and Figure 15 is a schematic plan view showing the arrangement of sub-pixels and line lines of a display panel according to another exemplary embodiment), the auxiliary sub-pixels Pa in the component area CA can be arranged in a matrix shape. As Figures 14 to 15 As shown in the exemplary embodiment of, different from the exemplary embodiment of Figures 10 to 11 the auxiliary sub-pixels Pa are arranged in multiple aligned rows and columns in the component area CA. Therefore, the portion of the transmission area TA arranged between adjacent columns of the auxiliary sub-pixels Pa can extend from the upper edge of the component area CA to the lower edge of the component area CA. The portion of the transmission area TA arranged between adjacent rows can extend from the edge of the component area CA in the +x direction to the edge of the component area CA in the -x direction.

[0217] Since Figure 14 and Figure 15 the exemplary embodiments of only show a part of the display panel, many sub-pixels are omitted. Moreover, since the plan view only shows the line lines required for description, many line lines are omitted. The plan view shows the component area CA and a part of the main display area MDA outside the component area CA. Figure 14 Shows the first data line D1, the 2-1 data line D 2-1 , the 2-2 data line D 2-2 , the third data line D3, the 4-1 data line D 4-1 and the 4-2 data line D 4-2 among the line lines, and Figure 15The first bridge wiring B1 and the second bridge wiring B2 among the wiring lines are shown. In Figure 14 and Figure 15 In the exemplary embodiment, for the convenience of illustration, the first data line D1, the 2-1 data line D 2-1 , the 2-2 data line D 2-2 , the third data line D3, the 4-1 data line D 4-1 , the 4-2 data line D 4-2 , the first bridge wiring B1 and the second bridge wiring B2 are only shown as passing through the centers of the sub-pixels. However, the exemplary embodiments of the present inventive concept are not limited thereto, and the wiring lines may pass through any part of the corresponding sub-pixels. For example, the wiring lines may be modified in various ways, such as passing through the edges of the sub-pixels, etc. This also applies to the wiring lines shown in the accompanying drawings of the combined embodiments and their modifications described below.

[0218] According to the description of the display device 1 in the above-described exemplary embodiment with reference to Figures 10 to 13 , it can be applied to the display device according to the Figures 14 to 15 exemplary embodiment.

[0219] For example, as shown in the exemplary embodiment of Figure 14 , the first data line D1 extends substantially in the +y direction across the component area CA and is electrically connected to the pixel circuits of the 1-1 sub-pixel Sub 1-1 in the first row R1 of the main display area MDA, the pixel circuits of the 2-1 sub-pixel Sub 2-1 in the second row R2 in the component area CA, and the pixel circuits of the 3-1 sub-pixel Sub 3-1 in the third row R3 of the main display area MDA.

[0220] The 2-1 data line D 2-1 also extends in the +y direction and is electrically connected to the pixel circuit of the 1-2 sub-pixel Sub 1-2 in the first row R1 in the main display area MDA. However, the 2-1 data line D 2-1 is not connected to the auxiliary sub-pixel Pa in the component area CA, and the 2-1 data line D 2-1 terminates at a part adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction) in the main display area MDA or is located in a part of the component area CA.

[0221] The 2-2 data line D 2-2 extends in the -y direction and is electrically connected to the pixel circuit of the 3-2 sub-pixel Sub 3-2 in the third row R3 of the main display area MDA. However, the 2-2 data line D 2-2is not connected to the auxiliary sub-pixel Pa located in the component area CA, and the 2-2 data line D 2-2 terminates at a part adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction) of the main display area MDA or is located in a part of the component area CA.

[0222] As Figure 15 shown in the exemplary embodiment of, the first side of the first bridge wire B1 contacts the 2-1 data line D located adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction relative to the component area CA) 2-1 , and the second side of the first bridge wire B1 contacts the 2-2 data line D adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction relative to the component area CA) 2-2 , and thus, the 2-2 data line D 2-2 is electrically connected to the 2-1 data line D 2-1 . Therefore, the data signal Dm can be applied to the 3-2 sub-pixel Sub 2-2 through the 2-2 data line D 3-2 .

[0223] The description given above with reference to Figures 10 to 13 the exemplary embodiment of can be applied to Figures 14 to 15 the third data line D3, the 4-1 data line D 4-1 , the 4-2 data line D 4-2 and the second bridge wire B2 in the exemplary embodiment of.

[0224] When the first data line D1 extends substantially in the +y direction, the first data line D1 passes near the transmissive area TA. In this embodiment, it is necessary to increase the area of the transmissive area TA. Therefore, as Figure 14 shown in the exemplary embodiment of, the first data line D1 can be appropriately bent when passing between the auxiliary sub-pixels Pa in the component area CA, and thus, can be as close as possible to the third data line D3 extending in a straight line shape in the +y direction. As Figure 15 shown in the exemplary embodiment of, this structure can also be applied to the first bridge wire B1 and the second bridge wire B2. For example, the first bridge wire B1 can be appropriately bent when passing between the auxiliary sub-pixels Pa in the component area CA, and thus, can be as close as possible to the second bridge wire B2 extending in a straight line shape in the +y direction.

[0225] So far, the pixel group PG composed of the auxiliary sub-pixels Pa in the component area CA has been described (see Figure 5 and Figure 6 ) having the same as the pixel group PG composed of the main sub-pixels Pm in the main display area MDA (see Figure 4)Exemplary embodiments of the same configuration. However, the exemplary embodiments of the present inventive concept are not limited thereto.

[0226] For example, as Figure 16 and Figure 17 shown in the exemplary embodiments of ([[]]END]] Figure 16 and Figure 17 which is a schematic plan view showing the arrangement of sub-pixels and wiring lines of a display panel according to another exemplary embodiment), the pixel group PG in the main display area MDA may include a total of eight main sub-pixels Pm. The eight main sub-pixels Pm include a red sub-pixel Pr, a green sub-pixel Pg, a blue sub-pixel Pb, and a green sub-pixel Pg arranged in sequence in the +x direction in one row, and a blue sub-pixel Pb, a green sub-pixel Pg, a red sub-pixel Pr, and a green sub-pixel Pg arranged in sequence in the +x direction in the row below it. In contrast, the pixel group PG in the component area CA may include a total of six auxiliary sub-pixels Pa. The six auxiliary sub-pixels Pa include a red sub-pixel Pr, a green sub-pixel Pg, and a blue sub-pixel Pb arranged in sequence in the +x direction in one row, and a blue sub-pixel Pb, a green sub-pixel Pg, and a red sub-pixel Pr arranged in sequence in the +x direction in the row below it. With this configuration, a transmissive area TA with a larger area can be ensured in the component area CA.

[0227] In this embodiment, the pixel circuits of the 1st - 5th sub-pixels Sub 1-5 and the pixel circuits of the 3rd - 5th sub-pixels Sub 3-5 are electrically connected to each other through the fifth data line D5. Among them, the 1st - 5th sub-pixels Sub 1-5 are main sub-pixels Pm in the first row R1 adjacent to the lower side of the component area CA (for example, adjacent in the -y direction), and the 3rd - 5th sub-pixels Sub 3-5 are main sub-pixels Pm in the third row R3 adjacent to the upper side of the component area CA (for example, adjacent in the +y direction). The fifth data line D5 spans across the component area CA, but is not connected to the pixel circuits of the auxiliary sub-pixels Pa located in the component area CA. Since the number of main sub-pixels Pm included in the pixel group PG in the main display area MDA is greater than the number of auxiliary sub-pixels Pa included in the pixel group PG in the component area CA, the fifth data line D5 is not connected to the pixel circuits of the auxiliary sub-pixels Pa.

[0228] The 6 - 1st data line D 6-1 is electrically connected to the 1st - 6th sub-pixels Sub 1-6 located in the first row R1. However, the 6 - 1st data line D 6-1 extends in the +y direction in the main display area MDA, but does not extend across the component area CA. For example, the 6 - 1st data line D6-1 may terminate in a part adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction) or located in a part of the component area CA that can reach the main display area MDA. The 6-2 data line D 6-2 is electrically connected to the 3-6 sub-pixel Sub located in the third row R3 3-6 However, the 6-2 data line D 6-2 extends in the -y direction in the main display area MDA, but does not extend across the component area CA. For example, the 6-2 data line D 6-2 may terminate in a part adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction) or located in a part of the component area CA that can reach the main display area MDA.

[0229] As Figure 17 shown in the exemplary embodiment of 6-1 the 6-1 data line D 6-2 and the 6-2 data line D 6-1 are electrically connected to each other through the third bridge wiring B3, where the third bridge wiring B3 is located on a layer different from the 6-1 data line D 6-2 and the 6-2 data line D 6-1 and has one side in contact with the 6-1 data line D 6-2 and the other side in contact with the 6-2 data line D. In addition, the third bridge wiring B3 has a part extending along at least a part of the fifth data line D5, and thus, the area of the transmissive area TA can be large. The third bridge wiring B3 does not pass through the part of the component area CA occupied by the auxiliary sub-pixel Pa and extends substantially in the +y direction along the outside of the auxiliary sub-pixel Pa (e.g., in the +x direction).

[0230] The above reference Figure 10 and Figure 11 to the exemplary embodiments of 4-1 the 4-1 data line D 4-2 the 4-2 data line D 6-1 and the second bridge wiring B2 can be applied to the 6-1 data line D 6-2 the 6-2 data line D 6-1 and the third bridge wiring B3. For example, the 6-1 data line D 6-2 and the 6-2 data line D 2-1 can be located on the same layer as the first data line D1, the 2-1 data line D 2-2 and the 2-2 data line D 2-1 and the third bridge wiring B3 can be located on the same layer as the first bridge wiring B1. The first bridge wiring B1 and the third bridge wiring B3 can be located on a layer covering the first data line D1, the 2-1 data line D 2-2, the 6-1 data line D 6-1 and the 6-2 data line D 6-2 on the insulating layer.

[0231] has been referred to Figure 16 and Figure 17 Exemplary embodiments have been described in which the number of main sub-pixels Pm included in the pixel group PG in the main display area MDA is greater than the number of auxiliary sub-pixels Pa included in the pixel group PG in the component area CA. However, the description given with reference to Figure 16 and Figure 17 Exemplary embodiments can be applied to exemplary embodiments in which the number of main sub-pixels Pm included in the pixel group PG in the main display area MDA is equal to the number of auxiliary sub-pixels Pa included in the pixel group PG in the component area CA. For example, the resolution in the component area CA is lower than about 1 / 2 of the resolution in the main display area MDA.

[0232] Exemplary embodiments of the inventive concept are not limited to Figures 10 to 17 the number of line lines or sub-pixels shown in the exemplary embodiments. For example, in an exemplary embodiment, the display panel may include at least one first data line that extends across the component area CA from a lower row (such as the first row R1) adjacent to the lower side of the component area CA (e.g., adjacent in the -y direction) to an upper row (such as the third row R3) adjacent to the upper side of the component area CA (e.g., adjacent in the +y direction). The at least one first data line electrically connects the main sub-pixels Pm in the lower row and the upper row to the auxiliary sub-pixels Pa in the component area CA. At least one lower second data line is electrically connected to the main sub-pixels Pm in the lower row and does not extend across the component area CA. At least one upper second data line is electrically connected to the main sub-pixels Pm in the upper row and does not extend across the component area CA. The display panel includes at least one bridge line having a first end connected to one of the lower second data lines and a second end connected to one of the upper second data lines. The at least one bridge line is arranged on a layer different from the at least one first data line, and each of the at least one bridge lines has an overlapping portion extending along at least a part of one of the first data lines as described above.

[0233] A data line electrically connected to a pixel circuit of a main sub-pixel Pm in a part adjacent to the lower side (e.g., adjacent in the -y direction) of a component area CA in a main display area MDA can be electrically connected to a data line through a jumper line located on a layer different from the data line. The data line is electrically connected to a pixel circuit of a main sub-pixel Pm in a part adjacent to the upper side (e.g., adjacent in the +y direction) of the component area CA in the main display area MDA. The jumper line has a part extending along at least a part of the data line across the component area CA, and thus, the area of the transmissive area TA can be large. Additionally, since the resolution in the component area CA is lower than about 1 / 2 of the resolution in the main display area MDA, the jumper line does not pass through a part occupied by auxiliary sub-pixels Pa in the component area CA and extends substantially in the +y direction along the outside of the auxiliary sub-pixels Pa.

[0234] So far, a display device having a display panel 10 and a component 20 as an electronic component has been described. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, the display panel 10 as described above itself is also within the scope of the inventive concept.

[0235] According to one or more exemplary embodiments of the inventive concept, a display panel and a display device including the display panel can be implemented, in which the display panel has an extended display area so as to display an image even in an area where a component as an electronic component is arranged. However, the scope of the inventive concept is not limited by these effects.

[0236] It should be understood that the exemplary embodiments described herein should be considered only in a descriptive sense and not for the purpose of limitation. The description of features or aspects in each exemplary embodiment should generally be considered as available for other similar features or aspects in other exemplary embodiments. Although one or more exemplary embodiments have been described with reference to the drawings, those of ordinary skill in the art will understand that various changes can be made in form and detail without departing from the scope and spirit defined in the appended claims.

Claims

1. A display panel, comprising: A first-1 sub-pixel and a first-2 sub-pixel, the first-1 sub-pixel and the first-2 sub-pixel are arranged in a main display area above a substrate, and the main display area is located outside a component area in a plan view; A second-1 sub-pixel and a second-2 sub-pixel, the second-1 sub-pixel and the second-2 sub-pixel are arranged in the component area above the substrate, the second-1 sub-pixel and the second-2 sub-pixel include thin film transistors, and each of the thin film transistors has a semiconductor layer; And A conductive layer, the conductive layer is arranged between the semiconductor layer and the substrate, and the conductive layer includes an opening with a polygonal shape in the component area in the plan view, and at least one inner angle of the opening is an obtuse angle.

2. The display panel according to claim 1, wherein, In the plan view, the conductive layer overlaps with the thin film transistors of the second-1 sub-pixel and the second-2 sub-pixel.

3. The display panel according to claim 1, wherein, In the plan view, the conductive layer overlaps with all the thin film transistors included in the second-1 sub-pixel and the second-2 sub-pixel.

4. The display panel according to claim 1, wherein, In the plan view, the conductive layer overlaps with the pixel electrodes included in the second-1 sub-pixel and the second-2 sub-pixel.

5. The display panel according to claim 1, further comprising: A metal layer, the metal layer is arranged between the substrate and the thin film transistor included in the first-1 sub-pixel.

6. The display panel according to claim 5, wherein, The metal layer overlaps with a part of the semiconductor layer of the thin film transistor of the first-1 sub-pixel, and the part of the semiconductor layer overlaps with the gate electrode of the thin film transistor of the first-1 sub-pixel.

7. The display panel according to claim 5, wherein, The conductive layer and the metal layer are arranged in the same layer.

8. The display panel according to claim 1, wherein, The opening of the conductive layer defines a transmission area in the component area.

9. The display panel according to claim 8, wherein, The light transmittance in the component area is different from the light transmittance in the main display area.

10. The display panel according to claim 8, further comprising: An organic insulating layer, the organic insulating layer is arranged between the substrate and the pixel electrodes included in the second-1 sub-pixel and the second-2 sub-pixel, and the organic insulating layer includes a hole corresponding to the opening of the conductive layer.

11. The display panel according to claim 10, wherein, In the plan view, the hole of the organic insulating layer overlaps with the opening of the conductive layer.

12. The display panel according to claim 1, wherein, The group including the first-1 sub-pixel and the first-2 sub-pixel repeatedly appears in the main display area, and the group including the second-1 sub-pixel and the second-2 sub-pixel repeatedly appears in the component area.

13. The display panel according to claim 12, wherein, The group including the second-1 sub-pixel and the second-2 sub-pixel is arranged above the conductive layer.

14. The display panel according to claim 12, wherein, In the plan view, the group including the second-1 sub-pixel and the second-2 sub-pixel overlaps with the conductive layer.

15. The display panel according to claim 1, wherein, The opening of the conductive layer has an octagonal shape.

16. The display panel according to claim 1, further comprising: A bridge wiring, the bridge wiring transmits a signal to a sub-pixel arranged beside the component area in the main display area.

17. The display panel according to claim 1, wherein, In the plan view, the bridge wiring overlaps with the conductive layer in the component area.

18. The display panel according to claim 1 further includes: A driving voltage line, which is in the main display area, and the driving voltage line is electrically connected to the 1-1st sub-pixel to apply a driving voltage to the 1-1st sub-pixel, wherein the conductive layer is electrically connected to the driving voltage line.

19. The display panel according to claim 18, wherein, The driving voltage line is arranged in a layer different from the layer where the conductive layer is arranged.

20. The display panel according to claim 1, wherein, The component area has a circular shape in the plan view.

21. A display panel, comprising: A 1-1st sub-pixel and a 1-2nd sub-pixel, which are arranged above a substrate in a main display area, and the main display area is located outside a component area in the plan view; A 2-1st sub-pixel and a 2-2nd sub-pixel, which are arranged above the substrate in the component area, the 2-1st sub-pixel and the 2-2nd sub-pixel include thin film transistors, and each of the thin film transistors has a semiconductor layer; And A conductive layer, which is arranged between the semiconductor layer and the substrate, and the conductive layer includes an opening with a polygonal shape in the component area in the plan view, and the conductive layer overlaps with the thin film transistors of the 2-1st sub-pixel and the 2-2nd sub-pixel in the plan view.

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