System and method for controlling vehicle system starting

Abstract

A method includes storing, by a microcontroller, cache data of the microcontroller into a dynamic random access memory (DRAM) in response to the microcontroller receiving a power down command. The method includes operating, by a DRAM controller, the DRAM in a standby state in response to the microcontroller storing the cache data into the DRAM. The method includes determining, by the DRAM controller and while the DRAM is operating in the standby state, a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof. The method includes determining, by the DRAM controller, whether a hang-up to storage condition is satisfied based on the temporal characteristic, the charge characteristic, or the combination thereof. The method includes storing, by the DRAM controller, the cache data of the DRAM into a read-only memory (ROM) in response to the suspend-to-storage condition being satisfied.

Description

Technical Field

[0001] The present disclosure relates to systems and methods for controlling the startup of a vehicle system. Background Art

[0002] The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

[0003] A vehicle system may include one or more dynamic random access memories (DRAMs) used by a microcontroller to perform various vehicle functions. For example, a vehicle infotainment and / or cockpit system may include one or more DRAMs having a storage space of 16, 24, or 32 gigabytes (GB), which are used by the microcontroller to execute vehicle infotainment and / or cockpit system routines.

[0004] In addition, as the complexity of the routines executed by the microcontroller increases, the vehicle infotainment and / or cockpit system may need to access the data of the DRAM at a predefined speed and energy efficiency. To access data according to the predefined speed and / or energy efficiency, the vehicle infotainment and / or cockpit system may execute a "suspend to ram" routine after receiving a power-off command, so as to operate the DRAM in a standby state. That is, the microcontroller of the vehicle infotainment and / or cockpit system moves at least a set of data used to execute various routines into the DRAM until the vehicle receives a power-on command, and supplies electrical energy from the power supply to the DRAM to refresh the data until the vehicle receives a power-on command.

[0005] However, the DRAM can only retain data until the power supply runs out (for example, the DRAM can operate in the standby mode for 72 to 80 hours). Thus, when the vehicle infotainment and / or cockpit system receives a power-on command after the power supply runs out, due to data loss, the final initialization / startup of the vehicle infotainment and / or cockpit system may be a time-consuming and resource-intensive process. The present disclosure addresses these and other problems of the DRAM operating in the standby state. Summary of the Invention

[0006] This section provides an overview of the present disclosure, rather than a full disclosure of its entire scope or all of its features.

[0007] The present disclosure provides a method for managing cache data stored by a vehicle control system. The method includes storing cache data of a microcontroller in a dynamic random access memory (DRAM) by the microcontroller in response to the microcontroller receiving a power-down command. The method includes operating the DRAM in a standby state by a DRAM controller in response to the microcontroller storing the cache data in the DRAM, wherein the DRAM can be operated in a standby state, an on state, and an off state. The method includes determining, by the DRAM controller and while the DRAM is operating in the standby state, a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof. The method includes determining, by the DRAM controller, whether a suspend-to-storage device condition is satisfied based on the time characteristic, the charge characteristic, or a combination thereof. The method includes storing the cache data of the DRAM in a read-only memory (ROM) by the DRAM controller in response to the suspend-to-storage device condition being satisfied.

[0008] In a variant of the method of the above paragraph, which can be implemented individually or in any combination, the method further includes: determining by the microcontroller whether a power-on command is received; and obtaining cache data from the ROM by the microcontroller in response to the suspend-to-storage device condition being satisfied. In one embodiment, the method further includes obtaining cache data from the DRAM by the microcontroller in response to the suspend-to-storage device condition not being satisfied. In one embodiment, the method further includes performing one or more infotainment control routines by the microcontroller in response to obtaining cache data from one of the DRAM and the ROM. In one embodiment, the time characteristic indicates the amount of time the DRAM operates in the standby state; and in response to the amount of time being greater than a threshold amount of time, the suspend-to-storage device condition is satisfied. In one embodiment, the charging characteristic indicates the amount of charge of the DRAM; and in response to the amount of charge being less than a threshold amount of charge, the suspend-to-storage device condition is satisfied. In one embodiment, the ROM has a sequential read speed of at least 4.2 gigabytes per second. In one embodiment, the ROM has a sequential write speed of at least 2.8 gigabytes per second. In one embodiment, the method further includes performing a bootloader routine in response to the microcontroller receiving a power-on command and the DRAM operating in the off state. In one embodiment, the method further includes performing a suspend-to-DRAM routine in response to the microcontroller receiving a power-on command and the DRAM operating in the standby state.

[0009] The present disclosure provides a vehicle control system including a dynamic random access memory (DRAM), where the DRAM can operate in a standby state, an active state, and a shutdown state. The vehicle control system includes a DRAM controller, a microcontroller, and a read-only memory (ROM). The DRAM, the DRAM controller, the microcontroller, and the ROM are communicatively coupled to each other. The microcontroller is configured to store the cache data of the microcontroller into the DRAM in response to the microcontroller receiving a power-off command. The DRAM controller is configured to operate the DRAM in one of a shutdown state and a standby state in response to the microcontroller receiving a power-off command. The DRAM controller is configured to determine a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof when the DRAM operates in the standby state. The DRAM controller is configured to determine whether a suspend-to-storage device condition is satisfied based on the time characteristic, the charge characteristic, or a combination thereof. The DRAM controller is configured to store the cache data of the DRAM into the ROM in response to the suspend-to-storage device condition being satisfied.

[0010] In a variant of the method in the above paragraph that can be implemented individually or in any combination, the microcontroller is further configured to: determine whether a power-on command is received; and obtain the cache data from the ROM in response to the suspend-to-storage device condition being satisfied. In one embodiment, the microcontroller is further configured to obtain the cache data from the DRAM in response to the suspend-to-storage device condition not being satisfied. In one embodiment, the microcontroller is further configured to execute one or more infotainment control routines in response to obtaining the cache data from one of the DRAM and the ROM. In one embodiment, the time characteristic indicates the amount of time the DRAM operates in the standby state; and in response to the amount of time being greater than a threshold amount of time, the suspend-to-storage device condition is satisfied. In one embodiment, the charging characteristic indicates the amount of charge of the DRAM; and in response to the amount of charge being less than a threshold amount of charge, the suspend-to-storage device condition is satisfied. In one embodiment, the ROM has a sequential read speed of at least 4.2 gigabytes per second. In one embodiment, the ROM has a sequential write speed of at least 2.8 gigabytes per second. In one embodiment, the microcontroller is further configured to execute a bootloader routine in response to the microcontroller receiving a power-on command and the DRAM operating in the shutdown state. In one embodiment, the microcontroller is further configured to execute a suspend-to-DRAM routine in response to the microcontroller receiving a power-on command and the DRAM operating in the standby state.

[0011] From the description provided herein, additional applicable scopes will be apparent. It should be understood that the description and specific examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To better understand the present disclosure, various embodiments thereof will now be described by way of example with reference to the accompanying drawings, wherein:

[0013] Figure 1 is a functional block diagram of an exemplary vehicle in accordance with the teachings of the present disclosure;

[0014] Figure 2 is a functional block diagram of an exemplary vehicle control system in accordance with the teachings of the present disclosure;

[0015] Figure 3 is a flowchart illustrating an exemplary control routine for managing cache data stored by a vehicle control system in accordance with the teachings of the present disclosure;

[0016] Figure 4A is a flowchart illustrating an exemplary subroutine of a control routine for managing cache data stored by a vehicle control system in accordance with the teachings of the present disclosure;

[0017] Figure 4B is a flowchart illustrating another exemplary subroutine of a control routine for Figure 4A in accordance with the teachings of the present disclosure;

[0018] Figure 4C is a flowchart illustrating another exemplary subroutine of a control routine for Figure 4A in accordance with the teachings of the present disclosure; and

[0019] Figure 4D is a flowchart illustrating another exemplary subroutine of a control routine for Figure 4A in accordance with the teachings of the present disclosure.

[0020] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure in any way. Detailed Description

[0021] The following description is merely exemplary in nature and is not intended to limit the present disclosure, application, or uses. It should be understood that throughout the drawings, corresponding reference numerals indicate the same or corresponding parts and features.

[0022] The present disclosure provides a vehicle system having a DRAM, a DRAM controller, a microcontroller, and a read-only memory (ROM), where the ROM has a sequential read speed of at least 4.2 gigabytes per second and a sequential write speed of at least 2.8 gigabytes per second. The microcontroller is configured to store cache data of the microcontroller into the DRAM in response to the DRAM operating in a standby state. The DRAM controller is configured to operate the DRAM in one of a shutdown state and a standby state in response to the microcontroller receiving a power-down command. When the DRAM operates in a standby state, the DRAM controller is configured to determine a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof, and determine whether a "suspend to storage" condition is satisfied. The DRAM controller moves cache data from the DRAM to the ROM in response to the suspend to storage condition being satisfied.

[0023] By performing a "suspend to storage" routine as described herein (i.e., storing cache data of the DRAM into the ROM in response to the "suspend to storage" condition being satisfied), data employed by the vehicle control system can be stored by the vehicle control system for an increased period of time, such as beyond the depletion of the power source coupled to the DRAM. Additionally, the microcontroller can obtain data at an increased speed and efficiency in response to receiving a power-on command, as described in further detail below.

[0024] Reference Figure 1 , environment 100 is shown, and the environment generally includes vehicle 110. In one embodiment, vehicle 110 includes one or more vehicle systems 120, one or more electronic control modules (ECMs) 130, multiple power sources 140, and a vehicle interface 150 communicatively coupling one or more ECMs 130 to one or more vehicle systems 120. As an example, vehicle interface 150 can include a controller area network (CAN) bus, a local interconnect network (LIN) bus, and / or a clock extended peripheral interface (CXPI) bus for exchanging data and signals between one or more ECMs 130 and one or more vehicle systems 120.

[0025] One or more ECMs 130 are configured to control and / or monitor one or more vehicle systems 120. As an example, ECM 130 can include a startup module 132 configured to control one or more functions of the infotainment system 122 among one or more vehicle systems 120. In one embodiment, infotainment system 122 includes various components for performing infotainment control routines, such as a display device of the infotainment system, one or more navigation modules, one or more vehicle-to-vehicle or vehicle-to-infrastructure cellular connectivity modules, etc. Reference is made below to Figure 2Provide additional details regarding the startup module 132. Although the startup module 132 is shown as part of the infotainment system 122, it should be understood that the startup module 132 can be provided as part of various other types of vehicle systems and is not limited to the examples described herein, such as cockpit systems, internal combustion control systems, powertrain control systems, transmission control systems, brake control systems, body control systems, climate control systems, suspension control systems, and / or other types of vehicle systems.

[0026] The power source 140 can be provided by an energy storage device (such as the vehicle 110's battery) configured to provide electrical energy to various components of the vehicle 110, such components as one or more ECMs 130 and one or more vehicle systems 120. As an example, the plurality of power sources 140 includes a main power source 140-1 configured to provide electrical energy when the vehicle 110 is powered on. As another example, the plurality of power sources 140 includes a backup power source 140-2 configured to provide electrical energy when the vehicle 110 is powered off, where the backup power source 140-2 and the main power source 140-1 have different electrical characteristics (such as power output, charge time, depletion time, etc.). It should be understood that the vehicle 110 can include known electrical interfaces and / or power converter circuits for physically coupling and electrically coupling the power source 140 to one or more ECMs 130 and one or more vehicle systems 120.

[0027] In one embodiment and with reference to Figure 2, the startup module 132 may include a read-only memory (ROM) circuit 200, a dynamic random access memory (DRAM) system 210, and a microcontroller 220 that are communicatively coupled to each other via known communication protocols. In one embodiment, the ROM circuit 200 is a non-volatile memory circuit that stores data used by the microcontroller 220 when executing one or more routines, such as a mask ROM circuit, a programmable ROM circuit, an erasable programmable ROM circuit, or an electrically erasable programmable ROM circuit. In one embodiment, the ROM circuit 200 has a sequential read speed of at least 4.2 gigabytes per second (GB / s), and the ROM circuit 200 has a sequential write speed of at least 2.8 GB / s. As an example, the ROM circuit 200 is a fast non-volatile memory (NVMe), a solid-state drive (SSD)-type memory circuit including a communication interface and one or more driver circuits that operate together according to a Peripheral Component Interconnect Express (PCIe) standard such as the PCI 4.0 and PCIe 5.0 standards. As another example, the ROM circuit 200 may be a Universal Flash Storage 4.0 (UFS 4.0) or UFS 4.1-type non-volatile memory circuit. It should be understood that the ROM circuit 200 may be provided by various other types of non-volatile memory circuits that have a sequential read speed of at least 4.2 GB / s and a sequential write speed of at least 2.8 GB / s and are not limited to the examples described herein.

[0028] In one embodiment, the DRAM system 210 includes a DRAM circuit 212 and a DRAM controller 214. In one embodiment, the microcontroller 220 includes a data control module 222, a bootloader module 224, an infotainment control module 226, and a cache circuit 228. In one embodiment, the DRAM circuit 212 is a volatile memory circuit including a plurality of addressable banks, each of the plurality of addressable banks including transistors and capacitors. The DRAM circuit 212 stores cache data used by the bootloader module 224 and the infotainment control module 226 while executing a bootloader routine and an infotainment control routine (described in more detail below), respectively. As an example, each bit of the cache data is assigned and stored in a corresponding one of the plurality of addressable banks (e.g., 16,000,000,000 addressable banks corresponding to an example capacity of the DRAM circuit 212). To store a bit of the cache data, a transistor selectively couples a capacitor to a standby power supply 140-2 to obtain a charge, where a charged capacitor indicates a logic high (e.g., "1"), and where a discharged capacitor indicates a logic low (e.g., "0").

[0029] In one embodiment, the DRAM circuit 212 can operate in an on state, an off state, and a standby state. As used herein, the "on state" refers to a state in which the microcontroller 220 has received (or is receiving) a power-on command and the bootloader module 224 or the infotainment control module 226 is executing a bootloader routine or an infotainment control routine, respectively. The power-on command can include, but is not limited to, the operator of the vehicle 110 turning on the vehicle 110 and / or activating the ignition system of the vehicle 110. As used herein, the "standby state" refers to a state in which the microcontroller 220 has received (or is receiving) a power-off command and the DRAM controller 214 executes a "suspend to ram" routine, which will be described in further detail below. The power-off command can include, but is not limited to, the operator of the vehicle 110 turning off the vehicle 110 and / or deactivating the ignition system of the vehicle 110. As used herein, the "off state" refers to the following state: in which the microcontroller 220 has received a power-off command, the DRAM controller 214 is unable to execute the "suspend to ram" routine due to the depletion of electrical energy from the backup power supply 140-2, and the DRAM controller 214 has executed (or started to execute) a "suspend to storage device" routine. That is, due to the depletion of electrical energy from the backup power supply 140-2 for refreshing the addressable banks of the DRAM circuit 212, the DRAM circuit 212 loses the cached data stored therein.

[0030] When the DRAM circuit 212 transitions from the on state to the standby state, the microcontroller 220 and the DRAM controller 214 jointly initiate a "suspend to ram" routine. That is, the data control module 222 retrieves the cached data from the cache circuit 228 and provides the cached data to the DRAM controller 214, which in turn stores the cached data in the DRAM circuit 212. In addition, as described above, the DRAM controller 214 periodically refreshes the addressable banks of the DRAM circuit 212 to preserve / maintain the cached data by selectively coupling the capacitors to the backup power supply 140-2 via transistors.

[0031] When the DRAM circuit 212 operates in a standby state, the DRAM controller 214 is configured to determine a time characteristic associated with the DRAM circuit 212, a charge characteristic associated with the DRAM circuit 212, or a combination thereof. In one embodiment, the time characteristic indicates the amount of time the DRAM circuit 212 has been operating in the standby state. To perform the functions described herein, the DRAM controller 214 may include a timer module 216 that is configured to increment a timer value of the timer module while the DRAM circuit 212 operates in the standby state. Additionally, the DRAM controller 214 may include a charging circuit 218 that is configured to measure the amount of charge of a capacitor of the DRAM circuit 212 (e.g., sense amplifier circuit) and / or the backup power supply 140-2 (e.g., voltage, current, and / or electrical power / energy sensors).

[0032] The DRAM controller 214 determines whether a "suspend to storage" condition is satisfied based on a comparison of the charge characteristic with a threshold charge characteristic and / or the time characteristic and / or the time characteristic, and stores the cache data in the ROM circuit 200 when the "suspend to storage" condition is satisfied. As an example, when the amount of charge (as indicated by the charge characteristic) is less than a threshold amount of charge, the DRAM controller 214 determines that the "suspend to storage" condition is satisfied. In one embodiment, the threshold amount of charge may correspond to a predefined voltage level of the capacitor for maintaining and / or preserving the accuracy of the data stored by a given capacitor. As another example, when the amount of time (as indicated by the time characteristic) is greater than a threshold amount of time, the DRAM controller 214 determines that the "suspend to storage" condition is satisfied. In one embodiment, the threshold amount of time may correspond to the amount of time (e.g., 72 hours, 80 hours, and other predefined time values) that the backup power supply 140-2 is depleted when providing charge (i.e., refresh signal) to the DRAM circuit 212.

[0033] The data control module 222 is configured to selectively store the cache data employed by the bootloader module 224 and the infotainment control module 226 in one of the cache circuit 228, the DRAM circuit 212, and the ROM circuit 200. As an example and as described above, when the DRAM circuit 212 operates in the standby mode and executes the "suspend to ram" routine, the data control module 222 provides the cache data to the DRAM circuit 212 via the DRAM controller 214.

[0034] As another example, the data control module 222 is configured to obtain cache data from the ROM circuit 200 and store the cache data in the cache circuit 228 when the "suspend to storage device" condition is satisfied and in response to receiving a power-on command. Subsequently, when the data control module 222 stores the cache data into the cache circuit 228, the bootloader module 224 may execute a bootloader routine (e.g., a known boot routine for powering on and initializing the microcontroller 220).

[0035] As an additional example, the data control module 222 is configured to obtain cache data from the DRAM 212 and store the cache data in the cache circuit 228 in response to the "suspend to storage device condition" not being satisfied and in response to receiving a power-on command (i.e., the DRAM circuit 212 operates in a standby state). Subsequently, when the data control module 222 stores the cache data into the cache circuit 228, the infotainment control module 226 may execute an infotainment control routine (e.g., an image / video display routine for displaying vehicle settings and / or controls of the vehicle 110, navigation instructions of the vehicle 110, connectivity settings of the vehicle 110, etc. via a display device of the infotainment system 122).

[0036] Reference Figure 3 , a flowchart illustrating an example routine 300 for managing cache data stored by a vehicle control system (e.g., the startup module 132) is shown. At 304, the routine 300 stores the cache data of the microcontroller 220 into the DRAM circuit 212 in response to the microcontroller 220 receiving a power-off command. At 308, the DRAM controller 214 operates the DRAM circuit 212 in a standby state in response to the microcontroller storing the cache data into the DRAM circuit 212. That is, at 308, the microcontroller 220 and the DRAM controller 214 execute a "suspend to RAM" routine.

[0037] At 312, when the DRAM circuit 212 operates in a standby state, the DRAM controller 214 determines a time characteristic associated with the DRAM circuit 212, a charge characteristic associated with the DRAM circuit 212, or a combination thereof. At 316, the DRAM controller 214 determines whether the suspend to storage device condition is satisfied based on the time characteristic, the charge characteristic, or a combination thereof. At 320, the DRAM controller 214 stores the cache data of the DRAM circuit 212 into the ROM circuit 200 in response to the "suspend to storage device" condition being satisfied. That is, at step 320, the DRAM controller 214 executes a "suspend to storage device" routine.

[0038] Reference Figures 4A to 4D, a flowchart is shown illustrating exemplary subroutines 400-1, 400-2, 400-3, 400-4 (collectively referred to hereinafter as "routine 400") for managing cache data stored by a vehicle control system (such as startup module 132). In Figures 4A to 4B , each of the example steps in the example steps of routine 400 is illustrated by a dashed arrow.

[0039] Referring Figure 4A , subroutine 400-1 corresponds to a portion of the routine, where startup module 132 may be executed in response to receiving a power-on command and before an infotainment control routine has been executed. At step 401, data control module 222 loads data from ROM circuit 200 into bootloader module 224. At step 402, bootloader module 224 executes a bootloader routine and provides a copy of the data (hereinafter referred to as the "boot image") to DRAM controller 214, which stores the boot image in DRAM circuit 212. At step 403, DRAM controller 212 moves the boot image into cache circuit 228, and infotainment control module 226 obtains the boot image via data control module 222 to execute an infotainment control routine at step 404. To perform the functions described at steps 401 through 404, microcontroller 220, ROM circuit 200, and DRAM system 210 may jointly execute, for example, a known boot / startup routine based on the von-Neumann architecture.

[0040] Referring Figure 4B , after subroutine 400-1 and after receiving a power-off command, subroutine 400-2 is executed. That is, subroutine 400-2 corresponds to executing a "suspend to RAM" routine and optionally corresponds to executing a "suspend to storage device" routine. At step 405, DRAM controller 214 designates the state of DRAM circuit 212 to operate in a standby state and saves the data currently stored in DRAM circuit 212 at step 406. At step 407, DRAM controller 214 stores the cache data of cache circuit 228 into DRAM circuit 212.

[0041] At step 408, DRAM controller 214 continues to execute the "suspend to RAM" routine by refreshing the addressable banks of DRAM circuit 212. Additionally, at step 408, as described above, DRAM controller 214 determines one of the following: (i) a subsequent power-on command has been received, or (ii) whether a "suspend to storage device" condition has been met before a subsequent power-on command is received. In response to receiving a subsequent power-on command before the "suspend to storage device" condition is met, startup module 132 executesFigure 4C the subroutine 400-3 shown in Figure 4D the subroutine 400-4 shown in

[0042] Referring to Figure 4C and in response to receiving a subsequent power-on command before the "suspend to storage device" condition is satisfied, the DRAM controller 214 designates the DRAM circuit 212 to operate in an on state at step 409 and moves data from the DRAM circuit 212 to the cache circuit 228 at step 410. At step 411, the data control module 222 provides the cache data to the infotainment control module 226 for performing the infotainment control routines described herein. Referring to Figure 4D and in response to the "suspend to storage device" condition being satisfied before receiving a subsequent power-on command, the DRAM controller 214 moves data from the DRAM circuit 212 to the ROM circuit 200 at step 412, thereby saving and maintaining the data for the subsequent power-on command.

[0043] Based on the above, a general overview of the present disclosure is provided below, rather than a comprehensive summary. In a first implementation A1, a method for managing cache data stored by a vehicle control system includes storing cache data of a microcontroller into a dynamic random access memory (DRAM) by the microcontroller in response to the microcontroller receiving a power-off command. The method includes operating the DRAM in a standby state by the DRAM controller in response to the microcontroller storing the cache data into the DRAM, where the DRAM can operate in a standby state, an on state, and an off state. The method includes determining, by the DRAM controller and while the DRAM is operating in the standby state, a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof. The method includes determining, by the DRAM controller, whether a suspend to storage device condition is satisfied based on the time characteristic, the charge characteristic, or a combination thereof. The method includes storing, by the DRAM controller, the cache data of the DRAM into a read-only memory (ROM) in response to the suspend to storage device condition being satisfied.

[0044] In a second implementation A2 that may include the first implementation A1, the method further includes: determining, by the microcontroller, whether a power-on command is received; and obtaining, by the microcontroller, the cache data from the ROM in response to the suspend to storage device condition being satisfied. In a third implementation A3 that may include any combination of the first implementation A1 to the second implementation A2, the method further includes obtaining, by the microcontroller, the cache data from the DRAM in response to the suspend to storage device condition not being satisfied.

[0045] In a fourth implementation A4 that can include any combination of the first implementation A1 to the third implementation A3, the method further includes executing, by a microcontroller, one or more infotainment control routines in response to obtaining cache data from one of a DRAM and a ROM. In a fifth implementation A5 that can include any combination of the first implementation A1 to the fourth implementation A4, a time characteristic indicates an amount of time for which the DRAM operates in a standby state; and in response to the amount of time being greater than a threshold amount of time, a suspend-to-storage device condition is satisfied.

[0046] In a sixth implementation A6 that can include any combination of the first implementation A1 to the fifth implementation A5, a charge characteristic indicates an amount of electric charge of the DRAM; and in response to the amount of electric charge being less than a threshold amount of electric charge, a suspend-to-storage device condition is satisfied. In a seventh implementation A7 that can include any combination of the first implementation A1 to the sixth implementation A6, the ROM has a sequential read speed of at least 4.2 gigabytes per second.

[0047] In an eighth implementation A8 that can include any combination of the first implementation A1 to the seventh implementation A7, the ROM has a sequential write speed of at least 2.8 gigabytes per second. In a ninth implementation A9 that can include any combination of the first implementation A1 to the eighth implementation A8, the method further includes executing a bootloader routine in response to the microcontroller receiving a power-on command and the DRAM operating in a shutdown state. In a tenth implementation A10 that can include any combination of the first implementation A1 to the ninth implementation A9, the method further includes executing a suspend-to-DRAM routine in response to the microcontroller receiving a power-on command and the DRAM operating in a standby state.

[0048] In an eleventh implementation A11, a vehicle control system includes a dynamic random access memory (DRAM), where the DRAM can operate in a standby state, an on state, and a shutdown state. The vehicle control system includes a DRAM controller, a microcontroller, and a read-only memory (ROM). The DRAM, the DRAM controller, the microcontroller, and the ROM are communicatively coupled to each other. The microcontroller is configured to store cache data of the microcontroller in the DRAM in response to the microcontroller receiving a power-off command. The DRAM controller is configured to operate the DRAM in one of a shutdown state and a standby state in response to the microcontroller receiving a power-off command. The DRAM controller is configured to determine a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof when the DRAM operates in a standby state. The DRAM controller is configured to determine whether a suspend-to-storage device condition is satisfied based on the time characteristic, the charge characteristic, or a combination thereof. The DRAM controller is configured to store cache data of the DRAM in the ROM in response to the suspend-to-storage device condition being satisfied.

[0049] In a twelfth implementation A12 that may include an eleventh implementation A11, the microcontroller is further configured to determine whether a power-on command is received and obtain cache data from the ROM in response to the suspend-to-storage condition being satisfied. In a thirteenth implementation A13 that may include any combination of the eleventh implementation A11 to the twelfth implementation A12, the microcontroller is further configured to obtain cache data from the DRAM in response to the suspend-to-storage condition not being satisfied. In a fourteenth implementation A14 that may include any combination of the eleventh implementation A11 to the thirteenth implementation A13, the microcontroller is further configured to execute one or more infotainment control routines in response to obtaining cache data from one of the DRAM and the ROM.

[0050] In a fifteenth implementation A15 that may include any combination of the eleventh implementation A11 to the fourteenth implementation A14, the time characteristic indicates the amount of time the DRAM operates in the standby state; and in response to the amount of time being greater than a threshold amount of time, the suspend-to-storage condition is satisfied. In a sixteenth implementation A16 that may include any combination of the eleventh implementation A11 to the fifteenth implementation A15, the charge characteristic indicates the amount of charge of the DRAM; and in response to the amount of charge being less than a threshold amount of charge, the suspend-to-storage condition is satisfied.

[0051] In a seventeenth implementation A17 that may include any combination of the eleventh implementation A11 to the sixteenth implementation A16, the ROM has a sequential read speed of at least 4.2 gigabytes per second. In an eighteenth implementation A18 that may include any combination of the eleventh implementation A11 to the seventeenth implementation A17, the ROM has a sequential write speed of at least 2.8 gigabytes per second.

[0052] In a nineteenth implementation A19 that may include any combination of the eleventh implementation A11 to the eighteenth implementation A18, the microcontroller is further configured to execute a bootloader routine in response to the microcontroller receiving a power-on command and the DRAM operating in the off state. In a twentieth implementation A20 that may include any combination of the eleventh implementation A11 to the nineteenth implementation A19, the microcontroller is further configured to execute a suspend-to-DRAM routine in response to the microcontroller receiving a power-on command and the DRAM operating in the standby state.

[0053] Unless otherwise expressly specified herein, when describing the scope of the present disclosure, all numerical values indicating mechanical / thermal properties, percentage compositions, dimensions, and / or tolerances or other characteristics should be understood to be modified by the word "about" or "approximately". This modification is desirable for various reasons, including industrial practices, materials, manufacturing and assembly tolerances, and testing capabilities.

[0054] As used herein, the phrase "at least one of A, B, and C" should be construed to mean the logical (A or B or C), using the non-exclusive logical "or", and should not be construed as "at least one of A, at least one of B, and at least one of C".

[0055] In this application, the terms "controller" and / or "module" may refer to, be part of, or include the following: application specific integrated circuit (ASIC); digital, analog, or mixed analog / digital discrete circuits; digital, analog, or mixed analog / digital integrated circuits; combinational logic circuits; field programmable gate array (FPGA); processor circuits (shared, dedicated, or group) that execute code; memory circuits (shared, dedicated, or group) that store code executed by the processor circuits; other suitable hardware components that provide the functions; or a combination of some or all of the above, such as in a system on a chip.

[0056] The term "memory" is a subset of the term "computer-readable medium". The term "computer-readable medium" as used herein does not cover transient electrical or electromagnetic signals propagated through a medium (such as on a carrier wave); thus, the term "computer-readable medium" can be considered tangible and non-transitory. Non-limiting examples of non-transitory, tangible computer-readable media are non-volatile memory circuits (such as flash memory circuits, erasable programmable read-only memory circuits, or mask read-only circuits), volatile memory circuits (such as static random access memory circuits or dynamic random access memory circuits), magnetic storage media (such as analog or digital tapes or hard disk drives), and optical storage media (such as CDs, DVDs, or Blu-ray discs).

[0057] The devices and methods described in this application can be implemented in part or in whole by a special-purpose computer created by configuring a general-purpose computer to execute one or more specific functions embodied in a computer program. The functional blocks, process block components, and other elements described above serve as software specifications and can be transformed into a computer program by the routine work of a skilled technician or programmer.

[0058] The description of the present disclosure is merely exemplary in nature, and thus, variations that do not depart from the essence of the present disclosure are intended to be within the scope of the present disclosure. These variations should not be regarded as departing from the spirit and scope of the present disclosure.

Claims

1. A method for managing cache data stored by a vehicle control system, the method comprising: storing, by a microcontroller in response to the microcontroller receiving a power-off command, the cache data of the microcontroller into a dynamic random access memory (DRAM); operating, by a DRAM controller in response to the microcontroller storing the cache data into the DRAM, the DRAM in a standby state, wherein the DRAM is capable of operating in the standby state, an on state, and an off state; determining, by the DRAM controller and when the DRAM is operating in the standby state, a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof; determining, by the DRAM controller, whether a suspend-to-storage condition is satisfied based on the time characteristic, the charge characteristic, or a combination thereof; and storing, by the DRAM controller in response to the suspend-to-storage condition being satisfied, the cache data of the DRAM into a read-only memory (ROM).

2. The method according to claim 1, further comprising: determining, by the microcontroller, whether a power-on command is received; and obtaining, by the microcontroller in response to the suspend-to-storage condition being satisfied, the cache data from the ROM.

3. The method according to claim 2, further comprising obtaining, by the microcontroller, the cache data from the DRAM in response to the suspend-to-storage condition not being satisfied.

4. The method according to claim 3, further comprising executing, by the microcontroller, one or more infotainment control routines in response to obtaining the cache data from one of the DRAM and the ROM.

5. The method according to claim 1, wherein: the time characteristic indicates an amount of time the DRAM operates in the standby state; and in response to the amount of time being greater than a threshold amount of time, the suspend-to-storage condition is satisfied.

6. The method according to claim 1, wherein: a charge characteristic indicates an amount of charge of the DRAM; and in response to the amount of charge being less than a threshold amount of charge, the suspend-to-storage condition is satisfied.

7. The method according to claim 1, wherein the ROM has a sequential read speed of at least 4.2 gigabytes per second.

8. The method according to claim 1, wherein the ROM has a sequential write speed of at least 2.8 gigabytes per second.

9. The method according to claim 1, further comprising executing a bootloader routine in response to the microcontroller receiving a power-on command and the DRAM operating in the off state.

10. The method according to claim 1, further comprising executing a suspend-to-DRAM routine in response to the microcontroller receiving a power-on command and the DRAM operating in the standby state.

11. A vehicle control system, comprising: a dynamic random access memory (DRAM), wherein the DRAM is capable of operating in a standby state, an on state, and an off state; a DRAM controller; Microcontroller; and a read-only memory (ROM), wherein: the DRAM, the DRAM controller, the microcontroller, and the ROM are communicatively coupled to each other; the microcontroller is configured to store cache data of the microcontroller into the DRAM in response to the microcontroller receiving a power-off command; the DRAM controller is configured to operate the DRAM in one of the off state and the standby state in response to the microcontroller receiving the power-off command; the DRAM controller is configured to determine a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof when the DRAM is operating in the standby state; the DRAM controller is configured to determine whether a suspend-to-storage device condition is satisfied based on the time characteristic, the charge characteristic, or the combination thereof; and the DRAM controller is configured to store the cache data of the DRAM into the ROM in response to the suspend-to-storage device condition being satisfied.

12. The system of claim 11, wherein the microcontroller is further configured to: determine whether a power-on command is received; and obtain the cache data from the ROM in response to the suspend-to-storage device condition being satisfied.

13. The system of claim 12, wherein the microcontroller is further configured to obtain the cache data from the DRAM in response to the suspend-to-storage device condition not being satisfied.

14. The system of claim 13, wherein the microcontroller is further configured to execute one or more infotainment control routines in response to obtaining the cache data from one of the DRAM and the ROM.

15. The system of claim 11, wherein: the time characteristic indicates an amount of time the DRAM operates in the standby state; and in response to the amount of time being greater than a threshold amount of time, the suspend-to-storage device condition is satisfied.

16. The system of claim 11, wherein: a charging characteristic indicates an amount of charge of the DRAM; and in response to the amount of charge being less than a threshold amount of charge, the suspend-to-storage device condition is satisfied.

17. The system of claim 11, wherein the ROM has a sequential read speed of at least 4.2 gigabytes per second.

18. The system of claim 11, wherein the ROM has a sequential write speed of at least 2.8 gigabytes per second.

19. The system of claim 11, wherein the microcontroller is further configured to execute a bootloader routine in response to the microcontroller receiving a power-on command and the DRAM operating in the off state.

20. The system of claim 11, wherein the microcontroller is further configured to execute a suspend-to-DRAM routine in response to the microcontroller receiving a power-on command and the DRAM operating in the standby state.

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