Method and device for multiplication and accumulation operation
By using specific components and calculation processes in the multiplication and accumulation computing device, the problem of low efficiency of floating point multiplication and accumulation computing at low power is solved, and floating point operations with high power efficiency and high computing efficiency are achieved.
Patent Information
- Application Number
- CN202380081104.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-03-24
- Filing Date
- 2023-11-01
- Publication Date
- 2025-06-27
AI Technical Summary
The prior art is difficult to realize high-power efficiency floating point multiplication accumulation operation at low power, and floating point operation has problems in terms of large complexity and high power consumption.
By using components such as exponential adder, mantissa multiplier, exponential subtractor, mantissa shifter, mantissa adder and overflow counter in the multiplication accumulation calculation device, a series of operations are performed to implement floating-point multiplication accumulation operations, and the exponent is updated through normalization and rounding operations.
A floating point multiplication accumulation operation that provides high power efficiency at very low power is realized, and through this operation, it provides high computing efficiency to the artificial intelligence processor.
Smart Images
Figure CN120225989A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to floating-point multiply-accumulate (MAC) operation techniques for low-power artificial neural network computations. Background Art
[0002] Generally, for artificial neural network processing in various fields, an artificial intelligence (AI) processor with high power efficiency is required. To this end, artificial intelligence processors applying a processing-in-memory (PIM) architecture based on non-volatile memory have been developed.
[0003] Since such artificial intelligence processors generally only support operations of 8-bit fixed-point data types, it is necessary to study operation schemes using floating-point data types for artificial intelligence processors, and floating-point operations have problems in terms of high complexity and high power consumption.
[0004] Meanwhile, Korean Patent Application Publication No. 10-2022-0156268, entitled "Artificial Intelligence Accelerator", discloses an artificial intelligence accelerator that performs accumulation operations. Summary of the Invention
[0005] Technical Problem An object of the present disclosure is to provide a floating-point multiply-accumulate operation with high power efficiency at very low power.
[0006] Another object of the present disclosure is to provide high computational efficiency to an artificial intelligence processor through floating-point multiply-accumulate operations.
[0007] Technical Solution According to an embodiment for achieving the above object, there is provided a multiply-accumulate operation method performed by a multiply-accumulate operation device, the multiply-accumulate operation method including: calculating, by an exponent subtractor, a difference between a value obtained by adding a first exponent and a second exponent using an exponent adder and an exponent of a floating-point value to be added; calculating, by a mantissa multiplier, a value obtained by multiplying a first mantissa and a second mantissa; shifting, by a mantissa shifter, the value obtained by multiplying the first mantissa and the second mantissa or a mantissa value of the floating-point value to be added by the difference; adding, by a mantissa adder, the shifted first mantissa value and the shifted second mantissa value to each other; accumulating, by an accumulation register, values within a preset bit value of a mantissa bit width in a result of an addition operation of the shifted first mantissa value and the shifted second mantissa value, determining, by an overflow counter, an overflow count based on an overflow value by which the result of the addition operation of the shifted first mantissa value and the shifted second mantissa value exceeds the preset bit value of the mantissa bit width; performing normalization and rounding based on the value accumulated in the accumulation register and the overflow count; and updating, by an exponent updater, the exponent using the normalized and rounded value.
[0008] The multiplication-accumulation operation device may include a magnetoresistive random access memory-compute in memory (MRAM-CIM) core and a high-precision neural core.
[0009] The operations performed by the exponent adder, the mantissa multiplier, the exponent subtractor, the mantissa shifter, the mantissa adder, and the overflow counter may be performed in the MRAM-CIM core.
[0010] The operation of the exponent adder may be performed in Cell_0 of the MRAM-CIM core.
[0011] The operation of the mantissa multiplier may be performed in Cell_1 of the MRAM-CIM core.
[0012] The operations performed by the exponent subtractor, the mantissa shifter, the mantissa adder, and the overflow counter may be performed in the non-linear functional unit (NFU) and the special functional unit (SFU) of the MRAM-CIM core.
[0013] The normalization and rounding operations may be performed in the high-precision neural core.
[0014] Here, the preset bit value of the mantissa bit width may be preset to any bit value for floating-point operations.
[0015] Here, the accumulating step may include: accumulating the values of the results of the addition operation that fall within the preset bit value of the mantissa bit width.
[0016] Here, the determining step may include: storing the overflow value of the result of the addition operation that exceeds the preset bit value of the mantissa bit width, and increasing the overflow count by the overflow value.
[0017] In addition, according to an embodiment for achieving the above object, a multiply-accumulate operation device is provided, including: a memory configured to store a control program for multiply-accumulate operations; and a processor configured to execute the control program stored in the memory, wherein the processor is configured to: execute control to calculate, by an exponent subtractor, a difference between a value obtained by adding a first exponent and a second exponent using an exponent adder and an exponent of a floating-point value to be added, execute control to calculate, by a mantissa multiplier, a value obtained by multiplying a first mantissa by a second mantissa, execute control to shift, by a mantissa shifter, the value obtained by multiplying the first mantissa by the second mantissa or a mantissa value of the floating-point value to be added by the difference, execute control to add, by a mantissa adder, the shifted first mantissa value and the shifted second mantissa value to each other, execute control to accumulate, by an accumulation register, values within a preset bit value of a mantissa bit width in a result of an addition operation of the shifted first mantissa value and the shifted second mantissa value, execute control to determine, by an overflow counter, an overflow count based on an overflow value that the result of the addition operation of the shifted first mantissa value and the shifted second mantissa value exceeds the preset bit value of the mantissa bit width, execute control to perform normalization and rounding based on the value accumulated in the accumulation register and the overflow count, and execute control to update, by an exponent updater, the exponent using the normalized and rounded value.
[0018] The processor may be configured to execute control such that operations performed by the exponent adder, the mantissa multiplier, the exponent subtractor, the mantissa shifter, the mantissa adder, and the overflow counter are executed in a magnetoresistive random access memory - in-memory computing (MRAM-CIM) core.
[0019] The processor may be configured to execute control such that the operation of the exponent adder is executed in Cell_0 of the MRAM-CIM core.
[0020] The processor may be configured to execute control such that the operation of the mantissa multiplier is executed in Cell_1 of the MRAM-CIM core.
[0021] The processor may be configured to execute control such that operations performed by the exponent subtractor, the mantissa shifter, the mantissa adder, and the overflow counter are executed in a non-linear functional unit (NFU) and a special functional unit (SFU) of the MRAM-CIM core.
[0022] The processor may be configured to execute control such that the normalization and rounding operations are executed in a high-precision neural core.
[0023] Here, the preset bit value of the mantissa bit width may be preset to any bit value for floating-point operations.
[0024] Here, the processor may be configured to accumulate values for which the result of the addition operation falls within the preset bit value of the mantissa bit width.
[0025] Here, the processor may be configured to store the overflow value for which the result of the addition operation exceeds the preset bit value of the mantissa bit width, and increase the overflow count by the overflow value.
[0026] Advantageous Effects The present disclosure can provide a floating-point multiply-accumulate operation with high power efficiency at very low power.
[0027] In addition, the present disclosure can provide high computational efficiency to an artificial intelligence processor through the floating-point multiply-accumulate operation. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 is a block diagram showing a multiply-accumulate operation device according to an embodiment of the present disclosure; Figure 2 is a block diagram showing a detailed configuration of a multiply-accumulate operation device according to an embodiment of the present disclosure; Figure 3 is a block diagram showing an operation of a multiply-accumulate operation device according to an embodiment of the present disclosure; Figure 4 is a block diagram showing a multiply-accumulate operation device according to an embodiment of the present disclosure; Figure 5 is a flowchart showing an operation of a multiply-accumulate operation method according to an embodiment of the present disclosure; and Figure 6 is a block diagram showing a configuration of a computer system according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0029] The advantages and features of the present disclosure and the method for realizing the advantages and features of the present disclosure will be clarified with reference to the embodiments described in detail later together with the accompanying Figure 1 drawings. However, the present disclosure can be implemented in various forms and is not limited to the embodiments described later, and providing these embodiments makes the present disclosure thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. The present disclosure should be defined by the scope of the appended claims. Throughout the specification, the same reference numerals are used to denote the same components.
[0030] It should be understood that although the terms "first" and "second" may be used herein to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Thus, it is obvious that, without departing from the technical spirit of the present disclosure, the first component described below may optionally be the second component.
[0031] The terms used in this specification are only for describing embodiments and are not intended to limit the present disclosure. In this specification, unless specifically stated to the contrary in the context, singular expressions include plural meanings. It should be understood that the terms "including" or "comprising" used in the specification indicate that the described components or steps are not intended to exclude the possibility of the presence or addition of one or more other components or steps.
[0032] Unless otherwise defined, all terms used in this specification can be interpreted to have the same meaning as the terms commonly understood by those skilled in the art to which the present disclosure pertains. In addition, unless clearly defined in this specification, terms defined in commonly used dictionaries should not be interpreted to have an ideal or overly formal meaning.
[0033] In this specification, each of the phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C", and "at least one of A, B or C" may include any one of the items listed together in the corresponding phrase, any one of the phrases, or all possible combinations thereof.
[0034] Hereinafter, embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, the same reference numerals are assigned to indicate the same or corresponding elements, and repeated descriptions will be omitted.
[0035] Figure 1 is a block diagram showing a multiply-accumulate operation device according to an embodiment of the present disclosure, Figure 2 is a block diagram showing a detailed configuration of a multiply-accumulate operation device according to an embodiment of the present disclosure, and Figure 3 is a block diagram showing the operation of a multiply-accumulate operation device according to an embodiment of the present disclosure.
[0036] Referring to Figure 1 , the multiply-accumulate operation device according to an embodiment may include a magnetoresistive random access memory-in-memory computing (MRAM-CIM) core 110, a high-precision neural core 130, a bus 150, a dynamic RAM (DRAM) controller 170, and a static RAM (SRAM) 190.
[0037] As Figure 2As shown, the MRAM-CIM core 110 may include MRAM cells Cell_0 111 and Cell_1 113, a neural function unit (NFC) 115 / a special function unit (SFU) 117.
[0038] Return reference Figure 1 , and the high-precision arithmetic core 130 may support high-precision arithmetic.
[0039] The bus 150 may provide a path for the MRAM-CIM core 110 and the high-precision neural core 130 to communicate with the DRAM controller 170 and the SRAM 190. Here, the SRAM 190 may have an on-chip memory structure.
[0040] The multiply-accumulate operation device may be connected to an external memory through the DRAM controller 170 and the SRAM 190.
[0041] As Figure 3 shown, Cell_0 111 and Cell_1 113 may receive signals through the bus 150 and then provide the signals to the NFU 115 / SFU 117.
[0042] Hereinafter, the process of performing an operation using the multiply-accumulate operation device will be described.
[0043] Figure 4 is a block diagram showing a multiply-accumulate operation device according to an embodiment of the present disclosure.
[0044] Refer to Figure 4 , the multiply-accumulate operation device according to an embodiment of the present disclosure includes an exponent adder 110, a first register 111, an exponent subtractor 112, a second register 113, a mantissa multiplier 120, a first mantissa register 121, a mantissa shifter 122, a mantissa adder 123, an accumulation register 124, an overflow counter 125, and a normalizer 126.
[0045] The first exponent register 111 may store the result of performing an addition operation on the first exponent Exp.A and the second exponent Exp.B.
[0046] The exponent subtractor 112 may perform a subtraction operation to calculate the difference between the result of the addition operation and the exponent of the floating-point value to be added.
[0047] The second exponent register 113 may store the result of the subtraction operation.
[0048] The mantissa multiplier 120 may perform a multiplication operation on the first mantissa Man.A and the second mantissa Man.B.
[0049] The first mantissa register 121 may store the result of the multiplication operation of the first mantissa and the second mantissa.
[0050] The mantissa shifter 122 can shift the value obtained by multiplying the first mantissa by the second mantissa or the mantissa value of the floating-point value to be added by the difference depending on the subtraction operation received from the exponent subtractor.
[0051] The mantissa adder 123 can perform an addition operation on the shifted first mantissa value and the shifted second mantissa value.
[0052] The Accumulation Register (Accum Reg) 124 can accumulate the values within a preset mantissa bit width in the result of the addition operation of the shifted first mantissa value and the shifted second mantissa value.
[0053] Here, the accumulation register 124 can accumulate the values where the result of the addition operation falls within 2 bits of the mantissa bit width.
[0054] The bit value of the mantissa bit width can be preset to any bit value for performing floating-point operations.
[0055] Here, the arbitrary bit value can support up to 8 bits, and in the embodiments of the present disclosure, it will be described based on 2 bits.
[0056] In this case, the accumulation register 124 can accumulate the values where the result of the addition operation falls within 2 bits of the mantissa bit width.
[0057] The Overflow Counter (Ovf counter) 125 can determine the number of overflows (overflow count) that occur based on the operation value obtained by performing an addition operation by the mantissa adder.
[0058] Here, the overflow counter 125 can store the overflow value where the result of the addition operation exceeds 2 bits, which is an example of the preset value of the mantissa bit width, and can increase the overflow count by the overflow value.
[0059] The Normalizer (Normalization and Rounding) 126 can perform normalization and rounding based on the value accumulated in the accumulation register and the overflow count determined by the overflow counter.
[0060] Here, the normalizer 126 can transfer the normalized and rounded value to the exponent updater 114.
[0061] Finally, the exponent updater 114 can change the exponent using the subtraction operation result stored in the second exponent register and the normalized and rounded value.
[0062] For example, the exponent updater 114 can reduce the error in the result value by performing exponent updates only on a part of the MAC results during 1000 floating-point multiply-accumulate (MAC) operations, where the part of the MAC results is multiplied and accumulated for the values within 2 bits of the mantissa bit width through normalization and rounding.
[0063] For example, assume that 256 MAC operations are partial MAC operations and a total of 1000 MAC operations are performed. Then, the exponential update occurs only four times instead of 1000 times.
[0064] Here, more specifically, the multiply-accumulate operation device can perform multiply-accumulate operations in the MRAM-CIM core 110 and the high-precision neural core 130, which are MRAM-CIM-based artificial intelligence processors.
[0065] The operations performed by the exponent adder 110, mantissa multiplier 120, exponent subtractor 112, mantissa shifter 122, mantissa adder 123, and overflow counter 125 can be executed in the MRAM-CIM core 110.
[0066] The operation of the exponent adder 110 can be executed in Cell_0 111 of the MRAM-CIM core 110. The operation of the mantissa multiplier 120 can be executed in Cell_1 113 of the MRAM-CIM core 110. The operations performed by the exponent subtractor 112, mantissa shifter 122, mantissa adder 123, and overflow counter 125 can be executed in the non-linear functional unit (NFU) 115 and the special functional unit (SFU) 117 of the MRAM-CIM core 110.
[0067] Meanwhile, the normalization and rounding operations of the normalizer 126 can be executed in the high-precision neural core 130.
[0068] The high-precision neural core 130 can support a floating-point 16-bit data type or higher to process normalization and rounding operations without loss of accuracy.
[0069] In this case, the high-precision neural core 130 can correspond to a processor core including a normalization and rounding operation unit.
[0070] Here, the high-precision neural core 130 can use the results of the exponent adder 110, mantissa multiplier 120, exponent subtractor 112, mantissa shifter 122, mantissa adder 123, and overflow counter 125 calculated in the MRAM-CIM core to process normalization and rounding operations.
[0071] Figure 5 It is an operation flowchart showing a multiply-accumulate operation method according to an embodiment of the present disclosure.
[0072] Refer to Figure 5 , in step S210, the exponent adder can perform an addition operation on the first exponent and the second exponent.
[0073] Here, in step S210, the first exponent register 111 may store the result of performing an addition operation on the first exponent Exp.A and the second exponent Exp.B.
[0074] In step S220, the exponent subtractor 112 may perform a subtraction operation to calculate the difference between the result of the addition operation and the exponent of the floating-point value to be added.
[0075] Here, in step S220, the second exponent register 113 may store the result of the subtraction operation.
[0076] In step S230, the mantissa multiplier 120 may perform a multiplication operation on the first mantissa Man.A and the second mantissa Man.B.
[0077] Here, in step S230, the first mantissa register 121 may store the result of the multiplication operation of the first mantissa and the second mantissa.
[0078] In step S240, the mantissa shifter 122 may shift the value obtained by multiplying the first mantissa by the second mantissa or the mantissa value of the floating-point value to be added by the difference depending on the subtraction operation received from the exponent subtractor.
[0079] In step S250, the mantissa adder 123 may perform an addition operation on the shifted first mantissa value and the shifted second mantissa value.
[0080] In step S260, the accumulator register (Accum Reg) 124 may accumulate the value within the preset mantissa bit width in the result of the addition operation of the shifted first mantissa value and the shifted second mantissa value.
[0081] Here, in step S260, the accumulator register 124 may accumulate the value within 2 bits of the mantissa bit width in the result of the addition operation.
[0082] The bit value of the mantissa bit width may be preset to any bit value for performing floating-point operations.
[0083] Here, the arbitrary bit value may support up to 8 bits, and in the embodiments of the present disclosure, it will be described based on 2 bits.
[0084] In this case, in step S260, the accumulator register 124 may accumulate the value within 2 bits of the mantissa bit width in the result of the addition operation.
[0085] In step S270, the overflow counter (Ovf counter) 125 may determine the number of times of overflow occurrence (overflow count) based on the operation value obtained by performing the addition operation by the mantissa adder.
[0086] Here, in step S270, the overflow counter 125 can store an overflow value when the result of the addition operation exceeds 2 bits, which is an example of a preset value of the mantissa bit width, and can increment the overflow count by the overflow value.
[0087] In step S280, the normalizer (normalize and round) 126 can perform normalization and rounding based on the value accumulated in the accumulation register and the overflow count determined by the overflow counter.
[0088] Here, in step S280, the normalizer 126 can transfer the normalized and rounded value to the exponent updater 114.
[0089] Finally, in step S290, the exponent updater 114 can change the exponent using the result of the subtraction operation stored in the second exponent register and the normalized and rounded value.
[0090] For example, in step S290, the exponent updater 114 can reduce the error in the result value by performing exponent updates only on a part of the MAC results during 1000 floating-point multiply-accumulate operations (MAC), where the part of the MAC results are multiplied and accumulated for values within 2 bits of the mantissa bit width through normalization and rounding.
[0091] For example, assuming that 256 MAC operations are part of the MAC operations and a total of 1000 MAC operations are performed, the exponent update occurs only four times instead of 1000 times.
[0092] The multiply-accumulate operation device and method according to an embodiment of the present disclosure can perform floating-point multiply-accumulate operations with high power efficiency at very low power.
[0093] The multiply-accumulate operation device and method according to an embodiment of the present disclosure can be implemented in a computer system such as a computer-readable storage medium.
[0094] Figure 6 is a block diagram showing the configuration of a computer system according to an embodiment of the present disclosure.
[0095] Referring to Figure 6 , the computer system 1000 according to an embodiment can include one or more processors 1010, a memory 1030, a user interface input device 1040, a user interface output device 1050, and a storage 1060, which communicate with each other through a bus 1020. The computer system 1000 can also include a network interface 1070 connected to a network.
[0096] Each processor 1010 may be a central processing unit (CPU) or a semiconductor device for executing programs or processing instructions stored in the memory 1030 or the storage 1060. The processor 1010 may be a type of CPU and may control all operations of the multiply-accumulate operation device.
[0097] The processor 1010 may include all types of devices capable of processing data. The term "processor" as used herein may refer to a data processing device embedded in hardware that has circuitry physically configured to execute functions represented in, for example, code or instructions included in a program. A data processing device embedded in hardware may include, for example, a microprocessor, a CPU, a processor core, a multiprocessor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc., but is not limited thereto.
[0098] The memory 1030 may store various types of data for all operations, such as a control program for executing the multiply-accumulate operation method according to an embodiment. Specifically, the memory 1030 may store a plurality of applications executed by the multiply-accumulate operation device, as well as data and instructions for the operations of the multiply-accumulate operation device.
[0099] Each of the memory 1030 and the storage 1060 may be a storage medium including at least one of a volatile medium, a non-volatile medium, a removable medium, a non-removable medium, a communication medium, an information transfer medium, or a combination thereof. For example, the memory 1030 may include a read only memory (ROM) 1031 or a random access memory (RAM) 1032.
[0100] According to an embodiment, a computer-readable storage medium for storing a computer program may be provided. The computer-readable storage medium may include instructions that enable a processor to execute a method, the method including: an operation of calculating, by an exponent subtractor, a difference between a value obtained by adding a first exponent and a second exponent using an exponent adder and an exponent of a floating-point value to be added; an operation of calculating, by a mantissa multiplier, a value obtained by multiplying a first mantissa by a second mantissa; an operation of shifting, by a mantissa shifter, a value obtained by multiplying the first mantissa by the second mantissa or a mantissa value of the floating-point value to be added by the difference; an operation of adding, by a mantissa adder, a shifted first mantissa value and a shifted second mantissa value to each other; an operation of accumulating, by an accumulation register, values within a preset bit value of a mantissa bit width in a result of the addition operation of the shifted first mantissa value and the shifted second mantissa value; an operation of determining, by an overflow counter, an overflow count based on an overflow value that the result of the addition operation of the shifted first mantissa value and the shifted second mantissa value exceeds the preset bit value of the mantissa bit width; an operation of performing normalization and rounding based on the value accumulated in the accumulation register and the overflow count; and an operation of updating, by an exponent updater, an exponent using the normalized and rounded value.
[0101] According to an embodiment, a computer program stored in a computer-readable storage medium may be provided. The computer program may include instructions that enable a processor to execute a method, the method including: an operation of calculating, by an exponent subtractor, a difference between a value obtained by adding a first exponent and a second exponent using an exponent adder and an exponent of a floating-point value to be added; an operation of calculating, by a mantissa multiplier, a value obtained by multiplying a first mantissa by a second mantissa; an operation of shifting, by a mantissa shifter, a value obtained by multiplying the first mantissa by the second mantissa or a mantissa value of the floating-point value to be added by the difference; an operation of adding, by a mantissa adder, a shifted first mantissa value and a shifted second mantissa value to each other; an operation of accumulating, by an accumulation register, values within a preset bit value of a mantissa bit width in a result of the addition operation of the shifted first mantissa value and the shifted second mantissa value; an operation of determining, by an overflow counter, an overflow count based on an overflow value that the result of the addition operation of the shifted first mantissa value and the shifted second mantissa value exceeds the preset bit value of the mantissa bit width; an operation of performing normalization and rounding based on the value accumulated in the accumulation register and the overflow count; and an operation of updating, by an exponent updater, the exponent using the normalized and rounded value.
[0102] The specific embodiments shown and described herein are illustrative examples of the present disclosure and are not intended to limit the scope of the present disclosure in any way. For the sake of brevity, conventional electronic devices, control systems, software development, and other functional aspects of the system may not be described in detail. In addition, the connecting lines or connectors shown in the various presented figures are intended to represent exemplary functional relationships and / or physical or logical couplings between the various elements. It should be noted that there may be many alternative or additional functional relationships, physical connections, or logical connections in the actual device. Furthermore, no item or component may be necessary for the practice of the present disclosure unless an element is specifically described as "necessary" or "critical".
[0103] Therefore, the spirit of the present disclosure should not be limited by the above embodiments in a restrictive manner, and it should be understood that the scope of all the appended claims and their equivalents belongs to the scope of the spirit of the present disclosure.
Claims
1. A multiply-accumulate operation method performed by a multiply-accumulate operation device, the multiply-accumulate operation method comprising: Calculating, by an exponent subtractor, a difference between a value obtained by adding a first exponent and a second exponent using an exponent adder and an exponent of a floating-point value to be added; Calculating, by a mantissa multiplier, a value obtained by multiplying a first mantissa by a second mantissa; Shifting, by a mantissa shifter, the value obtained by multiplying the first mantissa by the second mantissa or a mantissa value of the floating-point value to be added by the difference; Adding, by a mantissa adder, the shifted first mantissa value and the shifted second mantissa value to each other; Accumulating, by an accumulation register, values within a preset bit value of a mantissa bit width in a result of an addition operation of the shifted first mantissa value and the shifted second mantissa value; Determining, by an overflow counter, an overflow count based on an overflow value that the result of the addition operation of the shifted first mantissa value and the shifted second mantissa value exceeds the preset bit value of the mantissa bit width; Performing normalization and rounding based on the value accumulated in the accumulation register and the overflow count; And Updating, by an exponent updater, the exponent using the normalized and rounded value.
2. The multiply-accumulate operation method according to claim 1, wherein, The multiply-accumulate operation device includes a magnetoresistive random access memory-in-memory computing (MRAM-CIM) core and a high-precision neural core.
3. The multiply-accumulate operation method according to claim 2, wherein, Operations performed by the exponent adder, the mantissa multiplier, the exponent subtractor, the mantissa shifter, the mantissa adder, and the overflow counter are performed in the MRAM-CIM core.
4. The multiplication and accumulation operation method according to claim 3, wherein, The operation of the exponent adder is performed in Cell_0 of the MRAM-CIM core.
5. The multiplication and accumulation operation method according to claim 3, wherein, The operation of the mantissa multiplier is performed in Cell_1 of the MRAM-CIM core.
6. The multiply-accumulate operation method according to claim 3, wherein, Operations performed by the exponent subtractor, the mantissa shifter, the mantissa adder, and the overflow counter are performed in a non-linear functional unit (NFU) and a special functional unit (SFU) of the MRAM-CIM core.
7. The multiply-accumulate operation method according to claim 2, wherein, The normalization and rounding operations are performed in the high-precision neural core.
8. The multiply-accumulate operation method according to claim 7, wherein, The preset bit value of the mantissa bit width is preset to any bit value for floating-point operations.
9. The multiplication and accumulation operation method according to claim 8, wherein, The accumulating step includes: Accumulating values within the preset bit value of the mantissa bit width in the result of the addition operation.
10. The multiplication and accumulation operation method according to claim 9, wherein, The determining step includes: Storing the overflow value that the result of the addition operation exceeds the preset bit value of the mantissa bit width, and increasing the overflow count by the overflow value.
11. A multiply-accumulate operation device, comprising: A memory configured to store a control program for multiply-accumulate operations; And A processor configured to execute the control program stored in the memory Among them, the processor is configured to: execute control to calculate, by an exponent subtractor, the difference between the value obtained by adding a first exponent and a second exponent using an exponent adder and the exponent of the floating-point value to be added; execute control to calculate, by a mantissa multiplier, the value obtained by multiplying a first mantissa by a second mantissa; execute control to shift, by a mantissa shifter, the value obtained by multiplying the first mantissa by the second mantissa or the mantissa value of the floating-point value to be added by the difference; execute control to add, by a mantissa adder, the shifted first mantissa value and the shifted second mantissa value to each other; execute control to accumulate, by an accumulation register, the value within a preset bit value of the mantissa bit width in the result of the addition operation of the shifted first mantissa value and the shifted second mantissa value; execute control to determine, by an overflow counter, an overflow count based on the overflow value that the result of the addition operation of the shifted first mantissa value and the shifted second mantissa value exceeds the preset bit value of the mantissa bit width; execute control to perform normalization and rounding based on the value accumulated in the accumulation register and the overflow count; and execute control to update, by an exponent updater, the exponent using the normalized and rounded value.
12. The multiply-accumulate operation device according to claim 11, wherein, The processor is configured to execute control such that the operations performed by the exponent adder, the mantissa multiplier, the exponent subtractor, the mantissa shifter, the mantissa adder, and the overflow counter are performed in a magnetoresistive random access memory - in-memory computing (MRAM-CIM) core.
13. The multiply-accumulate operation device according to claim 12, wherein, The processor is configured to execute control such that the operation of the exponent adder is performed in Cell_0 of the MRAM-CIM core.
14. The multiply-accumulate operation device according to claim 12, wherein, The processor is configured to execute control such that the operation of the mantissa multiplier is performed in Cell_1 of the MRAM-CIM core.
15. The multiply-accumulate operation device according to claim 12, wherein, The processor is configured to execute control such that the operations performed by the exponent subtractor, the mantissa shifter, the mantissa adder, and the overflow counter are performed in a non-linear functional unit (NFU) and a special functional unit (SFU) of the MRAM-CIM core.
16. The multiply-accumulate operation device according to claim 11, wherein, The processor is configured to execute control such that the normalization and rounding operations are performed in a high-precision neural core.
17. The multiply-accumulate operation device according to claim 11, wherein The preset bit value of the mantissa bit width is preset to any bit value for floating-point operations.
18. The multiply-accumulate operation device according to claim 17, wherein, The processor is configured to accumulate the value in the result of the addition operation that falls within the preset bit value of the mantissa bit width.
19. The multiply-accumulate operation device according to claim 18, wherein, The processor is configured to store the overflow value that the result of the addition operation exceeds the preset bit value of the mantissa bit width, and increase the overflow count by the overflow value.