Low resistivity gap fill

Abstract

Embodiments of the present disclosure relate to methods for metal gap fill with lower resistivity. Particular embodiments provide methods of forming tungsten gap fill without a high resistance nucleating layer. Some embodiments of the present disclosure utilize a nucleation underlayer to facilitate growth of metal gap fill.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to methods for depositing metal gap fills within substrate features. More specifically, embodiments of the present disclosure are directed to methods for providing gap fills with improved resistivity. Background Art

[0002] Gap fill processes are a component of some semiconductor manufacturing processes. Gap fill processes can be used to fill gaps (or features) with insulating or conductive materials. For example, shallow trench isolation, intermetal dielectric layers, passivation layers, dummy gates are typically achieved through gap fill processes.

[0003] As device geometries continue to shrink (e.g., critical dimensions <20 nm, <10 nm, and smaller), the reduction in metal volume creates higher resistivity for metal interconnects.

[0004] Typically, for tungsten gap fills, a nucleation layer including silicon or boron is deposited on top of a PVD tungsten liner prior to forming the tungsten bulk fill to facilitate the formation / growth of the bulk fill on the PVD liner. However, due to the presence of BW and / or WSi, these nucleation layers result in the formation of a relatively high-resistance stack.

[0005] Accordingly, there is a need to provide gap fill methods with lower resistivity. Specifically, there is a need for gap fill methods that do not use a nucleation layer between the PVD liner and the bulk fill material. Summary of the Invention

[0006] One or more embodiments of the present disclosure are directed to methods for metal gap fills. The method includes exposing a surface of a substrate having at least one feature therein to a nucleation pre-soak to form a nucleation bottom layer. The feature extends a certain depth from the surface of the substrate to the bottom and has two sidewalls. A metal liner is deposited on the nucleation bottom layer by physical vapor deposition (PVD). A metal gap fill is deposited on the metal liner and the nucleation bottom layer.

[0007] Additional embodiments of the present disclosure are directed to methods for metal gap fills. The method includes exposing a surface of a substrate having at least one feature therein to a nucleation pre-soak including silane to form a silicon nucleation bottom layer. The feature extends a certain depth from the surface of the substrate to the bottom and has two sidewalls. A tungsten-containing metal liner is deposited on the silicon nucleation bottom layer by physical vapor deposition (PVD). A tungsten-containing metal gap fill is deposited on the metal liner and the silicon nucleation bottom layer.

[0008] Further embodiments of the present disclosure are directed to a method of metal gap filling. The method includes exposing a substrate surface having at least one feature therein to a nucleation pre-soak comprising diborane to form a boron nucleation bottom layer. The feature extends a certain depth from the substrate surface to the bottom and has two sidewalls. A metal liner comprising tungsten is deposited on the boron nucleation bottom layer by physical vapor deposition (PVD). A metal gap fill comprising tungsten is deposited on the metal liner and the boron nucleation bottom layer. Brief Description of the Drawings

[0010] To enable a detailed understanding of the above-described features of the present disclosure, a more specific description of the present disclosure as briefly outlined above may be had by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments. The embodiments described herein are shown by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals represent like elements.

[0011] Figure 1 A process flow diagram of a deposition method according to one or more embodiments is shown;

[0012] Figures 2A to 2D A cross-sectional view of a substrate during processing according to one or more embodiments is shown; and

[0013] Figure 3 A schematic top view of a multi-chamber processing system according to one or more embodiments is shown. Detailed Description

[0014] Before describing some exemplary embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0015] As used herein, the term "about" means approximate or close and means a variation of ±15% or less of the numerical value in the context of the numerical value or range set forth. For example, values that differ by ±14%, ±10%, ±5%, ±2%, ±1%, ±0.5% or ±0.1% will satisfy the definition of "about".

[0016] As used in this specification and the appended claims, the term "substrate" or "wafer" refers to a surface or a portion of a surface on which a process acts. Those skilled in the art will also understand that a reference to a substrate may refer only to a portion of the substrate, unless the context clearly indicates otherwise. Additionally, a reference to depositing on a substrate may mean a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0017] As used herein, the "substrate surface" refers to any substrate on which film processing is performed during a manufacturing process or the surface of a material formed on a substrate. For example, depending on the application, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any film processing step disclosed can also be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as indicated by the context. Thus, for example, when a film / layer or a portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0018] The substrate surface can have one or more features formed therein, one or more layers formed thereon, and combinations of the above. The shape of the feature can be any suitable shape, including but not limited to trenches, holes, and vias (circular or polygonal). As used in this context, the term "feature" refers to any intentional surface irregularity. Suitable examples of features include but are not limited to trenches having a top, two sidewalls, and a bottom extending into the substrate, and vias having one or more sidewalls extending into the substrate to the bottom.

[0019] The term "on" indicates direct contact between elements. The term "directly on" indicates direct contact between elements with no intervening elements.

[0020] As used in this specification and the appended claims, the terms "precursor", "reactant", "reaction gas", etc. are used interchangeably to refer to any gaseous species capable of reacting with the substrate surface.

[0021] Embodiments of the present disclosure advantageously provide methods for depositing metal gap fills having a low resistivity. Relative to methods using a nucleation layer on a metal liner, specific embodiments advantageously provide methods for depositing metal gap fills with reduced resistivity. In some embodiments, the metal liner and / or the metal of the metal gap fill disclosed includes tungsten.

[0022] Embodiments of the present disclosure are described by the figures, which show processes, substrates, and apparatuses in accordance with one or more embodiments of the present disclosure. The processes, schemes, and resulting substrates shown are merely illustrative of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0023] Referring Figures 1 to 2D , the present disclosure relates to a method 100 for depositing metal gap fills. Figure 1 A process flow diagram of a deposition method 100 in accordance with one or more embodiments of the present disclosure is depicted. Figures 2A to 2D A substrate 200 during processing in accordance with one or more embodiments of the present disclosure is depicted.

[0024] Figure 2A A substrate 200 having a substrate surface 205 is shown. As described above, the substrate surface refers to the exposed surface of the substrate on which a layer can be formed. The substrate surface 205 has at least one feature 210 formed therein. Although only a single feature is shown in the figures, those skilled in the art will recognize that multiple features will be affected by the disclosed method, and each feature will be affected in a similar manner.

[0025] The at least one feature 210 has an opening 212 with a width of W. The opening 212 is formed in the top surface 215 of the substrate 200. The feature 210 also has one or more sidewalls 214 and extends a depth D from the top surface 215 to the bottom 216. Although straight, vertical sidewalls are shown in the figures, the disclosed method can also be performed on inclined, irregular, or concave sidewalls.

[0026] In some embodiments, the width W of the opening 212 is greater than or equal to about 10 nm, greater than or equal to about 15 nm, greater than or equal to about 20 nm, greater than or equal to about 25 nm, greater than or equal to about 30 nm, or greater than or equal to about 35 nm. In some embodiments, the width W is in the range of about 5 nm to about 15 nm, or in the range of about 10 nm to about 35 nm.

[0027] In some embodiments, the depth D of the feature 210 is greater than or equal to about 50 nm, greater than or equal to about 75 nm, greater than or equal to about 100 nm, greater than or equal to about 150 nm, greater than or equal to about 200 nm, or greater than or equal to about 250 nm. In some embodiments, the depth D is in the range of about 50 nm to about 250 nm, or in the range of about 200 nm to about 250 nm.

[0028] Those skilled in the art will recognize the increasing challenges in depositing metal gap fills in features with a narrowing width (also known as critical dimension (CD)) and / or an increasing depth. The aspect ratio of at least one feature 210 is defined as the depth D of the feature 210 divided by the width W. In some embodiments, at least one feature has an aspect ratio (D:W) greater than or equal to about 2:1, greater than or equal to about 5:1, greater than or equal to about 10:1, or greater than or equal to about 20:1.

[0029] Reference Figure 1 and Figure 2B , method 100 begins at operation 110. At 110, a nucleation underlayer 220 is formed on the substrate surface 205 and within at least one feature 210. In some embodiments, as Figure 2B shown, the nucleation underlayer 220 is continuous and deposited on the top surface 215, sidewalls 214, and bottom 216.

[0030] At operation 110, the nucleation underlayer 220 is formed by exposing the substrate surface to a nucleation pre-soak. In some embodiments, the nucleation pre-soak comprises a silicon compound. In some embodiments, the nucleation pre-soak comprises a boron compound. As used herein, a "silicon compound" or "boron compound" is any material capable of forming a silicon or boron layer, respectively, on the substrate surface.

[0031] In some embodiments, the silicon compound comprises or consists essentially of silane (SiH4), disilane, trisilane, tetrasilane, cyclopentasilane, or cyclohexasilane. In some embodiments, the boron compound comprises or consists essentially of borane, diborane (B2H6), triborane, tetraborane, or cycloborane. As used in this context, a process gas that "consists essentially of a specified material" contains, in moles, greater than about 95%, greater than about 98%, greater than about 99%, or greater than about 99.5% of the specified material, excluding any inert diluent or carrier gas.

[0032] In some embodiments, the nucleation underlayer is substantially conformal. As used in this context, a "substantially conformal" layer has an average thickness that varies by less than 10%, 5%, or 2% of the average thickness of the layer. In some embodiments, the nucleation underlayer has a thickness less than or less than . In some embodiments, the nucleation underlayer comprises 1 to 2 monolayers of silicon and / or boron.

[0033] In some embodiments, operation 110 represents a chemical vapor deposition (CVD) process. In some embodiments, the temperature of the CVD process is in the range of about 250°C to about 450°C, in the range of about 250°C to about 350°C, or in the range of about 350°C to about 450°C. In some embodiments, the CVD process is performed without plasma.

[0034] After the nucleation underlayer 220 is formed, method 100 proceeds to operation 120. Referring Figure 2C , method 100 proceeds at operation 120, where the metal liner 230 is deposited on the nucleation underlayer 220. In some embodiments, the metal liner 230 is deposited by a physical vapor deposition process. In some embodiments, the metal liner is not continuous. In some embodiments, the metal liner does not cover the sidewalls 214 of the feature 210. In some embodiments, the average thickness of the metal liner 230 outside of at least one feature 210 is less than or equal to about

[0035] Without being bound by theory, it is believed that the presence of the nucleation underlayer 220 promotes the growth of the metal gap fill 240 (described below) in regions not covered by the metal liner 230. Additionally, the order of formation prevents the nucleation underlayer 220 from forming a high-resistance BW and / or WSi between the metal liner 230 and the metal gap fill 240.

[0036] After the metal liner 230 is formed, method 100 proceeds to operation 130. Referring Figure 2D , method 100 proceeds at operation 130, where the metal gap fill 240 is deposited on the metal liner 230 and the nucleation underlayer 220. In some embodiments, the metal gap fill 240 is deposited by an atomic layer deposition (ALD) process. In some embodiments, the metal gap fill 240 is deposited by a chemical vapor deposition (CVD) process. In some embodiments, the metal gap fill 240 is deposited by an atomic layer deposition (ALD) process followed by a chemical vapor deposition (CVD) process.

[0037] In some embodiments, the metal gap fill 240 is formed directly on the metal liner 230 and the nucleation sublayer 220. In other words, in some embodiments, the metal gap fill 240 is deposited on the metal liner 230 without a typical nucleation layer. As described above, without being bound by theory, it is believed that the disclosed method provides metal gap fill without using or forming a high-resistance nucleation layer. In some embodiments, the metal liner 230 and the metal gap fill 240 are referred to as a metal stack. In some embodiments, the nucleation sublayer does not increase the resistance of the metal stack. Additionally, the inventors have surprisingly found that the presence of the nucleation sublayer 220 does not adversely affect the adhesion of the metal stack to the underlying substrate.

[0038] Figure 3 is a schematic top view of an exemplary multi-chamber processing system 300 in accordance with embodiments of the present disclosure. The processing system 300 generally includes a factory interface 302, load lock chambers 304, 306, transfer chambers 308, 310 having respective transfer robots 312, 314, hold chambers 316, 318, and processing chambers 320, 322, 324, 326, 328, 330. As detailed herein, wafers in the processing system 300 can be processed in various chambers and transferred between various chambers without exposing the wafers to the surrounding environment external to the processing system 300 (e.g., the surrounding atmospheric environment such as may exist in a semiconductor foundry). For example, between the various processes performed on a wafer in the processing system 300, the wafer can be processed in various chambers and transferred between various chambers in a low-pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without breaking the low-pressure or vacuum environment. Thus, the processing system 300 can provide an integrated solution for some processing of wafers.

[0039] Examples of processing systems that can be suitably modified in accordance with the teachings provided herein include or an integrated processing system or other suitable processing systems commercially available from Applied Materials, Inc. of Santa Clara, California. It is contemplated that other processing systems (including processing systems from other manufacturers) can be adapted to benefit from the aspects described herein.

[0040] In Figure 3In the illustrated example, the factory interface 302 includes a docking station 340 and a factory interface robot 342 to facilitate wafer transfer. The docking station 340 is configured to receive one or more front opening unified pods (FOUPs) 344. In some examples, each factory interface robot 342 generally includes a blade 348 disposed at one end of the corresponding factory interface robot 342, and the blade is configured to transfer wafers from the factory interface 302 to the load lock chambers 304, 306.

[0041] The load lock chambers 304, 306 have respective ports 350, 352 coupled to the factory interface 302 and respective ports 354, 356 coupled to the transfer chamber 308. The transfer chamber 308 further has respective ports 358, 360 coupled to the hold chambers 316, 318 and respective ports 362, 364 coupled to the process chambers 320, 322. Similarly, the transfer chamber 310 has respective ports 366, 368 coupled to the hold chambers 316, 318 and respective ports 370, 372, 374, 376 coupled to the process chambers 324, 326, 328, 330. The ports 354, 356, 358, 360, 362, 364, 366, 368, 370, 372, 374, 376 can be, for example, slit valve openings having slit valves for allowing wafers to pass therethrough by the transfer robots 312, 314 and for providing a seal between the respective chambers to prevent gas transfer between the respective chambers. Generally, any port is open for transferring wafers therethrough. Otherwise, the port is closed.

[0042] The load lock chambers 304, 306, the transfer chambers 308, 310, the hold chambers 316, 318, and the process chambers 320, 322, 324, 326, 328, 330 can be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), a gas source, various valves, and ducts fluidly coupled to the various chambers. In operation, the factory interface robot 342 transfers wafers from the FOUP 344 to the load lock chamber 304 or 306 via the port 350 or 352. Then, the gas and pressure control system evacuates the load lock chamber 304 or 306. The gas and pressure control system further maintains the transfer chambers 308, 310 and the hold chambers 316, 318 in an internal low pressure or vacuum environment (which can include an inert gas). Thus, the evacuation of the load lock chamber 304 or 306 facilitates the transfer of wafers between, for example, the atmospheric environment of the factory interface 302 and the low pressure or vacuum environment of the transfer chamber 308.

[0043] When the wafer is in the evacuated load lock chamber 304 or 306, the transfer robot 312 transfers the wafer from the load lock chamber 304 or 306 to the transfer chamber 308 via the port 354 or 356. The transfer robot 312 can then transfer the wafer to any processing chamber 320, 322 and / or transfer the wafer between any processing chambers 320, 322 for processing via the corresponding ports 362, 364, and transfer the wafer to the holding chambers 316, 318 and / or transfer the wafer between the holding chambers 316, 318 via the corresponding ports 358, 360 for holding awaiting further transfer. Similarly, the transfer robot 314 can access the wafer in the holding chamber 316 or 318 via the port 366 or 368, and can transfer the wafer to any processing chamber 324, 326, 328, 330 and / or transfer the wafer between any processing chambers 324, 326, 328, 330 for processing via the corresponding ports 370, 372, 374, 376, and transfer the wafer to the holding chambers 316, 318 and / or transfer the wafer between the holding chambers 316, 318 via the corresponding ports 366, 368 for holding awaiting further transfer. The transfer and holding of the wafer within and among the various chambers can be performed in a low pressure or vacuum environment provided by the gas and pressure control system.

[0044] The processing chambers 320, 322, 324, 326, 328, 330 can be any suitable chambers for processing the wafer. In some embodiments, the processing chamber 320 can perform nucleation pre-soaking, the processing chamber 322 can perform a PVD deposition process, and the processing chamber 324 can perform an ALD and / or CVD deposition process.

[0045] The system controller 390 is coupled to the processing system 300 for controlling the processing system 300 or its components. For example, the system controller 390 can use direct control of the chambers 304, 306, 308, 316, 318, 310, 320, 322, 324, 326, 328, 330 of the processing system 300, or control the operation of the processing system 300 by controlling the controllers associated with the chambers 304, 306, 308, 316, 318, 310, 320, 322, 324, 326, 328, 330. In operation, the system controller 390 enables the collection of data and feedback from the respective chambers to coordinate the execution of the processing system 300.

[0046] The system controller 390 generally includes a central processing unit (CPU) 392, a memory 394, and support circuitry 396. The CPU 392 can be one of any form of general-purpose processor that can be used in an industrial environment. The memory 394 or non-transitory computer-readable medium is accessible by the CPU 392 and can be one or more memories such as random-access memory (RAM), read only memory (ROM), floppy disks, hard disks, or any other form of local or remote digital memory. The support circuitry 396 is coupled to the CPU 392 and can include a cache, clock circuitry, input / output subsystems, power supplies, and the like. The various methods disclosed herein can generally be implemented under the control of the CPU 392 by the CPU 392 executing computer instruction code stored, for example, as software routines in the memory 394 (or the memory of a particular processing chamber). When the computer instruction code is executed by the CPU 392, the CPU 392 controls the chamber to perform the process according to the various methods.

[0047] Other processing systems may employ other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 308, 310 and holding chambers 316, 318. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer device in a processing system.

[0048] The process can generally be stored as software routines in the memory of the system controller 390, and when executed by a processor, the software routines cause the processing chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) that is remote from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be executed in hardware. Thus, the process can be implemented in software and used with a computer system, implemented in hardware as, for example, an application specific integrated circuit or other type of hardware, or implemented as a combination of software and hardware. When executed by a processor, the software routines transform a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chamber such that the process is performed.

[0049] Embodiments of the present disclosure are directed to non-transitory computer-readable media. In one or more embodiments, the non-transitory computer-readable media includes instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the operations of any of the methods described herein (e.g., the gap filling method 100). In one or more embodiments, the controller causes the processing chamber to perform the operations of the deposition method 100. In one or more embodiments, the controller causes the processing chamber to perform the operation of depositing a nucleation bottom layer on a substrate surface having at least one feature (operation 110). The at least one feature includes at least one surface defining a via having a bottom surface and at least one sidewall. In one or more embodiments, the controller causes the processing chamber to deposit a metal liner on the substrate surface (operation 120).

[0050] For ease of description, spatial relative terms, such as "beneath", "below", "lower", "above", "upper", etc., may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. It should be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "below" or "beneath" another element or feature would then be oriented "above" the other element or feature. Thus, the exemplary term "below" can include both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein are to be interpreted accordingly.

[0051] In the context of describing the materials and methods discussed herein (particularly in the context of the following claims), the terms "a", "an", "the", and similar referents shall be construed to cover both the singular and the plural unless otherwise indicated herein or clearly contradicted by context. Unless otherwise indicated herein, the recitation of ranges of values herein is merely intended as a shorthand method of referring individually to each separate value falling within the range, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein is merely intended to better illuminate the materials and methods and does not impose a limitation on the scope unless otherwise stated. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0052] References to "one embodiment", "certain embodiments", "one or more embodiments", or "an embodiment" throughout this specification mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of phrases such as "in one or more embodiments", "in certain embodiments", "in one embodiment", or "in an embodiment" throughout various places in this specification are not necessarily referring to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner.

[0053] Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for metal gap filling, the method comprising: Exposing a substrate surface having at least one feature to a nucleation pre-soak to form a nucleation bottom layer, the feature extending a certain depth from the substrate surface to the bottom and having two sidewalls; Depositing a metal liner on the nucleation bottom layer by physical vapor deposition (PVD); And Depositing a metal gap fill on the metal liner and the nucleation bottom layer.

2. The method according to claim 1, wherein the aspect ratio of the at least one feature is at least 5:

1.

3. The method according to claim 1, wherein the metal liner and the metal gap fill comprise tungsten.

4. The method according to claim 1, wherein the nucleation pre-soak comprises a silicon compound.

5. The method according to claim 4, wherein the nucleation pre-soak consists essentially of silane (SiH4).

6. The method according to claim 1, wherein the nucleation pre-soak comprises a boron compound.

7. The method according to claim 6, wherein the nucleation pre-soak consists essentially of diborane (B2H6).

8. The method according to claim 1, wherein the nucleation bottom layer comprises 1 to 2 silicon and / or boron monolayers.

9. The method according to claim 1, wherein an average thickness of the metal gasket on the substrate surface outside the at least one feature is about 10. The method according to claim 1, wherein the metal gap fill is deposited by atomic layer deposition (ALD).

11. The method according to claim 1, wherein the metal gap fill is deposited by chemical vapor deposition (CVD).

12. The method according to claim 1, wherein the metal gap fill is directly formed on the metal liner and the nucleation bottom layer.

13. The method according to claim 1, wherein the nucleation bottom layer does not increase the resistance of the stack of the metal liner and the metal gap fill.

14. The method according to claim 1, wherein the nucleation bottom layer does not adversely affect the adhesion of the stack of the metal liner and the metal gap fill.

15. A method for metal gap filling, the method comprising: Exposing a substrate surface having at least one feature to a nucleation pre-soak containing silane to form a silicon nucleation bottom layer, the feature extending a certain depth from the substrate surface to the bottom and having two sidewalls; Depositing a tungsten-containing metal liner on the silicon nucleation bottom layer by physical vapor deposition (PVD); And Depositing a tungsten-containing metal gap fill on the metal liner and the silicon nucleation bottom layer.

16. The method according to claim 15, wherein the silicon nucleation bottom layer on average comprises 1 to 2 silicon monolayers.

17. The method according to claim 15, wherein the metal gap fill is directly formed on the metal liner and the nucleation bottom layer.

18. A method for metal gap filling, the method comprising: Exposing a substrate surface having at least one feature to a nucleation pre-soak containing diborane to form a boron nucleation bottom layer, the feature extending a certain depth from the substrate surface to the bottom and having two sidewalls; Depositing a tungsten-containing metal liner on the boron nucleation bottom layer by physical vapor deposition (PVD); And Depositing a tungsten-containing metal gap fill on the metal liner and the boron nucleation bottom layer.

19. The method according to claim 18, wherein the boron nucleation underlayer on average comprises 1 to 2 boron monolayers.

20. The method according to claim 18, wherein the metal gap filling is formed directly on the metal liner and the nucleation underlayer.

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