Method for producing electronic device

Abstract

The invention relates to a method for producing an electronic device, comprising the following steps: providing an electronic semiconductor chip having a contact surface, said contact surface having a layer, said layer having gold; providing a carrier having a mating contact surface; arranging capsules on the mating contact surfaces, the capsules each having a robust outer shell which encloses the supercooled metal liquid, the supercooled metal liquid having tin; arranging the electronic semiconductor chip on the carrier such that the contact surface faces the mating contact surface; and opening the capsule, where the supercooled metal liquid wets the mating contact surface and the contact surface, where tin and gold form an intermetallic compound.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing an electronic device.

[0002] This patent application claims the priority of German Patent Application 10 2022 130 878.2, the disclosure of which is incorporated herein by reference. Background Art

[0003] It is known to use AuSn solder joints for manufacturing electronic devices. In the known methods, the manufacturing of such solder joints requires high temperatures, which can cause strong metal stresses in the case of different coefficients of thermal expansion of the components connected to each other. Summary of the Invention

[0004] The object of the present invention is to provide a method for manufacturing an electronic device. The method is achieved by a method having the features of the independent claims. Different improvement schemes are proposed in the dependent claims.

[0005] The method for manufacturing an electronic device comprises the following steps: providing an electronic semiconductor chip having a contact surface, the contact surface having a layer, the layer having gold; providing a carrier having a mating contact surface; setting a capsule on the mating contact surface, wherein the capsules each have a solid outer shell, the outer shell surrounding a supercooled metal liquid, wherein the supercooled metal liquid has tin; setting the electronic semiconductor chip on the carrier such that the contact surface faces the mating contact surface; and opening the capsule, wherein the supercooled metal liquid wets the mating contact surface and the contact surface, and wherein tin and gold form an intermetallic compound.

[0006] The method enables the formation of a solder joint between the contact surface of the electronic semiconductor chip and the mating contact surface of the carrier. Herein, the manufacturing of the solder joint is advantageously carried out at a low temperature, particularly at a temperature below the melting temperature of the intermetallic compound. Thereby, the method advantageously enables the manufacturing of a solder joint having only small mechanical stresses, even in the case of different coefficients of thermal expansion of the components connected to each other.

[0007] In one embodiment of the method, another method step for annealing the electronic semiconductor chip and the carrier is carried out after opening the capsule. Annealing can, for example, improve the quality and uniformity of the solder joint manufactured by the method.

[0008] In one embodiment of the method, the annealing is carried out at a temperature between 150 °C and 180 °C. Advantageously, only a small amount of mechanical stress is generated in the solder joint produced by the method due to this relatively low temperature.

[0009] In one embodiment of the method, the formation of the intermetallic compound takes place at a temperature below 200 °C. For example, the formation of the intermetallic compound can take place at a temperature of 180 °C. Advantageously, only a small amount of mechanical stress is thereby generated in the welded joint produced by the method.

[0010] In one embodiment of the method, the placement of the electronic semiconductor chip on the carrier is effected by means of a heatable tool. The heatable tool can for example be a heated bond head. The use of the heatable tool enables the electronic semiconductor chip to be placed on the carrier and heated simultaneously to a temperature sufficient for the production of the intermetallic compound.

[0011] In one embodiment of the method, the electronic semiconductor chip is pressed against the carrier to open the capsule, in particular by means of a pressure between 0.05 kgf / mm 2 and 0.2 kgf / mm 2 The pressing of the electronic semiconductor chip against the carrier can for example be effected by means of the tool for placing the electronic semiconductor chip on the carrier. Advantageously, a controlled and reliable opening of the capsule is thereby achieved.

[0012] In one embodiment of the method, the opening of the capsule is effected by dissolving the solid outer shell, for example by an etching process, for example in an atmosphere having formic acid. Advantageously, a controlled and reliable opening of the capsule is also thereby achieved. An advantage of this embodiment is that this embodiment enables the capsules arranged on a plurality of mating contact surfaces of the carrier to be opened simultaneously.

[0013] In one embodiment of the method, the capsules are placed by spraying using a mask, by a printing method using a screen printing or a printing template, by spin coating or by contactless needle dispensing (Nadeldosieren). The method enables the placement of the capsules to be restricted to the mating contact surfaces of the carrier.

[0014] In one embodiment of the method, the capsules for placement on the mating contact surfaces are dissolved in a solvent. After the placement of the capsules, the solvent evaporates. Advantageously, the solvent can simplify the placement of the capsules on the mating contact surfaces of the carrier.

[0015] In one embodiment of the method, the layer thickness of the layer having gold and the amount of the capsules arranged on the mating contact surfaces are designed such that gold has a molar fraction of at least 60% in the formed intermetallic compound. In this case, the intermetallic compound formed by the method has beneficial metallic properties.

[0016] In one embodiment of the method, the layer having gold has a layer thickness between 1 μm and 3 μm, in particular between 1 μm and 2 μm. The layer having gold can for example have a layer thickness of 1.5 μm. Advantageously, this enables the production of intermetallic compounds with a beneficial mass fraction of gold.

[0017] In one embodiment of the method, the capsule is applied as a layer having a layer thickness between 1 μm and 5 μm, in particular having a layer thickness between 2 μm and 3 μm. Advantageously, this layer thickness of the capsule enables the production of intermetallic compounds with a beneficial mass fraction of tin.

[0018] In one embodiment of the method, the capsule is applied as a single-layered layer. Advantageously, in this case, it is possible to achieve particularly uniform wetting of the mating contact surfaces and the contact surfaces by the supercooled molten metal.

[0019] In one embodiment of the method, the electronic semiconductor chip is an optoelectronic semiconductor chip. The electronic semiconductor chip can for example be a light-emitting diode chip (LED chip).

[0020] In one embodiment of the method, the carrier is a QFN chip housing. In this case, the components of the carrier and the components of the electronic semiconductor chip can have significantly different coefficients of thermal expansion. Advantageously, the method still enables the production of welded joints with only a small amount of mechanical stress. Description of the Drawings

[0021] The above-described properties, features, and advantages of the present invention, as well as the ways and means of achieving them, become clearer and more understandable in connection with the following description of embodiments, which are elaborated in detail in conjunction with the accompanying drawings. Here, they are shown schematically respectively:

[0022] Figure 1 A cross-sectional side view showing an electronic semiconductor chip having a contact surface;

[0023] Figure 2 A cross-sectional side view showing a carrier having a mating contact surface;

[0024] Figure 3 A view showing a capsule dissolved in a solvent, the capsule being arranged on the mating contact surface using a mask.

[0025] Figure 4 A view showing the capsule arranged on the mating contact surface after evaporation of the solvent;

[0026] Figure 5 A top view showing the mating contact surface together with the capsule arranged thereon;

[0027] Figure 6Shows the arrangement of an electronic semiconductor chip on a carrier;

[0028] Figure 7 Shows wetting of a contact surface and a mating contact surface by a supercooled metallic liquid contained in a capsule after opening the capsule;

[0029] Figure 8 Shows a soldered joint formed by an intermetallic compound between the contact surface and the mating contact surface; and

[0030] Figure 9 Shows a top view of an electronic device formed by a carrier and an electronic semiconductor chip. Detailed Description

[0031] Figure 1 Shows a schematic cross-sectional side view of an electronic semiconductor chip 100. The electronic semiconductor chip 100 has a front side 101 and a contact side 102 opposite to the front side 101.

[0032] The electronic semiconductor chip 100 can be, for example, an optoelectronic semiconductor chip, such as a light-emitting diode chip (LED chip). In this case, the front side 101 of the electronic semiconductor chip 100 can be provided for light emission.

[0033] A contact surface 110 is formed at the contact side 102 of the electronic semiconductor chip 100. The contact surface 110 is provided for electrically, mechanically, and thermally contacting the electronic semiconductor chip 100 via soldering. In addition to the contact surface 110, the electronic semiconductor chip 100 can have additional contact surfaces for electrical contact, which can be provided at the contact side 102 or the front side 101 of the electronic semiconductor chip 100. In the Figure 1 example shown, the electronic semiconductor chip 100 has another contact surface at its front side 101.

[0034] A layer 120 is provided on the contact surface 110 at the contact side 102 of the electronic semiconductor chip 100, and the layer has gold. The layer 120 has a layer thickness 125, which can be, for example, between 1 μm and 3 μm, especially between 1 μm and 2 μm. For example, the layer thickness 125 of the layer 120 can be 1.5 μm. Below the layer 120 having gold, additional layers can be formed at the contact surface 110 of the electronic semiconductor chip 100, such as one or more metal layers with low solubility, such as layers containing nickel (Ni), palladium (Pd), platinum (Pt). However, the layer 120 having gold forms the outermost layer of this layer stack in any case.

[0035] Figure 2Shows a schematic cross-sectional side view of the carrier 200. The carrier 200 can also be referred to as a substrate. The carrier 200 can be configured, for example, as a ceramic carrier, a printed circuit board (PCB), a semiconductor chip, or other carriers. In Figure 2 In the example shown, the carrier 200 is configured as a QFN chip housing 205 having a lead frame section embedded in a plastic material.

[0036] The carrier 200 has an upper side 201 and a lower side 202 opposite to the upper side 201. At the upper side 201 of the carrier 200, mating contact surfaces 210 are formed. The mating contact surfaces 210 are provided for conductively connecting to the contact surfaces 110 of the electronic semiconductor chip 100 by means of solder joints.

[0037] Figure 3 Shows an enlarged cross-sectional side view of a part of the mating contact surfaces 210 formed at the upper side 201 of the carrier 200. At the mating contact surfaces 210, a coating 220 is formed, which in the example shown has a low-solubility metal layer and a layer made of a well-wettable metal covering the metal layer. The low-solubility layer can contain, for example, nickel, palladium, or platinum. The well-wettable layer can have, for example, gold, palladium, or platinum. The well-wettable layer can have a thickness of less than 200 nm, for example.

[0038] Figure 3 Shows the carrier 200 during the process step of setting the capsules 300 on the mating contact surfaces 210. The capsules 300 can be configured, for example, spherically and each have a solid outer shell 310. In each capsule 300, the solid outer shell 310 encloses a supercooled metal liquid 320. The supercooled metal liquid 320 has tin (Sn), suitably pure tin. The outer shell 310 can have, for example, tin oxide. Each of the capsules can have a diameter 305 between 0.5 μm and 10 μm, especially between 1 μm and 5 μm, for example.

[0039] In Figure 3 In the example shown, the capsules 300 are set on the mating contact surfaces 210 of the carrier 200 by a spraying method using a mask 500. For this purpose, the capsules 300 are dissolved in a solvent 340. The solvent 340 evaporates after being sprayed onto the mating contact surfaces 210 of the carrier 200, so that only the capsules 300 remain on the mating contact surfaces 210.

[0040] An alternative possibility for setting the capsules 300 on the mating contact surfaces 210 is a printing method using screen printing or a printing template, spin coating, or application by non-contact needle jetting. In these methods, the capsules 300 can also first be dissolved in a solvent, which then evaporates.

[0041] The capsule 300 is provided as layer 330 on the mating contact surface 210 of the carrier 200. The layer 330 has a layer thickness 335, which can be, for example, between 1 μm and 5 μm, particularly between 2 μm and 3 μm, for example. It can be suitable when the layer 330 is a single layer of the capsule 300.

[0042] Figure 4 Schematic cross-sectional side view showing a part of the mating contact surface 210 of the carrier 200 after evaporation of the solvent 340 together with the capsules 300 provided thereon. Figure 5 Top view showing a part of the mating contact surface 210 together with the capsules 300 provided thereon.

[0043] Figure 6 Shown at execution time between Figure 4 and Figure 5 Schematic cross-sectional side view of a part of the carrier 200 during the processing step for setting the electronic semiconductor chip 100 on the carrier 200 after the illustration shown, together with the capsules 300 provided on the mating contact surface 210. The electronic semiconductor chip 100 is set on the carrier 200 such that the contact surface 110 of the electronic semiconductor chip 100 faces the mating contact surface 210 of the carrier 200 and the capsules 300 provided thereon.

[0044] The setting of the electronic semiconductor chip 100 in the example shown in Figure 6 is carried out by means of a tool 600 shown only schematically. This can be referred to as an attachment step. The tool 600 can be configured as a heated bond head and heats the electronic semiconductor chip 100 to a fixed temperature, for example 180 °C, during its setting on the carrier 200. The carrier 200 can be at room temperature, for example 25 °C, during this time.

[0045] At the same time, as the electronic semiconductor chip 100 is set on the carrier 200 or after that, the outer shell 310 of the capsule 300 is opened so that the supercooled metal liquid 320 contained in the capsule 300 flows out. Subsequently, the supercooled metal liquid 320 wets the mating contact surface 210 of the carrier 200 and the contact surface 110 of the electronic semiconductor chip 100, where an intermetallic compound 400 is formed from the tin of the supercooled metal liquid 320 and the gold of the layer at the contact surface 110 of the electronic semiconductor chip 100. The process is schematically shown in the cross-sectional side view in Figure 7

[0046] After the intermetallic compound 400 solidifies, the intermetallic compound forms a solder joint 410 that conductively connects the contact surface 110 of the electronic semiconductor chip 100 to the mating contact surface 210 of the carrier 200. This processing stage is inFigure 8 is schematically shown in a sectional side view.

[0047] The capsule 300 can be opened by pressing the electronic semiconductor chip 100 against the carrier 200, for example by means of a pressure of 0.05 kgf / mm 2 and 0.2 kgf / mm 2 The pressing of the electronic semiconductor chip 100 against the carrier 200 can be carried out, for example, by means of a tool 600 for placing the electronic semiconductor chip 100 on the mating contact surface 210 of the carrier 200. Pressing the electronic semiconductor chip 600 can, however, also be carried out by means of another tool.

[0048] An alternative possibility for opening the capsule 300 consists in dissolving the outer shell 310 of the capsule 300, for example by means of an etching process. This can be carried out, for example, in an atmosphere having formic acid.

[0049] After the capsule 300 has been opened and the supercooled metal liquid 320 has flowed out, another method step for annealing the electronic semiconductor chip 100 and the carrier 200 can be carried out in order to improve the quality of the intermetallic compound 400. The annealing can be carried out, for example, at a temperature between 150 °C and 180 °C. Thus, the formation of the intermetallic compound 400 takes place generally at a temperature of less than 200 °C.

[0050] The layer thickness 125 of the layer 120 having gold at the contact surface 110 of the electronic semiconductor chip 100 and the amount of the capsule 300 provided on the mating contact surface 210 of the carrier 200 are expediently designed such that gold has a substance amount share of at least 60% (atomic percentage % at) in the formed intermetallic compound 400.

[0051] Figure 9 A top view of the electronic device 10 formed by connecting the electronic semiconductor chip 100 to the carrier 200 is shown schematically. If the electronic semiconductor chip 100 is an optoelectronic semiconductor chip, then the electronic device 10 is an optoelectronic device.

[0052] The invention is illustrated and described in detail according to preferred embodiments. Nevertheless, the invention is not limited to the disclosed examples. Other variants can be derived by those skilled in the art.

[0053] List of reference signs

[0054] 10 Electronic device

[0055] 100 Electronic semiconductor chip

[0056] 101 Front side

[0057] 102 Contact side

[0058] 110 Contact surface

[0059] 120 Layer (with gold)

[0060] 125 Layer thickness

[0061] 200 Carrier

[0062] 201 Upper side

[0063] 202 Lower side

[0064] 205 QFN chip housing

[0065] 210 Mating contact surface

[0066] 220 Cladding

[0067] 300 Capsule

[0068] 305 Diameter

[0069] 310 Outer shell

[0070] 320 Supercooled metallic liquid

[0071] 330 Layer

[0072] 335 Layer thickness

[0073] 340 Solvent

[0074] 400 Intermetallic compound

[0075] 410 Welding joint

[0076] 500 Mask

[0077] 600 Tool

Claims

1. A method for manufacturing an electronic device (10), comprising the following steps: - Providing an electronic semiconductor chip (100) having a contact surface (110), the contact surface having a layer (120) which has gold; - Providing a carrier (200) having a mating contact surface (210); - Placing a capsule (300) on the mating contact surface (210), wherein the capsule (300) respectively has a rigid outer shell (310) which encloses a supercooled metal liquid (320), and wherein the supercooled metal liquid (320) has tin; - Placing the electronic semiconductor chip (100) on the carrier (200) such that the contact surface (110) faces the mating contact surface (210); - Opening the capsule (300), wherein the supercooled metal liquid (320) wets the mating contact surface (210) and the contact surface (110), and wherein tin and gold form an intermetallic compound (400).

2. The method according to claim 1, wherein the following method steps are performed after opening the capsule (300): - Annealing the electronic semiconductor chip (100) and the carrier (200).

3. The method according to claim 2, wherein the annealing is performed at a temperature between 150 °C and 180 °C.

4. The method according to any one of the above claims, wherein the intermetallic compound (400) is formed at a temperature below 200 °C.

5. The method according to any one of the above claims, wherein the electronic semiconductor chip (100) is placed by means of a heatable tool (600).

6. The method according to any one of the above claims, In order to open the capsule (300), the electronic semiconductor chip (100) is pressed against the carrier (200), especially with a pressure between 0.05 kgf / mm 2 and 0.2 kgf / mm 2 .

7. The method according to any one of claims 1 to 5, wherein the capsule (300) is opened by dissolving the rigid outer shell (310), for example by an etching method, for example in an atmosphere having formic acid.

8. The method according to any one of the above claims, wherein the capsule (300) is placed by spraying using a mask (500), by a printing method using a screen printing or a printing template, by spin coating or by non-contact needle dispensing.

9. The method according to any one of the above claims, wherein the capsule (300) for placement on the mating contact surface (210) is dissolved in a solvent (340), wherein the solvent (340) evaporates after the capsule (300) is placed.

10. The method according to any one of the above claims, wherein the layer thickness (125) of the layer (120) having gold and the amount of the capsule (300) placed on the mating contact surface (210) are designed such that in the formed intermetallic compound (400), gold has a substance amount share of at least 60%.

11. The method according to any one of the above claims, wherein the layer (120) having gold has a layer thickness (125) between 1 μm and 3 μm, especially between 1 μm and 2 μm.

12. The method according to any one of the preceding claims, wherein the capsule (300) is applied as a layer (330) with a layer thickness (335) between 1 μm and 5 μm, in particular with a layer thickness (335) between 2 μm and 3 μm.

13. The method according to any one of the preceding claims, wherein the capsule (300) is applied as a single-layered layer (330).

14. The method according to any one of the preceding claims, wherein the electronic semiconductor chip (100) is an optoelectronic semiconductor chip.

15. The method according to any one of the preceding claims, wherein the carrier (200) is a QFN chip housing.

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