Microelectronic devices including stepped structures and related methods

Abstract

A microelectronic device includes a stack structure including: an array region including first conductive structures vertically spaced apart from each other; and a step region horizontally adjacent to the array region and including second conductive structures vertically spaced apart from each other and coupled to the first conductive structures. The second conductive structures individually include portions extending in a first horizontal direction and additional portions extending in a second horizontal direction transverse to the first horizontal direction. The step region includes a step structure having a step partially defined by an edge of the second conductive structure. Some of the steps extend in the first horizontal direction and other of the steps extend in the second horizontal direction. Related memory devices, electronic systems, and methods are also described.

Description

[0001] Priority declaration

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 18 / 054,291, filed on November 10, 2022, "MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS". TECHNICAL FIELD

[0003] In various embodiments, the present disclosure generally relates to the field of microelectronic device design and fabrication. More particularly, the present disclosure relates to microelectronic devices including staircase structures partially defined by conductive structures, and to related memory devices, electronic systems, and methods. BACKGROUND ART

[0004] Microelectronic device designers generally desire to increase the integration or density of features within a microelectronic device by reducing the size of individual features and by reducing the separation distance between adjacent features. Additionally, microelectronic device designers generally desire to design architectures that are not only compact but also provide performance advantages and simplify design.

[0005] One example of a microelectronic device is a memory device. Memory devices are typically provided as internal integrated circuits in a computer or other electronic device. There are many types of memory devices, including but not limited to volatile memory devices such as dynamic random access memory (DRAM) devices; and non-volatile memory devices such as NAND flash memory devices. A typical memory cell of a DRAM device includes an access device such as a transistor and a memory storage structure such as a capacitor. Modern applications of semiconductor devices may employ a large number of memory cells arranged in a memory array, thereby presenting rows and columns of memory cells. Memory cells may be electrically accessed via digital lines (e.g., bit lines, data lines) and word lines (e.g., access lines) arranged along the rows and columns of the memory cells of the memory array. The memory array may be two-dimensional (2D) to present a single stack (e.g., a single layer, a single tier) of memory cells, or may be three-dimensional (3D) to present multiple stacks (e.g., multiple tiers, multiple layers) of memory cells.

[0006] A vertical memory array architecture generally includes an electrical connection between a conductive structure of one or more layers of conductive stack structures of a memory device and an access line (e.g., a word line) such that a memory cell of the vertical memory array can be uniquely selected for a write, read, or erase operation. A method of forming such an electrical connection includes forming a so-called "step" (or "rung") structure at an edge (e.g., a horizontal end) of one or more layers of conductive stack structures of the memory device. The step structure includes individual "steps" that define a contact region of the conductive structure, and a conductive contact structure can be positioned on the contact region to provide electrical access to the conductive structure.

[0007] As the size of memory cells has decreased, the density and complexity of memory arrays have increased. As the density of memory cells within a memory array has increased, the density of conductive interconnect structures configured to facilitate memory cell operation has also increased. For example, the spacing between adjacent conductive interconnect structures decreases as the memory cell density of the memory array increases. However, the increased density of conductive interconnect structures presents difficulties in fully forming the conductive interconnect structures that are in electrical communication with the memory cells. SUMMARY OF THE INVENTION

[0008] Embodiments described herein include devices containing microelectronic devices, the microelectronic devices including a step structure partially defined by a conductive structure, and the embodiments include related memory devices, electronic systems, and methods. According to one embodiment described herein, a microelectronic device includes a stack structure including: an array region including first conductive structures vertically spaced apart from each other; and a step region horizontally adjacent to the array region and including: second conductive structures vertically spaced apart from each other and coupled to the first conductive structures, the second conductive structures individually including a portion extending in a first horizontal direction and an additional portion extending in a second horizontal direction transverse to the first horizontal direction; and a step structure having steps partially defined by edge portions of the second conductive structures, some of the steps extending in the first horizontal direction and some of the steps extending in the second horizontal direction.

[0009] According to additional embodiments described herein, a memory device includes: a vertical stack of dynamic random access memory (DRAM) cells in an array region, each of the DRAM cells including a storage device horizontally adjacent to an access device; a first conductive line extending in a first horizontal direction within the array region and operatively associated with the vertical stack of DRAM cells; a second conductive line outside the array region and coupled to the first conductive line, the second conductive line individually including a first portion extending in the first horizontal direction and a second portion integral and continuous with the first portion and extending in a second horizontal direction orthogonal to the first horizontal direction; and a conductive contact in contact with a stepped structure having a horizontal curved step partially defined by a horizontal end portion of the second conductive line, the conductive contact including a first row of conductive contacts extending in the second horizontal direction and a second row of conductive contacts extending in the second horizontal direction and generally aligned with the first row of conductive contacts in the first horizontal direction.

[0010] Additionally, according to additional embodiments described herein, a method of forming a microelectronic device includes: forming a preliminary stack structure including a vertical alternating sequence of insulating and sacrificial materials disposed in a preliminary layer, the preliminary stack structure including an array region and a stepped region horizontally adjacent to the array region; forming a stepped structure located within the stepped region of the preliminary stack structure and individually having a step defined by a horizontal edge of the preliminary layer, the stepped structure including a partially curved horizontal cross-sectional shape at different vertical elevations thereof; replacing a portion of the sacrificial material within the array region with a first conductive structure; and replacing an additional portion of the sacrificial material within the stepped region with a second conductive structure individually aligned with and coupled to the first conductive structure, the second conductive structure individually including a portion extending in a first horizontal direction and an additional portion extending in a second horizontal direction transverse to the first horizontal direction.

[0011] According to other embodiments described herein, an electronic system includes: a processor operatively coupled to an input device and an output device; and a memory device operatively coupled to the processor, the memory device including: a stack structure including a vertical stack of memory cells; a stepped structure located within the stack structure and horizontally adjacent to the vertical stack of memory cells, the stepped structure individually including a step having at least a partially curved horizontal cross-sectional shape; and a non-linear conductive line partially defining the step of the stepped structure, two of the non-linear conductive lines being associated with one of the stepped structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figures 1A to 1C A simplified partial top view ( Figure 1A ) and a simplified partial cross-sectional view ( Figure 1B and 1C )

[0013] Figures 2A to 2K is a simplified partial perspective view showing a method of forming a microelectronic device according to an embodiment of the present disclosure ( Figures 2A to 2D and 2F), a simplified partial top view ( Figure 2E , 2G , 2I and 2J) and a simplified partial cross-sectional view ( Figure 2H and 2K ); and

[0014] Figure 3 is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. Detailed Description

[0015] The following description provides specific details, such as material types, material thicknesses, and processing conditions, in order to provide a thorough description of the embodiments described herein. However, those skilled in the art should understand that the embodiments disclosed herein may be practiced without these specific details. In fact, the embodiments may be practiced in conjunction with conventional manufacturing techniques employed in the semiconductor industry. Additionally, the description provided herein does not form a complete process flow for manufacturing a microelectronic device (e.g., a semiconductor device, a memory device), an apparatus, or an electronic system or a complete microelectronic device, apparatus, or electronic system. The structures described below do not form a complete microelectronic device, apparatus, or electronic system. Only those process operations and structures necessary for understanding the embodiments described herein are described in detail below. Additional operations for forming a complete microelectronic device, apparatus, or electronic system from the structures may be performed by conventional techniques.

[0016] The diagrams presented herein are for illustrative purposes only and are not intended to be actual views of any specific material, component, structure, device, or system. It is expected that the shapes depicted in the figures will vary due to, for example, manufacturing techniques and / or tolerances. Accordingly, the embodiments described herein should not be construed as limited to the specific shapes or regions shown, but should include, for example, shape deviations caused by manufacturing. For example, a region shown or described as box-shaped may have rough and / or non-linear features, and a region shown or described as circular may include some rough and / or linear features. Additionally, the acute angles shown may be rounded, and vice versa. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the exact shape of the regions and do not limit the scope of the claims. The figures are not necessarily to scale. Additionally, common elements between the figures may retain the same numerical reference.

[0017] As used herein, the term "memory device" means and includes a microelectronic device that exhibits memory functionality but is not necessarily limited thereto. By way of example only, the term "memory device" means and includes not only conventional memories (e.g., conventional volatile memories such as conventional DRAM; conventional non-volatile memories such as conventional NAND memories), but also application specific integrated circuits (ASICs) (e.g., system on a chip (SoC)), microelectronic devices that combine logic and memory, and graphics processing units (GPUs) incorporating memory.

[0018] As used herein, the terms "longitudinal", "vertical", "lateral", and "horizontal" refer to the major plane of a substrate (e.g., a base material, a base structure, a base configuration, etc.) on or in which one or more structures and / or features are formed and are not necessarily defined by the Earth's gravitational field. A "lateral" or "horizontal" direction is a direction generally parallel to the major plane of the substrate, while a "longitudinal" or "vertical" direction is a direction generally perpendicular to the major plane of the substrate. The major plane of the substrate is defined by a surface of the substrate that has a relatively large area compared to other surfaces of the substrate. Referring to the figures, a "horizontal" or "lateral" direction may be perpendicular to the indicated "Z" axis and may be parallel to the indicated "X" axis and / or parallel to the indicated "Y" axis; and a "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, perpendicular to the indicated "X" axis, and perpendicular to the indicated "Y" axis.

[0019] As used herein, features (e.g., regions, materials, structures, devices) described as being "adjacent" to each other mean and include features having one or more of the disclosed identities that are located closest (e.g., nearest) to each other. Additional features (e.g., additional regions, additional materials, additional structures, additional devices) that do not match one or more of the disclosed identities of the "adjacent" features may be disposed between the "adjacent" features. "Adjacent" features may be positioned directly adjacent to each other such that no other features intervene between the "adjacent" features; or "adjacent" features may be positioned indirectly adjacent to each other such that at least one feature having an identity other than the identity associated with at least one "adjacent" feature is located between the "adjacent" features. Thus, features described as being "vertically adjacent" to each other mean and include features having one or more of the disclosed identities that are located vertically closest (e.g., vertically nearest) to each other. Additionally, features described as being "horizontally adjacent" to each other mean and include features having one or more of the disclosed identities that are located horizontally closest (e.g., horizontally nearest) to each other.

[0020] As used herein, the term "intersection" means and includes the location where two or more features (e.g., regions, structures, materials, devices) or alternatively two or more portions of a single feature meet. For example, the intersection between a first feature extending in a first direction (e.g., the X direction) and a second feature extending in a second direction different from the first direction (e.g., the Y direction) can be the location where the first feature and the second feature meet.

[0021] As used herein, the "pitch" between two adjacent features refers to the distance between corresponding locations (e.g., points) within the two adjacent features.

[0022] As used herein, referring to an element as being "on" or "above" another element means and includes that the element is directly on top of the other element, directly adjacent to (e.g., directly laterally adjacent to, directly vertically adjacent to) the other element, directly under the other element, or in direct contact with the other element. It also includes that the element is indirectly on top of the other element, indirectly adjacent to (e.g., indirectly laterally adjacent to, indirectly vertically adjacent to) the other element, indirectly under the other element or nearby, and there are other elements in between. Conversely, when an element is referred to as being "directly on" or "directly adjacent to" another element, there is no intervening element.

[0023] As used herein, spatial relative terms such as "below", "beneath", "lower", "bottom", "above", "upper", "top", "front", "rear", "left", "right", etc. may be used for convenience to describe the relationship of one element or feature to another element or feature, as shown in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of the material in addition to the orientation depicted in the figures. For example, if the material in the figure is inverted, an element described as being "below" or "beneath" or "under" or "on the bottom of" another element or feature will be oriented "above" or "on the top of" the other element or feature. Thus, the term "below" can cover both the above and below orientations depending on the context in which the term is used, which will be apparent to those of ordinary skill in the art. The material can be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped, etc.), and the spatial relative descriptors used herein can be interpreted accordingly.

[0024] As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms.

[0025] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate the operation of one or more of the structure and the device in a predetermined manner.

[0027] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes the degree to which the given parameter, property, or condition is understood by one of ordinary skill in the art to conform to a degree of deviation (e.g., within an acceptable tolerance). By way of example, depending on the particular parameter, property, or condition being substantially met, the parameter, property, or condition may be met at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0028] As used herein, "about" or "substantially" with reference to a numerical value of a particular parameter includes the recited numerical value and the degree of deviation from the recited numerical value that is understood by one of ordinary skill in the art to be within the acceptable tolerance of the particular parameter. For example, "about" or "substantially" with respect to a numerical value may include additional numerical values that are within the range of 90.0% to 110.0% of the recited numerical value, such as within the range of 95.0% to 105.0% of the recited numerical value, within the range of 97.5% to 102.5% of the recited numerical value, within the range of 99.0% to 101.0% of the recited numerical value, within the range of 99.5% to 100.5% of the recited numerical value, or within the range of 99.9% to 100.1% of the recited numerical value.

[0029] As used herein, "conductive material" means and includes conductive materials such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe- and Ni-based alloys, Co- and Ni-based alloys, Fe- and Co-based alloys, Co- and Ni- and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steels, low-carbon steels, stainless steels); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)). Additionally, "conductive structure" means and includes a structure formed of and including a conductive material.

[0030] As used herein, "insulating material" means and includes electrical insulating materials such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x ), zirconium oxide (ZrO x ), tantalum oxide (TaO x ), and magnesium oxide (MgO x )) (one or more of these), at least one dielectric nitride material (e.g., silicon nitride (SiN y ), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y ), and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO x C z N y ). Chemical formulas containing one or more of "x", "y", and "z" herein (e.g., SiO x , AlO x , HfO x , NbO x , TiO x , SiN y , SiO x N y , SiO x C z N y ) represent materials having an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) for each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Since chemical formulas represent relative atomic ratios rather than strict chemical structures, insulating materials can include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values of "x", "y", and "z" (if present) can be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes a chemical compound having an elemental composition that cannot be represented by a ratio of well-defined natural numbers and that violates the law of definite proportions. Additionally, "insulating structure" means and includes a structure formed of and containing an insulating material.

[0031] Unless otherwise specified, the materials described herein can be formed by conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the materials can be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material can be selected by those skilled in the art. Unless the context otherwise indicates, material removal can be achieved by any suitable technique including but not limited to the following: etching, polishing planarization (e.g., chemical-mechanical planarization), or other known methods.

[0032] According to the embodiments described herein, a microelectronic device (e.g., a memory device, such as a 3D DRAM memory device) includes a stacked structure that includes: an array region that includes first conductive structures (e.g., access lines, digital lines) that are vertically spaced apart from each other; and a stepped region that is horizontally adjacent to the array region and includes second conductive structures (e.g., additional access lines, additional digital lines) that are vertically spaced apart from each other and coupled to the first conductive structures. The second conductive structures can individually extend horizontally on a multi-directional path (e.g., a non-linear horizontal path). For example, each of the second conductive structures individually includes a portion that extends in a first horizontal direction and an additional portion that extends in a second horizontal direction that is transverse to the first horizontal direction. The stepped region includes a stepped structure that has steps that are partially defined by edge portions of the second conductive structures. Some of the steps extend in the first horizontal direction, and some of the steps extend in the second horizontal direction.

[0033] In some embodiments, the stepped structure has at least a partially curved horizontal cross-sectional shape, such as a closed curve (e.g., a partial ellipse) horizontal cross-sectional shape, and is arranged relative to each other in a woven pattern (e.g., a hexagonal pattern, such as a hexagonal close-packed pattern). The microelectronic device includes conductive contacts on individual steps of the stepped structure. The conductive contacts of the individual stepped structures are aligned with each other in rows that extend in the second horizontal direction, and each individual stepped structure includes two or more of the conductive contacts on each vertical level of the steps. Compared with conventional microelectronic devices, forming a microelectronic device that includes a stepped structure having at least a partially curved horizontal cross-sectional shape helps to reduce the area of the microelectronic device. Additionally, forming the stepped structure of the present disclosure can provide a greater process margin (e.g., an increased area) for forming conductive contact structures on its steps, and / or provide space for forming a greater number of conductive contact structures in the stepped region. Furthermore, forming the stepped structure of the present disclosure in a woven pattern and forming the second conductive structures of the present disclosure can provide enhanced support within the microelectronic device.

[0034] In addition, forming the conductive structure of the present disclosure in the stepped region helps to optimize the utilization of the area of the stepped region, such that the area allocated to the stepped structure is reduced and the reliability of the microelectronic device structure is improved. Additionally, the second conductive structure can be substantially continuous with the first conductive structure at each vertical level of the stacked structure and can be formed during the formation of the first conductive structure. Thus, by forming the second conductive structure and the first conductive structure in a single processing operation, the manufacturing process can be simplified and the manufacturing cost can be reduced. Accordingly, the method of the present disclosure can reduce or eliminate process operations that are otherwise used in many conventional microelectronic devices to form the conductive structure and the stepped structure, so as to simplify the manufacturing process and reduce the complexity of the microelectronic device. Moreover, the multi-directional horizontal paths of the second conductive structure can significantly mitigate the capacitive coupling between horizontally adjacent second conductive structures, allowing for an increase in conductivity during the use and operation of the microelectronic device as compared to conventional microelectronic devices.

[0035] Figures 1A to 1C A simplified partial top view ( Figure 1A ) and simplified partial cross-sectional views ( Figure 1B and 1C ) of a microelectronic device structure 100 (e.g., a memory device, such as a 3D DRAM memory device) according to an embodiment of the present disclosure. From the description provided below, it will be apparent to those of ordinary skill in the art that the methods and structures described herein with reference to Figures 1A to 1C can be used in a variety of devices and electronic systems.

[0036] Figure 1A FIG. is a simplified partial top view of the microelectronic device structure 100; Figure 1B FIG. is a simplified partial cross-sectional view of the microelectronic device structure 100 taken along the section line B-B of Figure 1A ; and Figure 1C FIG. is a simplified partial cross-sectional view of the microelectronic device structure 100 taken along the section line C-C of Figure 1A .

[0037] Referring to Figure 1A , the microelectronic device structure 100 includes an array region 102 (also referred to herein as the "memory array region") and one or more stepped regions 104 (also referred to herein as "contact landing regions") positioned horizontally adjacent to the array region 102. In some embodiments, a single stepped region 104 is horizontally adjacent to the array region 102 in a first horizontal direction (e.g., in the X direction). In other embodiments, more than one (e.g., two) of the stepped regions 104 are horizontally adjacent to the array region 102 in the first horizontal direction (e.g., on two opposite sides thereof).

[0038] The stepped region 104 may include a stepped structure 130 that includes a conductive contact structure 142 coupled thereto. The conductive contact structure 142 may connect (e.g., electrically connect) one or more components of the microelectronic device structure 100 to the circuitry of a second microelectronic device structure or one or more additional components (e.g., a sub - word line driver).

[0039] Optionally, the conductive contact exit region 106 may be horizontally adjacent (e.g., in the X - direction) to the stepped region 104. In some embodiments, the conductive contact exit region 106 is located at a horizontal end (e.g., in the Y - direction) of the array region 102. The conductive contact exit region 106 may include additional conductive contacts for electrically connecting one or more components (e.g., the global conductive structure 127) of the microelectronic device structure 100 to additional circuitry external to the array region 102.

[0040] Reference Figure 1A and 1B , within the array region 102, the microelectronic device structure 100 includes a vertical stack (e.g., in the Z - direction) of memory cells 108 above a substrate structure 110. Each vertical stack of memory cells 108 includes a vertical stack of access devices 112 and a vertical stack of storage devices 114, where the storage devices 114 in the vertical stack of storage devices 114 are coupled to the access devices 112 in the vertical stack of access devices 112. The vertical stack of storage devices 114 vertically overlies (e.g., in the Z - direction) the substrate structure 110. The vertical stack of access devices 112 may be horizontally adjacent (e.g., in the Y - direction) to the vertical stack of storage devices 114.

[0041] The vertical stack of memory cells 108 may individually include vertically spaced (e.g., in the Z - direction) tiers of memory cells 108, where each memory cell 108 individually includes a storage device 114 horizontally adjacent to an access device 112. Although Figure 1A a specific number of vertical stacks of memory cells 108 is shown, the present disclosure is not limited thereto, and the array region 102 may include fewer or alternatively more vertical stacks of memory cells 108 than those shown.

[0042] The substrate structure 110 may include a conventional silicon substrate (e.g., a conventional silicon wafer), or another bulk substrate including a semiconducting material. As used herein, the term "bulk substrate" means not only silicon substrates, but also silicon-on-insulator (SOI) substrates such as silicon-on-sapphire (SOS) substrates and silicon-on-glass (SOG) substrates, silicon epitaxial layers on a substrate semiconductor base, and other substrates formed of one or more semiconducting materials (e.g., one or more of silicon materials such as single-crystalline silicon or polycrystalline silicon; silicon germanium; germanium; gallium arsenide; gallium nitride; and indium phosphide) and including the semiconducting material. In some embodiments, the substrate structure 110 includes a silicon wafer.

[0043] In some embodiments, the substrate structure 110 includes different materials, structures, devices, and / or regions formed therein and / or thereon. In some embodiments, the substrate structure 110 includes complementary metal-oxide-semiconductor (CMOS) circuitry, and devices configured to enable the operation of the vertical stack of memory cells 108 of the microelectronic device structure 100.

[0044] Reference Figure 1B , the substrate structure 110 may be electrically isolated from the vertical stack of memory cells 108 by a first insulating material 116 that vertically intervenes (e.g., in the Z direction) between the substrate structure 110 and the vertical stack of memory cells 108. The first insulating material 116 may be formed of and include an insulating material that is, for example, one or more of the following: oxide materials (e.g., silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, titanium dioxide (TiO2), hafnium oxide (HfO2), zirconium dioxide (ZrO2), hafnium dioxide (HfO2), tantalum oxide (TaO2), magnesium oxide (MgO), aluminum oxide (Al2O3), or a combination thereof) and amorphous carbon. In some embodiments, the first insulating material 116 includes SiO2.

[0045] Each access device 112 in the vertical stack of access devices 112 individually includes a channel region 118 that includes channel material 119 that is in electrical communication with at least a portion (e.g., a first electrode 144 of a horizontally adjacent memory device 114) of a horizontally adjacent (e.g., in the Y direction) memory device 114.

[0046] The channel material 119 may be formed of, for example, a semiconductive material (e.g., silicon) and include the semiconductive material. In some embodiments, the channel material 119 includes silicon, such as epitaxially grown silicon. In some embodiments, the channel material 119 includes a semiconductive material (e.g., polysilicon) doped with at least one N-type dopant or at least one P-type dopant. In some embodiments, at least some portions of the channel material 119 are doped with one of at least one N-type dopant (e.g., one or more of arsenic ions, phosphorus ions, and antimony ions) and at least one P-type dopant (e.g., one or more of boron ions, aluminum ions, and gallium ions), and at least other portions of the channel material 119 are doped with the other of at least one N-type dopant and at least one P-type dopant to form the channel region 118.

[0047] Each of the access devices 112 may be individually coupled (e.g., electrically connected) to one or more first conductive structures 120 (also referred to herein as "first conductive lines", "first access lines", or "first word lines"). The first conductive structures 120 that are vertically overlying (e.g., in the Z direction) the substrate structure 110 and within each other's horizontal boundaries (e.g., in the X direction, in the Y direction) may form a vertical stack structure 122 of the first conductive structures 120. The vertical stack structure 122 includes tiers of the first conductive structures 120 that are vertically spaced apart from each other (e.g., in the Z direction). The first conductive structures 120 within the array region 102 of the vertical stack structure 122 may be individually coupled to additional conductive structures within the stepped region 104 of the vertical stack structure 122, as described below.

[0048] The first conductive structure 120 may horizontally (e.g., in the X direction) extend through the microelectronic device structure 100 (e.g., through the vertical stack of memory cells 108) as a conductive line (e.g., word line), and may each be configured to couple to vertically adjacent (e.g., in the Z direction) access devices 112 (e.g., the channel regions 118 of adjacent access devices 112). The first conductive structure 120 may be configured to couple to vertically adjacent access devices 112. Refer to Figure 1B , the access devices 112 may be individually vertically located (e.g., in the Z direction) between portions of the first conductive structure 120. In some embodiments, the access devices 112 are individually vertically located (e.g., in the Z direction) within the vertical boundaries of the first conductive structure 120. In other embodiments, the first conductive structure 120 is configured as a digital line (e.g., a horizontal digital line).

[0049] The first conductive structure 120 can be individually formed of and include a conductive material, such as one or more of the following: metals (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold); metal alloys; metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides); materials including at least one of titanium nitride (TiN x ), tantalum nitride (TaN x ), tungsten nitride (WN x ), titanium aluminum nitride (TiAl x N y ), iridium oxide (IrO x ), ruthenium oxide (RuO x ), alloys thereof; a conductive doped semiconductor material (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.); polysilicon; or other materials exhibiting conductivity. In some embodiments, the first conductive structure 120 individually includes tungsten. In other embodiments, the first conductive structure 120 individually includes TiN x .

[0050] The first conductive structure 120 can be individually configured to provide sufficient voltage to a channel region 118 that is directly vertically adjacent (e.g., in the Z direction) to a corresponding access device 112, to couple a storage device 114 that is horizontally adjacent (e.g., in the Y direction) and associated with the access device 112 to, for example, a conductive pillar structure (e.g., a digit line), which vertically extends (e.g., in the Z direction) through or proximate to a vertical stack of access devices 112 of the vertical stack of memory cells 108. Each first conductive structure 120 can individually include a gate structure configured to provide sufficient voltage (e.g., a threshold switching voltage) to a channel region 118 that is vertically adjacent (e.g., in the Z direction) to the first conductive structure 120, to electrically connect a conductive wiring structure coupled to the access device 112 including the channel region 118 to a horizontally adjacent (e.g., in the Y direction) storage device 114.

[0051] A vertical stack structure 122 including the first conductive structures 120 can intersect a vertical stack of memory cells 108 in the array region 102, such as intersecting a vertical stack of access devices 112 of the vertical stack of memory cells 108. Individual first conductive structures 120 of the vertical stack structure 122 can intersect individual levels (e.g., layer 131) of the memory cells 108 in the vertical stack of memory cells 108. Individual first conductive structures 120 can intersect and include a portion (e.g., the gates of the access devices 112) of a plurality of vertical stacks of access devices 112.

[0052] Reference Figure 1A, the first conductive structures 120 can individually extend through and intersect several vertically stacked access devices 112 of the vertically stacked memory cells 108. In some embodiments, each of the first conductive structures 120 extends through horizontally adjacent (e.g., in the X direction) vertically stacked memory cells 108. In some embodiments, the first conductive structures 120 extending in a first horizontal direction (e.g., in the X direction) are spaced apart from each other in a second horizontal direction orthogonal to the first horizontal direction (e.g., in the Y direction).

[0053] Although Figure 1A and 1B the first conductive structures 120 of the vertically stacked structure 122 are shown individually intersecting and forming portions of a particular amount of the vertically stacked memory cells 108, the present disclosure is not limited thereto. In other embodiments, the first conductive structures 120 of the vertically stacked structure 122 individually intersect and form portions of fewer or alternatively more vertically stacked memory cells 108 than those shown.

[0054] As Figure 1B shown, in some embodiments, the first conductive structures 120 that are vertically adjacent (e.g., in the Z direction) between vertically adjacent (e.g., in the Z direction) access devices 112 are spaced apart from each other by a second insulating material 124. The second insulating material 124 can be formed of and include an insulating material that is different from the channel material 119 and has an etch selectivity relative to the channel material 119. In some embodiments, the second insulating material 124 is formed of and includes one or more of the materials described above with reference to the first insulating material 116. In some embodiments, the second insulating material 124 is formed of an oxide material (e.g., SiO2) and includes the oxide material.

[0055] Returning to Figure 1A, the microelectronic device structure 100 may include conductive pillar structures 126 that extend vertically (e.g., in the Z direction) through the microelectronic device structure 100. The conductive pillar structures 126 may also be referred to herein as "digit lines", "digit line pillar structures", or "vertical digit lines". The conductive pillar structures 126 may be coupled to the access devices 112 to facilitate the operation of the memory cells 108 in the vertical stack of memory cells 108. Each conductive pillar structure 126 extends directly vertically to be horizontally adjacent (e.g., in the Y direction) to and in contact with the access devices 112 of the vertical stack of memory cells 108. In some embodiments, each vertical stack of memory cells 108 includes one of the conductive pillar structures 126 that extends vertically (e.g., in the Z direction) and is horizontally adjacent (e.g., in the Y direction) to the vertical stack of memory cells 108 (e.g., close to the access devices 112 of the memory cells 108). In some embodiments, the conductive pillar structures 126 are in electrical communication with the substrate structure 110( Figure 1B ). In other embodiments, the conductive pillar structures 126 are configured to be coupled to the access lines (e.g., vertical access lines, vertical word lines) of the vertical stack of memory cells 108.

[0056] The conductive pillar structures 126 may be individually formed of and include a conductive material, which is, for example, one or more of the following: metals (e.g., one or more of tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold); metal alloys; metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides); materials including at least one of titanium nitride (TiN x ), tantalum nitride (TaN x ), tungsten nitride (WN x ), titanium aluminum nitride (TiAl x N y ), iridium oxide (IrO x ), ruthenium oxide (RuO x ), and alloys thereof; conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.); or other materials exhibiting conductivity. In some embodiments, the conductive pillar structures 126 include tungsten.

[0057] The microelectronic device structure 100 may include a global conductive structure 127 (e.g., a global conductive line, a global digital line), which is shown in dashed lines and is formed vertically (e.g., in the Z direction) above the conductive pillar structure 126 and is in electrical communication with the conductive pillar structure 126. The global conductive structure 127 may or may not vertically overlie (e.g., in the Z direction) the vertical stack of memory cells 108. In some embodiments, the global conductive structure 127 extends horizontally (e.g., in the Y direction) through the microelectronic device structure 100. For example, the global conductive structure 127 may be coupled to the conductive pillar structure 126 and to additional conductive contacts within the conductive contact exit region 106. In some such embodiments, the global conductive structure 127 extends generally continuously horizontally through the array region 102 and terminates in each of the conductive contact exit regions 106. The first longitudinal end of the global conductive structure 127 may terminate in one of the conductive contact exit regions 106, and the second longitudinal end of the global conductive structure 127 may terminate in another of the conductive contact exit regions 106, but other configurations may be contemplated.

[0058] For convenience, only the global conductive structure 127 that is close to the conductive contact exit region 106 is shown coupled to the conductive pillar structure 126 in Figure 1A , but it should be understood that additional global conductive structures 127 may be coupled to the remainder of the conductive pillar structure 126. In some embodiments, each of the global conductive structures 127 is coupled to more than one (e.g., two, three, four, six, eight) of the conductive pillar structures 126. The global conductive structure 127 may be formed of and include a conductive material, which is, for example, one or more of the materials described above with reference to the conductive pillar structure 126.

[0059] Referring to Figure 1B , each of the access devices 112 may be surrounded by a dielectric material 128, which may also be referred to herein as a "gate dielectric material". The channel region 118 is separated from the first conductive structure 120 by the dielectric material 128. The first conductive structure 120 is separated from the access devices 112 by the dielectric material 128. In some embodiments, the portion of the first conductive structure 120 that is directly vertically adjacent (e.g., in the Z direction) to the horizontal boundary of the dielectric material 128 (e.g., in the X direction, in the Y direction) and is within the horizontal boundary may be referred to as a "gate electrode".

[0060] In some embodiments, each of the access devices 112 is substantially surrounded by a dielectric material 128, which in turn is substantially surrounded by a first conductive structure 120. In some such embodiments, since each of the access devices 112 is individually substantially surrounded by one of the first conductive structures 120, the access devices 112 individually include so-called "fully-depleted surround gate" access devices (e.g., fully-depleted surround gate transistors).

[0061] The dielectric material 128 may be formed of and include an insulating material. By way of non-limiting example, the dielectric material 128 may include one or more of the following: phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, SiO2, TiO2, ZrO2, HfO2, TaO2, MgO, Al2O3, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si3N4)), oxynitrides (e.g., silicon oxynitride, another gate dielectric material, dielectric carbonitride materials (e.g., silicon carbonitride (SiC x N y ))), or dielectric carbon oxynitride materials (e.g., silicon carbon oxynitride (SiO x C y N z ))).

[0062] In some embodiments, the dielectric material 128 is also located on the surface of the first conductive structure 120 and between the first conductive structure 120 and the second insulating material 124. The portion of the dielectric material 128 on the surface of the second insulating material 124 may not be referred to as "gate dielectric" material.

[0063] As Figure 1A shown, the storage device 114 is in electrical communication with the conductive plate structure 129. The conductive plate structure 129 may be formed of and include a conductive material, which is, for example, one or more of the materials of one or more electrodes (e.g., the second electrode 146) of the storage device 114. In some embodiments, the conductive plate structure 129 includes substantially the same material composition as one or more of the electrodes of the storage device 114. In other embodiments, the conductive plate structure 129 includes a material composition different from any of the electrodes of the storage device 114. The conductive plate structure 129 may be referred to herein as a "conductive plate" or a "ground structure". The conductive plate structure 129 extends horizontally as a conductive plate (e.g., in the X direction). In some embodiments, the conductive plate structure 129 extends horizontally in substantially the same direction and is substantially parallel to the first conductive structure 120. The conductive plate structure 129 may be horizontally located (e.g., in the Y direction) between vertical stacks of memory cells 108, such as between vertical stacks of storage devices 114.

[0064] As Figure 1B shown, optionally, the access device 112 at the vertical uppermost (e.g., in the Z direction) may form a multiplexer 136. In some embodiments, the global conductive structure 127 is individually in electrical communication with the multiplexer 136 to selectively couple the global conductive structure 127 to one of the conductive pillar structures 126 through the multiplexer 136. In some embodiments, the multiplexer 136 is individually in electrical communication with one of the first conductive structures 120 horizontally adjacent (e.g., in the Y direction) to the multiplexer 136.

[0065] Optionally, the access device 112 vertically adjacent (e.g., vertically below the multiplexer 136) to the multiplexer 136 may individually include a transistor 138 configured to electrically couple the horizontally adjacent (e.g., in the X direction) conductive pillar structure 126 to the conductive plate structure 129 through an additional conductive structure (e.g., a semiconductive material). The transistor 138 may include a so-called "bleed" transistor or "leakage" transistor configured to provide a bias voltage to the conductive pillar structure 126 coupled thereto (e.g., the conductive pillar structure 126 horizontally adjacent (e.g., in the Y direction)). In some embodiments, the first conductive structure 120 coupled to the transistor 138 is in electrical communication with a voltage such as a drain voltage V dd or a voltage source V ss . In use and operation, the transistor 138 is configured to provide a negative voltage to the unselected (e.g., deactivated) vertically stacked conductive pillar structures 126 of the memory cell 108. The transistor 138 is configured to electrically connect the unselected conductive pillar structures 126 to the corresponding conductive plate structure 129 (e.g., a ground structure, a cell plate) to which it can be coupled to a negative voltage. In some embodiments, each vertical stack of the memory cells 108 includes at least one (e.g., one) of the multiplexers 136 and at least one (e.g., one) of the transistors 138.

[0066] Although the vertical uppermost access device 112 is shown as a multiplexer 136 and the access device 112 vertically adjacent to the multiplexer 136 is shown as a transistor 138, other configurations may be considered for the sake of clear and easy understanding of the drawings and the related description. For example, alternatively, the vertical lowermost access device 112 (e.g., proximal to the base structure 110) may be formed as a multiplexer 136 and the access device 112 vertically adjacent to the multiplexer 136 may include a transistor 138.

[0067] As Figure 1A shown, in connection with Figure 1B, the vertical stack of the memory devices 114 vertically overlies (e.g., in the Z direction) the substrate structure 110. Each of the memory devices 114 individually includes a first electrode 144 (e.g., an external electrode), a second electrode 146 (e.g., an internal electrode), and a dielectric material therebetween. For convenience, in Figure 1A , only three (3) of the memory devices 114 are shown as including the first electrode 144 and the second electrode 146, but it should be understood that each of the memory devices 114 may include the first electrode 144 and the second electrode 146. In some such embodiments, the memory devices 114 individually include capacitors. However, the present disclosure is not limited thereto, and in other embodiments, the memory devices 114 may each individually include other structures, such as phase change memory (PCM), resistive random access memory (RRAM), conductive-bridge random access memory (conductive-bridge RAM), or another structure for storing logical states.

[0068] At least a portion of each memory device 114 is in electrical communication with a horizontally adjacent (e.g., in the X direction) access device 112. In some embodiments, the first electrode 144 of each memory device 114 is in electrical communication with (and in direct contact with) a horizontally adjacent access device 112. The first electrode 144 and the second electrode 146 may be individually formed of and include a conductive material. In some embodiments, one or more of the first electrode 144 and the second electrode 146 include titanium nitride. In some embodiments, the second electrode 146 includes a material composition substantially the same as that of the first electrode 144.

[0069] The second electrode 146 may be in electrical communication with one of the conductive plate structures 129 of the vertical stack of the memory cells 108. In some embodiments, the second electrode 146 is substantially integral with the conductive plate structure 129. In some embodiments, the horizontally adjacent (e.g., in the X direction) vertical stacks of the second electrodes 146 of the memory devices 114 are in electrical communication with the same conductive plate structure 129.

[0070] Continuing to refer to Figure 1A and 1B , the first conductive structure 120 within the array region 102 of the vertical stack structure 122 may be coupled to the second conductive structure 140 (also referred to herein as "second conductive line", "second access line", or "second word line") within the stepped region 104. The second conductive structure 140 of the vertical stack structure 122 may vertically overlie (e.g., in the Z direction) the substrate structure 110 and be located within the horizontal boundaries (e.g., in the X direction, in the Y direction) of the stepped region 104. Each of the first conductive structures 120 may be individually coupled to one of the second conductive structures 140.

[0071] The second conductive structure 140 may physically contact the first conductive structure 120 along a vertical interface that coincides with the horizontal boundary between the stepped region 104 and the array region 102. The first conductive structure 120 and the second conductive structure 140 at each vertical level individually exhibit substantially the same vertical position (e.g., in the Z direction) relative to each other. In addition, the upper surfaces of the first conductive structure 120 and the second conductive structure 140 at each vertical level may be substantially coplanar with each other, and the lower surfaces of the first conductive structure 120 and the second conductive structure 140 at each vertical level may be substantially coplanar with each other. The levels of the vertical spacing (e.g., in the Z direction) of the conductive structures of the vertical stack structure 122 may include a first portion (e.g., the first conductive structure 120) within the array region 102 and a second portion (e.g., the second conductive structure 140) within the stepped region 104. For the sake of clear and easy understanding of the drawings and the associated description, the second conductive structure 140 is distinguished from the first conductive structure 120 by its position (e.g., within the stepped region 104 and the array region 102, respectively). In other embodiments, for example, when the first conductive structure 120 is configured as a digital line and the conductive post structure 126 is configured as an access line, the second conductive structure 140 is configured as a digital line (e.g., a horizontal digital line).

[0072] The second conductive structure 140 may be formed of and include the conductive material, which is one or more of the materials described above with reference to the first conductive structure 120. The first conductive structure 120 and the second conductive structure 140 may include substantially the same material composition, with no easily distinguishable physical interface therebetween. In addition, the second conductive structure 140 may be substantially continuous with the first conductive structure 120 at each vertical level of the vertical stack structure 122 and may be formed during the formation of the first conductive structure 120 (e.g., substantially simultaneously). By forming the second conductive structure 140 during the formation of the first conductive structure 120, the manufacturing cost can be reduced. Alternatively, the second conductive structure 140 and the first conductive structure 120 may include different material compositions from each other, such that the material composition of the second conductive structure 140 is different from that of the first conductive structure 120.

[0073] Since more than one (e.g., two) of the stepped regions 104 may be horizontally adjacent to the array region 102 in the first horizontal direction (e.g., on its two opposite sides), the second conductive structure 140 may be horizontally adjacent to the first conductive structure 120 on its two opposite sides. In other embodiments, for example, when a single stepped region 104 is horizontally adjacent to the array region 102 in the first horizontal direction, the second conductive structure 140 may be horizontally adjacent to the first conductive structure 120 on only one of its sides.

[0074] The second conductive structure 140 may exhibit a different configuration (e.g., one or more different sizes and / or one or more different shapes) from the first conductive structure 120. For example, the first conductive structure 120 may individually exhibit a rectangular prism shape having a generally rectangular horizontal cross-section (e.g., generally linear) shape extending in the X direction. The portion of the second conductive structure 140 that is close to the horizontal boundary of the array region 102 (e.g., close to the vertical interface with the first conductive structure 120) may also exhibit a rectangular prism shape having a generally rectangular horizontal cross-section shape that generally extends linearly in the X direction. An additional portion of the second conductive structure 140 that is remote from the horizontal boundary of the array region 102 (e.g., remote from the first conductive structure 120) may individually exhibit at least a partially non-rectangular horizontal cross-section shape that extends along a non-linear horizontal path. For example, the second conductive structure 140 may individually include: a first portion that extends in a first horizontal direction (e.g., the X direction); and a second portion that is horizontally adjacent to the first portion and extends in a second horizontal direction (e.g., the Y direction), as described in further detail below.

[0075] The second conductive structure 140 may horizontally (e.g., in the X direction, in the Y direction) terminate at a step structure 130 that is located at the horizontal terminal portion of the vertical stack structure 122. The step structure 130 may be located within the step region 104; and may individually exhibit one or more closed curve horizontal cross-section shapes. As Figure 1A shown, the step structure 130 of the microelectronic device structure 100 may be defined by at least a partially non-linear (e.g., curved, arcuate) horizontal boundary (e.g., horizontal end, horizontal edge) of the vertical stack structure 122. For example, the step structure 130 may exhibit at least a partially curved horizontal cross-section shape (e.g., closed curve horizontal cross-section shape) at its different vertical elevations, and may be spaced apart from each other in the X direction and in the Y direction. In some embodiments, the step structure 130 individually exhibits a partially curved horizontal cross-section shape (e.g., in the XY plane) that individually includes a combination of linear horizontal extension portions and non-linear (e.g., arcuate) horizontal extension portions at its different vertical elevations (e.g., in the Z direction).

[0076] In some embodiments, the stepped structure 130 of the vertical stack structure 122 is horizontally adjacent (e.g., in the X direction) to the array region 102. In some such embodiments, the vertical stack structure 122 includes two of the stepped regions 104 that contain the stepped structure 130. For example, the vertical stack structure 122 may include some of the stepped structures 130 within a first stepped region 104a at a first horizontal end (e.g., in the X direction) of the microelectronic device structure 100, and may include some other of the stepped structures 130 within a second stepped region 104b at a second horizontal end of the microelectronic device structure 100 that is opposite the first horizontal end (e.g., in the X direction). Thus, each vertical stack structure 122 may individually include: a stepped region 104 (e.g., the first stepped region 104a) that contains some of the stepped structures 130 at a first horizontal end of the vertical stack structure 122; and an additional stepped region 104 (e.g., the second stepped region 104b) that contains some other of the stepped structures 130 at a second opposite horizontal end of the vertical stack structure 122. Although Figure 1A shown is one stepped region 104 that contains the stepped structure 130 at each horizontal end (e.g., in the X direction) of the vertical stack structure 122, the present disclosure is not limited thereto. In other embodiments, the vertical stack structure 122 includes one stepped region 104 that contains the stepped structure 130 of each vertical stack structure 122 (e.g., the stepped structure 130 at only one horizontal (e.g., in the X direction) end of each vertical stack structure 122).

[0077] Continuing to refer to Figure 1A , within an individual stepped region 104, its stepped structures 130 may be arranged such that portions of at least some of the stepped structures 130 are horizontally adjacent to each other and horizontally overlap each other in a plurality of horizontal directions (e.g., the X direction and the Y direction). The stepped structures 130 of the stepped region 104 may be arranged, for example, in a woven pattern (e.g., a hexagonal pattern, such as a hexagonal close-packed pattern). In some embodiments, the stepped structures 130 are arranged relative to each other in a hexagonal pattern that exhibits a repeating horizontal arrangement of seven (7) stepped structures 130, where one (1) of the seven (7) stepped structures 130 is generally horizontally centered among the other six (6) of the seven (7) stepped structures 130. The hexagonal pattern may exhibit three (3) different axes of symmetry about the center of the horizontally centered stepped structure 130 among the seven (7) stepped structures 130 in the same transverse plane (e.g., the XY plane). Different axes of symmetry that are directly radially adjacent to each other may be radially separated from each other by an angle θ of about 60 degrees.

[0078] In some embodiments, the stepped structure 130 individually exhibits a maximum lateral dimension (e.g., maximum length) in a second horizontal direction (e.g., the Y direction) that is greater than another maximum lateral dimension (e.g., maximum width) in a first horizontal direction (e.g., the X direction). The stepped structure 130 may individually exhibit a partially curved horizontal cross-sectional shape (e.g., a closed-curve horizontal cross-sectional shape) derived from the closed-curve horizontal cross-sectional shape (e.g., an oval horizontal cross-sectional shape) of the initial stepped structure used to form the stepped structure 130, as described in further detail below with reference to Figures 2A to 2K Further detailed description. Additionally, different vertical elevations (e.g., in the Z direction) within an individual stepped structure 130 may exhibit generally the same horizontal cross-sectional shape (e.g., generally the same closed-curve horizontal cross-sectional shape, such as generally the same oval horizontal cross-sectional shape), or one or more different vertical elevations within an individual stepped structure 130 may exhibit horizontal cross-sectional shapes that are different from each other (e.g., different closed-curve horizontal cross-sectional shapes; at least one closed-curve horizontal cross-sectional shape and at least one open-curve horizontal cross-sectional shape).

[0079] Each of the stepped structures 130 may exhibit a geometric configuration that is generally the same as each other of the stepped structures 130 (e.g., generally the same dimensions, generally the same shape), or one or more of the stepped structures 130 may exhibit a geometric configuration that is different from one or more of the stepped structures 130 (e.g., one or more different dimensions, different shapes). Additionally, horizontally adjacent stepped structures 130 may all be horizontally separated from each other by generally the same distance, or two or more horizontally adjacent stepped structures 130 may be horizontally separated from each other by a distance that is different from the distance between two or more other horizontally adjacent stepped structures 130. In some embodiments, the size, shape, and spacing of the stepped structures 130 relative to each other are generally uniform (e.g., invariant, equal, consistent). In additional embodiments, at least some of the stepped structures 130 have one or more of a different size (e.g., different overall horizontal area), different shape, and different spacing from at least another of the stepped structures 130.

[0080] Additionally, each of the stepped regions 104 may exhibit a geometric configuration that is substantially the same as each other of the stepped regions 104 (e.g., substantially the same dimensions, substantially the same shape), or one or more of the stepped regions 104 may exhibit a geometric configuration that is different from one or more of the stepped regions 104 (e.g., one or more different dimensions, different shapes). In some embodiments, each of the stepped regions 104 has a horizontal area that is substantially the same as each other of the stepped regions 104. In additional embodiments, at least one of the stepped regions 104 has a horizontal area that is different from at least another of the stepped regions 104 (e.g., a smaller horizontal area, a larger horizontal area).

[0081] Collective reference Figure 1A and Figure 1C , the vertically higher (e.g., in the Z direction) second conductive structure 140 may have a smaller horizontal dimension (e.g., in the Y direction) than the vertically lower second conductive structure 140, such that the horizontal edges of the second conductive structure 140 partially define the steps 132 of the stepped structure 130. The vertically higher second conductive structure 140 may have a relatively smaller horizontal dimension (e.g., in the X direction) than the vertically lower second conductive structure 140. In some embodiments, the memory cells 108 in a vertical stack of memory cells 108 that are vertically higher (e.g., in the Z direction) than other memory cells 108 are intersected by a first conductive structure 120, which in turn is horizontally adjacent to a second conductive structure 140 that has a relatively smaller horizontal dimension (e.g., in the X direction, in the Y direction) than the second conductive structure 140 associated with the vertically lower memory cells 108 in the vertical stack of memory cells 108.

[0082] The relatively vertically higher second conductive structure 140 may also have a relatively smaller horizontal dimension in an additional horizontal direction that is angularly offset from each of the X and Y directions. The steps 132 of an individual vertical tier include a first portion extending in a first horizontal direction (e.g., the X direction), a second portion extending in a second horizontal direction (e.g., the Y direction), and a third portion between the first and second portions and extending at an acute angle relative to the first and second horizontal directions. In some embodiments, at least some of the steps 132 of an individual vertical tier include individual angled linear portions that are horizontally adjacent to each other to define a relatively large closed-curve horizontal cross-sectional shape of the individual steps 132 of the stepped structure 130. In other embodiments, at least some of the steps 132 of an individual vertical tier individually include at least one non-linear (e.g., generally arcuate) portion that defines a section of the closed-curve horizontal cross-sectional shape of the individual steps 132 of the stepped structure 130. In other embodiments, at least two horizontal portions (e.g., two halves) of an individual stepped structure 130 are vertically offset from each other such that a set of steps 132 within the horizontal region of one of the at least two horizontal portions vertically underlies an additional set of steps 132 within the horizontal region of an additional one of the at least two horizontal portions. When viewed from a top view, the stepped structure 130 may exhibit a closed-curve horizontal shape, but at least two horizontally offset portions may individually exhibit different at least partially curved horizontal cross-sectional shapes (e.g., another closed-curve horizontal cross-sectional shape, an open-curve horizontal cross-sectional shape).

[0083] Each stepped structure 130 may exhibit both a positive slope and a negative slope in each of the X and Y directions. In some such embodiments, e.g., when the stepped structure 130 exhibits an elliptical (e.g., annular) cross-sectional shape, each stepped structure 130 may exhibit both a positive slope and a negative slope in an additional direction (e.g., at an acute angle to each of the X and Y directions). In some embodiments, a dashed line extending from the top of one half of an individual stepped structure 130 to the bottom of the stepped structure 130 may have a positive slope on its first side, and another dashed line extending from the top of the other half of the stepped structure 130 to the bottom of the stepped structure 130 may have a negative slope on its second opposite side. In some embodiments, for an individual vertical cross-section of an individual stepped structure 130, the positive and negative slopes of the stepped structure 130 have magnitudes that are generally the same as each other, corresponding to the change in the vertical dimension (e.g., in the Z direction) of the stepped structure 130 divided by the change in the horizontal dimension (e.g., in the X direction, in the Y direction).

[0084] In some embodiments, the stepped structure 130 individually forms a stadium structure having steps 132 that are partially defined by the edges (e.g., horizontal ends) of the second conductive structures 140 of the vertical stack structure 122. In some such embodiments, multiple (e.g., more than one) of the stepped structures 130 may be formed to be positioned at generally the same elevation (e.g., vertical position) within the vertical stack structure 122. During the formation of the steps 132 of the stepped structure 130, an initial stepped structure (e.g., configured generally similar to the stepped structure 130) may be formed at an upper vertical position within the vertical stack structure 122 within the horizontal boundaries of the stepped region 104. The microelectronic device structure 100 may then undergo one or more additional material removal processes (e.g., one or more trimming processes) to increase one or more depths (e.g., in the Z direction) of the initial stepped structure relative to the upper surface of the vertical stack structure 122 and form the stepped structure 130, as described in further detail below.

[0085] One or more (e.g., two) of the second conductive structures 140 may be associated with one of the stepped structures 130. For example, one stepped structure 130 may be operatively associated with two of the second conductive structures 140. Additionally, each of the second conductive structures 140 may be associated with multiple (e.g., two or more) of the stepped structures 130. The second conductive structures 140 may individually extend horizontally on a multi-directional path (e.g., a non-linear horizontal path) that will be associated with more than one of the stepped structures 130. For example, the second conductive structures 140 may individually include a first portion that extends in a first horizontal direction and a second portion that is horizontally adjacent to the first portion and extends in a second horizontal direction. As Figure 1A shown, for an individual stepped structure 130, the first portion (e.g., the portion extending in the X direction) of the second conductive structure 140 that is operatively associated with the stepped structure 130 partially defines the first portion of the step 132 of the stepped structure 130, and the second portion (e.g., the portion extending in the Y direction) of the second conductive structure 140 that is operatively associated with the stepped structure 130 partially defines the second portion of the step 132 of the stepped structure 130.

[0086] As Figure 1CAs shown, individual stepped structures 130 include: a central portion 148 (e.g., its lowermost step 132), which is partially defined by a vertically lowermost second conductive structure 140; and a bridging member 150 (e.g., its uppermost step 132), which is partially defined by a vertically uppermost second conductive structure 140. In some embodiments, the bridging members 150 of adjacent stepped structures 130 physically contact (e.g., extend together) with each other, and the central portions 148 of adjacent stepped structures 130 are spaced apart from each other. An individual vertically uppermost second conductive structure 140 may partially define the uppermost steps 132 of a plurality (e.g., two, three, four) of adjacent stepped structures 130. Additional material of the vertical stack structure 122 at the vertical level of the vertically uppermost second conductive structure 140 may be inserted between the stepped structures 130 and may separate the stepped structures 130 from each other. The portion of the second conductive structure 140 that partially defines the uppermost step 132 of the stepped structure 130 includes a bridging member 150 (e.g., a bridging region) common to three or more of the stepped structures 130.

[0087] In some embodiments, portions of the stepped structures 130 of adjacent rows partially horizontally overlap with each other in a horizontal direction (e.g., the Y direction), and additional portions of the stepped structures 130 of adjacent columns partially horizontally overlap with each other in another horizontal direction (e.g., the X direction). Some of the steps 132 of the stepped structures 130 that are horizontally adjacent to each other (e.g., in the X direction, in the Y direction) may horizontally overlap with each other in one or more of the X direction and the Y direction. For example, a portion of the vertically highest (e.g., in the Z direction) step 132 of a first stepped structure 130 may be generally laterally aligned (e.g., in the X direction) with a portion of the vertically highest step 132 of a second stepped structure 130, and another portion of the vertically highest step 132 of the first stepped structure 130 may be generally laterally aligned (e.g., in the Y direction) with a portion of the vertically highest step 132 of a third stepped structure 130. In some such embodiments, in a manner generally the same as the vertically highest step 132, portions of additional steps 132 (e.g., the second vertically highest step 132, the third vertically highest step 132) horizontally overlap with each other in the X direction and in the Y direction. Portions of additional steps 132 (e.g., the vertically lowest step 132 (corresponding to the central portion 148), the second vertically lowest step 132) may not horizontally overlap with each other in the X direction and in the Y direction.

[0088] The number of steps 132 of an individual stepped structure 130 may correspond to the number of levels of the memory cells 108 associated with the individual stepped structure 130. Although Figures 1A to 1CThe stepped structure 130 is shown to individually include a specific quantity (e.g., five (5)) of steps 132, but the present disclosure is not limited thereto. In other embodiments, each of the stepped structures 130 individually includes a desired number of steps 132, such as in the range of from about four (4) steps 132 to about eight (8) steps 132. However, the present disclosure is not limited thereto, and additional configurations may be contemplated. In some such embodiments, each vertical stack of memory cells 108 of the microelectronic device structure 100 individually includes a corresponding number of memory cells 108 associated with the total number of steps 132 of each group of stepped structures 130. In other embodiments, each group of stepped structures 130 includes a different number of steps 132.

[0089] In some embodiments, each of the stepped structures 130 individually includes the same number of steps 132 as each other. In some embodiments, each step 132 of an individual stepped structure 130 has a step face that is vertically offset (e.g., in the Z direction) by one level (e.g., one layer 131) from the step face of the vertically adjacent step 132 of the stepped structure 130, the level including the second conductive structure 140, the dielectric material 128, and the second insulating material 124. In some such embodiments, each second conductive structure 140 of the vertical stack structure 122 partially defines the step face of the step 132 at each horizontal end (e.g., in the X direction) of the stepped structure 130 of the vertical stack structure 122.

[0090] In other embodiments, the step faces of vertically adjacent (e.g., in the Z direction) steps 132 of the stepped structure 130 on the first horizontal side (e.g., in the X direction) of the vertical stack structure 122 are vertically offset (e.g., in the Z direction) from each other by two levels (e.g., two layers 131), the two levels individually including the second conductive structure 140, the dielectric material 128, and the second insulating material 124. In some such embodiments, the step faces of the steps 132 of an individual stepped structure 130 are formed by portions of every other second conductive structure 140 of the vertical stack structure 122; and the step faces of the steps 132 of vertically adjacent stepped structures 130 that are different from each other at the horizontally opposite ends (e.g., in the X direction) of the same vertical stack structure 122 may be partially defined by second conductive structures 140 that are vertically spaced apart (e.g., in the Z direction) by one level, the one level including the second conductive structure 140, the dielectric material 128, and the second insulating material 124.

[0091] As Figure 1B and 1CAs shown, a third insulating material 134 may be formed to fill openings (e.g., valleys, spaces, gaps) that vertically overlie and are within a horizontal region of the stepped structure 130. In some embodiments, one or more insulating liner materials are inserted between the stepped structure 130 and the third insulating material 134. To enable clear and easy understanding of the figures and the associated description, the portion of the third insulating material 134 within the horizontal region of the stepped structure 130 is omitted from Figure 1B In some embodiments, the third insulating material 134 includes SiO x (e.g., SiO2). In additional embodiments, the third insulating material 134 includes at least one different dielectric material such as silicon oxycarbide (SiO x C y ), silicon oxynitride (SiO x N y ), silicon oxycarbide hydride (SiC x O y H z ), or silicon oxycarbonitride (SiO x C y N z ) or one or more of them.

[0092] A fourth insulating material 137 may be formed to vertically overlie (e.g., in the Z direction) the vertical stack structure 122. The fourth insulating material 137, which may act as a mask material, may also vertically overlie (e.g., in the Z direction) the third insulating material 134 that covers the stepped structure 130. The fourth insulating material 137 may include one or more of the materials described above with reference to the first insulating material 116 (e.g., SiO2).

[0093] Continuing to refer to Figures 1A to 1C , a conductive contact structure 142 may be formed to extend through the third insulating material 134 and the fourth insulating material 137. The conductive contact structure 142 may be in electrical communication with the second conductive structure 140 of the vertical stack structure 122 at the step 132 of the stepped structure 130. For example, the conductive contact structure 142 may physically contact (e.g., land on) a portion of the upper surface of the second conductive structure 140 that partially defines the step face of the step 132. The conductive contact structure 142 may be formed at a horizontal end (e.g., a lateral end) of the second conductive structure 140. The conductive contact structure 142 may individually exhibit a generally circular horizontal cross-sectional shape, as Figure 1Ashown in the top view thereof. However, the present disclosure is not limited thereto. As a non-limiting example, in additional embodiments, the conductive contact structures 142 individually exhibit a generally rectangular horizontal cross-sectional shape (e.g., a generally square horizontal cross-sectional shape), or a different elongated horizontal cross-sectional shape (e.g., an oval horizontal cross-sectional shape). For example, the conductive contact structures 142 may be elongated in a direction in which a portion of the second conductive structure 140 extends (e.g., in the Y direction), or alternatively in a direction in which a portion of the step 132 extends (e.g., in the X direction).

[0094] In some embodiments, each step 132 of the individual step structures 130 may be in physical contact with one or more (e.g., two (2)) of the conductive contact structures 142. In other embodiments, only every other step 132 of the individual step structures 130 includes one or more conductive contact structures 142 in physical contact therewith. In some such embodiments, a set of conductive contact structures 142 within the horizontal region of the first step region 104A is in physical contact with the second conductive structure 140 of a different individual vertical stack structure 122 than an additional set of conductive contact structures 142 within the horizontal region of the second step region 104B. In some embodiments, the configuration of a set of conductive contact structures 142 of the step structure 130 within the first step region 104a is different from the configuration of an additional set of conductive contact structures 142 of the step structure 130 within the second step region 104b. For example, the step structure 130 within the first step region 104a of the vertical stack structure 122 may have conductive contact structures 142 that land on portions of an even number of second conductive structures 140 that partially define the steps 132 of the step structure 130; and the additional step structure 130 within the second step region 104b may have conductive contact structures 142 that land on portions of an odd number of second conductive structures 140 that partially define the steps 132 of the additional step structure 130. In response to the relative positions of the conductive contact structures 142 on the steps 132, the step structure 130 of the vertical stack structure 122 at the first horizontal end (e.g., in the X direction) of the microelectronic device structure 100 may exhibit a first configuration, and the additional step structure 130 at the second opposite horizontal end may exhibit a second configuration that is different from the first configuration.

[0095] The conductive contact structures 142 may be individually formed of and include a conductive material, such as one or more of the materials described above with reference to the conductive pillar structures 126. In some embodiments, the conductive contact structures 142 include a material composition that is substantially the same as that of the conductive pillar structures 126. In other embodiments, the conductive contact structures 142 include a material composition that is different from that of the conductive pillar structures 126. In some embodiments, the conductive contact structures 142 include tungsten.

[0096] By forming a stepped structure 130 to individually present at least a portion of a curved horizontal cross-sectional shape (e.g., a closed curve horizontal cross-sectional shape), the steps 132 of the stepped structure 130 can be individually formed to have a relatively large horizontal cross-sectional area without undesirably increasing the total width (e.g., horizontal footprint) of the stepped region 104 of the microelectronic device structure 100. A relatively large number of conductive contact structures 142 can be formed within the stepped region 104, which can permit the vertical stacking of a relatively large number of memory cells 108 to be formed within the array region 102. Compared with a conventional microelectronic device structure, forming the microelectronic device structure 100 to include the stepped region 104 containing the stepped structure 130 of the present disclosure can facilitate reducing the horizontal area of the microelectronic device structure 100. Additionally, a second conductive structure 140 that horizontally extends on a multi-directional (e.g., non-linear) path can facilitate the efficient use of the area of the stepped region 104, such that the area allocated to the stepped structure 130 is reduced and the reliability of the microelectronic device structure 100 is improved.

[0097] Figures 2A to 2K To illustrate the simplified partial perspective view ( Figures 1A to 1C and 2F), simplified partial top view ( Figures 2A to 2D , Figure 2E , 2G , 2I and 2J), and simplified partial cross-sectional view ( Figure 2H and 2K ) of the method of forming the microelectronic device structure 100 described above according to an embodiment of the present disclosure. Figure 2J Shows Fig.2I a simplified top view of the region J depicted by the dashed box in Figures 2A to 2K . For the sake of clarity and ease of understanding of this specification,

[0098] Reference Figure 2A , the microelectronic device structure 100 can be formed to include a preliminary stacked structure 121 vertically overlying a substrate structure 110. The preliminary stacked structure 121 can include a vertical alternating (e.g., in the Z direction) sequence of insulating materials and sacrificial materials arranged in a preliminary layer 125. Each of the preliminary layers 125 of the preliminary stacked structure 121 can individually include a sacrificial material vertically adjacent (e.g., directly vertically adjacent) to an insulating material. Subsequently, a portion of the sacrificial material of the preliminary layer 125 of the preliminary stacked structure 121 can be replaced with a conductive material to form a second conductive structure 140 ( Figures 1A to 1C ), as described in further detail below with reference to Figure 2C . Additionally, a portion of the insulating material of the preliminary layer 125 of the preliminary stacked structure 121 can form a second insulating material 124 ( Figure 1B and 1C ), as described in further detail below. Additionally, the initial stack structure 121 may include different horizontal regions to be processed to form the array regions 102( Figure 2C ) and the stepped regions 104( Figure 1A ) described previously herein. Figure 1A ).

[0099] The sacrificial material of each of the initial layers 125 of the initial stack structure 121 may be formed of and include at least one material (e.g., at least one insulating material), and the at least one material may be selectively removed relative to the insulating material of the initial layers 125 of the initial stack structure 121. The sacrificial material may be selectively etchable relative to the insulating material during common (e.g., collective, mutual) exposure to a first etchant; and the insulating material may be selectively etchable relative to the sacrificial material during common exposure to a second, different etchant. As used herein, a material is "selectively etchable" relative to another material if the material exhibits an etch rate that is at least about five times (5×), e.g., about ten times (10×), about twenty times (20×), or about forty times (40×) greater than the etch rate of the other material. By way of non-limiting example, depending on the material composition of the insulating material, the sacrificial material may be formed of and include one or more of the following: at least one semiconductor material (e.g., silicon germanium (SiGe), polysilicon); at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x , NbO x , TiO x , ZrO x , TaO x , and MgO x ); at least one dielectric nitride material (e.g., SiN y ); at least one dielectric oxynitride material (e.g., SiO x N y ); at least one dielectric oxycarbide material (e.g., SiO x C y ); at least one hydrogenated dielectric oxycarbide material (e.g., SiC x O y H z ); at least one dielectric carbon oxynitride material (e.g., SiO x C z N y)。In some embodiments, the sacrificial material of each of the preliminary layers 125 of the preliminary stack structure 121 is formed of and comprises at least one semiconductive material that is suitable for use as the channel material of access devices 112 ( Figure 1A ) formed within the array region 102 of the microelectronic device structure 100 ( Figure 1A and 1B ). For example, the sacrificial material may be formed of and comprise SiGe, for example.

[0100] One or more material removal (e.g., patterning) processes may be used to form the stepped structure 130 ( Figure 1A ) of the microelectronic device structure 100. In some embodiments, the upper surface of the preliminary stack structure 121 is patterned to form an opening (e.g., a central opening) that includes an initial central portion 148', which may be used during the formation of the subsequently formed stepped structure 130 (see Figure 2B ). The initial central portion 148' of the opening may be formed, for example, by forming and patterning one or more mask materials over the microelectronic device structure 100 and exposing the microelectronic device structure 100 to a suitable etchant. By way of non-limiting example, the uppermost material of the preliminary stack structure 121 may be patterned (e.g., masked, exposed, developed, and etched) to form the initial central portion 148'.

[0101] As Figure 2A shown, the remaining portion of the uppermost material of the preliminary stack structure 121 may include a preliminary bridge 149. At the processing stage depicted in Figure 2A , the preliminary bridge 149 may include a single continuous portion of the uppermost material of the preliminary stack structure 121 that generally surrounds the individual initial central portions 148'. The initial central portions 148' may be discrete openings separated by the remaining portion of the uppermost material of the preliminary stack structure 121. Thus, the initial central portions 148' may be non-continuous and discrete from each other in each of the X and Y directions. For example, the remaining portion of the uppermost material of the preliminary stack structure 121 horizontally intervenes (e.g., in the X direction, in the Y direction) between the initial central portions 148'. Thus, at the processing stage of Figure 2A , the initial central portions 148' may be considered to be formed of and include a plurality of openings that are separated from each other by intervening portions of the preliminary bridge 149.

[0102] The initial central portion 148' may include oval (e.g., annular) openings that are separated from each other in the X direction and in the Y direction. The initial central portion 148' may be individually horizontally defined by a single closed curve shape. In some embodiments, the initial central portion 148' individually exhibits a lateral dimension (e.g., length) in a second horizontal direction (e.g., the Y direction) that is greater than another lateral dimension (e.g., width) in a first horizontal direction (e.g., the X direction). At least some (e.g., each) of the initial central portions 148' may exhibit a generally oval (e.g., oblong, ovoid) horizontal cross-sectional shape. In other embodiments, the initial central portion 148' may individually exhibit a generally annular horizontal cross-sectional shape or a different closed curve horizontal cross-sectional shape (e.g., a horizontal cross-sectional shape, a rhombus horizontal cross-sectional shape, a rectangular horizontal cross-sectional shape, a square horizontal cross-sectional shape, a triangular horizontal cross-sectional shape).

[0103] Continuing to refer Figure 2A , some of the initial central portions 148' may be aligned with each other (e.g., in the Y direction), and some of the initial central portions 148' may be offset from each other (e.g., in the Y direction). The initial central portions 148' may be arranged in a woven pattern (e.g., a hexagonal pattern, a hexagonal close-packed pattern), which may facilitate an increase in the density of the stepped structure 130 ( Figure 1A ) within the stepped region 104 ( Figure 1A ). The initial central portions 148' may be arranged in rows extending in a first horizontal direction (e.g., the X direction) and columns extending in a second horizontal direction (e.g., the Y direction). In some embodiments, each of the initial central portions 148' in an individual column may be generally horizontally offset (e.g., in each of the X direction and the Y direction) from each of the initial central portions 148' in a horizontally adjacent (e.g., in the X direction) column. Additionally, at least one odd-numbered column of the initial central portions 148' may include an initial central portion 148' that is generally horizontally aligned (e.g., in the Y direction) with an initial central portion 148' in at least one other odd-numbered column of the initial central portions 148'; and at least one even-numbered column of the initial central portions 148' may include an initial central portion 148' that is generally horizontally aligned (e.g., in the Y direction) with an initial central portion 148' in at least one other even-numbered column of the initial central portions 148'.

[0104] Similarly, each of the initial central portions 148' of an individual row may be substantially horizontally offset (e.g., in each of the X and Y directions) from each of the initial central portions 148' in a horizontally adjacent (e.g., in the Y direction) row. Additionally, the initial central portion 148' of at least one odd-numbered row may include an initial central portion 148' that is substantially horizontally aligned (e.g., in the X direction) with the initial central portion 148' in at least one other odd-numbered row; and the initial central portion 148' of at least one even-numbered row may include an initial central portion 148' that is substantially horizontally aligned (e.g., in the X direction) with the initial central portion 148' in at least one other even-numbered row. Accordingly, the initial central portions 148' may be horizontally staggered from each other (e.g., offset from each other in each of the X and Y directions). However, the present disclosure is not limited thereto, and the initial central portions 148' may be arranged in other patterns (e.g., arranged in rows, where the initial central portion 148' of each row is aligned with the initial central portion 148' of each of the other rows). In some embodiments, each initial central portion 148' may be surrounded by six (6) other initial central portions 148' and may be arranged in a hexagonal pattern.

[0105] Each individual opening in the initial central portion 148' may have a substantially the same size (e.g., lateral dimension) and may be regularly spaced apart by a substantially the same distance. Accordingly, the pitch between the initial central portions 148' may be substantially uniform throughout the preliminary stack structure 121. The size and spacing of the initial central portions 148' may be selected to provide the desired lateral dimensions and lateral spacing for features subsequently formed in the microelectronic device structure 100, as described below.

[0106] Reference Figure 2B , after the initial central portions 148' ( Figure 2A ) are formed, the initial stepped structure 130' may be individually formed to include initial steps 132', where the initial steps 132' include the edges (e.g., multi-directional horizontal ends) of the preliminary layer 125 of the preliminary stack structure 121 (including its sacrificial material and insulating material). The initial stepped structure 130' includes a stepped cross-sectional profile in each of the ZX and ZY planes, as shown in the perspective view of Figure 2B . The stepped cross-sectional profile of the initial stepped structure 130' may be defined by the geometric configuration of the initial steps 132' of the initial stepped structure 130'. For the sake of clarity and ease of understanding of this specification, Figure 2B only a specific number (e.g., five (5)) of the initial steps 132' in the initial stepped structure 130' are shown; however, it should be understood that the initial stepped structure 130' may include a smaller or alternatively larger number of initial steps 132' than shown.

[0107] During the formation of the initial stepped structure 130', a portion of one or more mask materials may be patterned to develop an opening in the mask material and expose a portion of the uppermost preliminary layer 125 of the preliminary stack structure 121. For example, the opening in the mask material for forming the initial central portion 148' ( Figure 2A ) may be developed (e.g., in each of the X and Y directions, in an oval pattern) to form an enlarged opening. The uppermost preliminary layer 125 and another preliminary layer 125 (e.g., vertically below the uppermost preliminary layer 125) may be exposed to an etching chemical through the opening to remove the portion of the uppermost preliminary layer 125 exposed through the opening, and to remove the portion of another preliminary layer 125 (e.g., the second preliminary layer 125) at the location of the initial central portion 148'.

[0108] After removing the exposed portions of the uppermost preliminary layer 125 and another preliminary layer 125 through the opening, the mask material may be exposed to an etching chemical to remove (e.g., trim) an additional portion of the mask material and expose an additional portion of the uppermost preliminary layer 125 corresponding to the desired width (in the X direction) and desired length (in the Y direction) of the initial step 132' of the initial stepped structure 130' to be formed. After exposing the additional portion of the uppermost preliminary layer 125, the preliminary stack structure 121 is exposed to an etching chemical to remove the portion of the uppermost preliminary layer 125 and to remove the portion of an additional preliminary layer 125 (e.g., the second preliminary layer 125, the third preliminary layer 125) through the enlarged opening in the mask material, and to form an additional initial step 132'.

[0109] The process of trimming the masking material and etching the preliminary layer 125 can be repeated the desired number of times to form an initial stepped structure 130' (e.g., an oval stadium-like structure). Trimming the masking material and etching the preliminary layer 125 can be performed in a manner that radiates (e.g., diverges) laterally outward from the central portion 148 during the formation of the initial steps 132'. By sequentially trimming the masking material and etching the preliminary layer 125 each time, the central portion 148 of the initial stepped structure 130' can be recessed vertically relative to the surrounding initial steps 132', such that the central portion 148 serves as the lowermost initial step 132' of each of the initial stepped structures 130', and the surrounding initial steps 132' gradually rise vertically relative to the central portion 148. Thus, the lowermost preliminary layer 125 exposed during the formation of the initial stepped structure 130' is configured as its central portion 148, and as the initial steps 132' extend laterally outward from the central portion 148 of the preliminary bridging member 149, the initial steps 132' that laterally surround the central portion 148 continuously increase in vertical position. Thus, due to the material removal process for forming the initial stepped structure 130', the central portion 148 of the initial stepped structure 130' can be located at a position corresponding to the position of the initial central portion 148' ( Figure 2A ).

[0110] Continuing to refer to Figure 2B , each initial stepped structure 130' can exhibit both positive and negative slopes in each of the X and Y directions. In some such embodiments, e.g., when the initial stepped structure 130' exhibits an oval (e.g., circular ring-shaped) horizontal cross-sectional shape, each initial stepped structure 130' exhibits both positive and negative slopes in an additional direction (e.g., at an acute angle to each of the X and Y directions). As used herein, the term "oval" means and includes a plane curve that surrounds two foci such that for all points on the curve, the sum of the two distances to the foci is constant. Thus, the term oval generically refers to a circle, which is a special type of oval where the two foci are the same. As used herein, the term "oval" means and includes features (e.g., materials, regions, structures) having an oval shape. Due to the initial central portion 148' ( Figure 2A) includes openings having a closed-curve horizontal cross-sectional shape (e.g., an oval horizontal cross-sectional shape), the openings being separated from each other in the X direction and in the Y direction, so that the initial steps 132' of the initial stepped structure 130' extend from its central portion 148 in more than one direction. The initial layers 125 of the preliminary stack structure 121 may undergo a material removal process to expand (e.g., increase) the horizontal dimensions of the openings of the initial central portion 148' in each of the X direction and the Y direction and in all horizontal directions therebetween. Thus, the different vertical levels within the individual initial stepped structures 130' can be individually formed to exhibit a closed-curve horizontal cross-sectional shape (e.g., an oval horizontal cross-sectional shape), where the relatively vertically lower portions of the initial stepped structure 130' have a relatively smaller horizontal cross-sectional area than the relatively vertically higher portions of the initial stepped structure 130'.

[0111] In some embodiments, the initial steps 132' of the initial stepped structure 130' individually include linear portions 133. Each linear portion 133 can separate two adjacent linear portions 133. For example, the individual angled portions of the initial steps 132' can be substantially linear and are arranged horizontally adjacent to each other at an acute angle in the X direction and in the Y direction and with respect to each of the X direction and the Y horizontal directions, and form a closed-curve horizontal cross-sectional shape (e.g., a substantially oval horizontal cross-sectional shape). The initial steps 132' can individually include substantially linear portions that intersect each other at intersections and are separated by steep transition regions therebetween. The linear portions 133 of the individual initial steps 132' can respond to the formation of the individual angled linear portions in the openings of the mask material for forming the initial steps 132'. In other embodiments, the initial steps 132' of the initial stepped structure 130' individually include arcuate portions 135. The initial steps 132' can individually include a single closed-curve-shaped horizontal boundary such that the individual initial steps 132' have a closed-curve horizontal cross-sectional shape. The arcuate portions 135 of the individual initial steps 132' can respond to the formation of the arcuate portions in the openings of the mask material for forming the initial steps 132'.

[0112] In response to the braided pattern of the initial central portion 148'( Figure 2A ), some of the initial stepped structures 130' can be aligned with each other (e.g., in the Y direction), and some of the initial stepped structures 130' can be offset from each other (e.g., in the Y direction). The initial stepped structures 130' can be arranged in a braided pattern (e.g., a hexagonal pattern, such as a hexagonal close-packed pattern), which can facilitate the stepped region 104( Figure 1A) the density of the subsequently formed stepped structure therein increases. The initial stepped structure 130' can be arranged in rows extending in a first horizontal direction (e.g., the X direction) and columns extending in a second horizontal direction (e.g., the Y direction). In some embodiments, each of the initial stepped structures 130' in an individual column can be substantially horizontally offset (e.g., in each of the X and Y directions) from each of the initial stepped structures 130' in a horizontally adjacent (e.g., in the X direction) column. Additionally, at least one odd-numbered column of the initial stepped structures 130' can include an initial stepped structure 130' that is substantially horizontally aligned (e.g., in the Y direction) with an initial stepped structure 130' in at least one other odd-numbered column; and at least one even-numbered column of the initial stepped structures 130' can include an initial stepped structure 130' that is substantially horizontally aligned (e.g., in the Y direction) with an initial stepped structure 130' in at least one other even-numbered column.

[0113] Similarly, each of the initial stepped structures 130' in an individual row can be substantially horizontally offset (e.g., in each of the X and Y directions) from each of the initial stepped structures 130' in a horizontally adjacent (e.g., in the Y direction) row. Additionally, at least one odd-numbered row of the initial stepped structures 130' can include an initial stepped structure 130' that is substantially horizontally aligned (e.g., in the X direction) with an initial stepped structure 130' in at least one other odd-numbered row; and at least one even-numbered row of the initial stepped structures 130' can include an initial stepped structure 130' that is substantially horizontally aligned (e.g., in the X direction) with an initial stepped structure 130' in at least one other even-numbered row. Thus, the initial stepped structures 130' can be horizontally staggered from each other (e.g., offset from each other in each of the X and Y directions). However, the present disclosure is not limited thereto, and the initial stepped structures 130' can be arranged in other patterns (e.g., arranged in rows, where each row of the initial stepped structures 130' is aligned with each of the initial stepped structures 130' in other rows). In some embodiments, each of the initial stepped structures 130' is surrounded by six (6) other initial stepped structures 130' and can be arranged in a hexagonal pattern.

[0114] As Figure 2BAs shown, individual initial stepped structures 130' include an initial central portion 148' partially defined by the lowermost preliminary layer 125 exposed during the formation of the initial stepped structure 130' and a preliminary bridging member 149 partially defined by the uppermost preliminary layer 125. Additionally, the portion of the uppermost preliminary layer 125 that defines the uppermost initial step 132' of the initial stepped structure 130' can be common (e.g., shared) among a plurality (e.g., two, three, four) of adjacent initial stepped structures 130'. Thus, the remaining portion of the uppermost preliminary layer 125 separates adjacent initial stepped structures 130' from each other. In some embodiments, at least some of the preliminary bridging members 149 are individually defined by four (4) of the adjacent initial stepped structures 130', e.g., within the central portion of the stepped region 104( Figure 1A ), and are defined by two (2) or three (3) of the initial stepped structures 130', e.g., proximate the peripheral edge of the stepped region 104.

[0115] In some embodiments, portions of the initial stepped structures 130' (e.g., in the X direction, in the Y direction) overlap horizontally with each other, as described above. In some embodiments, one or more of the upper initial steps 132' of an individual initial stepped structure 130' (e.g., the first initial step 132', the second initial step 132' of the preliminary bridging member 149) overlap horizontally with one or more of the upper initial steps 132' of another initial stepped structure 130'. For example, one or more of the upper initial steps 132' of a first initial stepped structure 130' can overlap horizontally with additional upper initial steps 132' of a second initial stepped structure 130' that is horizontally adjacent to the first initial stepped structure 130'. In some embodiments, at least a portion (e.g., the central portion 148) of an individual initial stepped structure 130' does not overlap horizontally with at least a portion of an adjacent initial stepped structure 130'. For example, the central portions 148 of adjacent initial stepped structures 130' can be horizontally offset from each other (e.g., in each of the X and Y directions).

[0116] Next referring to Figure 2C , at least one additional material removal process (e.g., a trimming process) can be performed to at least partially shift the vertical elevation of at least some of the initial stepped structures 130'( Figure 2B ) and form the stepped structures 130 (including steps 132) described previously with reference to Figures 1A to 1C . For example, at least some portions of an individual initial stepped structure 130' can extend vertically deeper (e.g., in the Z direction) relative to at least some portions of the initial stepped structure 130' and relative to at least some portions of some others of the initial stepped structures 130' into the preliminary stack structure 121( Figure 2B) Additionally, trenches (e.g., slots, slits) may be formed to extend vertically through the preliminary stack structure 121, and the preliminary stack structure 121 may undergo a so-called replacement gate process to form a vertical stack structure 122 that includes a vertical alternating sequence of a second conductive structure 140 and a second insulating material 124. The replacement gate process may replace a portion of the sacrificial material of the preliminary layer 125 ( Figure 2B ) of the preliminary stack structure 121 ( Figure 2B ) with a conductive material to form the second conductive structure 140, as described in further detail below. Additionally, a conductive contact structure 142 may be formed to contact the second conductive structure 140 at the step 132 of the stepped structure 130, also described in further detail below.

[0117] An additional material removal process (e.g., one or more trimming processes) may increase the at least some portions of some of the stepped structures 130 relative to the upper surface of the preliminary stack structure 121 ( Figure 2B ) by one or more depths (e.g., in the Z direction) to at least partially reposition one or more portions of some of the stepped structures 130 at various (e.g., gradually decreasing) levels 152 (e.g., vertical elevations), as Figure 2C shown. The additional material removal process may allow the lower boundaries of some of the stepped structures 130 to be positioned closer to the lower boundary of the vertical stack structure 122 than some of the other stepped structures 130. Additional portions of the stepped structure 130 may be positioned proximal to the upper boundary of the vertical stack structure 122 (e.g., at the uppermost level 152), and other portions of the stepped structure 130 may be positioned at various levels 152 between the lowermost level 152 and the uppermost level 152. The stepped structure 130 may be individually located on one or more (e.g., two, three) of the levels 152 that include a stepped cross-sectional profile in the ZX plane, as Figure 2C shown.

[0118] In some embodiments, the exposed side surface 154 of the level 152 that defines the vertical stack structure 122 formed by the preliminary stack structure 121 ( Figure 2B ) includes a generally linear elongated portion that vertically overlies at least some of the steps 132 of the stepped structure 130 that are at least partially within vertically adjacent levels 152. In some such embodiments, at least one material removal process (e.g., at least one trimming process) is used to form the level 152 to terminate vertically below the position of the initial stepped structure 130' ( Figure 2B ) and to form the stepped structure 130 at the level 152. In some embodiments, the level 152 is formed to vary in the first horizontal direction (e.g., the X direction) from the array region 102 ( Figure 1A) decreases as the distance increases, and the elongated portion of the layer 152 extends in the second horizontal direction (e.g., the Y direction). The elongated portion of the layer 152 extends in a direction transverse to the direction in which the first conductive structure 120 ( Figure 1A ) extends through the array region 102. Additionally, the elongated portion of the stepped structure 130 may be generally parallel to the elongated portion of the layer 152 in the Y direction. Since the stepped structure 130 is located on one or more of the layers 152 and includes portions of the steps 132 that extend in the X direction and additional portions of the steps 132 that extend in the Y direction, the vertical height of the vertical stack structure 122 decreases along the first horizontal direction and along the second horizontal direction.

[0119] In some embodiments, the different horizontal portions of the individual stepped structures 130 are formed to be vertically offset from each other so as to span multiple individual layers 152. The different horizontal portions of the stepped structure 130 may be located within different layers 152 of the vertical stack structure 122, as Figure 2C shown. For example, the different horizontal portions of the individual stepped structures 130 may be vertically offset (e.g., vertically segmented) the individual layers 152 at the location of their uppermost step 132 (e.g., the bridging member 150), or alternatively at the location of their lowermost step 132 (e.g., the central portion 148). In some embodiments, the different horizontal portions of the individual stepped structures 130 are vertically offset one or more individual layers 152 at the location of their second step 132 (e.g., the uppermost step 132 adjacent to the bridging member 150). In other embodiments, the different horizontal portions of the individual stepped structures 130 are vertically offset one or more individual layers 152 at the location of their uppermost step 132, and all other steps 132 below the uppermost step 132 are generally continuous, but other configurations are contemplated. Since the elongated portion of the stepped structure 130 is generally parallel to the elongated portion of the layer 152 in the Y direction, the steps 132 that extend in the X direction are not segmented by the layer 152. Thus, the stepped structure 130 may exhibit a staggered (e.g., decreasing) slope among two or more of the layers 152.

[0120] Continuing to refer to Figure 2C , after forming the stepped structure 130 (including its steps 132) and the layers 152 within the preliminary stack structure 121 ( Figure 2B ), a third insulating material 134 ( Figure 1B and 1C ) may be formed above the steps 132 of the stepped structure 130, and a fourth insulating material 137 ( Figure 1B and 1C ) may be formed above the third insulating material 134. Thereafter, slots (e.g., slits, trenches) may be formed to extend vertically through the fourth insulating material 137 ( Figure 1Band 1C ) and a third insulating material 134( Figure 1B and 1C ) and a preliminary stack structure 121( Figure 2B ) where a portion of the sacrificial material of the preliminary layer 125( Figure 2B ) of the preliminary stack structure 121( Figure 2B ) can be selectively excavated through the slot, and then a dielectric material 128( Figure 1B and 1C ) and a second conductive structure 140(and a first conductive structure 120( Figure 1A and 1B )) can be formed within the resulting groove (e.g., void space) within the sacrificial material to form a vertical stack structure 122(including its layer 131, previously referenced herein Figure 1B and 1C ). Thereafter, the slot can be filled with an insulating material to form an isolation structure 158( Fig.2I ) therein.

[0121] The slot formed within the preliminary stack structure 121( Figure 2B ) can have a geometric configuration and a horizontal position corresponding to the geometric configuration and the horizontal position of the isolation structure 158( Fig.2I ) further described in detail below with reference to Fig.2I . The configuration and position of the slot can facilitate a multi-directional horizontal path of the second conductive structure 140 formed by means of replacement gate processing using the slot. The horizontal path and geometric configuration of the second conductive structure 140 are further described in detail below with reference to Figures 2D to 2J . After forming the slot within the preliminary stack structure 121( Figure 2B ), the replacement gate processing can include treating the portion of the preliminary stack structure 121 exposed within the slot with at least one wet etchant formulated to selectively remove a portion of the sacrificial material of the preliminary layer 125( Figure 2B ) of the preliminary stack structure 121 through the slot. The wet etchant can be selected to remove a portion of the sacrificial material while substantially not removing the portion of the sacrificial material of the preliminary layer 125 of the preliminary stack structure 121. The remaining portion of the insulating material of the preliminary layer 125 of the preliminary stack structure 121 can form the second insulating material 124( Figure 1B and 1C ) of the layer 131 of the vertical stack structure 122. Where the sacrificial material includes a semi-conductive material (e.g., SiGe) and an insulating material and includes a dielectric oxide material (e.g., SiO x, in some embodiments, such as SiO2), a wet etchant including tetramethylammonium hydroxide (TMAH) is used to selectively remove a portion of the sacrificial material close to the slot. After selectively removing the portion of the sacrificial material, the resulting groove can be filled with an insulating material and a conductive material to form a dielectric material 128, a second conductive structure 140, and a first conductive structure 120( Figure 1A and 1B ). The second conductive structure 140 and the first conductive structure 120 can be formed substantially simultaneously with each other by replacement gate processing.

[0122] After forming the vertical stack structure 122, a conductive contact structure 142 can be formed in a contact opening that is formed to extend through a third insulating material 134 and a fourth insulating material 137. For example, portions of each of the third insulating material 134 and the fourth insulating material 137 can be selectively removed, and a conductive material can be formed (e.g., delivered, deposited) within the contact opening to form the conductive contact structure 142. The conductive contact structure 142 can be formed to contact (e.g., physically contact, electrically contact) an individual second conductive structure 140 of a layer 131 of the vertical stack structure 122 at a step 132 of the stepped structure 130. For example, the conductive contact structure 142 can individually physically contact at least a portion of an upper surface of the second conductive structure 140 that defines a step face of the step 132 (e.g., land on the portion). To enable clear and easy understanding of the figures and the associated description, Figure 2C the surrounding materials including the third insulating material 134 and the fourth insulating material 137 are omitted in the

[0123] As described above, the stepped structure 130 can individually exhibit one or more closed curve horizontal cross-sectional shapes. As used herein, the term "closed curve horizontal cross-sectional shape" means and includes a horizontal cross-sectional shape having a horizontal boundary defined by a curve that has no endpoints and completely encloses a horizontal region. The curve can include arcuate (e.g., non-linear) portions and / or linear (e.g., non-arcuate) portions. A feature (e.g., structure, material, region) having a closed curve horizontal cross-sectional shape can have a horizontal boundary at least partially defined by a horizontal boundary of one or more additional features (e.g., structure, material, region) that interact with the feature within the horizontal plane (e.g., XY plane) of the closed curve horizontal cross-sectional shape. For example, at a particular vertical elevation, an individual stepped structure 130 can have a closed curve horizontal cross-sectional shape defined by a curve that has a horizontal end (e.g., side surface) of the vertical stack structure 122 and an isolation structure 158( Fig.2I) The portion defined by the horizontal ends (e.g., side surfaces) of one or more of them. The feature may exhibit a single (e.g., only one) closed curve horizontal cross-sectional shape at its different vertical elevations, and / or may exhibit multiple (e.g., more than one) different closed curve horizontal cross-sectional shapes at its different vertical elevations.

[0124] Since the stepped structure 130 can individually exhibit a closed curve horizontal cross-sectional shape (e.g., an oval horizontal cross-sectional shape), its steps 132 can be defined by at least partially non-linear (e.g., arcuate) horizontal ends of the layers 131 of the vertically stacked structure 122. An individual stepped structure 130 can be formed to span a full angle (e.g., an angle of 360 degrees) from the vertical centerline of its central portion 148. Thus, for an individual stepped structure 130, its steps 132 individually include a first portion 132a extending in a first horizontal direction (e.g., the X direction), a second portion 132b extending in a second horizontal direction (e.g., the Y direction), and a third portion 132c located between the first portion 132a and the second portion 132b and extending at an acute angle with respect to the first horizontal direction and the second horizontal direction.

[0125] The conductive contact structures 142 can be arranged in rows extending in the second horizontal direction (e.g., the Y direction). Individual rows of conductive contact structures 142 can be generally parallel to each other, as described below. In some embodiments, the conductive contact structures 142 are arranged in rows on the portion of the step 132 extending in the X direction (e.g., the first portion 132a of the step 132), rather than on the portion of the step 132 extending in the Y direction (e.g., the second portion 132b of the step 132). Individual rows of conductive contact structures 142 can extend in the Y direction and not in the X direction, but other configurations can be considered as long as the conductive contact structures 142 at a single step 132 are individually associated with only one of the second conductive structures 140. Since the elongated portion of the stepped structure 130 is generally parallel to the elongated portion of the layer 152 in the Y direction and the step 132 extending in the X direction is not segmented by the layer 152, the individual rows of conductive contact structures 142 are not segmented by the layer 152. Thus, an individual row of conductive contact structures 142 can be located within a single layer 152.

[0126] Although Figure 2CSome specific number of conductive contact structures 142 aligned within the stepped structure 130 are shown, but it should be understood that the number of conductive contact structures 142 is shown for illustrative purposes only, and the microelectronic device structure 100 may include additional rows of conductive contact structures 142 within additional stepped structures 130 at level 152. For example, adjacent stepped structures 130 may also include multiple rows of conductive contact structures 142, and the stepped structure 130 may individually include more than one row (e.g., two rows) of conductive contact structures 142, as described in further detail below.

[0127] Reference Figure 2D And as previously described, the vertical stack structure 122 within the stepped region 104 ( Figure 1A ) may include a second conductive structure 140 that vertically overlies (e.g., in the Z direction) the substrate structure 110 and is within the horizontal boundaries of each other (e.g., in the X direction, in the Y direction). The vertical stack structure 122 includes levels of second conductive structures 140 that are vertically spaced apart from each other (e.g., in the Z direction). To enable a clear and easy understanding of the figures and the associated description, Figure 2D the surrounding materials including vertically intervening insulating materials (e.g., dielectric material 128, second insulating material 124) are omitted in Figure 2D . As shown in the perspective view of

[0128] the second conductive structure 140 may be individually formed to exhibit a multi-directional (e.g., non-linear) horizontal path. For example, the second conductive structure 140 may individually include a first portion extending in a first horizontal direction (e.g., the X direction) and a second portion horizontally adjacent to the first portion and extending in a second horizontal direction (e.g., the Y direction). Figure 1A ) in the array region 102 ( Figure 1A ) may be greater than the horizontal region of the relatively vertically higher second conductive structure 140. An individual second conductive structure 140 positioned relatively farther vertically from the substrate structure 110 may exhibit a smaller horizontal region than another individual second conductive structure 140 positioned relatively closer vertically to the substrate structure 110. In some embodiments, the steps 132 of the stepped structure 130 vertically descend (e.g., in the Z direction) in a second horizontal direction that is generally transverse to the direction in which the first conductive structure 120 (

[0129] Next, reference is made to Figure 2E, the multi-directional horizontal paths exhibited by the second conductive structure 140, in combination with the woven pattern of the stepped structure 130, can separate (e.g., physically separate) the conductive contact structures 142 ( Figure 2D ) from each other by one or more desired distances. Figure 2E An enlarged portion of the multi-directional path of the second conductive structure 140 is shown in image A of Figure 2E , an enlarged portion of the woven pattern of the stepped structure 130 is shown in image B, and a combination of the enlarged portions of the multi-directional paths of the second conductive structure 140 and the stepped structure 130 is shown in image C. To enable clear and easy understanding of the drawings and the associated description, the surrounding material including the additional material of the vertical stack structure 122 is omitted in the top views of images A, B, and C of

[0130] As Figure 2E shown in image A of Fig.2I , the second conductive structure 140 may individually include a first portion 140a extending in a first horizontal direction (e.g., the X direction) and a second portion 140b horizontally adjacent to the first portion 140a and extending in a second horizontal direction (e.g., the Y direction). The first portion 140a and the second portion 140b of the second conductive structure 140 may generally cross each other (e.g., perpendicularly). In some embodiments, the second conductive structure 140 includes generally linear portions that intersect each other at an intersection 141 and are separated by a steep transition therebetween. The second portion 140b may be integral and continuous with the first portion 140a. Thus, the first portion 140a and the second portion 140b of the second conductive structure 140 may together form a continuous portion of a non-linear structure that has sharp corners at the intersections 141 between the individual linear portions. In some embodiments, each of the first portion 140a and the second portion 140b of the second conductive structure 140 includes a generally equal length. In additional embodiments, optionally, some of the first portion 140a of the second conductive structure 140 includes arcuate (e.g., non-linear) portions, as described in more detail below with reference to Fig.2I .

[0131] As Figure 2E shown in image B of Figure 2EImages B and C show that the stepped structure 130 individually includes a specific number (e.g., three (3)) of steps 132, but for illustrative purposes, the stepped structure 130 may individually include additional steps 132.

[0132] In Figure 2E Image C of, for illustrative purposes, the braided pattern of the stepped structure 130 is shown overlapping the multi-directional path of the second conductive structure 140 of Image A. In Image C, for clarity, the second conductive structure 140 is shown in dashed lines to indicate the position of the second conductive structure 140 relative to the stepped structure 130, but it should be understood that the second conductive structure 140 is vertically segmented by the stepped structure 130 and the layer 152, as Figure 2D depicted in. Since the second conductive structure 140 includes generally linear portions (e.g., a first portion 140a, a second portion 140b) that intersect each other at the intersection 141, one or more (e.g., two) of the intersections 141 may be vertically aligned with the central portion 148 of at least some (e.g., each) of the stepped structure 130, and one or more (e.g., two) additional intersections 141 may be vertically aligned with the bridging member 150. Therefore, the multi-directional horizontal path exhibited by the second conductive structure 140 in combination with the braided pattern of the stepped structure 130 that exhibits a generally oval cross-sectional shape may facilitate the formation of the conductive contact structure 142 ( Figure 2D ), such that the individual conductive contact structures 142 at a single step 132 of the stepped structure 130 are individually associated with only one of the second conductive structures 140.

[0133] As described above, for clarity, in Figure 2E Image C of, one or more mask materials (e.g., mask material 156) shown in dashed lines may be used to form the layer 152 of the vertical stack structure 122 ( Figure 2D ), in order to show the position of the mask material 156 relative to the second conductive structure 140 and the stepped structure 130. In addition to forming the second conductive structure 140 that exhibits a multi-directional horizontal path and forming the stepped structure 130 in a braided pattern, forming the layer 152 may increase the separation between the conductive contact structures 142 ( Figure 2D ) by one or more desired distances (e.g., at different heights), while providing a larger cross-sectional area for the conductive contact structures 142 on the individual steps 132 of the stepped structure 130.

[0134] Figure 2F To show the association with Figure 2DA perspective view of a portion of the microelectronic device structure 100 similar to the view, a simplified perspective view, but including additional material of the vertical stack structure 122. For clarity, the position of the second conductive structure 140 is represented by the path 140' and shown in dashed lines to show the position of the second conductive structure 140 relative to the step 132 of the stepped structure 130 and the layer 152. Since the second conductive structure 140 individually exhibits a multi-directional (e.g., non-linear) horizontal path, the path 140' of the second conductive structure 140 shows the direction of a first portion 140a extending in a first horizontal direction (e.g., the X direction) and a second portion 140b horizontally adjacent to the first portion 140a and extending in a second horizontal direction (e.g., the Y direction). The first portions 140a of the second conductive structure 140 may be within the horizontal boundaries of each other (e.g., in the X direction), and the second portions 140b of the second conductive structure 140 may be within the horizontal boundaries of each other (e.g., in the Y direction). Additionally, in response to the layer 152 decreasing as the distance from the array region 102 increases, the path 140' may decrease as the distance from the array region 102 ( Figure 1A ) in the first horizontal direction (e.g., the X direction) increases.

[0135] As Figure 2F shown, different groups of the second conductive structure 140 may terminate (e.g., be truncated) at different side surfaces 154 of the vertical stack structure 122 created by the formation of the layer 152. For an individual group of the second conductive structure 140 terminating at an individual side surface 154 of an individual layer 152, an additional group of the second conductive structure 140 vertically below the group of the second conductive structure 140 may extend beyond the side surface 154 and at least partially define a step 132 of one of the stepped structures 130. The configuration of the second conductive structure 140 (e.g., extending together along the path 140') helps to form the conductive contact structures 142 ( Figure 2D ) arranged in rows extending in the second horizontal direction (e.g., the Y direction). The multi-directional (e.g., non-linear) horizontal path exhibited by the second conductive structure 140, in combination with the configuration (e.g., horizontal shape) and arrangement (e.g., woven pattern) of the stepped structure 130, may facilitate a larger number of conductive contact structures 142 being located within the stepped region 104 ( Figure 1A ) compared to a conventional configuration, which may permit a larger number of vertical stacks of memory cells 108 ( Figure 1A ) to be located within the array region 102 ( Figure 1A ) compared to a conventional configuration.

[0136] With common reference to Figure 2G and 2H , an enlarged view of the stepped region 104 ( Figure 1A ) including the stepped structure 130 is shown. Figure 2GA simplified partial top view of a portion of the microelectronic device structure 100, and Figure 2H A simplified partial cross-sectional view of a portion of the microelectronic device structure 100. For clarity and ease of understanding of this specification, Figure 2G and 2H the surrounding materials including the third insulating material 134 and the fourth insulating material 137 are omitted. Additionally, the dimensions of the materials and / or structures of the present disclosure may not reflect the presence of additional materials and / or structures. For example, for clarity, the segmentation performed within the individual stepped structures 130 by the isolation structure 158 ( Fig.2I ) is omitted.

[0137] As Figure 2G shown, the maximum horizontal dimension of the central portion 148 of the individual stepped structure 130 in the first horizontal direction may be relatively smaller than the other maximum horizontal dimension of the central portion 148 in the second horizontal direction. For example, the first dimension D1 (e.g., width) of the central portion 148 of the individual stepped structure 130 in the X direction may be in the range of about 180 nanometers (nm) to about 320 nm, such as about 180 nm to about 220 nm, about 220 nm to about 260 nm, or about 260 nm to about 320 nm; and the second dimension D2 (e.g., length) of its central portion 148 in the Y direction may be in the range of about 280 nm to about 420 nm, such as about 280 nm to about 320 nm, about 320 nm to about 360 nm, or about 360 nm to about 420 nm. However, the present disclosure is not limited thereto, and the first dimension D1 and / or the second dimension D2 may individually be different from the values described above. In some embodiments, the second dimension D2 is greater than the first dimension D1. In other embodiments, for example, when the individual stepped structure 130 exhibits a generally circular-ring-shaped horizontal cross-sectional shape, the second dimension D2 is substantially equal to the first dimension D1.

[0138] The stepped structures 130 may be horizontally spaced apart from each other substantially uniformly (e.g., evenly), for example, in the X direction or in the Y direction. In some embodiments, a third dimension D3 (e.g., pitch) between the stepped structures 130 horizontally adjacent to each other in the X direction may be in the range of about 1.5 micrometers (μm) to about 2.5 μm, such as about 1.5 μm to about 1.8 μm, about 1.8 μm to about 2.1 μm, or about 2.1 μm to about 2.5 μm. However, the present disclosure is not limited thereto, and the third dimension D3 may be different from the values described above. In some embodiments, a fourth dimension D4 (e.g., pitch) between the stepped structures 130 horizontally adjacent to each other in the Y direction may be in the range of about 1.7 μm to about 2.7 μm, such as about 1.7 μm to about 2 μm, about 2 μm to about 2.3 μm, or about 2.3 μm to about 2.7 μm. However, the present disclosure is not limited thereto, and the fourth dimension D4 may be different from the values described above. In some embodiments, the fourth dimension D4 is greater than the third dimension D3. In some embodiments, the fourth dimension D4 corresponds to the horizontal pitch (e.g., in the Y direction) between the first conductive structures 120 ( Figure 1A ) of the array regions 102 ( Figure 1A ) horizontally adjacent to each other in the Y direction.

[0139] In addition, a fifth dimension D5 (e.g., pitch) between the centerlines C L in the X direction of the stepped structures 130 in horizontally adjacent columns of the stepped structures 130 may be in the range of about 0.5 μm to about 1.5 μm, such as about 0.5 μm to about 0.8 μm, about 0.8 μm to about 1.1 μm, or about 1.1 μm to about 1.5 μm. However, the present disclosure is not limited thereto, and the fifth dimension D5 may be different from the values described above. Further, a sixth dimension D6 (e.g., width in the X direction, width in the Y direction) of the step surface of an individual step 132 of the stepped structure 130 may be in the range of about 50 nm to about 150 nm, such as about 50 nm to about 75 nm, about 75 nm to about 100 nm, about 100 nm to about 125 nm, or about 125 nm to about 150 nm. However, the present disclosure is not limited thereto, and the sixth dimension D6 may be different from the values described above.

[0140] As Figure 2HAs shown, the seventh dimension D7 (e.g., vertical height) of the individual steps 132 of the stepped structure 130 in the Z direction can be in the range of about 75 nm to about 225 nm, such as about 75 nm to about 100 nm, about 100 nm to about 125 nm, about 125 nm to about 150 nm, about 150 nm to about 175 nm, about 175 nm to about 200 nm, or about 200 nm to about 225 nm. However, the present disclosure is not limited thereto, and the seventh dimension D7 can be different from the values described above. In some embodiments, the seventh dimension D7 of the individual steps 132 is substantially equal to each of the other steps 132. The eighth dimension D8 (e.g., vertical height) of the individual tiers 152 of the vertically stacked structure 122 in the Z direction can be in the range of about 350 nm (e.g., about 0.35 μm) to about 1150 nm (e.g., about 1.15 μm), such as about 350 nm to about 550 nm, about 550 nm to about 750 nm, about 750 nm to about 950 nm, or about 950 nm to about 1150 nm. However, the present disclosure is not limited thereto, and the eighth dimension D8 can be different from the values described above. In addition, the ninth dimension D9 (e.g., width) of the individual tiers 152 of the vertically stacked structure 122 in the X direction can be in the range of about 0.5 μm to about 1.5 μm, such as about 0.5 μm to about 0.8 μm, about 0.8 μm to about 1.1 μm, or about 1.1 μm to about 1.5 μm. However, the present disclosure is not limited thereto, and the ninth dimension D9 can be different from the values described above. In some embodiments, the ninth dimension D9 corresponds to (e.g., is substantially equal to) the center line C of the stepped structure 130 that is horizontally adjacent (e.g., in the X direction) to the horizontally adjacent columns. L The fifth dimension D5 between them.

[0141] Reference Fig.2I , shows an enlarged portion of the array region 102 including the first conductive structure 120 (shown in dashed lines) and a stepped region 104 including the stepped structure 130 and the second conductive structure 140. For the sake of clarity and easy understanding of this specification, Fig.2I Other components of the microelectronic device structure 100 are not shown, such as the vertical stacking of the memory cells 108 within the array region 102. Additionally, Fig.2I Some materials including the third insulating material 134 and the fourth insulating material 137 are omitted in the stepped region 104 of

[0142] The second conductive structure 140 may include a first portion 140a extending in a first horizontal direction (e.g., the X direction), and a second portion 140b horizontally adjacent to the first portion 140a and extending in a second horizontal direction (e.g., the Y direction). Additionally, optionally, the second conductive structure 140 may include a third portion 140c extending in the first horizontal direction (e.g., the X direction) and generally parallel to the first portion 140a. For illustrative purposes, some of the first portions 140a of the second conductive structure 140 (e.g., every other first portion 140a) are described herein as the third portion 140c. Thus, one of the second portions 140b of the second conductive structure 140 may be horizontally interposed between one of the first portions 140a and one of the third portions 140c.

[0143] In some embodiments, each of the first portion 140a and the second portion 140b includes a generally linear portion of the second conductive structure 140, and the third portion 140c includes its arcuate (e.g., non-linear) portion. Thus, the second conductive structure 140 may include generally linear portions, and arcuate portions that intersect each other at the intersection 141 and are separated by a steep transition therebetween. To enable a clear and easy understanding of the drawings and the associated description, the third portion 140c of the second conductive structure 140 differs from the first portion 140a in its position (e.g., being laterally offset from the first conductive structure 120 in the Y direction) and its shape (e.g., exhibiting an arcuate shape). Each of the first portion 140a, the second portion 140b, and the third portion 140c of the second conductive structure 140 may include generally the same material composition, with no readily distinguishable physical interface therebetween.

[0144] As Fig.2I shown, horizontally adjacent pairs of the second conductive structures 140 (including their first portions 140a, second portions 140b, and third portions 140c) may be separated from each other by the isolation structure 158 horizontally interposed therebetween. The isolation structure 158 may include those previously referred to herein with reference to Figure 2CThe described slot is filled (e.g., substantially filled) with one or more materials (e.g., an insulating material). The isolation structure 158 can individually include a first portion 158a extending in a first horizontal direction (e.g., the X direction), and a second portion 158b intersecting the first portion 158a at an intersection 159 and extending in a second horizontal direction (e.g., the Y direction). The first portion 158a and the second portion 158b of the isolation structure 158 can individually include substantially linear portions that intersect each other at the intersection 159. In some embodiments, the first portion 158a of the isolation structure 158 is located between parallel extending segments (e.g., the first portion 140a) of the second conductive structure 140, and the second portion 158b of the isolation structure 158 intersects its first portion 158a and extends generally parallel to an additional segment (e.g., the second portion 140b) of the second conductive structure 140, the additional segment being staggered between its parallel extending segments.

[0145] The isolation structure 158 can be formed of and include an insulating material that is, for example, one or more of the following: oxide materials (e.g., SiO2, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, TiO2, HfO2, ZrO2, HfO2, TaO2, MgO, Al2O3, or combinations thereof); and amorphous carbon. In some embodiments, the isolation structure 158 includes SiO2.

[0146] The first portion 158a of the isolation structure 158 may individually exhibit an elongated shape that is longer in the X direction than in the Y direction, and the second portion 158b of the isolation structure 158 may individually exhibit an elongated shape that is longer in the Y direction than in the X direction. In some embodiments, the width of the first portion 158a of the isolation structure 158 in the Y direction is less than the width of its second portion 158b in the X direction. By way of non-limiting example, the width of the first portion 158a may be in the range of about 50 nm to about 150 nm, and the width of the second portion 158b may be in the range of about 150 nm to about 450 nm. The size and shape of the isolation structure 158 may be set to facilitate electrical isolation of groups of the second conductive structures 140 on opposite sides of the second conductive structures 140 that are horizontally adjacent (e.g., in the Y direction). In some embodiments, the first portion 158a of the isolation structure 158 is within the horizontal boundary of the lowermost step 132 (e.g., the central portion 148) of the stepped structure 130. In some embodiments, the transition region between adjacent levels 152 may be positioned along the longitudinal centerline (e.g., in the Y direction) of the second portion 158b of the isolation structure 158. The first half of the individual second portion 158b of the individual isolation structure 158 may be within the horizontal boundary of the first level 152, and the second half of its second portion 158b may be within the horizontal boundary of the second level 152 adjacent to the first level 152.

[0147] In some embodiments, the first portion 140a of the second conductive structure 140 is proximal to the lateral side of the first portion 158a of the isolation structure 158, the second portion 140b is close to the lateral side of the second portion 158b, and the third portion 140c is close to the longitudinal end of the second portion 158b. The arcuate portion (e.g., the third portion 140c) of the second conductive structure 140 may be adjacent to the longitudinal end of the second portion 158b of the isolation structure 158, and its generally linear portions (e.g., the first portion 140a, the second portion 140b) may be adjacent to the lateral sides of the first portion 158a and the second portion 158b, respectively, but other configurations may be contemplated. For convenience, only one of the second conductive structures 140 is shown, which is adjacent to Fig.2I each of the isolation structures 158 within the stepped region 104 in, but it should be understood that the stepped region 104 may include additional (e.g., two) second conductive structures 140 on opposite sides of the isolation structure 158.

[0148] In some embodiments, the pattern of one of the second conductive structures 140 exhibits a so-called "mirror" pattern that is substantially symmetric about the first part 158a of the isolation structure 158 with respect to the other of the second conductive structures 140. Additionally, two adjacent second conductive structures 140 may exhibit mirror patterns that are substantially symmetric with respect to each other at substantially equal distances (e.g., horizontal midpoints) from the longitudinal ends of the second part 158b of the isolation structure 158 along a dashed line extending in the X direction (e.g., at substantially equal distances between adjacent first conductive structures 120 in the array region 102).

[0149] Compared to the linear conductive structures of conventional device architectures, additional benefits of the configuration of the second conductive structures 140 (e.g., non-linear conductive structures) include reduced leakage due to the coupling capacitance between adjacent conductive structures. Without being bound by any particular theory, it is believed that by reducing the surface area presented to adjacent conductive structures of the second conductive structures 140, unwanted leakage can be minimized (e.g., prevented). The reduced surface area of the third part 140c of the second conductive structure 140 (e.g., individually) presented to other third parts 140c of adjacent second conductive structures 140 is significantly less than the surface area of the full-length conductive structures of the full-length adjacent linear conductive structures of conventional device architectures.

[0150] As Fig.2I shown, the conductive contact structures 142 are arranged in rows (e.g., a first row 160, a second row 162) that extend in the Y direction and are spaced apart from each other in the X direction. The conductive contact structures 142 may be located at the horizontal ends (e.g., lateral ends) of the second conductive structures 140. In some embodiments, each of the first row 160 and the second row 162 of the conductive contact structures 142 extends substantially transverse to a direction (e.g., the X direction) in which the first conductive structures 120 extend within the array region 102, rather than extending substantially parallel to the direction in which the first conductive structures 120 extend. Thus, each of the first row 160 and the second row 162 of the conductive contact structures 142 extends in a single horizontal direction (e.g., the Y direction). The first row 160 and the second row 162 of the conductive contact structures 142 are located on the second part 140b of the second conductive structures 140 and not on their first part 140a and third part 140c.

[0151] The first row 160 of the conductive contact structure 142 can horizontally extend parallel to each other in the Y direction. Each pair of the first rows 160 can horizontally overlap each other in the Y direction and can be separated from each other in the X direction by the second part 158b of the isolation structure 158. Similarly, the second row 162 of the conductive contact structure 142 can also horizontally extend parallel to each other in the Y direction. Each pair of the second rows 162 can horizontally overlap each other in the Y direction and can be separated from each other in the X direction and horizontally separated from each other by the second part 158b of the isolation structure 158. In addition, the first row 160 can be substantially aligned with the second row 162 in the X direction. The second row 162 can horizontally extend in series with the first row 160 in the Y direction.

[0152] Continuing to refer Fig.2I , the stepped structure 130 can individually include more than one (e.g., two) of the rows 160, 162 of the conductive contact structure 142 operatively associated therewith. In some embodiments, the stepped structure 130 individually includes one of the first rows 160 and one of the second rows 162 that are substantially horizontally aligned with each other in the X direction. The first row 160 and the second row 162 of the conductive contact structure 142 of an individual stepped structure 130 can be located within a single (e.g., only one) tier 152 of the vertical stacking structure 122.

[0153] In some embodiments, more than one (e.g., two) of the conductive contact structures 142 are located on the individual steps 132 of an individual stepped structure 130. For example, the uppermost conductive contact structure 142 within one of the first rows 160 and the uppermost conductive contact structure 142 within one of the second rows 162 can each be located on the uppermost step 132 (e.g., the bridge 150) of an individual stepped structure 130. In addition, the lowermost conductive contact structure 142 within the one of the first rows 160 and the lowermost conductive contact structure 142 within the one of the second rows 162 can each be located on the lowermost step 132 (e.g., the central portion 148) of an individual stepped structure 130. The additional conductive contact structures 142 between the uppermost and lowermost conductive contact structures 142 of the rows 160, 162 can be arranged similarly (e.g., two of the conductive contact structures 142 on the individual steps 132 between the uppermost step 132 and the lowermost step 132).

[0154] In some embodiments, one or more of the conductive contact structures 142 in the first row 160 have substantially the same vertical height as one or more additional conductive contact structures 142 in the second row 162, and the second row 162 is adjacent to the first row 160 within a single vertical tier 152 of the vertical stacking structure 122. Some of the conductive contact structures 142 on the steps 132 of the stepped structure 130 can be electrically isolated from each other by the first part 158a of the isolation structure 158, as Fig.2I As shown in. Optionally, some of the conductive contact structures 142 on the steps 132 of the stepped structure 130 may be electrically isolated from each other by additional isolation structures (e.g., additional dielectric-filled slots), as described in further detail below.

[0155] Figure 2J Shown Fig.2I A simplified top view of region J depicted by a dashed box in. To enable a clear and easy understanding of the drawings and the associated description, some features (e.g., materials, structures, regions) of the microelectronic device structure 100 at the processing stage depicted in Figure 2J are omitted from Fig.2I including some materials of the vertical stack structure 122.

[0156] During the formation of the second conductive structure 140, the sacrificial portion (e.g., the end portion 164) of the second conductive structure 140 may initially be formed to extend in the Y direction and intervene between the first portions 140a of adjacent second conductive structures 140 (e.g., connecting them to each other). In some embodiments, the end portion 164 may be separated (e.g., electrically isolated) from adjacent second conductive structures 140 (e.g., their first portions 140a) close to the perimeter (e.g., the outer horizontal boundary) of the vertical stack structure 122. For example, a dielectric-filled structure 166 (e.g., a deep trench isolation structure) may be formed to extend in the Y direction, proximal to the end portion 164 of the second conductive structure 140, separating the first portions 140a and thus separating adjacent second conductive structures 140 from each other. As Figure 2J shown in, the dielectric-filled structure 166 may be formed on opposite sides of the second portion 158b of the isolation structure 158 and intersect with its first portion 158a. Thus, the elongated portion of the dielectric-filled structure 166 may be generally parallel to each of the second portion 158b of the isolation structure 158 and the second portion 140b of the second conductive structure 140.

[0157] Additionally, optionally, a support structure 168 (e.g., a dielectric-filled support structure) may be formed between adjacent conductive contact structures 142 of individual rows 160, 162. For example, the support structure 168 may be formed to extend in the X direction and separate (e.g., electrically isolate) the conductive contact structures 142 horizontally adjacent to each other in the Y direction. As Figure 2J shown in, one or more (e.g., multiple) of the support structures 168 may be formed on opposite sides of the first portion 158a of the isolation structure 158 and may intersect with its second portion 158b. Thus, the elongated portion of the support structure 168 may be generally parallel to each of the first portion 158a of the isolation structure 158 and the first portion 140a of the second conductive structure 140.

[0158] The upper surfaces of the dielectric fill structure 166 and the support structure 168 may be generally coplanar with each other, and the lower surfaces of the dielectric fill structure 166 and the support structure 168 may be generally coplanar with each other. Thus, the dielectric fill structure 166 may have the same height as the support structure 168. The dielectric fill structure 166 and the support structure 168 may be individually formed of and include an insulating material, such as one or more of the materials described above with reference to the isolation structure 158 (e.g., SiO2). In some embodiments, the support structure 168 may be formed (e.g., substantially simultaneously) during the formation of the dielectric fill structure 166 to reduce manufacturing costs. Additionally, one or more of the dielectric fill structure 166 and the support structure 168 may be configured and positioned, for example, to provide support for the vertical stack structure 122 proximal to the second conductive structure 140 and the stepped structure 130( Fig.2I ).

[0159] Referring Figure 2K , the microelectronic device structure 100 may be formed to include additional vertical stack structures 122 horizontally adjacent to each other. Figure 2K A microelectronic device structure 100 including a plurality (e.g., two) of the vertical stack structures 122 is schematically shown in Figure 2K . For example, each vertical stack structure 122 may individually include a first stepped region 104a at a first horizontal end (e.g., in the X direction), and include a second stepped region 104b at a second horizontal end (e.g., in the X direction) opposite the first horizontal end. For clarity and ease of understanding of this specification, Figure 1A other components of the microelectronic device structure 100, such as the vertical stacks of the memory cells 108(

[0160] As Figure 2K shown in

[0161] The distance N between the array regions 102 of the horizontally adjacent vertical stack structures 122 may be divided substantially equally between the horizontally adjacent second stepped regions 104b, e.g., such that each second stepped region 104b spans half of the distance N (e.g., N / 2) between the array regions 102 of the adjacent vertical stack structures 122. In other regions of the microelectronic device structure 100, two of the first stepped regions 104a may be adjacent to each other (e.g., horizontally adjacent) and proximal to an additional centerline between the adjacent vertical stack structures 122.

[0162] Reference Fig.2I , in combination with Figure 2K , the configuration of the conductive contact structures 142 of the stepped structure 130 within the first stepped region 104a may be different from the configuration of the additional conductive contact structures 142 of the stepped structure 130 within the second stepped region 104b. For example, the stepped structure 130 of the vertical stack structure 122 within the first stepped region 104a may include conductive contact structures 142 on the even-numbered steps 132, and the additional stepped structure 130 within the second stepped region 104b may include conductive contact structures 142 on the odd-numbered steps 132, as described above. The stepped regions 104 that are horizontally adjacent (e.g., in the X direction) to the array region 102 of the vertical stack structure 122 may alternate between a first configuration and a second configuration of the conductive contact structures 142 on the steps 132 of the stepped structure 130, where two of the stepped regions 104 that are horizontally adjacent to each other (e.g., the first stepped region 104a, the second stepped region 104b) have a similar configuration. In additional embodiments, the configurations of the first stepped region 104a and the second stepped region 104b may be substantially the same as each other. Since the stepped structure 130 facilitates reducing the area of the microelectronic device structure 100, the horizontal region allocated to the stepped region 104 that includes the stepped structure 130 may be reduced compared to the stepped regions of conventional microelectronic device structures.

[0163] Thus, according to some embodiments, a microelectronic device includes a stack structure that includes: an array region that includes first conductive structures that are vertically spaced apart from each other; and a stepped region that is horizontally adjacent to the array region and includes second conductive structures that are vertically spaced apart from each other and coupled to the first conductive structures. The second conductive structures individually include portions that extend in a first horizontal direction and additional portions that extend in a second horizontal direction that is transverse to the first horizontal direction. The stepped region includes a stepped structure that has steps that are partially defined by edge portions of the second conductive structures. Some of the steps extend in the first horizontal direction and some of the other steps extend in the second horizontal direction.

[0164] In addition, according to additional embodiments of the present disclosure, a memory device includes a vertical stack of dynamic random access memory (DRAM) cells within an array region. Each of the DRAM cells includes a storage device horizontally adjacent to an access device. The memory device includes a first conductive line extending in a first horizontal direction within the array region and operatively associated with the vertical stack of DRAM cells, and a second conductive line external to the array region and coupled to the first conductive line. The second conductive line individually includes a first portion extending in the first horizontal direction, and a second portion integral and continuous with the first portion and extending in a second horizontal direction orthogonal to the first horizontal direction. The memory device includes a conductive contact that contacts a stepped structure having a horizontal curved step partially defined by a horizontal end portion of the second conductive line. The conductive structure includes a first row of conductive contacts extending in the second horizontal direction, and a second row of conductive contacts extending in the second horizontal direction and generally aligned with the first row of conductive contacts in the first horizontal direction.

[0165] In addition, according to some embodiments of the present disclosure, a method of forming a microelectronic device includes: forming a preliminary stack structure including a vertical alternating sequence of insulating material and sacrificial material disposed in a preliminary layer. The preliminary stack structure includes an array region and a stepped region horizontally adjacent to the array region. The method includes forming a stepped structure located within the stepped region of the preliminary stack structure and individually having a step defined by a horizontal edge of the preliminary layer. The stepped structure includes a partially curved horizontal cross-sectional shape at different vertical elevations thereof. The method includes replacing a portion of the sacrificial material within the array region with a first conductive structure, and replacing an additional portion of the sacrificial material within the stepped region with a second conductive structure individually aligned with and coupled to the first conductive structure. The second conductive structure individually includes a portion extending in a first horizontal direction and an additional portion extending in a second horizontal direction transverse to the first horizontal direction.

[0166] Structures, assemblies, and devices according to embodiments of the present disclosure may be included in an electronic system of the present disclosure. For example, Figure 3 is a block diagram of an illustrative electronic system 300 according to an embodiment of the present disclosure. The electronic system 300 may include, for example, a computer or computer hardware component, a server or other networked hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g. or a tablet computer), an e-book, a navigation device, etc. The electronic system 300 includes at least one memory device 302. The memory device 302 may include, for example, a microelectronic device structure, a microelectronic device structure assembly, a relatively large microelectronic device structure assembly, and previously herein referred to Figures 1A to 2K Embodiments of one or more of the described microelectronic devices. The electronic system 300 may further include at least one electronic signal processor device 304 (often referred to as a "microprocessor"). Optionally, the electronic signal processor device 304 may include microelectronic device structures, microelectronic device assemblies, relatively large microelectronic device assemblies, and those described previously herein with reference to Figures 1A to 2K Embodiments of one or more of the described microelectronic devices. Although in Figure 3 , the memory device 302 and the electronic signal processor device 304 are depicted as two (2) separate devices, in additional embodiments, a single (e.g., only one) memory / processor device having the functions of the memory device 302 and the electronic signal processor device 304 is included in the electronic system 300. In such embodiments, the memory / processor device may include microelectronic device structures, microelectronic device assemblies, relatively large microelectronic device assemblies, and one or more of the microelectronic devices described previously herein with reference to Figures 1A to 2K The electronic system 300 may further include one or more input devices 306 for inputting information into the electronic system 300 by a user, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 300 may further include one or more output devices 308 for outputting (e.g., visual or audio output) information to the user, such as one or more of a monitor, display, printer, audio output jack, and speaker. In some embodiments, the input device 306 and the output device 308 may include a single touchscreen device that can be used to input information into the electronic system 300 and output visual information to the user. The input device 306 and the output device 308 may be in electrical communication with one or more of the memory device 302 and the electronic signal processor device 304.

[0167] Thus, according to embodiments of the present disclosure, an electronic system includes a processor operably coupled to an input device and an output device, and a memory device operably coupled to the processor. The memory device includes: a stack structure including a vertical stack of memory cells; and a stepped structure located within the stack structure and horizontally adjacent to the vertical stack of memory cells. The stepped structure individually includes steps having at least a partially curved horizontal cross-sectional shape. The memory device includes non-linear conductive lines that partially define the steps of the stepped structure. Two of the non-linear conductive lines are associated with one of the stepped structures.

[0168] Embodiments of the present disclosure may be further characterized in the manner set forth below but not limited to the manner set forth below.

[0169] Example 1: A microelectronic device includes a stacked structure, the stacked structure including: an array region including first conductive structures vertically spaced apart from each other; and a stepped region horizontally adjacent to the array region and including: second conductive structures vertically spaced apart from each other and coupled to the first conductive structures, the second conductive structures individually including a portion extending in a first horizontal direction and an additional portion extending in a second horizontal direction transverse to the first horizontal direction; and a stepped structure having steps partially defined by edge portions of the second conductive structures, some of the steps extending in the first horizontal direction and some of the steps extending in the second horizontal direction.

[0170] Example 2: The microelectronic device according to Example 1 further includes conductive contacts on the steps of the stepped structure, the conductive contacts arranged in rows extending in the second horizontal direction.

[0171] Example 3: The microelectronic device according to Example 2, wherein the stepped structure individually has two or more of the conductive contacts at each vertical level of its steps, and the conductive contacts at a corresponding vertical level are electrically isolated from each other.

[0172] Example 4: The microelectronic device according to any one of Examples 1 to 3, wherein the stepped structure individually exhibits one or more partially enclosed curved horizontal cross-sectional shapes.

[0173] Example 5: The microelectronic device according to any one of Examples 1 to 4, wherein at least two horizontal portions of one of the stepped structures are located at at least two different vertical levels within the stacked structure, and a set of second conductive structures within one of the at least two different vertical levels is vertically located below an additional set of second conductive structures within the other of the at least two different vertical levels.

[0174] Example 6: The microelectronic device according to any one of Examples 1 to 5, wherein each of the stepped structures is horizontally separated between at least two vertical levels of the stacked structure, and each of the at least two vertical levels of the stacked structure vertically spans a different set of second conductive structures and each of the at least two vertical levels of the stacked structure.

[0175] Example 7: The microelectronic device according to any one of Examples 1 to 6, wherein the steps of at least one of the stepped structures individually have at least a partially curved horizontal shape, the at least partially curved horizontal shape including: a first portion extending in the first horizontal direction; a second portion extending in a second horizontal direction transverse to the first horizontal direction; and at least one additional portion located between the first portion and the second portion and extending at an acute angle with respect to the first horizontal direction and the second horizontal direction.

[0176] Example 8: The microelectronic device according to any one of Examples 1 to 7 further includes a vertical stack of memory cells in the array region of the stack structure. Each vertical stack of memory cells includes: a vertical stack of access devices; and a vertical stack of storage devices that is horizontally adjacent to the vertical stack of access devices.

[0177] Example 9: A memory device includes: a vertical stack of dynamic random access memory (DRAM) cells in an array region, each of the DRAM cells including a storage device horizontally adjacent to an access device; a first conductive wire that extends in a first horizontal direction in the array region and is operatively associated with the vertical stack of DRAM cells; a second conductive wire that is outside the array region and coupled to the first conductive wire, the second conductive wire individually including a first portion that extends in the first horizontal direction and a second portion that is integral and continuous with the first portion and extends in a second horizontal direction orthogonal to the first horizontal direction; and a conductive contact that contacts a stepped structure having a horizontal curved step that is partially defined by a horizontal end portion of the second conductive wire, the conductive contact including a first row of conductive contacts that extend in the second horizontal direction and a second row of conductive contacts that extend in the second horizontal direction and are generally aligned with the first row of conductive contacts in the first horizontal direction.

[0178] Example 10: The memory device according to Example 9, wherein the horizontal curved step of the stepped structure individually has a partially arcuate horizontal boundary.

[0179] Example 11: The memory device according to Example 9 or Example 10, wherein the conductive contact is operatively coupled to the access device of each of the DRAM cells by means of the first conductive wire and the second conductive wire.

[0180] Example 12: The memory device according to any one of Examples 9 to 11, wherein one of the conductive contacts in the first row of conductive contacts has a substantially the same vertical height as an additional one of the conductive contacts in the second row of conductive contacts that is horizontally adjacent to the first row of conductive contacts.

[0181] Example 13: The memory device according to any one of Examples 9 to 12, wherein the stepped structure individually has different closed curve horizontal cross-sectional shapes at its different vertical elevations.

[0182] Example 14: The memory device according to any one of Examples 9 to 13, wherein at least some of the second conductive wires are oriented substantially symmetrically about a horizontal midpoint between adjacent second conductive wires.

[0183] Example 15: The memory device according to any one of Examples 9 to 14 further includes an isolation structure horizontally adjacent to the second conductive line. The isolation structure individually includes: a first portion horizontally located between parallel extension sections of the second conductive line; and a second portion horizontally intersecting the first portion and extending substantially parallel to an additional section of the second conductive line, the additional section of the second conductive line being staggered between the parallel extension sections of the second conductive line.

[0184] Example 16: The memory device according to any one of Examples 9 to 15 further includes a first stepped region horizontally adjacent to the array region and a second stepped region horizontally adjacent to the array region on a side opposite to the first stepped region. The configuration of a set of conductive contacts in the first stepped region is different from the configuration of an additional set of conductive contacts in the second stepped region.

[0185] Example 17: A method of forming a microelectronic device, the method includes: forming a preliminary stacked structure including a vertical alternating sequence of an insulating material and a sacrificial material arranged in a preliminary layer, the preliminary stacked structure including an array region and a stepped region horizontally adjacent to the array region; forming a stepped structure located in the stepped region of the preliminary stacked structure and individually having steps defined by horizontal edges of the preliminary layer, the stepped structure including a partially curved horizontal cross-sectional shape at its different vertical elevations; replacing a portion of the sacrificial material in the array region with a first conductive structure; and replacing an additional portion of the sacrificial material in the stepped region with a second conductive structure individually aligned with and coupled to the first conductive structure, the second conductive structure individually including: a portion extending in a first horizontal direction; and an additional portion extending in a second horizontal direction transverse to the first horizontal direction.

[0186] Example 18: The method according to Example 17, wherein forming the stepped structure includes: forming a preliminary stepped structure individually having an elliptical horizontal cross-sectional shape; and vertically extending at least some portions of at least some of the preliminary stepped structures to relatively lower vertical positions within the preliminary stacked structure.

[0187] Example 19: The method according to Example 18, wherein forming the stepped structure includes: removing material of the preliminary stacked structure to form a central opening arranged in a hexagonal pattern; and removing additional material of the preliminary stacked structure to form a series of preliminary steps of the preliminary stepped structure gradually outward and generally surrounding the central opening; and vertically extending portions of the preliminary stepped structure deeper into the preliminary stacked structure relative to other portions of the preliminary stepped structure.

[0188] Example 20: The method according to any one of Examples 17 to 19 further includes forming a linear portion of a first conductive structure in an array region substantially simultaneously with forming a non-linear portion of a second conductive structure in a stepped region.

[0189] Example 21: An electronic system, comprising: a processor operatively coupled to an input device and an output device; and a memory device operatively coupled to the processor, the memory device including: a stacked structure including a vertical stack of memory cells; a stepped structure located within the stacked structure and horizontally adjacent to the vertical stack of memory cells, the stepped structure individually including steps having at least a partially curved horizontal cross-sectional shape; and non-linear conductive lines partially defining the steps of the stepped structure, two of the non-linear conductive lines being associated with one of the stepped structures.

[0190] Example 22: The electronic system according to Example 21, wherein: the stepped structures are spaced apart from each other in a first horizontal direction and in a second horizontal direction; and the stepped structures in each row are horizontally staggered such that a first row of stepped structures is offset from a second row of stepped structures horizontally adjacent to the first row in the first horizontal direction and in the second horizontal direction.

[0191] Example 23: The electronic system according to Example 21 or Example 22, wherein a portion of the non-linear conductive line defining the uppermost step of some of the stepped structures includes a bridging portion common to three or more of some of the stepped structures.

[0192] Example 24: The electronic system according to any one of Examples 21 to 23, wherein the non-linear conductive line includes a first linear portion horizontally interleaved with a second linear portion, at least some of the first linear portion and at least some of the second linear portion having substantially equal lengths with respect to each other.

[0193] Example 25: The electronic system according to any one of Examples 21 to 24, wherein the memory device is a three-dimensional (3D) dynamic random access memory (DRAM) device.

[0194] Although certain illustrative embodiments have been described in connection with the figures, those of ordinary skill in the art will recognize and understand that the embodiments encompassed by the present disclosure are not limited to those expressly shown and described herein. Rather, various additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments encompassed by the present disclosure (such as those claimed herein, including legal equivalents). Additionally, features of one disclosed embodiment can be combined with features of another disclosed embodiment while still being within the scope of the present disclosure.

Claims

1. A microelectronic device, comprising: A stacked structure, comprising: An array region, comprising first conductive structures vertically spaced apart from each other; and A stepped region, horizontally adjacent to the array region and comprising: Second conductive structures, vertically spaced apart from each other and coupled to the first conductive structures, the second conductive structures individually comprising: A portion extending in a first horizontal direction; and An additional portion extending in a second horizontal direction transverse to the first horizontal direction; and A stepped structure having steps partially defined by edge portions of the second conductive structures, some of the steps extending in the first horizontal direction and some of the steps extending in the second horizontal direction.

2. The microelectronic device according to claim 1, further comprising conductive contacts on the steps of the stepped structure, the conductive contacts arranged in rows extending in the second horizontal direction.

3. The microelectronic device according to claim 2, wherein the stepped structure individually has two or more of the conductive contacts at each vertical level of its steps, and the conductive contacts at a corresponding vertical level are electrically isolated from each other.

4. The microelectronic device according to claim 1 or claim 2, wherein the stepped structure individually exhibits a horizontal cross-sectional shape of one or more partially enclosed curves.

5. The microelectronic device according to claim 1 or claim 2, wherein at least two horizontal portions of one of the stepped structures are located at at least two different vertical levels within the stacked structure, and a set of the second conductive structures within one of the at least two different vertical levels is vertically located below an additional set of the second conductive structures within the other of the at least two different vertical levels.

6. The microelectronic device according to claim 1 or claim 2, wherein each of the stepped structures is horizontally separated between at least two vertical levels of the stacked structure, and each of the at least two vertical levels of the stacked structure vertically spans a different set of the second conductive structures and each of the at least two vertical levels of the stacked structure.

7. The microelectronic device according to claim 1 or claim 2, wherein the steps of at least one of the stepped structures individually have at least a partially curved horizontal shape, the at least partially curved horizontal shape comprising: A first portion extending in the first horizontal direction; A second portion extending in the second horizontal direction transverse to the first horizontal direction; And At least one additional portion located between the first portion and the second portion and extending at an acute angle with respect to the first horizontal direction and the second horizontal direction.

8. The microelectronic device according to claim 1 or claim 2, further comprising a vertical stack of memory cells within the array region of the stacked structure, each vertical stack of memory cells comprising: A vertical stack of access devices; And A vertical stack of storage devices, horizontally adjacent to the vertical stack of access devices.

9. The microelectronic device according to claim 2, wherein the conductive contact contacts a horizontal bending step of the stepped structure, and the conductive contact includes: The first row of the conductive contacts, which extends in the second horizontal direction; And The second row of the conductive contacts, which extends in the second horizontal direction and is substantially aligned with the first row of the conductive contacts in the first horizontal direction.

10. The microelectronic device according to claim 9, wherein the horizontal bending steps of the stepped structure each have a partially arcuate horizontal boundary.

11. The microelectronic device according to claim 9 or claim 10, further comprising a vertical stack of dynamic random access memory (DRAM) cells in the array region, each of the DRAM cells including a storage device horizontally adjacent to an access device, wherein the conductive contacts are operatively coupled to the access devices of each of the DRAM cells by the first conductive structure and the second conductive structure.

12. The microelectronic device according to claim 9 or claim 10, wherein one of the conductive contacts in the first row of the conductive contacts has a substantially the same vertical height as an additional one of the conductive contacts in the second row of the conductive contacts that is horizontally adjacent to the first row of the conductive contacts.

13. The microelectronic device according to claim 4, wherein the stepped structure has a different partially enclosed curve horizontal cross-sectional shape at its different vertical elevations.

14. The microelectronic device according to claim 9 or claim 10, wherein at least some of the second conductive structures are oriented substantially symmetrically about a horizontal midpoint between adjacent second conductive structures.

15. The microelectronic device according to claim 9 or claim 10, further comprising an isolation structure horizontally adjacent to the second conductive structure, and the isolation structure individually includes: A first portion, which is horizontally located between parallel extension sections of the second conductive structure; And A second portion, which horizontally intersects the first portion and extends substantially parallel to an additional section of the second conductive structure, and the additional section of the second conductive structure is staggered between the parallel extension sections of the second conductive structure.

16. The microelectronic device according to claim 9 or claim 10, wherein the stepped region includes a first stepped region horizontally adjacent to the array region and a second stepped region horizontally adjacent to the array region on a side opposite to the first stepped region, and the configuration of a set of the conductive contacts in the first stepped region is different from the configuration of an additional set of the conductive contacts in the second stepped region.

17. A method of forming a microelectronic device, the method comprising: Forming a preliminary stack structure, the preliminary stack structure including a vertical alternating sequence of an insulating material and a sacrificial material arranged in a preliminary layer, and the preliminary stack structure includes an array region and a stepped region horizontally adjacent to the array region; Form a stepped structure, the stepped structure being located in the stepped area of the preliminary stacked structure and individually having steps defined by the horizontal edges of the preliminary layers, the stepped structure including a partially curved horizontal cross-sectional shape at its different vertical elevations; Replace a portion of the sacrificial material in the array area with a first conductive structure; And Replace an additional portion of the sacrificial material in the stepped area with a second conductive structure that is individually aligned with and coupled to the first conductive structure, the second conductive structure individually including: A portion extending in a first horizontal direction; And An additional portion extending in a second horizontal direction transverse to the first horizontal direction.

18. The method according to claim 17, wherein forming the stepped structure includes: Forming a preliminary stepped structure having an elliptical horizontal cross-sectional shape individually; And Vertically extending at least some portions of at least some of the preliminary stepped structures to relatively lower vertical positions within the preliminary stacked structure.

19. The method according to claim 18, wherein forming the stepped structure includes: Removing material of the preliminary stacked structure to form a central opening arranged in a hexagonal pattern; And Removing additional material of the preliminary stacked structure to form a series of preliminary steps of the preliminary stepped structure that gradually extends outward and generally surrounds the central opening; And Vertically extending portions of the preliminary stepped structure deeper into the preliminary stacked structure relative to other portions of the preliminary stepped structure.

20. The method according to claim 17 or claim 18, further comprising forming a linear portion of the first conductive structure in the array area substantially simultaneously with forming a non-linear portion of the second conductive structure in the stepped area.

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