High power seed high patterning on piezoelectric thin films for piezoelectric device fabrication
By using a method of matching the grain size and orientation of the high power seed layer and the piezoelectric layer in piezoelectric devices, the problem of high loss tangent (LT) caused by brittle properties in patterned piezoelectric materials is solved, and more efficient piezoelectric device performance is achieved.
Patent Information
- Application Number
- CN202380083302.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-10-31
- Filing Date
- 2023-10-27
- Publication Date
- 2025-06-27
AI Technical Summary
The prior art faces difficulties in the manufacturing of patterned piezoelectric materials due to the brittle properties of the piezoelectric materials, resulting in a higher loss tangent (LT) of piezoelectric devices.
The high-power seed layer is placed on the bottom electrode with a target bias power greater than 3kW by physical vapor deposition technology, and a piezoelectric layer and a top electrode are formed thereon. The high-power seed layer matches the grain size and orientation of the piezoelectric layer to improve the nucleation and crystal growth of the material.
In this way, the loss tangent (LT) of the piezoelectric device is significantly reduced, and the efficiency and performance of the device is improved. The LT is below 1500ppm, which is 7% to 15% higher than conventional components.
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Figure CN120226491A_ABST
Abstract
Description
BACKGROUND OF THE DISCLOSURE
[0001] FIELD
[0002] Embodiments of the present disclosure generally relate to piezoelectric devices. More specifically, embodiments disclosed herein relate to methods of patterning piezoelectric layers for piezoelectric device fabrication.
[0003] RELATED ART DESCRIPTION
[0004] Piezoelectric materials are materials that accumulate charge when a mechanical stress is applied and are often used in piezoelectric devices in sensors and transducers such as gyro sensors, inkjet printheads, ultrasonic technology, and other microelectromechanical systems (MEMS) devices, including acoustic resonators for mobile phones and other wireless electronic devices. Patterning piezoelectric materials during the fabrication of piezoelectric devices can be difficult due to the brittle nature of the piezoelectric materials.
[0005] Accordingly, there is a need in the art for improved methods of forming piezoelectric materials. SUMMARY OF THE INVENTION
[0006] In one embodiment, a method of forming a piezoelectric device is disclosed. The method includes disposing a bottom electrode over a substrate. A high-power seed layer is disposed over the bottom electrode via physical vapor deposition with a target bias power greater than 3 kW. A piezoelectric layer is over the bottom electrode. A top electrode is formed over the piezoelectric layer in a top electrode pattern.
[0007] In another embodiment, a piezoelectric device is disclosed. The piezoelectric device includes a bottom electrode disposed over a substrate, a high-power seed layer disposed over the bottom electrode, a piezoelectric layer disposed over the high-power seed layer, and a top electrode disposed over the piezoelectric layer. The high-power seed layer has a high-power seed layer grain size and a high-power seed layer grain orientation. The piezoelectric layer has a piezoelectric grain size and a piezoelectric grain orientation. The grain size of the high-power seed layer matches the piezoelectric grain size, and the grain orientation of the high-power seed layer matches the piezoelectric grain orientation.
[0008] In yet another embodiment, a method of forming a piezoelectric device is disclosed. The method includes disposing a bottom electrode over a substrate. A high-power seed layer is disposed over the bottom electrode with a target bias power greater than 3 kW. A piezoelectric layer is disposed over the bottom electrode. An intermediate electrode is disposed over the piezoelectric layer. A second high-power seed layer is disposed over the intermediate electrode with a target bias power greater than 3 kW. A bottom electrode is disposed over the second piezoelectric layer. A top electrode is disposed over the piezoelectric layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] In order to understand the above - stated features of the present disclosure in a manner that can be detailed, a more specific description of the present disclosure briefly outlined above can be referred to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only show exemplary embodiments and should not be regarded as a limitation of the scope, since the present disclosure may admit other equally effective embodiments.
[0010] Figure 1 is a schematic top view of a piezoelectric device according to an embodiment described herein.
[0011] Figure 2A and Figure 2B is a schematic cross - sectional view of a piezoelectric device according to an embodiment described herein.
[0012] Figure 3 is a flowchart of a method for forming a piezoelectric device according to an embodiment described herein.
[0013] Figures 4A to 4I is during Figure 3 a schematic side view of a substrate during the method of forming a piezoelectric device according to an embodiment described herein.
[0014] Figure 5 is a schematic cross - sectional view of a laser etching system according to an embodiment described herein.
[0015] For the sake of facilitating understanding, wherever possible, the same element symbols are used to designate the same elements common to the figures. It is contemplated that the elements and features of one embodiment can be advantageously combined in other embodiments without further recitation. Detailed Description
[0016] Embodiments of the present disclosure generally relate to piezoelectric devices. More specifically, the embodiments disclosed herein relate to piezoelectric devices and methods for manufacturing piezoelectric layers for use in the manufacture of piezoelectric devices.
[0017] Patterning the piezoelectric material in a piezoelectric device may face challenges due to the brittle and hard nature of the piezoelectric material. For a piezoelectric device, it is advantageous to pattern the piezoelectric material such that the loss tangent (LT) of the component is low. The LT of a piezoelectric device is a measure of the signal loss related to the actuation momentum of the piezoelectric material. By the methods disclosed herein, improvements in patterning the piezoelectric material can be achieved, and thus improvements in LT can be achieved. The methods disclosed herein achieve patterning the piezoelectric material with increased throughput. In certain embodiments, a laser etching system is utilized to pattern the piezoelectric material. For example, the laser etching system includes laser process tuning to adjust the parameters of the laser to improve the patterning performance and throughput.
[0018] Figure 1is a schematic top view of a piezoelectric device 100 according to an embodiment described herein. The piezoelectric device 100 can be fabricated according to the methods described herein. Figure 1 The illustrated piezoelectric device 100 can be partially fabricated and other processing operations can be used to form a functional device. The piezoelectric device 100 can be used in sensing applications (e.g., gyro sensors), ultrasonic technology, inkjet printing, or microelectromechanical systems (MEMS) devices, including acoustic resonators for mobile phones and other wireless electronic devices.
[0019] The piezoelectric device 100 includes a substrate 102 (shown in FIG. 2), a primary seed layer 101 (shown in FIG. 2), a bottom electrode 104, a high-power seed layer 109 (shown in FIG. 2), a piezoelectric layer 106, and a top electrode 108. The substrate 102 can have a diameter ranging from about 100 mm to about 750 mm and can be formed of a variety of materials, including silicon (Si), silicon carbide (SiC), graphite coated with SiC, or silicon dioxide (SiO2). In one example, the surface area of the substrate 102 is about 1,000 cm 2 or more, such as about 2,000 cm 2 or more, about 4,000 cm 2 or more.
[0020] The primary seed layer 101 is disposed on the substrate 102. The bottom electrode 104 is disposed above the substrate 102. As Figure 2A and Figure 2B shown, the bottom electrode 104 is disposed on the primary seed layer 101. The bottom electrode 104 is the bottom electrode of the piezoelectric device 100. The bottom electrode 104 includes a conductive material, such as platinum (Pt), molybdenum (Mo), SrRuO3, LaNiO3, CaRuO3, LaSrMnO3, etc. The bottom electrode 104 has a thickness ranging from about 5 nm to about 350 nm, such as about 50 nm to about 200 nm, about 75 nm to about 175 nm, about 100 nm to about 150 nm, for example about 125 nm.
[0021] The high-power seed layer 109 is disposed on the bottom electrode 104. The piezoelectric layer 106 is disposed above the bottom electrode 104. As Figure 2A and Figure 2BAs shown, the piezoelectric layer 106 is disposed above the high-power seed layer 109. In some embodiments, the piezoelectric layer 106 may be formed of one or more layers including aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), lead magnesium niobate-lead titanate (PMN-PT), or LiNbO3 (LNO). The piezoelectric layer 106 may have a thickness of about 100 nm to about 3000 nm, such as about 750 nm to about 1500 nm, such as about 1000 nm. In some embodiments that may be combined with other embodiments described herein, the thickness of the piezoelectric layer 106 may vary over the high-power seed layer 109. In other embodiments that may be combined with other embodiments described herein, the thickness of the piezoelectric layer 106 is constant over the high-power seed layer 109. The piezoelectric layer 106 and the high-power seed layer 109 are selectively etched via a laser etching process to form an exposed portion 112 of the bottom electrode 104. The exposed portion 112 allows access to the bottom electrode 104.
[0022] The top electrode 108 is disposed above the piezoelectric layer 106. In one embodiment, the top electrode 108 is disposed on the piezoelectric layer 106. The top electrode 108 is configured as the top electrode of the finished piezoelectric device. In some embodiments, the top electrode 108 may be made of the same or different material as the bottom electrode 104. The top electrode 108 includes a conductive material such as platinum (Pt), molybdenum (Mo), SrRuO3, LaNiO3, CaRuO3, LaSrMnO3, etc. The top electrode 108 may have a thickness of about 5 nm to about 3000 nm, such as about 50 nm to about 150 nm, for example about 100 nm.
[0023] As Figure 1 shown, the top electrode 108 may be patterned on the piezoelectric layer 106 as needed. The top electrode 108 may be formed with a top electrode pattern 110. The top electrode pattern 110 may be predetermined before manufacturing to conform to the specifications of the piezoelectric device 100. The top electrode pattern 110 of the top electrode 108 is not limited to Figure 1 the pattern shown, and may be adjusted as needed. For example, the top electrode pattern 110 may include a circular, rectangular, square, or irregular pattern.
[0024] Figure 2AFIG. 0 is a schematic cross-sectional view of the piezoelectric device 100 along the cut line A-A. In the illustrated embodiment, the piezoelectric device 100 includes a primary seed layer 101 and a high-power seed layer 109. The primary seed layer 101 is disposed above the substrate 102. In one embodiment, the primary seed layer 101 is disposed on the substrate 102. The bottom electrode 104 is disposed above the primary seed layer 101. The primary seed layer 101 may include materials such as aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), etc. The primary seed layer 101 may have a thickness of about 1 nm to about 100 nm, such as about 5 nm to about 50 nm, such as about 30 nm.
[0025] The high-power seed layer 109 is disposed above the bottom electrode 104. In one embodiment, the high-power seed layer 109 is disposed on the bottom electrode 104. The piezoelectric layer 106 is disposed above the high-power seed layer 109. In some embodiments that can be combined with other embodiments described herein, the thickness of the piezoelectric layer 106 may vary on the top surface of the high-power seed layer 109. In other embodiments that can be combined with other embodiments described herein, the thickness of the piezoelectric layer 106 is constant on the top surface of the high-power seed layer 109. The piezoelectric layer 106 and the high-power seed layer 109 are selectively etched via a laser etching process to form an exposed portion 112 of the bottom electrode 104. The exposed portion 112 allows access to the bottom electrode 104.
[0026] In certain embodiments, the high-power seed layer 109 may be formed of the same or different materials as the primary seed layer 101. The high-power seed layer 109 may include materials such as aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), etc., but other materials are also contemplated by the present disclosure. The high-power seed layer 109 may have a thickness of about 1 nm to about 50 nm, such as about 5 nm to about 25 nm, such as about 10 nm.
[0027] The top electrode 108 is disposed above the piezoelectric layer 106. The top electrode 108 is configured as the top electrode 108 of the finished piezoelectric device.
[0028] Figure 2BIt is a schematic cross-sectional view of the alternative piezoelectric device 200 at the cut line A-A. The alternative piezoelectric device 200 further includes an intermediate electrode 208, a second high-power seed layer 209, and a second piezoelectric layer 206. The intermediate electrode 208 is disposed above the piezoelectric layer 106. In certain embodiments, the intermediate electrode 208 may be formed of the same or different material as the bottom electrode 104 or the top electrode 108. The intermediate electrode 208 may comprise a conductive material such as platinum (Pt), molybdenum (Mo), SrRuO3, LaNiO3, CaRuO3, LaSrMnO3, etc. The intermediate electrode 208 may have a thickness of about 5 nm to about 500 nm, such as about 50 nm to about 150 nm, for example about 100 nm.
[0029] The second high-power seed layer 209 is disposed above the intermediate electrode 208. The second high-power seed layer 209 may be formed of the same or different material as the primary seed layer 101. The second high-power seed layer 209 may comprise materials such as aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), etc. The second high-power seed layer 209 may have a thickness of about 1 nm to about 50 nm, such as about 5 nm to about 25 nm, for example about 10 nm.
[0030] The second piezoelectric layer 206 is disposed above the second high-power seed layer 209. In certain embodiments, the second piezoelectric layer 206 may be formed of the same or different material as the piezoelectric layer 106. In certain embodiments, the second piezoelectric layer 206 may consist of one or more layers that contain one or more of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), lead magnesium niobate-titanate (PMN-PT), or lithium niobate (LiNbO3). The second piezoelectric layer 206 has a thickness of about 100 nm to about 3000 nm, such as about 750 nm to about 1500 nm, such as about 1000 nm. In some embodiments combinable with other embodiments described herein, the thickness of the second piezoelectric layer 206 may vary on the top surface of the second high-power seed layer 209. In other embodiments combinable with other embodiments described herein, the thickness of the second piezoelectric layer 206 is constant on the top surface of the second high-power seed layer 209. The second piezoelectric layer 206 and the second high-power seed layer 209 are selectively etched via a laser etching process to form exposed portions of the intermediate electrode 208. These exposed portions allow access to the intermediate electrode 208.
[0031] The top electrode 108 is disposed above the second piezoelectric layer 206. The top electrode 108 is configured as the top electrode of the finished piezoelectric device.
[0032] Figure 3 Is a method 300 for forming the piezoelectric devices 100 and 200 as Figures 4A to 4H shown in the flowchart.Figures 4A - 4H Is a schematic cross-sectional view of substrate 102 during methods 300 of forming piezoelectric devices 100 and 200.
[0033] At operation 301, as Figure 4A shown, a primary seed layer 101 is disposed over substrate 102. The primary seed layer can be disposed via physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), inkjet printing, or other deposition processes performed in a suitable chamber. In certain embodiments, the deposition process is performed at about 25°C to about 600°C, such as about 400°C to about 600°C, and such as about 500°C. In certain embodiments, the deposition is a PVD process, and the target in the chamber is negatively biased during the deposition process by a pulsed or continuous power supply providing DC power, the power level of the DC power being from about 400W to about 3000W, such as about 1000W to about 2000W, or such as about 600W to about 800W.
[0034] At operation 302, as Figure 4B shown, a bottom electrode 104 is disposed over the primary seed layer 101. The bottom electrode 104 is disposed via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition processes performed in a suitable chamber. In certain embodiments, the deposition process is performed at about 25°C to about 600°C, such as about 400°C to about 600°C, and such as about 500°C. In certain embodiments, the deposition is a PVD process, and the target in the deposition chamber is negatively biased during the deposition process by a pulsed or continuous power supply providing DC power, the power level of the DC power being about 400W to about 1000W, such as about 600W to about 800W.
[0035] At operation 303, as Figure 4C shown, a high-power seed layer 109 is disposed over the bottom electrode 104. The high-power seed layer 109 is disposed via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition processes performed in a suitable chamber. In certain embodiments, the deposition process is performed at about 25°C to about 600°C, such as about 400°C to about 600°C, and such as about 500°C. In certain embodiments, the high-power seed layer 109 is deposited on the bottom electrode 104 when the target in the deposition chamber is negatively biased by a pulsed or continuous power supply providing DC power. The high-power seed layer 109 is deposited when the target in the deposition chamber is biased at a power level greater than about 3kW (such as about 6kW to about 20kW, such as about 8kW). The high-power seed layer 109 includes a high-power seed layer grain size and a high-power seed layer grain orientation.
[0036] At operation 304, asFigure 4D As shown, the piezoelectric layer 106 is disposed above the high-power seed layer 109. The piezoelectric layer 106 is disposed via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition processes performed in a suitable chamber. In certain embodiments, the deposition process is performed at about 25°C to about 600°C, such as about 400°C to about 600°C, and such as about 500°C. In certain embodiments, the deposition is a PVD process, and the target in the deposition chamber is negatively biased during the deposition process by a pulsed or continuous power supply providing DC power, and the power level of the DC power is about 400W to about 1000W, such as about 600W to about 800W. The piezoelectric layer 106 includes a piezoelectric grain size and a piezoelectric grain orientation. In one embodiment, the high-power seed layer grain size matches the piezoelectric grain size, and the high-power seed layer grain orientation matches the piezoelectric grain orientation.
[0037] The high-power deposition of the high-power seed layer 109 allows for a reduction in the loss tangent (LT) of the piezoelectric device 100. By reducing the LT of the piezoelectric device 100, the efficiency of the device is improved. The high-power deposition of the high-power seed layer 109 results in an increase in the nucleation of the piezoelectric layer 106, a stronger surface adhesion between the piezoelectric layer 106 and the high-power seed layer 109, an increase in the grain size and lattice orientation match between the high-power seed layer 109 and the piezoelectric layer 106, and a stronger crystal growth of the piezoelectric layer 106, which leads to higher performance. This increase in the material property match between the high-power seed layer 109 and the piezoelectric layer 106 results in an LT lower than about 1500 ppm, such as about 1300 ppm. For example, compared to a conventional piezoelectric device with a deposition layer of 3 kW, the LT of the conventional device is about 1500 ppm, while the LT of a high-power seed layer device deposited at 6 kW is about 1300 ppm (an improvement of about 13% compared to the conventional component). The high-power piezoelectric device can be improved compared to the conventional device when the LT loss reduction exceeds 7%, such as exceeding 13%, such as exceeding 15%.
[0038] At operation 305, as Figure 4E shown, the top electrode 108 is disposed above the piezoelectric layer 106. The top electrode 108 is disposed via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition processes performed in a suitable chamber. In certain embodiments, the deposition process is performed at about 25°C to about 600°C, such as about 400°C to about 600°C, and such as about 500°C. In certain embodiments, the deposition is a PVD process, and the target in the deposition chamber is negatively biased during the deposition process by a pulsed or continuous power supply providing DC power, and the power level of the DC power is about 400W to about 1000W, such as about 600W to about 800W.
[0039] At alternative operation 306, as Figure 4FAs shown, before depositing the top electrode 108, the intermediate electrode 208 is placed above the piezoelectric layer 106 to form an alternative piezoelectric device 200. The intermediate electrode 208 is placed by PVD, CVD, PECVD, ALD, inkjet printing, or other deposition processes performed in a suitable chamber. In some embodiments, the deposition process is performed at about 25°C to about 600°C, such as about 400°C to about 600°C, and such as about 500°C. In some embodiments, the deposition is a PVD process, and the target in the deposition chamber is negatively biased by a pulsed or continuous power supply providing DC power, and the power level of the DC power is about 400W to about 1000W, such as from about 600W to about 800W.
[0040] At alternative operation 307, as Figure 4G shown, the second high-power seed layer 209 is placed above the intermediate electrode 208. The second high-power seed layer 209 is placed via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition processes performed in a suitable chamber. In some embodiments, the deposition process is performed at about 25°C to about 600°C, such as about 400°C to about 600°C, and such as about 500°C. In some embodiments, the deposition is a PVD process, and the second high-power seed layer 209 is deposited while the target in the second deposition chamber is negatively biased by a pulsed or continuous power supply providing DC power. The second high-power seed layer 209 is deposited when the power level of the target in the deposition chamber is greater than about 3 kW (such as about 6 kW to about 20 kW, such as about 8 kW). The second high-power seed layer 209 includes a second high-power seed layer grain size and a second high-power seed layer grain orientation.
[0041] In alternative operation 308, as Figure 4H shown, the second piezoelectric layer 206 is placed above the second high-power seed layer 209. The second piezoelectric layer 206 is placed via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition processes performed in a suitable chamber. In some embodiments, the deposition process is performed at about 25°C to about 600°C, such as about 400°C to about 600°C, and such as about 500°C. In some embodiments, the deposition is a PVD process, and the target in the deposition chamber is negatively biased by a pulsed or continuous power supply providing DC power during the deposition process, and the power level of the DC power is about 400W to about 1000W, such as about 600W to about 800W. The second piezoelectric layer includes a second piezoelectric grain size and a second piezoelectric grain orientation. In one embodiment, the second high-power seed layer grain size matches the second piezoelectric grain size, and the second high-power seed layer grain orientation matches the second piezoelectric grain orientation.
[0042] The high-power deposition of the second high-power seed layer 209 allows for a reduction in the loss tangent (LT) of the alternative piezoelectric device 200. By reducing the LT of the piezoelectric device 200, the efficiency of the device is improved. The high-power deposition of the second high-power seed layer 209 results in increased nucleation of the second piezoelectric layer 206, stronger surface adhesion between the second piezoelectric layer 206 and the second high-power seed layer 209, increased grain size and grain orientation matching between the second high-power seed layer 209 and the second piezoelectric layer 206, and stronger crystal growth of the second piezoelectric layer 206, which leads to higher performance. This increase in the material property match between the high-power seed layer 109 and the piezoelectric layer 106 results in an LT of less than about 1500 ppm, such as about 1300 ppm. For example, compared to a conventional piezoelectric device with a 3 kW deposited layer, the LT of the conventional device is about 1500 ppm, while the LT of a high-power seed layer assembly deposited at 6 kW is about 1300 ppm (about 13% improvement over the conventional device). The high-power piezoelectric device can be improved compared to the conventional device when the LT loss reduction exceeds 7%, such as more than 13%, such as more than 15%.
[0043] In alternative operation 309, as Figure 4I shown, the top electrode 108 is disposed over the second piezoelectric layer 206. The top electrode 108 is disposed via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition processes performed in a suitable chamber. In certain embodiments, the deposition process is performed at about 25°C to about 600°C, such as about 400°C to about 600°C, and such as about 500°C. In certain embodiments, the deposition is a PVD process, and the target in the deposition chamber is negatively biased during the deposition process by a pulsed or continuous power supply providing DC power, the power level of the DC power being about 400 W to about 1000 W, such as about 600 W to about 800 W.
[0044] In alternative operations 306 to 309, the subsequent deposition of the electrodes, high-power seed layer, and piezoelectric layer can be repeated by the user to achieve the desired thickness and functionality of the piezoelectric device.
[0045] Figure 5 is a schematic cross-sectional view of a laser etching system 500. The laser etching system is used in a method for patterning a piezoelectric layer with the laser etching system 500 during the manufacture of the piezoelectric device 100.
[0046] The laser etching system 500 includes a substrate 102 disposed on the surface of a worktable 502. The substrate 102 may also include a bottom electrode 104 and a piezoelectric layer 106 disposed thereon. In some embodiments, a top electrode 108 is also disposed above the bottom electrode 104. In some embodiments, a primary seed layer 101 is disposed between the bottom electrode 104 and the substrate 102. In some embodiments, a high-power seed layer 109 is disposed between the piezoelectric layer 106 and the bottom electrode 104. In some embodiments, an intermediate electrode 208 is disposed above the piezoelectric layer 106. A second high-power seed layer 209 is disposed above the intermediate electrode 208. A second piezoelectric layer 206 is disposed above the second high-power seed layer 209. The top electrode 108 is disposed above the second piezoelectric layer 206.
[0047] The worktable 502 is disposed in the laser etching system 500 such that the surface of the worktable 502 is positioned opposite a scanner 504. The scanner 504 includes a laser source 514, an optical array 516, and a laser 506 extending from the optical array 516. The laser etching system 500 is operable to etch the piezoelectric layer 106 or the second piezoelectric layer 206 to expose the bottom electrode 104 or the intermediate electrode 208. The laser etching system 500 is operable to provide a laser pulse to the substrate 102 such that the piezoelectric layer 106 is etched. The laser etching system 500 includes a controller 508. The controller 508 communicates with the worktable 502 and the scanner 504.
[0048] The controller 508 is generally designed to facilitate the control and automation of aspects of the methods described herein. The controller 508 may be coupled or in communication with the laser source 514, the optical array 516, the worktable 502, and the scanner 504. The worktable 502 and the scanner 504 may provide information to the controller 508 regarding the method and the alignment of the substrate 102. The controller 508 may communicate or be coupled with a CPU (i.e., a computer system). The CPU may be a hardware unit or a combination of hardware units capable of executing software applications and processing data. In some configurations, the CPU includes a central processing unit (CPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a graphics processing unit (GPU), and / or a combination of such units. The CPU is generally configured to execute one or more software applications and process stored media data. The controller 508 may include a non-volatile computer-readable medium for storing instructions for forming a cutting path along the substrate as described herein. The non-volatile computer-readable medium may be part of the CPU.
[0049] The laser 506 is a fiber laser. In one embodiment combinable with other embodiments described herein, the laser 506 has a Gaussian beam profile. In another embodiment combinable with other embodiments described herein, the laser 506 is an ultraviolet (UV) laser. In another embodiment combinable with other embodiments described herein, the laser 506 is an infrared laser. In another embodiment combinable with other embodiments described herein, the laser 506 has a Bessel-type beam profile. In yet other embodiments, the laser 506 is a multi-focus laser and uses a bi-focal lens as part of the optical array 516. Multiple lenses may also be used in the optical array 516 to diffract the laser 506 and form multiple foci in the substrate 102. The laser 506 communicates with the controller 508. The controller 508 may control other input parameters or output parameters of the laser 506.
[0050] The stage 502 includes a stage actuator 510. The stage actuator 510 allows the stage 502 to scan in the X, Y, and Z directions, as indicated by the coordinate system shown Figure 5 The stage 502 is coupled to the controller 508 to provide position information of the stage 502 to the controller 508. Additionally, the stage 502 communicates with the controller 508 such that the stage 502 can be moved in a desired direction to etch the piezoelectric layer 106.
[0051] The scanner 504 includes a scanner actuator 512. The scanner actuator 512 allows the scanner 504 to scan in the X, Y, and Z directions, as indicated by the coordinate system shown Figure 5 The laser source 514 and the optical array 516 are disposed in or on the scanner 504. The scanner 504 is coupled to the controller 508 to provide position information of the scanner 504 to the controller 508. In one embodiment combinable with other embodiments described herein, the scanner 504 is a galvoscanner.
[0052] In one embodiment combinable with other embodiments described herein, the laser etching system 500 that performs the method for etching can utilize both the scanner 504 and the stage 502 to direct the laser 506 onto the substrate 102. In another embodiment combinable with other embodiments described herein, the laser etching system 500 that performs the method for etching can utilize only the scanner 504 to direct the laser 506 onto the substrate 102. In yet another embodiment combinable with other embodiments described herein, the laser etching system 500 that performs the method for etching can utilize only the stage 502 to direct the laser 506 onto the substrate 102.
[0053] In general, the present disclosure provides piezoelectric devices and methods of patterning piezoelectric layers for use in the manufacture of piezoelectric devices. The loss tangent (LT) property of a piezoelectric device can significantly affect the performance of the device. By depositing a high-power seed layer at high power, the property match between the high-power seed layer and the piezoelectric layer is optimized, thereby reducing the LT and resulting in a significant performance improvement.
[0054] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be conceived without departing from the basic scope thereof, and the scope of the present disclosure is determined by the appended claims.
Claims
1. A method of forming a piezoelectric device, the method comprising: Placing a bottom electrode above a substrate; Placing a high-power seed layer above the bottom electrode via physical vapor deposition with a target bias power greater than 3 kW; Placing a piezoelectric layer above the bottom electrode; And Forming a top electrode in a top electrode pattern above the piezoelectric layer.
2. The method of claim 1, the method further comprising placing a primary seed layer between the substrate and the bottom electrode.
3. The method of claim 2, wherein the primary seed layer, the bottom electrode, the piezoelectric layer, and the top electrode are placed using one of physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or inkjet printing.
4. The method of claim 1, wherein the piezoelectric device has a loss tangent (LT) of less than 1500 ppm.
5. The method of claim 1, wherein the piezoelectric device has a loss tangent (LT) of less than 1300 ppm.
6. The method of claim 1, wherein the high-power seed layer comprises aluminum nitride (AlN) or scandium-doped aluminum nitride (ScAlN).
7. The method of claim 1, the method further comprising: Placing an intermediate electrode above the piezoelectric layer; Placing a second high-power seed layer above the intermediate electrode with a target bias power greater than 3 kW; And Placing a second piezoelectric layer above the bottom electrode.
8. The method of claim 7, wherein the bottom electrode, the intermediate electrode, and the top electrode comprise one or more of the following: platinum (Pt), molybdenum (Mo), SrRuO3, LaNiO3, CaRuO3, or LaSrMnO3.
9. The method of claim 7, wherein the second high-power seed layer comprises aluminum nitride (AlN) or scandium-doped aluminum nitride (ScAlN).
10. The method of claim 7, wherein the piezoelectric layer and the second piezoelectric layer comprise one or more of the following: aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), lead magnesium niobate-titanate (PMN-PT), or LaNiO3 (LNO).
11. A piezoelectric device, the piezoelectric device comprising: A bottom electrode placed above a substrate; A high-power seed layer placed above the bottom electrode, the high-power seed layer having a high-power seed layer grain size and a high-power seed layer grain orientation; A piezoelectric layer placed above the high-power seed layer, the piezoelectric layer having a piezoelectric grain size and a piezoelectric grain orientation, wherein the high-power seed layer grain size matches the piezoelectric grain size, and the high-power seed layer grain orientation matches the piezoelectric grain orientation; And A top electrode placed above the piezoelectric layer.
12. The piezoelectric device of claim 11, wherein the piezoelectric layer further comprises: An intermediate electrode disposed above the piezoelectric layer; A second high-power seed layer disposed above the intermediate electrode, the second high-power seed layer having a second high-power seed layer grain size and a second high-power seed layer grain orientation; And A second piezoelectric layer disposed above the second high-power seed layer, the second piezoelectric layer having a second piezoelectric grain size and a second piezoelectric grain orientation, wherein the second high-power seed layer grain size matches the second piezoelectric grain size, and the second high-power seed layer grain orientation matches the second piezoelectric grain orientation.
13. The piezoelectric device according to claim 12, wherein the piezoelectric device has a loss tangent (LT) of less than 1500 ppm.
14. The piezoelectric device according to claim 12, wherein the piezoelectric device has a loss tangent (LT) of less than 1300 ppm.
15. A method of forming a piezoelectric device, the method comprising: Disposing a bottom electrode above a substrate; Disposing a high-power seed layer above the bottom electrode at a target bias power greater than 3 kW; Disposing a piezoelectric layer above the bottom electrode; And Disposing an intermediate electrode above the piezoelectric layer; Disposing a second high-power seed layer above the intermediate electrode at a target bias power greater than 3 kW; And Disposing a second piezoelectric layer above the bottom electrode; And Disposing a top electrode above the piezoelectric layer.
16. The method according to claim 15, the method further comprising disposing a primary seed layer between the substrate and the bottom electrode.
17. The method according to claim 16, wherein the primary seed layer, the bottom electrode, the piezoelectric layer, the intermediate electrode, the second piezoelectric layer, and the top electrode are disposed using one of physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or inkjet printing.
18. The method according to claim 15, wherein the bottom electrode, the intermediate electrode, and the top electrode comprise one or more of the following: platinum (Pt), molybdenum (Mo), SrRuO3, LaNiO3, CaRuO3, or LaSrMnO3.
19. The method according to claim 15, wherein the high-power seed layer and the second high-power seed layer comprise aluminum nitride (AlN) or scandium-doped aluminum nitride (ScAlN).
20. The method according to claim 15, wherein the piezoelectric layer and the second piezoelectric layer comprise one or more of the following: aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), lead magnesium niobate-lead titanate (PMN-PT), or LaNiO3 (LNO).