DIE test method, test system, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a DIE test method and system, electronic equipment and a storage medium, and belongs to the technical field of memories. The method comprises the steps that a first connector and a second connector on a target probe board card are connected in an inserted mode, an installation groove is further formed in the target probe board card, and a probe electrically connected with the second connector is arranged in the installation groove so that a bare chip to be tested installed in the installation groove can be electrically connected with the second connector; obtaining target ball position layout data of the bare chip to be tested; and according to the target ball position layout data, wafer probe testing is carried out on the bare chip to be tested through the first connector and the second connector. The test mainboard is used as a universal board, and the target probe board card is detachably connected with the test mainboard, so that one test mainboard can be adapted to the test of a plurality of chips to be tested under various different models, and the test system is simpler and lower in cost.

Description

Technical Field

[0001] This application relates to the technical field of memory, and in particular, to a DIE testing method, a testing system, an electronic device, and a storage medium. Background Art

[0002] Wafer probe testing, namely Chip Probing, is a key link in the chip manufacturing process. The main purposes include screening out unqualified chips, reducing packaging costs, estimating the electrical performance parameters of devices and circuits, and detecting chip functions to ensure design compliance. In related technologies, usually, an installation slot for accommodating a bare chip (DIE) to be tested is provided in a test main board. The bare chip to be tested is fixed in the test main board, and the test main board is used to test the bare chip to be tested. When different bare chips to be tested need to be tested, different test main boards need to be replaced. And corresponding test programs are loaded on different test main boards, resulting in a more complex and costly test system based on wafer probe testing in related technologies. Summary of the Invention

[0003] The main purpose of the embodiments of this application is to propose a DIE testing method, a testing system, an electronic device, and a storage medium, which can reduce the complexity of the testing system for wafer probe testing and reduce the testing cost.

[0004] To achieve the above object, a first aspect of the embodiments of this application proposes a DIE testing method, which is applied to a test main board. A first connector is provided on the test main board. The method includes: Plug the first connector into a second connector on a target probe card. The target probe card further has an installation slot, and probes electrically connected to the second connector are provided in the installation slot to electrically connect the bare chip to be tested installed in the installation slot and the second connector; Obtain the target ball position layout data of the bare chip to be tested; According to the target ball position layout data, perform wafer probe testing on the bare chip to be tested through the first connector and the second connector.

[0005] To achieve the above object, a second aspect of the embodiments of this application proposes a DIE testing system. The DIE testing system includes: A host computer; A test main board, which is communicatively connected to the host computer; a first connector is provided on the test main board; Multiple probe boards, each of which is provided with a second connector detachably connected to the first connector. An installation groove is also provided in the probe board, and a probe electrically connected to the second connector is arranged in the installation groove. The probe is used to electrically connect the bare chip under test installed in the installation groove and the second connector; Wherein, when one of the probe boards is used as the target probe board, the test main board executes the method described in any one of the first aspects to perform wafer probe testing on the bare chip under test in the installation groove of the target probe board.

[0006] To achieve the above object, a third aspect of the embodiments of the present application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the DIE testing method described in any one of the first aspects is implemented.

[0007] To achieve the above object, a fourth aspect of the embodiments of the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the DIE testing method described in any one of the first aspects is implemented.

[0008] The DIE testing method, testing system, electronic device and storage medium provided by the present application make the test main board a general board and provide probe boards corresponding to each chip model one by one. Therefore, when testing multiple bare chips under test, only the corresponding probe board needs to be selected as the target probe board and detachably connected to the test main board through the first connector and the second connector. At this time, the test main board can automatically match the test cases and the target ball position layout data of the chips under test on the target probe board, and the wafer probe testing of each chip under test of different models can be realized automatically. At this time, since the test main board only needs to be replaced synchronously with the target probe board connected to it when the signal of the bare chip under test changes without any change, the degree of automation can be higher. Therefore, compared with the related art, the embodiments of the present application can adapt a test main board to the testing of multiple chips under test of multiple different models, and the testing system is simpler and the cost is lower. Description of the Drawings

[0009] Figure 1 It is a schematic diagram of the system framework of the testing system corresponding to the DIE testing method provided by the present application; Figure 2 It is a schematic flowchart of an embodiment of the DIE testing method provided by the present application; Figure 3 It is a schematic diagram of the testing steps in an embodiment of the DIE testing method provided by the present application; Figure 4It is a schematic diagram of the hardware structure of the device corresponding to the DIE test method provided by this application.

[0010] Reference numerals: Host computer 100, Test main board 200, first connector 210, Probe card 300, second connector 310, mounting groove 320. Detailed implementation manners

[0011] In order to make the objectives, technical solutions and advantages of this application clearer, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0012] It should be noted that although functional module division is performed in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different module division in the device or a different order in the flowchart. Terms such as "first" and "second" in the description, claims and the above-mentioned drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence.

[0013] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0014] First, several terms involved in this application are analyzed: DIE, that is, a chip, is a small piece of semiconductor material in an integrated circuit, on which a given functional circuit is manufactured.

[0015] Refer to Figure 1 As shown, according to a DIE test system provided by an embodiment of this application, the DIE test system includes: Host computer 100; Test main board 200, the test main board 200 is communicatively connected to the host computer 100; a first connector 210 is provided on the test main board 200; Multiple probe cards 300, each probe card 300 is provided with a second connector 310 detachably connected to the first connector 210, and an installation groove 320 is further provided in the probe card 300. Probes electrically conductive with the second connector 310 are provided in the installation groove 320, and the probes are used to electrically connect the bare chip under test installed in the installation groove 320 and the second connector 310; Among them, when one of the probe cards 300 is used as the target probe card 300, the test main board 200 performs the following steps: Plug the first connector 210 into the second connector 310 on the target probe card 300. Among them, an installation groove 320 is also provided in the target probe card 300, and probes electrically connected to the second connector 310 are provided in the installation groove 320 to electrically connect the bare chip under test installed in the installation groove 320 and the second connector 310; Obtain the target ball position layout data of the bare chip under test; According to the target ball position layout data, perform wafer probe testing on the bare chip under test through the first connector 210 and the second connector 310.

[0016] It can be understood that in some embodiments, a power module, an indication module, and an algorithm module are integrated on the test main board 200. The power module is used to provide power for the test main board 200 and provide different powers for the bare chip under test. The indication module can indicate the test process or test results by setting indicator lights. For example, when the bare chip under test is in the test, it controls the indicator light to display one color. Another example is that if the test result indicates that the test passes, it controls the indicator light to display another color. Another example is that if the test result indicates that the test fails, it controls the indicator light to display another color, and so on. The algorithm module can be used to provide a test logic adapted to the bare chip under test, such as providing test cases corresponding one by one to the signals of the bare chip.

[0017] The first connector 210 and the second connector 310 determine the flow direction of test data during the test process. In some embodiments, both the first connector 210 and the second connector 310 are set as high-speed connectors, so as to ensure the accuracy of the test results. The embodiments of the present application do not limit the model of the high-speed connector, and those skilled in the art can selectively set it according to actual needs. In some embodiments, when it is necessary to test the read and write functions of the bare chip under test, the DQ signal pins, CA signal pins, etc. of the bare chip under test can be connected to the test main board 200 through the first connector 210 and the second connector 310. In other embodiments, different signal pins can also be selected according to actual needs to be connected to the test main board 200 for function and / or electrical testing. In this regard, the embodiments of the present application do not make restrictions, and those skilled in the art can selectively set according to actual needs.

[0018] It can be understood that the test main board 200 realizes data communication with the bare chip under test through the SOC interface, and the first connector 210 and the second connector 310 serve as physical interfaces to carry data transmission between the SOC interface and the bare chip under test. In this way, the test efficiency can be improved and the difficulty of fault location can be reduced.

[0019] In some embodiments, an anti-fooling structure and a locking structure are provided on the second connector 310, so that the first connector 210 and the second connector 310 can protect the connectors during the automatic connection process and reduce the probability of the connectors loosening during the test. For example, when replacing the bare chips to be tested of the same model, the first connector 210 and the second connector 310 are not easily loosened due to the existence of the locking structure, thereby affecting the test results. The embodiments of the present application do not limit the specific structures of the anti-fooling structure and the lock, and those skilled in the art can selectively set them according to actual needs.

[0020] The host computer 100 is used to provide a user operation interface to visualize the test results and provide an interface to implement parameter configuration during the wafer probe test. The embodiments of the present application do not limit how to design the interface of the host computer 100, and those skilled in the art can selectively set it according to the actual situation. By setting the host computer 100, remote monitoring of the test results and the test process can be achieved.

[0021] It can be understood that, as shown in Figure 2 According to a DIE test method provided by an embodiment of the present application, which is applied to a test main board 200, a first connector 210 is provided on the test main board 200, and the method includes: Step S100: Plug the first connector 210 and the second connector 310 on the target probe card 300. Among them, an installation slot 320 is further provided in the target probe card 300, and a probe electrically connected to the second connector 310 is provided in the installation slot 320 to electrically connect the bare chip to be tested installed in the installation slot 320 and the second connector 310; Step S200: Obtain the target ball position layout data of the bare chip to be tested; Step S300: According to the target ball position layout data, perform wafer probe testing on the bare chip to be tested through the first connector 210 and the second connector 310.

[0022] Therefore, by using the test main board 200 as a general board and providing the probe board cards 300 corresponding to each chip model one by one, when testing multiple bare chips to be tested, only the corresponding probe board card 300 needs to be selected as the target probe board card 300 and detachably connected to the test main board 200 through the first connector 210 and the second connector 310. At this time, the test main board 200 can automatically match the test cases with the target ball position layout data of the chips to be tested on the target probe board card 300, and thus the wafer probe test of each chip to be tested with different models can be automated. At this time, since the test main board 200 only needs to synchronously replace the connected target probe board card 300 when the signals of the bare chips to be tested change without any modification, the degree of automation can be higher. Therefore, the embodiment of the present application can adapt to the tests of multiple chips to be tested under multiple different models through one test main board 200, and the test system is simpler and the cost is lower.

[0023] The embodiment of the present application does not limit how the first connector 210 and the second connector 310 are plugged. Those skilled in the art can set an automatic plugging and unplugging device to realize the automatic plugging and unplugging of the first connector 210 and the second connector 310. In other embodiments, the plugging and unplugging between the first connector 210 and the second connector 310 can also be realized manually.

[0024] The target probe board card 300 is a probe board card 300 corresponding to each model of the bare chip to be tested one by one. The installation groove 320 is used to install the bare chip to be tested. The embodiment of the present application does not limit the structure of the installation groove 320.

[0025] The first connector 210 and the second connector 310 are used to realize the physical connection between the test main board 200 and the bare chip to be tested.

[0026] The target ball position layout data records the association relationship between each solder ball and the signal in the bare chip to be tested, so that the function of the signal pin corresponding to each port of the second connector 310 can be determined based on the target ball position layout data. At this time, on the premise of determining the solder pins involved in the test case, the port of the second connector 310 through which the test case flows can be clarified based on the target ball position layout data, and thus the automatic test of the bare chip to be tested can be realized.

[0027] The embodiment of the present application does not limit the test items involved in the wafer probe test. Those skilled in the art can selectively set according to actual needs. For example, the wafer probe test includes at least one of electrical test, performance test and function test. Among them, the function test includes read and write operations, etc. The electrical test includes voltage test, resistance test, etc. Among them, the electrical test results can be obtained through an external test instrument.

[0028] It is understandable that obtaining the target ball position layout data of the bare chip to be tested includes: In response to a layout import request, extracting the chip model of the bare chip to be tested from the layout import request; According to the chip model, querying the matching target ball position layout file from a preset configuration library; Obtaining the target ball position layout data according to the target ball position layout file.

[0029] By saving the ball position layout file in the configuration library and determining the target ball position layout file through the chip signal, when testing bare chips of different production batches of the same model, the automatic matching of test cases can be achieved by directly importing the ball position layout file, improving the test efficiency.

[0030] The chip model can trigger the layout import request through configuration on the visual interface, or can automatically trigger the layout import request through the content in the preset test sequence file, or can generate the layout import request after directly scanning to obtain the chip signal. In this regard, the embodiments of the present application do not limit how to trigger the layout import request.

[0031] The target ball position layout file is the ball position layout file corresponding one-to-one to the chip model of the target probe card 300.

[0032] The target ball position layout file defines the signals corresponding one-to-one to each solder ball on the bare chip. For example, based on the target ball position layout file, the positions of the solder balls of DQ signals / power supply signals / CA signals and differential CLK / DQS signals, etc. in the bare chip can be quickly identified, that is, the solder pins connected to each port in the second connector 310 can be determined, so that the mapping relationship between each port of the first connector 210 and each solder pin can be determined through the mapping relationship between the ports of the first connector 210 and the second connector 310.

[0033] It is understandable that according to the target ball position layout data, wafer probe testing of the bare chip to be tested is performed through the first connector 210 and the second connector 310, including: According to the target ball position layout data, determining the first mapping relationship between the second connector 310 and each pin to be tested on the bare chip to be tested; Obtaining the second mapping relationship between each port when the first connector 210 and the second connector 310 are electrically connected; According to the first mapping relationship and the second mapping relationship, determining the third mapping relationship between each port of the first connector 210 and each pin to be tested on the bare chip to be tested; Performing wafer probe testing on the bare chip to be tested according to the third mapping relationship.

[0034] The second mapping relationship is pre-configured. In some embodiments, the number of ports of the second connectors 310 on different probe cards 300 is different. At this time, the connection states of the ports of the first connector 210 can be detected in sequence, so that the second mapping relationship between the ports when the first connector 210 and the second connector 310 are electrically connected can be obtained.

[0035] Through the third mapping relationship, the data flow of the test data in each test case for testing can be determined without manual configuration, so that the requirements of automated testing can be met, and the test cost can be reduced by reducing the probability of human participation.

[0036] The pins to be tested are the pins participating in the wafer test among the soldered pins on the bare chip to be tested.

[0037] It can be understood that wafer probe testing of the bare chip to be tested according to the third mapping relationship includes: According to the third mapping relationship, determine the first target port and the second target port in the first connector 210 that correspond one-to-one to the target ports of the pins with the functions to be tested and the pins to be tested electrically on the bare chip to be tested; Generate a target test case according to the first target port and the second target port; Perform wafer probe testing on the bare chip to be tested according to the target test case.

[0038] By classifying the ports on the first connector 210 respectively to obtain the first target port and the second target port, the target test case related thereto can be determined more quickly.

[0039] The embodiments of the present application do not limit how the target test case is generated. In some embodiments, it can be obtained through the graphical operation of the host computer 100. In other embodiments, based on the historical test cases, by adding transmission instructions towards the first target port and the second target port in the historical test cases, it can be ensured that the test data in the test case can be sent to the bare chip to be tested through the corresponding first target port or second target port.

[0040] It can be understood that generating a target test case according to the first target port and the second target port includes: Obtain a test case file; Determine the test instructions corresponding to the first target port and the second target port in the test case file; Package the first target port and the corresponding test instructions and package the second target port and the corresponding test instructions to obtain a target test case.

[0041] The test case file is a collection of test instructions supported by bare chips to be tested of various different chip models and the test logic corresponding to the test instructions.

[0042] By setting the test case file, the design of test items can be decoupled from the actual test network, and automatic adaptation can be performed according to the network connection situation in actual applications, so that the test process can be simplified, and the test cost and the complexity of the test system can be reduced.

[0043] It can be understood that after performing wafer probe testing on the bare chip to be tested through the first connector 210 and the second connector 310 according to the target ball position layout data, the method further includes: Obtaining the test result of the wafer probe test and the chip identification data of the bare chip to be tested; Generating the qualified product identification data and classification display data of the bare chip to be tested according to the test result; Binding and displaying the qualified product identification data, the chip identification data, and the classification display data.

[0044] The chip identification data is used to identify the bare chip to be tested and corresponds one-to-one with the bare chip to be tested. It can be a custom ID or the chip code of the bare chip to be tested. The test result is the result feedback after testing based on the target test. The classification display data is used to classify the test result according to the test item, so that the cause of the failure can be determined more intuitively.

[0045] In some embodiments, multiple bare chips to be tested are provided. Binding and displaying the qualified product identification data, the chip identification data, and the classification display data can distinguish different bare chips to be tested, which is more convenient for managing the test results in the test scenario of multiple bare chips to be tested.

[0046] It can be understood that before performing wafer probe testing on the bare chip to be tested through the first connector 210 and the second connector 310 according to the target ball position layout data, the method further includes: Determining the in-position state of the bare chip to be tested through the first connector 210 and the second connector 310; When it is detected that there is a bare chip to be tested in the installation slot 320, perform wafer probe testing on the bare chip to be tested through the first connector 210 and the second connector 310 according to the target ball position layout data.

[0047] By implementing the detection of the in-position state of the bare chip to be tested, when multiple bare chips to be tested of the same model are tested in sequence, automatic testing of multiple bare chips to be tested can be achieved, further simplifying the test process and improving the test efficiency.

[0048] The following refers to Figure 3As shown, a DIE test method according to an embodiment of the present application is described. In the method, a test main board 200 sends test-related data to a first connector 210 through an SOC interface to implement the test of a bare chip to be tested. Taking the case where there are multiple bare chips to be tested and multiple models are set as an example, reference is made to Figure 3 as shown: Step 1: Determine the bare chip to be tested, and use the probe card 300 corresponding to the bare chip to be tested as the target probe card 300. For example, in some embodiments, multiple bare chips waiting to be tested and the probe card 300 are respectively managed in different bins. After determining the bare chip to be tested at the current moment, the probe card 300 corresponding to the bare chip to be tested can be selected according to a preset matching relationship.

[0049] Step 2: Connect the test main board 200 and the target probe card 300 through a connector. Among them, a first connector 210 is provided on the test main board 200, and a second connector 310 detachably plugged into the second connector 310 is provided on the target probe card 300. Both the first connector 210 and the second connector 310 are high-speed connectors. In some embodiments, the interiors of the first connector 210 and the second connector 310 are made of gold-plated materials and are provided with anti-fooling and locking structures; to ensure that abnormal plugging will not occur during the replacement or plugging of the bare chip, thereby affecting the test results.

[0050] Step 3: Turn on the host computer 100 and power on the test main board 200 at the same time; Step 4: Import a test configuration file into the test main board 200 through the host computer 100 and start the test. The test main board 200 implements wafer probe testing of the bare chip to be tested based on the test configuration file. Among them, the test configuration file includes: a target ball position layout file and a test case file.

[0051] Step 5: During the test, the test main board 200 communicates with the host computer 100 in real time, feeds back the test status and results, and displays them on the interface of the host computer 100.

[0052] When the bare chip at the current moment has completed the above steps 1 to 5, use the bare chip of the same model as the bare chip to be tested again, replace the bare chip in the target probe board and restart the test. When the test of the bare chip of this model is completed, refer to steps 1 to 5 to re-determine the target probe board and the bare chip to be tested, and re-import the test configuration file for testing.

[0053] An embodiment of the present application also provides an electronic device. The electronic device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the above DIE test method is implemented. The electronic device can be any intelligent terminal including a tablet computer, an in-vehicle computer, etc.

[0054] Please refer to Figure 4 , Figure 4 which schematically shows the hardware structure of an electronic device according to another embodiment. The electronic device includes: A processor 401, which can be implemented in ways such as a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application; A memory 402, which can be a NAND flash. The relevant program codes are stored in the memory 402 and are called by the processor 401 to execute the DIE test method of the embodiments of the present application; An input / output interface 403, which is used to implement information input and output; A communication interface 404, which is used to implement communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or through wireless means (such as mobile network, WIFI, Bluetooth, etc.); A bus 405, which transmits information between various components of the device (such as the processor 401, the memory 402, the input / output interface 403, and the communication interface 404); Among them, the processor 401, the memory 402, the input / output interface 403, and the communication interface 404 are communicatively connected to each other inside the device through the bus 405.

[0055] The embodiments of the present application also provide a computer-readable storage medium. The computer-readable storage medium is a computer-readable storage medium. This storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned DIE test method is implemented.

[0056] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory can include high-speed random access memory, and can also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory optionally includes a memory remotely provided relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above-mentioned network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0057] The embodiments described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0058] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than those shown in the figures, or combine certain steps, or different steps.

[0059] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0060] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and their appropriate combinations.

[0061] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0062] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects and indicates that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item) of the following" or its similar expression refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0063] In several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the above division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be in electrical, mechanical or other forms.

[0064] The units described above as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0065] In addition, the functional units in each embodiment of this application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0066] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes: various media that can store programs, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0067] The preferred embodiments of the embodiments of this application have been described above with reference to the accompanying drawings. However, this does not limit the scope of the rights of the embodiments of this application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of this application shall fall within the scope of the rights of the embodiments of this application.

Claims

1. A DIE testing method, characterized in that: Applied to a test mainboard, the test mainboard is provided with a first connector, the method comprises: Inserting the first connector into a second connector on a target probe card, wherein the target probe card is further provided with an installation slot, wherein the installation slot is provided with a probe electrically connected to the second connector, so as to electrically connect the bare chip to be tested installed in the installation slot with the second connector; Acquiring target ball position layout data of the bare chip to be tested; According to the target ball position layout data, a wafer probe test is performed on the bare chip to be tested through the first connector and the second connector.

2. The DIE testing method according to claim 1, characterized in that: The step of obtaining target ball position layout data of the bare chip to be tested comprises: In response to a layout import request, extracting a chip model of the bare chip to be tested from the layout import request; According to the chip model, a matching target ball position layout file is searched from a preset configuration library; The target ball position layout data is obtained according to the target ball position layout file.

3. The DIE testing method according to claim 1, characterized in that: The step of performing a wafer probe test on the bare chip to be tested through the first connector and the second connector according to the target ball position layout data comprises: Determine a first mapping relationship between the second connector and each pin to be tested on the bare chip to be tested according to the target ball position layout data; Acquire a second mapping relationship between ports of the first connector and the second connector when the first connector and the second connector are electrically connected; Determine, according to the first mapping relationship and the second mapping relationship, a third mapping relationship between each port of the first connector and each pin to be tested on the bare chip to be tested; According to the third mapping relationship, a wafer probe test is performed on the bare chip to be tested.

4. The DIE testing method according to claim 3, characterized in that: The step of performing a wafer probe test on the bare chip to be tested according to the third mapping relationship includes: According to the third mapping relationship, determine a first target port and a second target port in the first connector that correspond one-to-one to the target ports of the functional pins to be tested on the bare chip to be tested and the electrical pins to be tested; Generate a target test case according to the first target port and the second target port; Performing a wafer probe test on the bare chip to be tested according to the target test case.

5. The DIE testing method according to claim 4, characterized in that: The generating a target test case according to the first target port and the second target port includes: Get the test case file; Determining in the test case file a test instruction corresponding to the first target port and the second target port; The first target port and the corresponding test instruction are encapsulated, and the second target port and the corresponding test instruction are encapsulated to obtain a target test case.

6. The DIE testing method according to claim 1, characterized in that: After performing a wafer probe test on the bare chip to be tested through the first connector and the second connector according to the target ball position layout data, the method further includes: Obtaining the test result of the wafer probe test and the chip identification data of the bare chip to be tested; According to the test results, generating good product identification data and classification display data of the bare chip to be tested; The good product identification data, the chip identification data and the classification display data are bound and displayed.

7. The DIE testing method according to claim 1, characterized in that: Before performing a wafer probe test on the bare chip to be tested through the first connector and the second connector according to the target ball position layout data, the method further includes: Determining the in-place status of the bare chip to be tested through the first connector and the second connector; When it is detected that the bare chip to be tested exists in the mounting slot, a wafer probe test is performed on the bare chip to be tested through the first connector and the second connector according to the target ball position layout data.

8. A DIE testing system, characterized in that: The DIE test system includes: Host computer; A test mainboard, the test mainboard is communicatively connected with the host computer; the test mainboard is provided with a first connector; A plurality of probe cards, each of which is provided with a second connector detachably connected to the first connector, and a mounting slot is further provided in the probe card, wherein a probe electrically connected to the second connector is provided in the mounting slot, and the probe is used to electrically connect a bare chip to be tested installed in the mounting slot with the second connector; Wherein, when one of the probe cards is used as a target probe card, the test mainboard executes the method according to claim 1 to perform a wafer probe test on the bare chip to be tested in the installation slot of the target probe card.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, the memory stores a computer program, and the processor implements the DIE testing method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the DIE testing method according to any one of claims 1 to 7 is implemented.

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