Array substrate and display device

Abstract

Signal delay is suppressed by reducing parasitic capacitance. An array substrate (21) is provided with: a gate wiring (26); a source wiring (27) that intersects the gate wiring (26); a switching element (23) provided at an intersection between the gate wiring (26) and the source wiring (27); a semiconductor film (23A) provided on the switching element (23); a first insulating film (F2) interposed between the gate wiring (26) and the semiconductor film (23A); and a second insulating film (F4) interposed between the semiconductor film (23A) and the source wiring (27). The source wiring (27) overlaps the gate wiring (26) with the first insulating film (F2) and the second insulating film (F4) therebetween.

Description

Technical Field

[0001] The technology disclosed in this specification relates to an array substrate and a display device. Background Art

[0002] The following Patent Document 1 discloses an array substrate for a liquid crystal display device. In the array substrate described in Patent Document 1, by increasing the thickness of the wiring, the cross-sectional area becomes larger and the resistance value decreases. When the resistance value decreases, the time constant becomes smaller, and the delay of the signal can be suppressed.

[0003] Prior art literature Patent Literature Patent Document 1: Patent No. 4592677 Summary of the invention Technical Problems to be Solved by the Invention The time constant τ of the signal transmission circuit (RC circuit) is expressed by τ=RC, and depends on the electrostatic capacitance (parasitic capacitance) C in addition to the resistance value R. Due to the driving voltage of the transistor of the input signal, the resistance value of the peripheral circuit, etc., reducing the parasitic capacitance of the transmission circuit is more effective in suppressing signal delay than reducing the resistance value of the transmission circuit.

[0004] The technology disclosed in this specification is a technology that has been accomplished based on the above-mentioned circumstances, and its purpose is to reduce the parasitic capacitance of wiring and suppress signal delay.

[0005] Technical solutions for solving technical problems (1) The array substrate described in this specification comprises: a gate wiring; a source wiring intersecting the gate wiring; a switch element provided at the intersection of the gate wiring and the source wiring; a semiconductor film provided on the switch element; a first insulating film provided as a layer between the gate wiring and the semiconductor film; and a second insulating film provided as a layer between the semiconductor film and the source wiring. The source wiring overlaps the gate wiring via the first insulating film and the second insulating film.

[0006] (2) In the array substrate described in (1), the switch element has a source electrode, and the source electrode is connected to the semiconductor film. The source electrode wiring may be connected to the source electrode, thereby being connected to the semiconductor film via the source electrode, and the source electrode is provided between the first insulating film and the second insulating film.

[0007] (3) In the array substrate described in (1) or (2) above, the source electrode may not overlap with the gate wiring.

[0008] (4) In the array substrate described in any one of (1) to (3) above, the array substrate includes a relay electrode, the switching element has a drain, and the drain is connected to the semiconductor film. The relay electrode may be connected to the drain and thus connected to the semiconductor film via the drain, and the drain is disposed between the first insulating film and the second insulating film.

[0009] (5) A display device related to the technology described in this specification includes: the array substrate described in any one of (1) to (4) above; and a counter substrate that faces the array substrate.

[0010] Advantageous Effects According to the technology described in this specification, it is possible to reduce the parasitic capacitance of the wiring and suppress the delay of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a plan view of a liquid crystal panel.

[0012] Figure 2 It is a cross-sectional view of a liquid crystal panel.

[0013] Figure 3 It is an enlarged plan view of an array substrate.

[0014] Figure 4 It is Figure 3 an enlarged view near the TFT of

[0015] Figure 5 It is Figure 4 a cross-sectional view taken along line A-A of

[0016] Figure 6 It is a diagram showing a signal waveform of a transmitted grayscale signal.

[0017] Figure 7 It is a cross-sectional view corresponding to the cross-section taken along line A-A in an array substrate of an existing structure. DETAILED DESCRIPTION OF THE INVENTION

[0018] 《Embodiment》 Refer to Figures 1 to 6 to describe an embodiment of the present invention. In this embodiment, a liquid crystal panel 11 (an example of a "display panel") included in a liquid crystal display device 10 (an example of a "display device") is exemplified. The X-axis, Y-axis, and Z-axis are shown in some of the drawings, and the directions of the respective axes are depicted as directions common to each drawing. In addition, regarding the up and down directions, with Figure 2 as a reference, the upper side of the drawing is set as the front side, and the lower side of the drawing is set as the back side.

[0019] 1. Outline of Liquid Crystal Panel Figure 1is a plan view of the liquid crystal panel 11. As Figure 1 shown, the overall planar shape of the liquid crystal panel 11 of the present embodiment is a horizontally long and substantially square shape. The long side direction of the liquid crystal panel 11 coincides with the X-axis direction, the short side direction coincides with the Y-axis direction, and the plate thickness direction coincides with the Z-axis direction.

[0020] The liquid crystal panel 11 can display an image using illumination light irradiated from a backlight device (lighting device). The central side portion of the screen in the liquid crystal panel 11 is a display area (pixel area) AA for displaying an image. In contrast, the outer peripheral side portion in a frame shape surrounding the display area AA in the screen is a non-display area (frame area) NAA that does not display an image. The range surrounded by the single-dot chain line in Figure 1 is the display area AA.

[0021] As Figure 1 shown, the liquid crystal panel 11 has a pair of substrates 20, 21 made of glass that are substantially transparent and have excellent light transmittance. Among the pair of substrates 20, 21, the substrate disposed on the front side is the counter substrate 20 (CF substrate), and the substrate disposed on the back side is the array substrate 21 (active matrix substrate, element substrate). Various films are laminated on the inner surface side of the glass substrate for both the counter substrate 20 and the array substrate 21.

[0022] The short side dimension of the array substrate 21 is larger than the short side dimension of the counter substrate 20, and one end portion in the long side direction does not overlap with the counter substrate 20. A driver (signal supply unit, mounting component) 12 and a flexible substrate (mounting component) 13 are mounted at the non-overlapping portion. The driver 12 is composed of an LSI chip having a drive circuit inside, and is mounted on the array substrate 21 by COG (Chip On Glass) for the mounting area of the array substrate 21. The driver 12 processes various signals transmitted via the flexible substrate 13.

[0023] The driver 12 is mounted on the flexible substrate 13. The driver 12 is composed of an LSI chip having a drive circuit inside. The driver 12 is mounted on the flexible substrate 13 and processes various signals supplied from an external control substrate.

[0024] In the non-display area NAA of the array substrate 21, a pair of gate circuit portions 14 are provided at positions adjacent to both sides ( Figure 1 the left side and the right side) in the X-axis direction with respect to the display area AA. The gate circuit portion 14 supplies a scan signal to a gate wiring 26 described later. The gate circuit portion 14 is provided on the array substrate 21 in a monolithic manner using a metal film or the like constituting the gate wiring 26 and the source wiring 27. The gate circuit portion 14 has a shift register circuit or the like for sequentially supplying scan signals to a plurality of gate wirings 26.

[0025] The flexible substrate 13 is configured such that a plurality of wiring patterns (not shown) are formed on a base material made of an insulating and flexible synthetic resin material (such as a polyimide-based resin, etc.). One end side of the flexible substrate 13 is connected to the array substrate 21, and the other end side is connected to an external control substrate (signal supply source). Various signals supplied from the control substrate are transmitted to the liquid crystal panel 11 via the flexible substrate 13.

[0026] Figure 2 is a schematic cross-sectional view of the display area AA of the liquid crystal panel 11. As Figure 2 shown, the liquid crystal panel 11 sandwiches a liquid crystal layer 29 containing liquid crystal molecules whose optical properties change with the application of voltage between a pair of substrates 20 and 21.

[0027] On the inner surface side of the substrate 20 facing the display area AA, color filters 30 presenting three colors of red (R), green (G), and blue (B) are provided. These color filters 30 are arranged to overlap with the respective pixel electrodes 24 of the array substrate 21 in a top view. A light-shielding portion 31 is provided between adjacent color filters 30. The light-shielding portion 31 functions as a separator between the color filters 30. In the liquid crystal panel 11, the RGB color filters 30 arranged along the X-axis direction and the three pixel electrodes 24 opposed to the respective color filters 30 constitute three-color pixels PX.

[0028] On the substrate 20, a monolithic counter electrode 22 extending over the entire area of the display area AA is provided. The counter electrode 22 is made of the same transparent electrode material as the pixel electrode 24 and is arranged to face all the pixel electrodes 24 in the display area AA with the liquid crystal layer 29 interposed therebetween.

[0029] Alignment films 32 are provided on the innermost surfaces of the pair of substrates 20 and 21, respectively. Polarizing plates 33 are provided on the outermost surfaces of the pair of substrates 20 and 21, respectively.

[0030] 2. Wiring and TFT Figure 3 is an enlarged view of the display area AA of the array substrate 21. As Figure 3 shown, a plurality of gate wirings 26 (wiring, scanning wiring) and a plurality of source wirings 27 (wiring, image wiring) in a grid pattern are provided on the inner surface side of the display area AA of the array substrate 21.

[0031] The gate wiring 26 extends along the X-axis direction across the display area AA. The source wiring 27 extends along the Y-axis direction vertically through the display area AA. A plurality of gate wirings 26 are arranged at intervals in the Y-axis direction. A plurality of source wirings 27 are arranged at intervals along the X-axis direction. The gate wiring 26 and the source wiring 27 are composed of two metal films (described later), and the two metal films are disposed on different layers at least with a gate insulating film F2 therebetween.

[0032] The gate wiring 26 and the source wiring 27 cross when viewed from the Z-axis direction, and a TFT 23 (an example of a "switching element") is formed near each crossing portion. A rectangular area surrounded by the gate wiring 26 and the source wiring 27 corresponds to the pixel PX. A pixel electrode 24 (transparent electrode) is formed inside the pixel PX. Each metal film constituting the gate wiring 26 and the source wiring 27 has conductivity.

[0033] Refer to Figure 4 , and the configuration of the TFT 23 and the wirings 26 and 27 will be described. Figure 4 is a plan view of an enlarged view of the vicinity of the TFT 23. As Figure 4 shown, the TFT 23 has a semiconductor film 23A, a gate 23G, a source 23S, and a drain 23D.

[0034] A gate 23G protruding in the Y-axis direction is connected to the gate wiring 26 extending in the X-axis direction. The gate 23G is disposed so that at least a part thereof overlaps with the semiconductor film 23A.

[0035] A part of the source wiring 27 extending in the Y-axis direction has a source convex portion 27A protruding in the X-axis direction. The source convex portion 27A is provided at a position that does not overlap with the gate wiring 26. Thus, the capacitance component generated between the source convex portion 27A and the gate wiring 26 is suppressed.

[0036] The source 23S is provided at the protruding end of the source convex portion 27A so that at least a part thereof overlaps with the source convex portion 27A. The source convex portion 27A and the source 23S are electrically connected and at the same potential in the Z-axis direction at the overlapping portion. The source 23S is provided at a position that does not overlap with the gate wiring 26, and the capacitance component generated between the source 23S and the gate wiring 26 is suppressed.

[0037] The pixel electrode 24 is connected to the drain 23D of the TFT 23 via a contact electrode 34 (an example of a "relay electrode", refer to Figure 5 ).

[0038] The TFT 23 has a semiconductor film 23A made of a semiconductor material. One end side of the semiconductor film 23A is connected to the source 23S, and the other end side is connected to the drain 23D. The semiconductor film 23A is disposed to overlap with the gate 23G provided on the back side with a gate insulating film F2 therebetween.

[0039] 2.1 Regarding various films Next, with reference to Figure 5 , various films that are stacked on the glass substrate of the array substrate 21 and form wirings 26, 27, TFT 23, etc. will be described. Figure 5 is a cross-sectional view taken along line A-A of Figure 4 . Figure 4 Line A-A of

[0040] is a line that, after crossing TFT 23 in the X-axis direction, bends along the Y-axis direction at point 27B on the source wiring 27, and vertically penetrates the intersection of the source wiring 27 and the gate wiring 26 in the Y-axis direction.

[0041] On the glass substrate of the array substrate 21, a first metal film F1, a gate insulating film F2 (an example of a "first insulating film"), a semiconductor film 23A, a second metal film F3, a second insulating film F4, a third metal film F5, a protective film F6, a planarization film F7, and a transparent electrode film F8 are stacked in sequence from the lower layer side (glass substrate side).

[0042] The first metal film F1, the second metal film F3, and the third metal film F5 are each made of a metal such as copper or aluminum and have electrical conductivity. The first metal film F1 forms the gate wiring 26, the gate 23G of the TFT 23, etc.

[0043] A part of the source wiring 27 extends convexly in the X-axis direction and overlaps with the source 23S at the end in the X-axis direction. A contact portion 27C that protrudes in the Z-axis direction and is in contact with the source 23S is formed at the portion of the source wiring 27 that overlaps with the source 23S.

[0044] The source wiring 27 is electrically connected to the source 23S at the contact portion 27C. Similarly, the contact electrode 34 has a contact portion 34A formed at the end of the contact electrode 34, and is connected to the drain 23D at the contact portion 34A.

[0045] The semiconductor film 23A is formed of a thin film using a semiconductor material such as an oxide semiconductor or amorphous silicon, and constitutes the channel of the TFT23. The gate insulating film F2, the second insulating film F4, and the protective film F6 are formed of inorganic materials such as silicon nitride (SiNx) and silicon oxide (SiO2). The gate insulating film F2 is sandwiched between the first metal film F1 and the semiconductor film 23A and insulates them. More specifically, in the TFT23, the gate insulating film F2 generates an electric field by being interposed between the gate 23G and the semiconductor film 23A, and controls the current flowing through the channel. In addition, the gate insulating film F2 also extends to the overlapping portion 36 where the gate wiring 26 and the source wiring 27 cross and overlap. The gate insulating film F2 is interposed between the gate wiring 26 and the source wiring 27 at this overlapping portion to prevent short circuits.

[0046] The second insulating film F4 is interposed between the second metal film F3 and the third metal film F5 to prevent short circuits between the second metal film F3 and the third metal film F5. Specifically, in addition to the contact portion 27C provided at the portion where the source 23S overlaps with the source wiring 27 and the contact portion 34A provided at the portion where the drain 23D overlaps with the contact electrode 34, short circuits at undesired portions are also prevented. In addition, the second insulating film F4 also extends to the overlapping portion 36 of the gate wiring 26 and the source wiring 27, and is interposed between the gate wiring 26 and the source wiring 27 to prevent short circuits.

[0047] The protective film F6 is formed in a planar shape over substantially the entire area of the array substrate 21 to protect various films laminated on the back side of the protective film F6. A contact hole 35 that penetrates the protective film F6 and the planarization film F7 in the film thickness direction (Z-axis direction) is formed in a portion of the protective film F6 and the planarization film F7 that overlaps with the contact electrode 34.

[0048] The planarization film F7 is formed of an organic material such as PMMA (acrylic resin). The film thickness of the planarization film F7 is much larger than that of other films laminated on the glass substrate, and the inner surface (the surface on the liquid crystal layer 29 side) of the array substrate 21 is planarized by the planarization film F7.

[0049] The transparent electrode film F8 is continuously formed over the inner peripheral surface and the bottom surface of the contact hole 35 and the surface of the planarization film F7. The portion of the transparent electrode film F8 formed on the inner surface side of the array substrate 21 is the pixel electrode 24. The transparent electrode film F8 contacts the contact electrode 34 at the bottom of the contact hole 35, and the pixel electrode 24 is electrically connected to the contact electrode 34 and the drain 23D connected to the contact electrode 34.

[0050] When the TFT 23 is turned on based on the scan signal transmitted by the gate wiring 26, the gradation signal (image signal) transmitted by the source wiring 27 is supplied to the pixel electrode 24 via the source 23S, the semiconductor film 23A, the drain 23D, and the contact electrode 34. At this time, the pixel electrode 24 is charged to the potential based on the gradation signal.

[0051] The liquid crystal panel 11 applies a prescribed electric field to the liquid crystal layer 29 based on the potential difference generated between the counter electrode 22 and each pixel electrode 24, whereby prescribed gradation display can be performed for each pixel PX.

[0052] 2.2 Regarding parasitic capacitance and signal delay The gradation signal input to the TFT 23 through the source wiring 27 is delayed due to the influence of the time constant τs of the source wiring. The time constant τs is expressed as τs = RsCs. Rs is the resistance value [Ω] of the source wiring 27, and Cs is the parasitic capacitance [F] of the source wiring 27.

[0053] As Figure 5 shown, the gate wiring 26 and the source wiring 27 overlap at the overlapping portion 36 with an insulator (the gate insulating film F2 and the second insulating film F4) interposed therebetween. The parasitic capacitance Cs2 is a capacitance component generated due to the physical structure of the wirings 26 and 27. If the parasitic capacitance Cs2 is large, the time constant τs of the source wiring 27 also becomes large, and the delay of the gradation signal input to the TFT 23 through the source wiring 27 becomes large.

[0054] Here, for comparison, the array substrate 121 of the existing configuration is described with reference to Figure 7 FIG. Figure 7 is a cross-sectional view taken along the line A-A (a broken line that crosses the TFT 23 and vertically passes through the overlapping portion 36 of the gate wiring 26 and the source wiring 27) corresponding to Figure 4 on the array substrate 121. The array substrate 121 includes a first metal film F11, a gate insulating film F12 (first insulating film), a semiconductor film 123A, a second metal film F13, a protective film F14, a planarization film F15, a transparent conductive film F16, etc. on a glass substrate.

[0055] The first metal film F11 and the second metal film F13 are each made of a metal such as copper or aluminum and have conductivity. The first metal film F11 forms the gate wiring 126, the gate 123G, etc. in the same manner as the first metal film F1 of the array substrate 21. The second metal film F13 forms the continuously formed source 123S, the source wiring 127, the drain 123D, etc. For convenience, in the continuously formed source 123S and source wiring 127, the portion extending along the Y-axis direction is defined as the source wiring 127, and the portion protruding and extending from the source wiring 27 in the X-axis direction and connected to the semiconductor film 123A is defined as the source 123S.

[0056] Both the source electrode 123S and the source wiring 127 of the array substrate 121 are formed of the second metal film F13. This is a configuration different from that of the array substrate 21 of the present invention, in which the source electrode 23S and the source wiring 27 are formed of separate metal films (the first metal film F1 and the third metal film F5), and an insulator (the second insulating film F4) is provided therebetween.

[0057] In addition, in the array substrate 21, a portion corresponding to the contact electrode 34 that is interposed between the drain electrode 23D and the transparent conductive film F16 and connected to both is not provided on the array substrate 121. The drain electrode 123D of the array substrate 121 is directly connected to the contact portion 134A formed of the transparent conductive film F16.

[0058] The semiconductor film 123A, the protective film F14, the planarization film F15, and the transparent conductive film F16 have the same configurations as the semiconductor film 23A, the protective film F6, the planarization film F7, and the transparent electrode film F8 of the array substrate 21, respectively.

[0059] The gate insulating film F12 is interposed between the semiconductor film 123A and the gate electrode 123G to insulate the two. In addition, in the overlapping portion 136 where the gate wiring 126 and the source wiring 127 overlap, the gate insulating film F12 is interposed between the gate wiring 126 and the source wiring 127 to insulate the two.

[0060] In the existing array substrate 121, the insulator interposed between the gate wiring 126 and the source wiring 127 is only the gate insulating film F12. In the array substrate 121, the distance L1 between the gate wiring 126 and the source wiring 127 depends on the thickness of the gate insulating film F12.

[0061] As a method for reducing the parasitic capacitance Csl of the overlapping portion 136, it is possible to consider increasing the thickness of the gate insulating film F12. However, changing the thickness of the gate insulating film F12 may affect the characteristics of the TFT123.

[0062] 3. Effect description In order to reduce the parasitic capacitance Cs2 of the overlapping portion 36 in the array substrate 21 of the present embodiment, it is considered to increase the distance L2 between the gate wiring 26 and the source wiring 27. The array substrate 21 of the present embodiment includes: a gate wiring 26; a source wiring 27 intersecting the gate wiring 26; a TFT23 provided at the intersection of the gate wiring 26 and the source wiring 27; a semiconductor film 23A provided on the TFT23; a gate insulating film F2 disposed in a layer between the gate wiring 26 and the semiconductor film 23A; and a second insulating film F4 disposed in a layer between the semiconductor film 23A and the source wiring 27, and the source wiring 27 overlaps the gate wiring 26 with the gate insulating film F2 and the second insulating film F4 interposed therebetween.

[0063] In such a configuration, as Figure 5 shown, between the gate wiring 26 and the source wiring 27, on the basis of sandwiching the gate insulating film F2 as an insulator, the second insulating film F4 is also sandwiched. Even if the thickness of the gate insulating film F2 is the same as that of the gate insulating film F12 (refer to Figure 7 ), the distance L2 between the gate wiring 26 and the source wiring 27 is only the amount greater than the thickness of the second insulating film F4, the distance L1 (refer to Figure 7 ). The parasitic capacitance Cs2 in the overlapping portion 36 is lower than the parasitic capacitance Cs1 at the distance L1. Along with the reduction of the parasitic capacitance, the time constant τs becomes smaller, and the delay of the signal input to the TFT23 from the source wiring 27 can be suppressed.

[0064] Refer to Figure 6 The graph 50 shown explains the suppression of the delay. The graph 50 is a graph schematically showing the signal waveforms applied to the sources 23S, 123S in the case where a grayscale signal of a rectangular wave (voltage value V0) is input to the source wirings 27, 127. In the graph 50, the horizontal axis is time and the vertical axis is voltage. The voltage waveform 51 in the graph 50 is the voltage waveform of the grayscale signal input to the source wiring 27. The voltage waveforms 52, 53 are the waveforms of the source voltages transmitted in the source wirings 27, 127 and applied to the sources 23S, 123S.

[0065] The voltage waveform 51 starts to be applied at the time t0, and at the time t0, the voltage rises from 0 to V0. Further, the voltage V0 is maintained during the period from the time t0 to the time t3, and the voltage drops from V0 to 0 at the time t3. For convenience, it is assumed that the voltage of the grayscale signal rises instantaneously and drops instantaneously.

[0066] The voltage waveform 52 is the waveform that appears at the source 123S when the grayscale signal of the voltage waveform 51 is applied to the source wiring 127 of the existing configuration of the array substrate 121 shown in Figure 7 . The time constant τ1 calculated by using the electrostatic capacitance C of the source wiring 127 as the parasitic capacitance Csl is applied to the voltage waveform 52.

[0067] As Figure 6 shown, the voltage waveform 52 rises from the time t0 as time passes and reaches the voltage V0 at the time t2. In the existing configuration of the array substrate 121, after applying the grayscale signal (voltage waveform 51), it takes the time t2 - t0 until the voltage reaches the voltage V0.

[0068] If the delay time is defined as the time (time t2) from the start of applying the grayscale signal (time t0) to reaching the voltage V0, the delay time of the array substrate 121 is t2 - t0.

[0069] The voltage waveform 53 represents the voltage of the source 23S when a grayscale signal with the voltage waveform 51 is input to the source wiring 27 of the array substrate 21 shown in Figure 5 FIG. The time constant τ2 calculated by using the electrostatic capacitance C of the source wiring 27 as the parasitic capacitance Cs2 is applied to the voltage waveform 53. As described above, since the distance L2 between the gate wiring 26 and the source wiring 27 is such that L1 < L2, the parasitic capacitance Cs2 is smaller than Cs1 (Cs1 > Cs2), and the time constant τ2 is smaller than τ1 (τ1 > τ2).

[0070] As Figure 6 shown, the voltage of the voltage waveform 53 rises from the time t0 as time elapses and reaches the voltage V0 at the time t1. The delay time of the array substrate 21 of the present embodiment is t1 - t0. Since the time constant τ1 > Δτ2, the delay time t1 - t0 of the array substrate 21 is shorter than the delay time t2 - t0 of the array substrate 121. The array substrate 21 of the present embodiment reaches the voltage V0 with a shorter delay time than the array substrate 121, and the signal delay of the source wiring 27 is suppressed compared with the array substrate 121.

[0071] The shortening of the delay time means that the time from when the grayscale signal is applied until the pixel performs a predetermined grayscale display is shortened. As a result, the refresh rate of the liquid crystal panel 11 can be increased and made high-frequency, or the number of pixels in the display area AA can be increased to make the liquid crystal panel 11 high-resolution.

[0072] In the array substrate 21 of the present embodiment, the TFT 23 has a source 23S connected to the semiconductor film 23A. The source wiring 27 is connected to the semiconductor film 23A via the source 23S by being connected to the source 23S, and the source 23S is provided between the gate insulating film F2 and the second insulating film F4.

[0073] As Figure 5 shown, the source wiring 27 is connected to the semiconductor film 23A via the source 23S, and the source wiring 27 does not directly contact the semiconductor film 23A. By not directly contacting, the material of the source wiring 27 and the forming process (such as chemical resistance to the liquid, annealing temperature, etc.) can be made inconsistent with the material characteristics of the semiconductor film 23A.

[0074] For example, as the material of the source wiring 27, a material that can be well connected to the source 23S but has low connection reliability with the semiconductor film 23A can be applied, or in the forming process of the source wiring 27, a liquid medicine with high aggressiveness to the semiconductor film 23A can be used. As a result, the degree of freedom of the material and process of the source wiring 27 with respect to the semiconductor film 23A is increased.

[0075] In addition, since the source electrode 23S and the source wiring 27 are formed in different layers via the second insulating film F4, their materials and formation processes can also be different. As a result, the degrees of freedom in material and formation process between the source electrode 23S and the source wiring 27 are increased.

[0076] The source wiring 27 is connected to the semiconductor film 23A via the source electrode 23S, so the degree of freedom in the arrangement of the source wiring 27 relative to the semiconductor film 23A is increased. For example, even at a position where the semiconductor film 23A does not overlap with the source wiring 27, electrical connection between the semiconductor film 23A and the source wiring 27 can be achieved via the source electrode 23S.

[0077] In the array substrate 21 of the present embodiment, the source electrode 23S does not overlap with the gate wiring 26. When the source electrode 23S does not overlap with the gate wiring 26, the capacitive component between the two is smaller than in the overlapping case. In the path of the gradation signal input from the source wiring 27 to the semiconductor film 23A via the source electrode 23S, the total value of the electrostatic capacitance between the source wiring 27 and the source electrode 23S, which are connected and at the same potential, and the gate wiring 26 is reduced, the time constant τ becomes smaller, and signal delay can be suppressed.

[0078] In the array substrate 21 of the present embodiment, the TFT 23 has a drain electrode 23D connected to the semiconductor film 23A, and the drain electrode 23D is provided between the gate insulating film F2 and the second insulating film F4.

[0079] Thus, similarly to the relationship between the source wiring 27 and the semiconductor film 23A described above, the degrees of freedom in material and formation process of the drain electrode 23D can be increased.

[0080] In addition, the liquid crystal display device 10 according to the present embodiment includes the array substrate 21 described above and a counter substrate 20 disposed opposite to the array substrate 21. In such a liquid crystal display device 10, the parasitic capacitance Cs2 of the source wiring 27 is reduced, so the signal (gradation signal) transmitted through the source wiring 27 is less likely to be passivated. As a result, the display quality is improved.

[0081] <Other Embodiments> (1) In the above embodiment, the TFT 23 (switching element) having the semiconductor film 23A, the source electrode 23S, and the drain electrode 23D is exemplified. The switching element may not have one or both of the source electrode and the drain electrode. In this case, a part of the semiconductor film is made conductive by a conductorization process, and the source wiring or the contact electrode is brought into contact with the conductorized portion, thereby electrically connecting the source wiring or the contact electrode to the switching element.

[0082] (2) In the above embodiment, the case where the source electrode 23S does not overlap with the gate wiring 26 is described as an example. However, a part or all of the source electrode 23S may overlap with the gate wiring 26 .

[0083] (3) In the above embodiment, the bottom-gate TFT 23 is described as an example in which the gate electrode 23G is provided on the back side of the semiconductor film 23A via the gate insulating film F2. The TFT is not limited to the bottom-gate type, and may be a top-gate type having a gate electrode on the front side of the semiconductor film. In addition, a dual-gate type having gate electrodes on the front side and the back side of the semiconductor film may be used.

[0084] (4) In the above embodiments, TFTs are described as examples of switching elements. However, the switching elements are not limited to TFTs, and other types of transistors (MOSFET, IGBT, etc.) may be used.

[0085] (5) As a driving method for the liquid crystal panel, an SSD method (Source Shared Driving (ソース・シェアド・ドライビング (Japanese)) may be applied, in which the display area AA is divided into a plurality of areas and a source signal is allocated to each divided area from one TFT. In the array substrate of the present invention, the delay time of the TFT can be shortened, so high-speed switching can be performed. By using a TFT capable of high-speed switching, the number of divisions of the display area of ​​the SSD method liquid crystal panel can be increased.

[0086] (6) In the above embodiment, the relative electrode 22 is provided on the relative substrate 20, and the orientation state of the liquid crystal molecules contained in the liquid crystal layer 29 is controlled by the longitudinal electric field generated between the pixel electrode 24 and the relative electrode 22 (longitudinal electric field liquid crystal mode). However, it is also possible to generate a transverse electric field in the liquid crystal layer 29, and control the orientation state of the liquid crystal molecules contained in the liquid crystal layer 29 by the transverse electric field (transverse electric field liquid crystal mode). In order to achieve the transverse electric field liquid crystal mode, instead of providing the relative electrode 22 on the relative substrate 20, for example, a common electrode overlapping with the pixel electrode 24 via an insulating film is provided on the array substrate 21, and a transverse electric field is generated between the pixel electrode 24 and the common electrode.

[0087] Description of Reference Numerals 11: liquid crystal panel; 21: array substrate; 22: opposite electrode; 23: TFT (an example of a switching element); 23A: semiconductor film; 23D: drain; 23G: gate; 23S: source; 26: gate wiring; 27: source wiring; 36: overlapping portion; F1: first metal film; F2: gate insulating film (an example of a first insulating film); F4: second insulating film.

Claims

1. An array substrate, characterized in that: It has: Gate wiring; a source wiring that intersects the gate wiring; a switch element provided at an intersection of the gate wiring and the source wiring; a semiconductor film disposed on the switching element; a first insulating film which is a layer arranged between the gate wiring and the semiconductor film; as well as a second insulating film disposed in a layer between the semiconductor film and the source wiring, The source wiring overlaps with the gate wiring via the first insulating film and the second insulating film.

2. The array substrate according to claim 1, characterized in that: The switching element has a source electrode connected to the semiconductor film. The source wiring is connected to the source electrode, thereby being connected to the semiconductor film via the source electrode. The source electrode is provided between the first insulating film and the second insulating film.

3. The array substrate according to claim 2, characterized in that: The source electrode does not overlap with the gate wiring.

4. The array substrate according to claim 2, characterized in that: The array substrate comprises relay electrodes. The switching element has a drain electrode connected to the semiconductor film. The relay electrode is connected to the drain electrode, thereby being connected to the semiconductor film via the drain electrode. The drain electrode is provided between the first insulating film and the second insulating film.

5. A display device, characterized in that: It has: The array substrate according to any one of claims 1 to 4; and The opposite substrate is opposite to the array substrate.

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