An instruction merging system based on cost model

Abstract

The present application relates to the field of integrated circuit technology, and in particular to an instruction merging system based on a cost model, which determines several reference merging schemes through 2×N instructions to be merged, and determines the number of copy instructions corresponding to each reference merging scheme, performs cost evaluation on the reference merging scheme according to the number of copy instructions, selects the reference merging scheme corresponding to the number of copy instructions that meets a first preset condition as the target merging scheme, and selects the reference merging scheme with a smaller number of copy instructions as the target merging scheme as much as possible, so that when each instruction to be merged is merged according to the target merging scheme, the number of additional copy instructions is smaller, thereby increasing the improvement of the instruction execution efficiency caused by the instruction merging operation, thereby improving the efficiency of instruction execution.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an instruction merging system based on a cost model. Background Art

[0002] Traditional GPU instruction execution involves significant instruction overhead. For example, instruction fetch, decoding, and transmission all consume significant time and hardware resources. Instruction merging, however, can combine multiple instructions with similar functions or dependencies into a single, composite instruction, reducing the total number of instructions and overall execution time, thereby improving GPU speed and efficiency.

[0003] Normally, an instruction includes a destination operand and a source operand. The destination operand and source operand contained in the instruction to be merged can be regarded as occupying a sub-register respectively, while the destination operand and source operand contained in the compound instruction can be regarded as occupying multiple sub-registers with consecutive addresses respectively. Therefore, when merging instructions, if the sub-register addresses corresponding to a set of operands of the two instructions to be merged are not consecutive, additional copy instructions need to be added. Obviously, if the merging of two instructions to be merged requires adding multiple copy instructions, the number of instructions will increase instead, which makes it difficult to achieve the expected improvement in instruction execution efficiency of the instruction merging operation, and may even lead to a decrease in instruction execution efficiency.

[0004] Therefore, how to determine a reasonable merging plan to maximize the efficiency of instruction execution has become an urgent problem to be solved. Summary of the Invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is:

[0006] An instruction merging system based on a cost model, the system comprising: a processor and a memory storing a computer program. When the computer program is executed by the processor, the following steps are implemented:

[0007] S101, obtaining 2×N instructions to be merged, where N is a positive integer, and the instructions to be merged include a destination operand and a source operand.

[0008] S102 : Determine, based on each instruction to be merged, several reference merging schemes and the number of copy instructions corresponding to each reference merging scheme.

[0009] S103 , selecting a reference merging solution corresponding to the number of copy instructions that meets a first preset condition as a target merging solution.

[0010] S104 , merging the instructions to be merged according to the target merging scheme to obtain a plurality of target merged instructions and a plurality of copy instructions.

[0011] The present invention has significant advantages over the prior art. By utilizing the above technical solution, the cost model-based instruction merging system provided by the present invention can achieve considerable technological advancement and practicality, and has wide industrial application value. It has at least the following advantages:

[0012] The present invention provides an instruction merging system based on a cost model, the system comprising: a processor and a memory storing a computer program, wherein when the computer program is executed by the processor, the following steps are implemented: S101, obtaining 2×N instructions to be merged, wherein N is a positive integer, and the instructions to be merged include a destination operand and a source operand; S102, determining, based on each instruction to be merged, several reference merging schemes and the number of copy instructions corresponding to each reference merging scheme; S103, selecting a reference merging scheme corresponding to the number of copy instructions that meets a first preset condition as a target merging scheme; S104, merging each instruction to be merged according to the target merging scheme to obtain several target merging instructions and several copy instructions.

[0013] It can be seen that several reference merging schemes are determined through 2×N instructions to be merged, and the number of copy instructions corresponding to each reference merging scheme is determined. The cost of the reference merging scheme is evaluated according to the number of copy instructions, and the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition is selected as the target merging scheme, so that the reference merging scheme with a smaller number of copy instructions is selected as the target merging scheme as much as possible, so that when each instruction to be merged is merged according to the target merging scheme, the additional number of copy instructions is smaller, thereby increasing the improvement of the instruction execution efficiency by the instruction merging operation, thereby improving the efficiency of instruction execution. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A schematic diagram of a first flow chart of a computer program being executed by a processor in a cost model-based instruction merging system provided in the first embodiment of the present invention;

[0016] Figure 2 A first schematic diagram of instruction merging in an instruction merging system based on a cost model provided in the first embodiment of the present invention;

[0017] Figure 3A second schematic diagram of instruction merging in a cost model-based instruction merging system provided in the first embodiment of the present invention;

[0018] Figure 4 A third schematic diagram of instruction merging in a cost model-based instruction merging system provided in the first embodiment of the present invention;

[0019] Figure 5 A fourth schematic diagram of instruction merging in a cost model-based instruction merging system provided in the first embodiment of the present invention;

[0020] Figure 6 A second flow chart of a computer program executed by a processor in a cost model-based instruction merging system provided in the second embodiment of the present invention;

[0021] Figure 7 A third flow chart of a computer program executed by a processor in a cost model-based instruction merging system provided in a third embodiment of the present invention;

[0022] Figure 8 A schematic diagram of constructing an instruction dependency chain in an instruction merging system based on a cost model according to a third embodiment of the present invention;

[0023] Figure 9 This is a fourth flow chart of a computer program executed by a processor in a cost model-based instruction merging system provided in the fourth embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0025] This embodiment provides an instruction merging system based on a cost model. Figure 1 , which is a first flow chart of a computer program executed by a processor in a cost model-based instruction merging system provided in Embodiment 1 of the present invention, wherein the system includes:

[0026] S101, obtaining 2×N instructions to be merged, where N is a positive integer, and the instructions to be merged include a destination operand and a source operand;

[0027] S102, determining a number of reference merging schemes and the number of copy instructions corresponding to each reference merging scheme based on each instruction to be merged;

[0028] S103, selecting a reference merging solution corresponding to the number of copy instructions that meets a first preset condition as a target merging solution;

[0029] S104 , merging the instructions to be merged according to the target merging scheme to obtain a plurality of target merged instructions and a plurality of copy instructions.

[0030] Among them, the instructions to be merged may include a target operand and several source operands, the reference merging scheme may include a merging combination of all instructions to be merged, and the number of copy instructions corresponding to the reference merging scheme may refer to the number of copy instructions added after all instructions to be merged are merged according to the reference merging scheme.

[0031] The first preset condition can be used to measure the impact of the reference merging solution on instruction execution efficiency, which is characterized by the fact that the fewer the number of copied instructions, the higher the instruction execution efficiency.

[0032] Specifically, see Figure 2 , which is a first schematic diagram of instruction merging in a cost model-based instruction merging system provided in Embodiment 1 of the present invention, wherein the first schematic diagram takes the merging of multiply-add instructions as an example, each multiply-add instruction to be merged includes a destination operand DST and three source operands SRC0, SRC1, and SRC2, SRC0_lo can represent the low-order portion of the first source operand after merging, SRC0_hi can represent the high-order portion of the first source operand after merging, SRC1_lo can represent the low-order portion of the second source operand after merging, SRC1_hi can represent the high-order portion of the second source operand after merging, SRC2_lo can represent the low-order portion of the third source operand after merging, and SRC2_hi can represent the high-order portion of the third source operand after merging. The high-order part of DST_lo can represent the low-order part of the destination operand calculated by the merged source operand, and DST_hi can represent the high-order part of the destination operand calculated by the merged source operand. It can be seen that when the instructions are merged, the source operands SRC0 in the two multiplication and addition instructions to be merged are merged into a single source operand according to the high-order part and the low-order part, the source operands SRC1 in the two multiplication and addition instructions to be merged are merged into a single source operand according to the high-order part and the low-order part, and the source operands SRC2 in the two multiplication and addition instructions to be merged are merged into a single source operand according to the high-order part and the low-order part. The destination operand calculated from the merged source operands is split according to the high-order part and the low-order part to obtain the destination operands corresponding to the two multiplication and addition instructions to be merged.

[0033] See also Figure 3, which is a second schematic diagram of instruction merging in a cost model-based instruction merging system provided in the first embodiment of the present invention. The third schematic diagram takes the merging of multiply-add instructions as an example. When the corresponding 32-bit operation bits %218_lo and %25_lo in two multiply-add instructions to be merged are not adjacent in address, %218_lo and %25_lo need to be spliced into a 64-bit register, thereby generating a copy operation.

[0034] See also Figure 4 , which is a third schematic diagram of instruction merging in a cost model-based instruction merging system provided in Example 1 of the present invention. In this third schematic diagram, taking the merging of multiply-add instructions as an example, there are address constraints on registers %119 and %120. If the first two multiply-add instructions are merged, then when the subsequent fourth and fifth multiply-add instructions are merged, %220 and %221 will both generate copy operations due to the address constraints. In addition, due to the data dependency problem, that is, the source operand %221 of the merged fourth and fifth multiply-add instructions is the target operand of the third multiply-add instruction, resulting in the inability to merge the third multiply-add instruction. However, if the second and third multiply-add instructions are merged, no copy operation will be generated due to the address constraint, effectively reducing the number of copy instructions.

[0035] See also Figure 5 , which is the fourth schematic diagram of instruction merging in a cost model-based instruction merging system provided in Example 1 of the present invention. In this fourth schematic diagram, multiplication and addition instruction merging is taken as an example. The %218_lo and %25_lo registers are reused in multiple instruction merging operations. Although a copy operation is generated at this time, there is still a performance benefit.

[0036] If there is no reference merging scheme corresponding to the number of copy instructions that meets the first preset condition, it means that performing the instruction merging operation at this time has a negative benefit on the instruction execution efficiency. Then the target merging scheme is not to merge the 2×N instructions to be merged. Accordingly, the number of target merge instructions and copy instructions are both 0.

[0037] The first embodiment of the present invention determines several reference merging schemes through 2×N instructions to be merged, and determines the number of copy instructions corresponding to each reference merging scheme, performs cost evaluation on the reference merging scheme according to the number of copy instructions, selects the reference merging scheme corresponding to the number of copy instructions that meets the first preset condition as the target merging scheme, and selects the reference merging scheme with a smaller number of copy instructions as the target merging scheme as much as possible, so that when each instruction to be merged is merged according to the target merging scheme, the additional number of copy instructions is smaller, thereby increasing the improvement of the instruction execution efficiency by the instruction merging operation, thereby improving the efficiency of instruction execution.

[0038] This embodiment 2 provides an instruction merging system based on a cost model, see Figure 6 , which is a second flow diagram of a computer program executed by a processor in a cost model-based instruction merging system provided in a second embodiment of the present invention, wherein determining, based on each instruction to be merged, several reference merging schemes and the number of copy instructions corresponding to each reference merging scheme includes:

[0039] S201, randomly combine 2×N instructions to be merged into pairs to form P temporary merging schemes. Each temporary merging scheme contains N temporary instruction combinations, where P = (2N-1)!!;

[0040] S202, taking each temporary merger plan as a reference merger plan;

[0041] S203: Determine the number of copy instructions corresponding to each reference merging solution.

[0042] Among them, when the 2×N instructions to be merged are randomly combined in pairs, a single instruction to be merged can only belong to one temporary instruction combination. There are P combination methods, that is, P temporary merging schemes, P = (2N-1)!! = (2N-1)×(2N-3)×(2N-5)×…×3×1, (2N-1)!! represents a double factorial calculation.

[0043] It should be noted that, for the convenience of description, this embodiment is described by taking the merging of two instructions to be merged into one instruction as an example. In actual application scenarios, implementers can adapt this embodiment to apply to scenarios where multiple instructions to be merged are merged into one instruction. Z×N instructions to be merged are randomly combined into Z of them to form P temporary merging schemes. In this case, the general calculation method is P=((Z×N)!) / ((Z!) N ×N!), Z can be an integer greater than 1.

[0044] In a specific implementation, determining the number of copy instructions corresponding to each reference merging solution includes:

[0045] S2031 , for the pth reference merging solution, determine the initial number of copy instructions a1=(L+1)×N for the reference merging solution, where L is the number of source operands in the instructions to be merged, and p is an integer in the range [1, P].

[0046] S2032, traverse each set of operands in each temporary instruction combination in the reference merging solution. When two sub-data corresponding to a set of operands belong to the same register, update the address constraint count value a2 to a2=a2+1, and obtain the corresponding address constraint count value a2 at the end of the traversal. The operands include the destination operand and the source operand. A single operand in a single instruction to be merged corresponds to one sub-data. A single register contains two sub-data. The initial value of a2 is 0.

[0047] S2033, traverse each set of destination operands in each temporary instruction combination in the reference merging solution, and when one set of destination operands is the same as the b sets of source operands, update the instruction dependency count value a3 to a3=a3+b-1, where the initial value of a3 is 0;

[0048] S2034, traverse each source operand group in each temporary instruction combination in the reference merging solution, and when one source operand group is the same as the source operand group c, update the instruction repeat count value a4 to a4=a4+c-1, where the initial value of a4 is 0;

[0049] S2035, determine the number of copy instructions A corresponding to the p-th reference merging solution p =a1-a2-a3-a4.

[0050] Among them, since each set of source operands and destination operands may generate a copy operation, the default copy operation in this embodiment is to copy one sub-data to the adjacent position in the register where the other sub-data is located. Therefore, by default, only one copy instruction is generated for each copy operation. The implementer can adjust the calculation method of the initial number of copy instructions according to actual conditions. For example, when the copy operation is to copy both sub-data to adjacent positions in a new register, then a1=2×(L+1)×N.

[0051] When two sub-data corresponding to a group of operands belong to the same register, it means that the group of operands does not need a copy operation and can directly obtain the operands required for the merge instruction from a single register. The address constraint count value can be increased by 1, and the address constraint count value can be subtracted from the initial number of copy instructions subsequently.

[0052] When one group of destination operands is the same as b groups of source operands, it means that the destination operand of one merge instruction can be reused in other b merge instructions. At this time, the group of destination operands only needs one copy operation to belong to the same register, so the instruction dependency count value is increased by b-1. Similarly, the instruction dependency count value is subsequently subtracted from the initial number of copied instructions.

[0053] When one set of source operands is identical to the c set of source operands, the source operands in this set only need one copy operation to be in the same register, so the instruction repeat count value is increased by c-1. Similarly, the instruction repeat count value is subsequently subtracted from the initial number of copy instructions.

[0054] The number of copy instructions A corresponding to the p-th reference merge solution p =a1-a2-a3-a4, which can accurately represent the number of additional copy instructions required for the p-th reference merging solution.

[0055] In a specific embodiment, selecting a reference merging solution corresponding to the number of copy instructions that meets the first preset condition as a target merging solution includes:

[0056] Determining the minimum number of copy instructions from the numbers of copy instructions corresponding to the P reference merging solutions as the number of copy instructions that meets the first preset condition;

[0057] A reference merging scheme corresponding to the number of copy instructions that meets the first preset condition is selected as the target merging scheme.

[0058] The number of copy instructions that meet the first preset condition can be expressed as min p∈(1,P) (A p ).

[0059] In one embodiment, the minimum number of copy instructions is determined from the numbers of copy instructions corresponding to P reference merging schemes. If the minimum number of copy instructions satisfies the condition of being less than N, the minimum number of copy instructions is determined as the number of copy instructions that satisfies the first preset condition to avoid the situation where the number of instructions remains unchanged or increases after the instructions are merged.

[0060] The second embodiment evaluates all merging schemes by enumeration, which can fully evaluate the optimization benefits and overheads, minimize the number of copy instructions generated, and obtain the optimal target merging scheme, thereby improving the efficiency of instruction execution.

[0061] This embodiment 3 provides an instruction merging system based on a cost model, see Figure 7 , which is a third flow diagram of a computer program executed by a processor in a cost model-based instruction merging system provided in Embodiment 3 of the present invention, wherein determining, based on each instruction to be merged, a plurality of reference merging schemes and the number of copy instructions corresponding to each reference merging scheme includes:

[0062] S301, forming M instruction dependency chains based on the destination operands and source operands of each instruction to be merged, where M is an integer less than or equal to N, and the instruction dependency chains include at least two instructions to be merged that have a dependency relationship, and the two instructions to be merged that have a dependency relationship meet the condition that the destination operand of one instruction to be merged is the source operand of the other instruction to be merged;

[0063] S302: Randomly combine the M instruction dependency chains in pairs to form Q first dependency chain combination schemes. A single first dependency chain combination scheme includes D first dependency chain combinations, where D = (M-1) / 2 when M is an odd number and D = M / 2 when M is an even number.

[0064] S303: For the qth first dependency chain combination scheme, retain the first dependency chain combinations that do not have a dependency relationship among the D first dependency chain combinations in the first dependency chain combination scheme, to obtain E first dependency chain combinations, wherein two first dependency chain combinations that have a dependency relationship meet the following conditions: among the multiple combinations to be merged determined based on the two first dependency chain combinations, there is one combination to be merged in which the target operand of one instruction to be merged is the source operand of another instruction to be merged, and q is an integer in the range [1, Q].

[0065] S304, determining f1 first combinations to be merged based on the E first dependency chain combinations, and forming a dependent instruction combination scheme from the f1 first combinations to be merged;

[0066] S305, randomly combine all instructions to be merged that do not belong to the f1 first to-be-merged combinations into pairs to form R(q) remaining instruction combination schemes;

[0067] S306 , forming R(q) intermediate merging schemes as reference merging schemes based on the dependent instruction combination scheme and the R(q) remaining instruction combination schemes;

[0068] S307, traverse Q first dependency chain combination solutions to obtain S reference merging solutions, where: ;

[0069] S308 , determining the number of copy instructions corresponding to each reference merging solution.

[0070] Among them, the first dependency chain combination scheme only involves the combination method of instruction dependency chains, that is, a single first dependency chain combination scheme contains D first dependency chain combinations. When there is a dependency relationship in the first dependency chain combination, the sub-data required by the instruction cannot be obtained, that is, among the several combinations to be merged determined by the first dependency chain combination, there is a combination to be merged in which the target operand of a to-be-merged instruction is the source operand of another to-be-merged instruction, which causes the instruction to fail to execute normally. Therefore, the first dependency chain combination that does not have a dependency relationship among the D first dependency chain combinations in the first dependency chain combination scheme is retained, and E first dependency chain combinations are obtained.

[0071] However, since the number of instructions to be merged included in the first dependency chain combination may be different, the instructions to be merged that do not constitute the first dependency chain combination, the instructions to be merged in the first dependency chain combination with a dependency relationship, and the independent instructions to be merged that do not belong to the instruction dependency chain, are the instructions to be merged that do not belong to the f1 first dependency chain combinations.

[0072] Specifically, see Figure 8 , which is a schematic diagram of the construction of an instruction dependency chain in an instruction merging system based on a cost model provided in the third embodiment of the present invention, wherein the schematic diagram takes the merging of multiplication and addition instructions as an example, where the destination operand of the first multiplication and addition instruction is the source operand of the second multiplication and addition instruction, the destination operand of the second multiplication and addition instruction is the source operand of the third multiplication and addition instruction, and the destination operand of the third multiplication and addition instruction is the source operand of the fourth multiplication and addition instruction, thus forming an instruction dependency chain of four multiplication and addition instructions.

[0073] In a specific embodiment, determining f1 first combinations to be merged based on E first dependency chain combinations, and forming a dependent instruction combination scheme from the f1 first combinations to be merged, includes:

[0074] S3041, for any first dependency chain combination, sequentially match the instructions to be merged in the two instruction dependency chains in the first dependency chain combination to obtain f1 first combinations to be merged;

[0075] S3042 , forming a dependent instruction combination scheme from the f1 first to-be-merged combinations.

[0076] Among them, in the instruction dependency chain, the instructions to be merged are sorted in the dependency order. If the destination operand of one instruction to be merged is the source operand of another instruction to be merged, then the instruction to be merged is before the other instruction to be merged to ensure that the other generation of merged instructions can obtain its source operand when executed.

[0077] The third embodiment effectively reduces the number of generated solutions by constructing a dependency chain, prioritizes solutions with greater potential for improving efficiency, reduces the computational burden, and improves the efficiency of generating instruction merging solutions.

[0078] This fourth embodiment provides an instruction merging system based on a cost model. Figure 9 , which is a fourth flow diagram of a computer program executed by a processor in a cost model-based instruction merging system provided in a fourth embodiment of the present invention, wherein determining, based on each instruction to be merged, a plurality of reference merging schemes and the number of copy instructions corresponding to each reference merging scheme includes:

[0079] S401, forming M instruction dependency chains based on the destination operands and source operands of each instruction to be merged, where M is an integer less than or equal to N, and the instruction dependency chains include at least two instructions to be merged that have a dependency relationship, and the two instructions to be merged that have a dependency relationship meet a condition: the destination operand of one instruction to be merged is the source operand of the other instruction to be merged;

[0080] S402, determining the merging priorities corresponding to the M instruction dependency chains according to the number of instructions to be merged contained in each of the M instruction dependency chains;

[0081] S403: Based on the merge priorities corresponding to the M instruction dependency chains, a dependency chain matching pair sequence is formed in descending order of the sum of the merge priorities. The dependency chain matching pair sequence includes M(M-1) / 2 dependency chain matching pairs.

[0082] S404, initialization selection flag I=1;

[0083] S405, using the Ith dependency chain matching pair in the dependency chain matching pair sequence as a second dependency chain combination, and randomly combining two of the remaining M-2 instruction dependency chains to form J dependency chain combination schemes;

[0084] S406, for the j-th dependency chain combination solution, determine T(j) basic merging solutions as reference merging solutions, where the initial value of j is 1 and j is an integer in the range [1, J].

[0085] S407: Determine the number of copy instructions corresponding to each reference merging solution.

[0086] When forming a sequence of dependency chain matching pairs, if the sum of the merged priorities of the dependency chain matching pairs is the same, they can be randomly sorted.

[0087] By randomly combining the remaining M-2 instruction dependency chains in pairs, J dependency chain combination schemes can be formed. In the j-th dependency chain combination scheme, several second to-be-merged combinations can be formed according to the second dependency chain combinations contained in the j-th dependency chain combination scheme, and T(j) basic merging schemes can be formed according to the instructions to be merged that are not in the second to-be-merged combinations, thereby determining T(j) reference merging schemes.

[0088] In a specific embodiment, selecting a reference merging solution corresponding to the number of copy instructions that meets the first preset condition as a target merging solution includes:

[0089] S408: Determine a minimum number of copy instructions from the numbers of copy instructions corresponding to the reference merging solutions. If the minimum number of copy instructions is less than a preset threshold, determine that the minimum number of copy instructions meets a first preset condition, and use the reference merging solution corresponding to the minimum number of copy instructions as the target merging solution.

[0090] S409, otherwise, update j=j+1 and return to step S406 until the target merging solution is determined or j=J+1. When j=J+1, execute step S410;

[0091] S410, update I=I+1, return to execute step S405, until the target merging solution is determined or I=(M(M-1) / 2)+1, when I=(M(M-1) / 2)+1, determine that the target merging solution is not to merge.

[0092] Among them, in order to improve the efficiency of scheme determination, the implementer can set a preset threshold. When the minimum number of copy instructions determined from the number of copy instructions corresponding to each reference merging scheme is less than the preset threshold, it can be considered that the expected instruction execution efficiency optimization effect can be achieved.

[0093] Specifically, when the minimum number of copy instructions is determined from the number of copy instructions corresponding to each reference merging scheme, if the minimum number of copy instructions is greater than or equal to the preset threshold, j can be updated, and a new batch of reference merging schemes can be determined with another dependency chain combination scheme. When j=J+1, it means that the J dependency chain combination schemes formed by the I-th dependency chain matching pair cannot meet expectations, and I can be updated at this time.

[0094] The fourth embodiment of the present invention determines a group of dependency chain matching pairs as fixed pairs by merging priorities, and then generates dependency chain combination schemes, as well as basic merging schemes under each dependency chain combination scheme, thereby effectively reducing the number of schemes generated. At the same time, schemes with a greater possibility of improving efficiency are generated by merging priorities. When the expected effect cannot be met, scheme generation is performed iteratively, thereby further reducing the number of schemes generated, reducing the computational burden, and improving the efficiency of instruction merging scheme generation.

[0095] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. An instruction merging system based on a cost model, characterized in that: The system includes: a processor and a memory storing a computer program. When the computer program is executed by the processor, the following steps are implemented: S101, obtaining 2×N instructions to be merged, where N is a positive integer, and the instructions to be merged include a destination operand and a source operand; S102: Determine, based on each instruction to be merged, several reference merging schemes and the number of copy instructions corresponding to each reference merging scheme. The method for determining, based on each instruction to be merged, several reference merging schemes and the number of copy instructions corresponding to each reference merging scheme includes randomly combining each instruction to be merged in pairs, forming instruction dependency chains based on each instruction to be merged, and determining the instruction dependency chains formed by each instruction to be merged and the merging priority corresponding to each instruction dependency chain. The method of randomly combining two instructions to be merged includes: S201, randomly combine 2×N instructions to be merged into pairs to form P temporary merging schemes. Each temporary merging scheme contains N temporary instruction combinations, where P = (2N-1)!!; S202, taking each temporary merger plan as a reference merger plan; S203: Determine the number of copy instructions corresponding to each reference merging solution. Determining the number of copy instructions corresponding to each reference merging solution includes: S2031 , for the pth reference merging solution, determine the initial number of copy instructions a1=(L+1)×N for the reference merging solution, where L is the number of source operands in the instructions to be merged, and p is an integer in the range [1, P]. S2032, traverse each set of operands in each temporary instruction combination in the reference merging solution. When two sub-data corresponding to a set of operands belong to the same register, update the address constraint count value a2 to a2=a2+1, and obtain the corresponding address constraint count value a2 at the end of the traversal. The operands include the destination operand and the source operand. A single operand in a single instruction to be merged corresponds to one sub-data. A single register contains two sub-data. The initial value of a2 is 0. S2033, traverse each set of destination operands in each temporary instruction combination in the reference merging solution, and when one set of destination operands is the same as the b sets of source operands, update the instruction dependency count value a3 to a3=a3+b-1, where the initial value of a3 is 0; S2034, traverse each source operand group in each temporary instruction combination in the reference merging solution, and when one source operand group is the same as the source operand group c, update the instruction repeat count value a4 to a4=a4+c-1, where the initial value of a4 is 0; S2035, determine the number of copy instructions A corresponding to the p-th reference merging solution p =a1-a2-a3-a4; S103, selecting a reference merging solution corresponding to the number of copy instructions that meets a first preset condition as a target merging solution; S104 , merging the instructions to be merged according to the target merging scheme to obtain a plurality of target merged instructions and a plurality of copy instructions.

2. The cost model-based instruction merging system according to claim 1, characterized in that: The selecting a reference merging solution corresponding to the number of copy instructions that meets the first preset condition as the target merging solution includes: Determining the minimum number of copy instructions from the numbers of copy instructions corresponding to the P reference merging solutions as the number of copy instructions that meets the first preset condition; A reference merging scheme corresponding to the number of copy instructions that meets the first preset condition is selected as the target merging scheme.

3. The cost model-based instruction merging system according to claim 1, wherein: The method of forming an instruction dependency chain based on each instruction to be merged includes: S301, forming M instruction dependency chains based on the destination operands and source operands of each instruction to be merged, where M is an integer less than or equal to N, and the instruction dependency chains include at least two instructions to be merged that have a dependency relationship, and the two instructions to be merged that have a dependency relationship meet the condition that the destination operand of one instruction to be merged is the source operand of the other instruction to be merged; S302: Randomly combine the M instruction dependency chains in pairs to form Q first dependency chain combination schemes. A single first dependency chain combination scheme includes D first dependency chain combinations, where D = (M-1) / 2 when M is an odd number and D = M / 2 when M is an even number. S303: For the qth first dependency chain combination scheme, retain the first dependency chain combinations without dependency relationships among the D first dependency chain combinations in the first dependency chain combination scheme, to obtain E first dependency chain combinations, wherein the first dependency chain combinations with dependency relationships meet the following conditions: among the multiple combinations to be merged determined according to the first dependency chain combinations, there is a combination to be merged in which the target operand of a to-be-merged instruction is the source operand of another to-be-merged instruction, and q is an integer in the range [1, Q]. S304, determining f1 first combinations to be merged based on the E first dependency chain combinations, and forming a dependent instruction combination scheme from the f1 first combinations to be merged; S305, randomly combine all instructions to be merged that do not belong to the f1 first to-be-merged combinations into pairs to form R(q) remaining instruction combination schemes; S306 , forming R(q) intermediate merging schemes as reference merging schemes based on the dependent instruction combination scheme and the R(q) remaining instruction combination schemes; S307, traverse Q first dependency chain combination solutions to obtain S reference merging solutions, where: ; S308 , determining the number of copy instructions corresponding to each reference merging solution.

4. The cost model-based instruction merging system according to claim 3, characterized in that: The step of determining f1 first combinations to be merged based on the E first dependency chain combinations, and forming a dependent instruction combination scheme from the f1 first combinations to be merged, includes: S3041, for any first dependency chain combination, sequentially match the instructions to be merged in the two instruction dependency chains in the first dependency chain combination to obtain f1 first combinations to be merged; S3042 , forming a dependent instruction combination scheme from the f1 first to-be-merged combinations.

5. The cost model-based instruction merging system according to claim 1, characterized in that: The method of merging the instruction dependency chains formed by the instructions to be merged and the merging priorities corresponding to the instruction dependency chains includes: S401, forming M instruction dependency chains based on the destination operands and source operands of each instruction to be merged, where M is an integer less than or equal to N, and the instruction dependency chains include at least two instructions to be merged that have a dependency relationship, and the two instructions to be merged that have a dependency relationship meet a condition: the destination operand of one instruction to be merged is the source operand of the other instruction to be merged; S402, determining the merging priorities corresponding to the M instruction dependency chains according to the number of instructions to be merged contained in each of the M instruction dependency chains; S403: Based on the merge priorities corresponding to the M instruction dependency chains, a dependency chain matching pair sequence is formed in descending order of the sum of the merge priorities. The dependency chain matching pair sequence includes M(M-1) / 2 dependency chain matching pairs. S404, initialization selection flag I=1; S405, using the Ith dependency chain matching pair in the dependency chain matching pair sequence as a second dependency chain combination, and randomly combining two of the remaining M-2 instruction dependency chains to form J dependency chain combination schemes; S406, for the j-th dependency chain combination solution, determine T(j) basic merging solutions as reference merging solutions, where the initial value of j is 1 and j is an integer in the range [1, J]. S407: Determine the number of copy instructions corresponding to each reference merging solution.

6. The cost model-based instruction merging system according to claim 5, characterized in that: The selecting a reference merging solution corresponding to the number of copy instructions that meets the first preset condition as the target merging solution includes: S408: Determine a minimum number of copy instructions from the numbers of copy instructions corresponding to the reference merging solutions. If the minimum number of copy instructions is less than a preset threshold, determine that the minimum number of copy instructions meets a first preset condition, and use the reference merging solution corresponding to the minimum number of copy instructions as the target merging solution. S409, otherwise, update j=j+1 and return to step S406 until the target merging solution is determined or j=J+1. When j=J+1, execute step S410; S410, update I=I+1, return to execute step S405, until the target merging solution is determined or I=(M(M-1) / 2)+1, when I=(M(M-1) / 2)+1, determine that the target merging solution is not to merge.

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