PCIE (Peripheral Component Interface Express) parameter optimization training method, device, equipment, medium and product

Abstract

The invention discloses a PCI E (Peripheral Component Interconnect Express) parameter optimization training method, device, equipment, medium and product, and relates to the technical field of computer hardware, the method comprises the following steps: acquiring test equalization parameters corresponding to each PCIE differential line channel, and determining the working state of the equipment according to the link bandwidth of a PCIE controller in the equipment enumeration stage; and performing multiple rounds of pressure test training on all the test equilibrium parameters according to the equipment working state as a parameter test state to obtain an optimal equilibrium parameter. The method and the device aim at automatically optimizing the PCIE signal parameters so as to improve the optimization efficiency of the PCIE signal parameters.

Description

Technical Field

[0001] The present application relates to the field of computer hardware technology, and in particular to a PCI E parameter optimization training method, device, equipment, medium and product. Background Art

[0002] In computer hardware systems, PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) links play a key role in data transmission. However, affected by factors such as link length, material properties, design layout, and PCB routing, PCIE signals are prone to attenuation or deformation during transmission. This will not only cause the PCIE training bandwidth to slow down and lose bandwidth, but in severe cases it may even cause device loss, greatly affecting the compatibility and stability of the board PCIE device.

[0003] At present, the main method for optimizing PCIE signals is to test the PCIE eye diagram with a high-bandwidth oscilloscope. If the eye diagram does not display well, the PCIEEQ (Equalization) parameters are manually modified through the BIOS (Basic Input / Output System), and then the eye diagram is tested again, and this process is repeated until the appropriate EQ parameters are found to meet the eye diagram test requirements. If the parameters that effectively improve the signal quality cannot be found, the hardware needs to be revised and the PCIE routing needs to be re-optimized. This traditional method has many disadvantages: First, the hardware cost is high, and high-end oscilloscopes are expensive, making it difficult for many small and medium-sized companies to afford it; second, the analysis and optimization process of PCIE signal quality is extremely complicated, requiring close cooperation between hardware engineers, BIOS engineers, and SI engineers, and consuming a lot of manpower; third, the number of EQ parameter combinations corresponding to the PCIE differential line lane is huge. Taking the PCIEx16 slot as an example, TxPreset has 16 settings and RxPreset has 8 settings. In theory, there are as many as (16×8)^16 adjustable parameters, and manual testing is almost impossible to complete. Each EQ parameter verification involves BIOS compilation, update, and entering the operating system to check bandwidth and test eye diagrams, which is a huge workload.

[0004] Therefore, how to automatically optimize PCIE signal parameters to improve the optimization efficiency of PCIE signal parameters is a technical problem that needs to be solved urgently.

[0005] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0006] The main objective of this application is to provide a PCIE parameter optimization training method, device, equipment, medium, and product, aiming to automatically optimize PCIE signal parameters to improve the optimization efficiency of PCIE signal parameters.

[0007] To achieve the above objective, this application proposes a PCIE parameter optimization training method, and the PCIE parameter optimization training method includes:

[0008] Obtain the test equalization parameters corresponding to each PCIE differential line channel, and determine the device working state according to the link bandwidth of the PCIE controller during the device enumeration stage;

[0009] Execute multiple rounds of stress test training on all the test equalization parameters according to the parameter test state of the device working state to obtain the optimal equalization parameters.

[0010] In an embodiment, the step of determining the device working state according to the link bandwidth of the PCIE controller during the device enumeration stage includes:

[0011] Detect whether the link bandwidth of the PCIE controller is the preset highest bandwidth threshold during the device enumeration stage;

[0012] If the link bandwidth is the highest bandwidth threshold, determine that the device working state is the parameter test state;

[0013] If the link bandwidth is not the highest bandwidth threshold, determine that the device working state is the parameter adjustment state.

[0014] In an embodiment, after the step of determining the device working state according to the link bandwidth of the PCIE controller during the device enumeration stage, the PCIE parameter optimization training method includes:

[0015] In response to the device working state being the parameter adjustment state, update the test equalization parameters that are undergoing stress test training according to the preset parameter automatic training module.

[0016] In an embodiment, the step of executing multiple rounds of stress test training on all the test equalization parameters according to the parameter test state of the device working state to obtain the optimal equalization parameters includes:

[0017] In response to the device working state being the parameter test state, perform the first round of stress test training on each test equalization parameter according to the preset first test number, record the test consecutive pass number of each test equalization parameter during the first round of stress test training, and use the test equalization parameters with the test consecutive pass number greater than the stable training number as the relatively optimal equalization parameters;

[0018] Perform multiple rounds of stress test training according to all the above-mentioned optimal balance parameters to obtain the optimal balance parameter.

[0019] In one embodiment, the step of performing multiple rounds of stress test training according to all the above-mentioned optimal balance parameters to obtain the optimal balance parameter includes:

[0020] Perform the second round of stress test training on each of the test balance parameters according to the preset second test times, and perform the third round of stress test on the optimal balance parameters that are stable after continuous second test times according to the preset third test times to obtain multiple final training balance parameters;

[0021] Determine the optimal balance parameter according to all the above-mentioned final training balance parameters.

[0022] In one embodiment, the step of determining the optimal balance parameter according to all the above-mentioned final training balance parameters includes:

[0023] Transmit each of the above-mentioned final training balance parameters to a preset balance parameter list in chronological order to form a balance parameter training list, and generate a formal BIOS firmware according to the balance parameter training list.

[0024] In addition, to achieve the above object, the present application also proposes a PCIE parameter optimization training device, and the device includes:

[0025] An acquisition module, configured to acquire the test balance parameters corresponding to each PCIE differential line channel, and determine the device working state according to the link bandwidth of the PCIE controller during the device enumeration phase;

[0026] A test training module, configured to perform multiple rounds of stress test training on all the above-mentioned test balance parameters according to the parameter test state of the device working state to obtain the optimal balance parameter.

[0027] In addition, to achieve the above object, the present application also proposes a PCIE parameter optimization training device, and the PCIE parameter optimization training device includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, and the computer program is configured to implement the steps of the PCIE parameter optimization training method as described above.

[0028] In addition, to achieve the above object, the present application also proposes a storage medium, and the storage medium is a computer-readable storage medium, and a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the PCIE parameter optimization training method as described above are implemented.

[0029] In addition, to achieve the above object, the present application further provides a computer product, which includes a computer program. The computer program contains computer program code means stored on a computer-readable medium or a carrier wave. The computer program code means is configured to cause a computer or a processor to execute steps of the PCIE parameter optimization training method as described above when executed.

[0030] Aiming at the problems of high cost, complex process and large parameter combinations in traditional PCIE signal optimization methods, which make manual testing difficult to complete, the embodiments of the present application provide a PCIE parameter optimization training method, which significantly improves the optimization efficiency of PCIE signal parameters through automated means. Specifically, by obtaining the test equalization parameters corresponding to each PCIE differential line channel, the working state of the device can be quickly determined according to the link bandwidth of the PCIE controller during the device enumeration phase. When the working state of the device is the parameter test state, multiple rounds of stress test training are performed on all test equalization parameters. Instead of relying on expensive oscilloscopes and manually adjusting parameters repeatedly like traditional methods, multiple rounds of tests are automatically performed, and parameters are continuously screened and optimized during the test process. Finally, the optimal equalization parameters are obtained, which not only avoids the high cost brought by high-end oscilloscopes, reduces the complex process of collaboration among engineers in multiple fields, but also greatly improves the optimization efficiency of PCIE signal parameters through automated multiple rounds of stress test training. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic flowchart of the first embodiment of the PCIE parameter optimization training method of the present application;

[0032] Figure 2 It is a schematic flowchart of the second embodiment of the PCIE parameter optimization training method of the present application;

[0033] Figure 3 It is a schematic block diagram of the PCIE parameter optimization training device of the present application;

[0034] Figure 4 It is a schematic diagram of the device structure of the hardware operating environment involved in the device of the present application;

[0035] Figure 5 It is a schematic diagram of the storage medium structure involved in the PCIE parameter optimization training method of the present application.

[0036] The realization, functional features and advantages of the object of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0038] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0039] In the application of PCIE technology, PCIE links often cause signal attenuation or deformation due to factors such as length, material, design, and PCB routing, which in turn leads to problems such as PCIE training bandwidth slowdown, bandwidth loss, and even device loss. In order to improve the compatibility and stability of PCIE devices on the board and reduce the bit error rate, adjusting PCIEEQ parameters has become a key means.

[0040] However, the existing PCIE signal optimization technology has many defects: on the one hand, it relies on high-bandwidth oscilloscopes to test PCIE eye diagrams. The high price of high-end oscilloscopes makes it difficult for small and medium-sized companies to afford the hardware costs; on the other hand, the PCIE signal quality analysis and optimization process is complicated, requiring hardware engineers, BIOS engineers and SI engineers to work together, and the labor cost is high. In addition, the number of EQ parameter combinations corresponding to PCIE differential lanes is huge. Taking the PCIEx16 slot as an example, there are theoretically as many as (16×8)^16 adjustable parameters, and manual testing is almost impossible to achieve. In addition, each EQ parameter verification involves a lot of work such as BIOS compilation, update, and entering the operating system to view bandwidth and test eye diagrams, which is a huge workload. These difficulties make PCIE device compatibility and stability a thorny issue in board design, so when engineers face such problems, they often prefer to reduce the speed (such as changing to PCIE GEN2 or GEN1) rather than modifying the EQ parameters to solve them.

[0041] Therefore, how to automatically optimize PCIE signal parameters to improve the optimization efficiency of PCIE signal parameters is a technical problem that needs to be solved urgently.

[0042] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art.

[0043] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or a device capable of realizing the above functions, a PCIE parameter optimization training device (such as a domestic Feiteng platform), etc. The following takes the PCIE parameter optimization training device as an example to illustrate this embodiment and the following embodiments.

[0044] Based on this, the embodiment of the present application provides a PCIE parameter optimization training method, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the PCIE parameter optimization training method of the present application.

[0045] Reference Figure 1, this application provides a method for optimizing and training PCIE parameters. In the first embodiment of the PCIE parameter optimization and training method, the PCIE parameter optimization and training method includes steps S10 to S20.

[0046] Step S10: Obtain the test equalization parameters corresponding to each PCIE differential line channel, and determine the device working state according to the link bandwidth of the PCIE controller during the device enumeration phase.

[0047] In this embodiment, since the PCIE differential line channel is the key path for data transmission, different PCIE differential line channels may vary due to factors such as hardware design and line layout. Therefore, it is necessary to obtain the test equalization parameters corresponding to each PCIE differential line channel to provide basic data for subsequent parameter optimization and training. Next, during the device enumeration phase, the link bandwidth of the PCIE controller is detected, so that the device working state can be accurately obtained, thereby providing an accurate and reliable determination condition for subsequent parameter optimization and training.

[0048] It should be noted that the PCIE differential line channel is the basic physical link for realizing high-speed data transmission. Each pair of PCIE differential line channels has its own corresponding initial EQ (Equalization) parameters. Among them, TxPreset (Transmit Preset) and RxPreset (Receive Preset) are important components of the initial EQ parameters.

[0049] TxPreset is responsible for adjusting the signal characteristics of the transmitter. It has 16 different setting options. These settings can change key parameters such as the amplitude, phase, and pre-emphasis of the transmitted signal to adapt to different transmission environments and requirements. For example, in the case of long-distance transmission or signals that are prone to attenuation, the strength and anti-interference ability of the transmitted signal can be enhanced by adjusting the settings of TxPreset.

[0050] RxPreset focuses on the signal processing at the receiver. It has 8 settings. Its function is to optimize the signal sampling, amplification, and equalization processing at the receiver to ensure that the received signal can be accurately parsed. For example, when the signal is interfered by noise during transmission, appropriate RxPreset settings can effectively suppress the noise and improve the quality of the received signal.

[0051] In a specific embodiment, taking the PCIe x16 slot as an example, it contains 16 pairs of differential lines (lanes). Since each pair of lanes can be independently set with TxPreset and RxPreset, theoretically, the number of adjustable PCIe parameters corresponding to the PCIe x16 slot is extremely large. The specific calculation method is as follows: for each pair of lanes, there are 16 settings for TxPreset and 8 settings for RxPreset, so the combination method for each pair of lanes is 16×8. And the PCIe x16 slot has 16 pairs of lanes. According to the principle of permutation and combination, the total number of adjustable parameter combinations is (16×8) to the 16th power, that is, (16*8)^16 kinds.

[0052] Further, in another embodiment, the above step S10: obtaining the test equalization parameters corresponding to each PCIe differential line channel may further include steps 100 to 900.

[0053] Step 100: Obtain the historical test data of the previous PCIe differential line channel test. The historical test data includes at least the TxPreset (i.e., the transmitter preset value) and RxPreset (i.e., the receiver preset value) of each pair of PCIe differential lines (lanes) and the corresponding test result (i.e., the number of test passes).

[0054] Step 200: Determine the EQ parameter set of each PCIe differential line channel. The EQ parameter set includes multiple initial EQ parameters. Specifically, taking the PCIe x16 slot as an example, there are 16 settings for TxPreset and 8 settings for RxPreset in each PCIe differential line channel, that is, the EQ parameter set of each PCIe differential line channel has n = 16×8 initial EQ parameters.

[0055] Step 300: Initialize the channel number lane_index = 0 of the current differential line channel (i.e., the current PCIe differential line channel to be processed), and preset the test pass count threshold (i.e., the preset test pass threshold); next, determine the search range of the current differential line channel, its starting index start = 0, and ending index end = n - 1.

[0056] Step 400: Calculate the middle index mid = (start + end) / / 2, and find the target EQ parameter specified by this middle index from the EQ parameter set of the current differential line channel.

[0057] Step 500: Detect whether there is a test result for the target EQ parameter in the historical test data.

[0058] Step 600: If there is a test result (i.e., the number of passes) for the target EQ parameter, based on the determination result that the number of passes ≥ the preset passing threshold, record the target EQ parameter as a possible test equalization parameter for the current differential line channel, update start = mid + 1, and return to execute Step 400 to check whether there are other initial EQ parameters that meet the conditions and are better in the second half interval (mid, end] of the current parameter set (i.e., the EQ parameter set of the current differential line channel) until all test EQ parameters that meet the condition that the number of passes ≤ the preset passing threshold are found from the current parameter set.

[0059] Step 700: If there is a test result for the target EQ parameter, based on the determination result that the number of passes ≤ the preset passing threshold, it can be determined that the target EQ parameter does not meet the requirements. Next, adjust the search range to [0, mid), update start = mid - 1, and return to execute Step 400.

[0060] Step 800: If there is no test result for the target EQ parameter, perform an actual PCIE differential line channel test based on the target EQ parameter to obtain the number of passes for the target EQ parameter. After recording the target EQ parameter and its number of passes in the historical test data, return to execute Step 600.

[0061] Step 900: After finishing the preprocessing of the EQ parameter set in the current differential line channel, update the channel number lane_index_c = lane_index + 1, and return to execute Step 400 to perform data preprocessing on the EQ parameter set in the next PCIE differential line channel of the current differential line channel until lane_index_c > 16, then determine that the data preprocessing of all PCIE differential line channels is completed. Next, integrate the test equalization parameters of all 16 pairs of lanes to obtain the test equalization parameter set for the entire PCIEx16 slot. This test equalization parameter set includes several test equalization parameters that meet the requirements of the preset number of passes.

[0062] Step S20: Perform multiple rounds of stress test training on all the test equalization parameters according to the device working state being the parameter test state to obtain the optimal equalization parameter.

[0063] In this embodiment, after determining that the device working state is the parameter test state, multiple rounds of stress test training are immediately performed on each test equalization parameter to obtain the optimal equalization parameter. Instead of relying on expensive oscilloscopes and manually adjusting parameters repeatedly as in traditional methods, multiple rounds of tests are automatically performed, and parameters are continuously screened and optimized during the test process. Finally, the optimal equalization parameter is obtained, which not only avoids the high cost brought by high-end oscilloscopes, reduces the complex process of collaboration among engineers in multiple fields, but also greatly improves the optimization efficiency of PCIE signal parameters through automated multiple-round stress test training.

[0064] In summary, in view of the problems existing in the traditional PCIE signal optimization method, such as high cost, complex process, and large parameter combinations making manual testing difficult to complete, the embodiment of the present application provides a PCIE parameter optimization training method, which significantly improves the optimization efficiency of PCIE signal parameters through automated means. Specifically, by obtaining the test equalization parameters corresponding to each PCIE differential line channel, the device working state can be quickly determined according to the link bandwidth of the PCIE controller during the device enumeration stage. When the device working state is the parameter test state, multiple rounds of stress test training are performed on all test equalization parameters. Instead of relying on expensive oscilloscopes and manually adjusting parameters repeatedly as in traditional methods, multiple rounds of tests are automatically performed, and parameters are continuously screened and optimized during the test process. Finally, the optimal equalization parameter is obtained, which not only avoids the high cost brought by high-end oscilloscopes, reduces the complex process of collaboration among engineers in multiple fields, but also greatly improves the optimization efficiency of PCIE signal parameters through automated multiple-round stress test training.

[0065] Further, based on the first embodiment of the present application above, a second embodiment of the PCIE parameter optimization training method of the present application is proposed. Referring to Figure 2 , the above step S10: determining the device working state according to the link bandwidth of the PCIE controller during the device enumeration stage may further include the following implementation steps S101 to S103.

[0066] Step S101: Detect whether the link bandwidth of the PCIE controller is a preset highest bandwidth threshold during the device enumeration stage.

[0067] In this embodiment, the link bandwidth of the PCIE controller is accurately detected during the device enumeration phase. Device enumeration is the process by which a computer platform identifies and locates each device connected to the PCIE bus. During this period, the computer platform communicates with the PCIE controller to read the key indicator of the link bandwidth of the PCIE controller, and compares this link bandwidth with a preset maximum bandwidth threshold. The preset maximum bandwidth threshold is set according to the standards and performance requirements of the PCIE device, representing the bandwidth range that the device should reach under ideal conditions. By comparing the link bandwidth of the PCIE controller with the preset maximum bandwidth threshold, the working efficiency of the current PCIE controller and the transmission capacity of the link can be initially judged.

[0068] It should be noted that the preset maximum bandwidth threshold can be customized according to application requirements, and this application does not make any restrictions here. For example, the preset maximum bandwidth threshold can be PCIE3.0 8GT / s or PCIE2.0 5GT / s.

[0069] Step S102: If the link bandwidth is the maximum bandwidth threshold, determine that the device working state is the parameter test state.

[0070] In this embodiment, if the link bandwidth of the PCIE controller is the preset maximum bandwidth threshold, determine that the device working state is the parameter test state, and perform multiple rounds of stress test training on the test equalization parameters corresponding to each pair of PCIE differential lines (lane) in this parameter test state, so as to quickly and accurately obtain the optimal equalization parameters, thereby improving the overall performance and stability of the PCIE device, and ensuring the efficiency and accuracy of data transmission.

[0071] Step S103: If the link bandwidth is not the maximum bandwidth threshold, determine that the device working state is the parameter adjustment state.

[0072] In this embodiment, if it is detected that the link bandwidth of the PCIE controller is not the preset maximum bandwidth threshold, determine that the device working state is the parameter adjustment state, and automatically adjust the test equalization parameters corresponding to each PCIE differential line channel through a preset parameter automatic training module. Specifically, according to the degree to which the link bandwidth of the PCIE controller deviates from the maximum bandwidth threshold, automatically adjust the settings of EQ parameters such as Tx Preset and Rx Preset, and try different parameter combinations to improve the signal quality and increase the link bandwidth. By continuously adjusting and optimizing, the link bandwidth gradually approaches or reaches the preset maximum bandwidth threshold, creating conditions for the stable operation of the device and efficient data transmission.

[0073] Further, in some other feasible embodiments, after step S10: determining the device operating state according to the link bandwidth of the PCIE controller during the device enumeration phase, the PCIE parameter optimization training method may further include the following implementation steps A10.

[0074] Step A10: In response to the device operating state being the parameter adjustment state, update the test equalization parameters that are undergoing stress test training according to a preset parameter automatic training module.

[0075] In this embodiment, in response to the device operating state being the parameter adjustment state, immediately call the preset parameter automatic training module to update the test equalization parameters that are undergoing stress test training as the optimization object. Specifically, the parameter automatic training module will update the test equalization parameters that are undergoing stress test training according to the built-in parameter automatic training algorithm. The update process set in this application is not random, but fully considers the characteristics of the PCIE link, the data feedback obtained from previous tests, and the preset optimization goals. For example, according to problems such as signal attenuation and bit error rate found in previous tests, the module will targetedly adjust parameter settings such as Tx Preset and Rx Preset. If it is found that the signal attenuates severely during transmission in the test, the parameter automatic training module may appropriately increase the pre-emphasis value of the signal in Tx Preset to enhance the transmission intensity of the signal; at the same time, according to the signal quality situation at the receiving end, adjust the relevant parameters of Rx Preset to optimize the signal processing ability of the receiving end. In this way, continuously update the test equalization parameters, hoping to find an optimal parameter combination, thereby improving the PCIE signal quality, increasing the link bandwidth, and enabling the device to reach a better operating state.

[0076] Further, in some feasible embodiments, step S20: performing multiple rounds of stress test training on all the test equalization parameters according to the device operating state being the parameter test state to obtain the optimal equalization parameters may further include the following implementation steps S201 to S202.

[0077] Step S201: In response to the device operating state being the parameter test state, perform the first round of stress test training on each of the test equalization parameters according to a preset first number of tests, record the number of consecutive passes of each test equalization parameter during the first round of stress test training, and use the test equalization parameters with the number of consecutive passes greater than the stable training number as relatively optimal equalization parameters.

[0078] In this embodiment, in response to the device operating state being the parameter test state, the first round of stress test training is performed on each of the test equalization parameters according to a preset first number of tests. The preset first number of tests is set based on a comprehensive consideration of the PCIE device characteristics and the actual application scenario. Its purpose is to comprehensively and accurately evaluate the performance of the test equalization parameters through a sufficient number of tests. During each test process, the computer platform strictly monitors the signal transmission situation of the PCIE link to determine whether it meets the requirements of stable transmission. If during a test, the PCIE link can stably transmit data without abnormal situations such as speed reduction, bandwidth loss, or device loss, then this test is considered to pass. The computer platform will record in real time the number of consecutive passes of each test equalization parameter during the first round of stress test training. When the number of consecutive passes of a certain test equalization parameter is greater than the preset stable training number, it indicates that this parameter shows good stability and adaptability under the current test conditions, and the computer platform will screen it out as a relatively optimal equalization parameter.

[0079] It should be noted that the preset first number of tests can be 50 times, or it can be customized according to application requirements. This application does not make any restrictions here. The stable training number can be customized according to user needs. It can be 50 times, or it can be customized according to user needs. This application does not make any restrictions here.

[0080] Step S202: Perform multiple rounds of stress test training according to all the relatively optimal equalization parameters to obtain the optimal equalization parameter.

[0081] In this embodiment, multiple rounds of stress test training are performed according to all the relatively optimal equalization parameters to obtain the optimal equalization parameter. That is to say, through multiple rounds of stable stress tests, various complex actual working scenarios can be simulated to comprehensively and deeply test the performance of the relatively optimal equalization parameters under different conditions. As the number of test rounds progresses, those equalization parameters that perform better in terms of signal stability, bandwidth maintenance ability, and anti-interference ability will gradually stand out, thus avoiding the limitations of determining parameters based on a single test or simple conditions, effectively eliminating the interference of accidental factors, and the selected optimal equalization parameter can best meet the operating requirements of the PCIE device. The finally obtained optimal equalization parameter can significantly improve the PCIE signal quality, reduce signal attenuation and bit error rate, enhance the stability of the PCIE link, reduce bandwidth speed reduction, device loss, etc. caused by signal problems, greatly improve the compatibility and overall performance of the PCIE device, and provide a solid guarantee for the stable operation of the system and efficient data transmission.

[0082] Further, in some other feasible embodiments, step S202: performing multiple rounds of stress test training according to all the optimal equilibrium parameters to obtain the optimal equilibrium parameter may further include the following implementation steps S2021 to step S2022.

[0083] Step S2021: Perform a second round of stress test training on each of the test equilibrium parameters according to a preset second test number, and perform a third round of stress test on the optimal equilibrium parameters that are continuously stable for the preset third test number after the second test number, to obtain multiple final training equilibrium parameters.

[0084] In this embodiment, perform a second round of stress test training on each test equilibrium parameter according to a preset second test number. The second test number may be 200 times, or may be customized according to user requirements, and the present application does not make any restrictions here; next, perform a third round of stress test on the optimal equilibrium parameters (i.e., the final candidate equilibrium parameters) that are continuously stable after passing 200 tests according to a preset third test number (which may be 1000 times, or may be customized according to user requirements, and the present application does not make any restrictions here), so that each final candidate equilibrium parameter that is continuously stable after passing 1000 tests can be used as a final training equilibrium parameter. After all the final candidate equilibrium parameters are enumerated, output all the final training equilibrium parameters, thereby significantly improving the accuracy and reliability of PCIE signal parameter optimization.

[0085] Step S2022: Determine the optimal equilibrium parameter according to all the final training equilibrium parameters.

[0086] In this embodiment, the optimal equilibrium parameter can be accurately obtained according to all the final training equilibrium parameters, which can greatly improve the PCIE signal quality, reduce the bit error rate, ensure the stable operation of the PCIE link, effectively improve the compatibility and stability of the PCIE device, avoid problems such as speed reduction, bandwidth loss, and device loss, and strongly guarantee the efficient and stable data transmission of the system.

[0087] In a specific embodiment, a PCIE EQ parameter automatic training module is developed in the UEFI BIOS. In this parameter automatic training module, the PCIE EQ parameters in the Feiteng PBF are automatically modified, and then a stable stress test is performed on the PCIE device for each EQ parameter. For example, in the first round of parameter screening, each EQ parameter is tested 50 times; in the second round of EQ parameter screening, each parameter is tested 200 times; and in the third round of parameter screening, each EQ parameter is tested 1000 times. During the PCIE device enumeration process, the link bandwidth of the PCIE device is checked, and during the training process, those EQ parameters that show speed reduction, bandwidth loss, or even device loss are excluded, and the parameters with stable PCIE Link (link connection) bandwidth are retained, that is, those that can be trained stably within the preset number of test times. For example, in the first screening, all PCIE stable EQ parameters for 50 consecutive times are found, and in the second round, all PCIE stable EQ parameters for 200 consecutive times are found, and so on. At the same time, the training process is recorded using the debug serial port, and through the debug serial port, the training situation of the PCIE device for each EQ parameter can be obtained.

[0088] Further, in some other feasible embodiments, the number of the optimal equalization parameters is at least one. In the above step S20: According to the device working state being the parameter test state, multiple rounds of stress test training are performed on all the test equalization parameters to obtain the optimal equalization parameters. The subsequent PCIE parameter optimization training method may further include the following implementation step B10.

[0089] Step B10: Transmit each of the final trained equalization parameters to a preset equalization parameter list in chronological order to form an equalization parameter training list, and generate a formal BIOS firmware based on the equalization parameter training list.

[0090] In this embodiment, after it is determined that all the equalization parameters have been enumerated, it means that the PCIE EQ parameter automatic training process has been completed. Next, the computer platform transmits each final trained equalization parameter to a preset equalization parameter list in chronological order to form an equalization parameter training list. Next, the optimal equalization parameters are screened out from the equalization parameter training list according to the preset evaluation criteria, and the optimal equalization parameters are used as the final recommended configuration and sent to the BIOS to generate a formal BIOS firmware (i.e., the formal BIOS version), so that during the subsequent device startup process, the computer platform will use this optimal EQ parameter configuration to initialize the PCIE link to ensure that the link can operate with the best performance.

[0091] It should be noted that the preset evaluation criterion is configured as the median value of the equalization parameters. This median value of the equalization parameters refers to the value in the middle position within the value range covered by the equalization parameter training list, and it is a benchmark for measuring and screening the optimal equalization parameters. The determination of this median value depends on the value situation of the equalization parameters. If it is a continuous value range, it can be obtained by calculating the average value of the values at both ends of the range. For example, if the value range is from a to b, the median value is (a + b) / 2; if the values are discrete, the value in the exact middle of all possible values is selected. Taking it as the preset evaluation criterion is because it can take into account various factors such as the stability of the link, the compatibility of the device, and the generality of the parameters during the automatic training process of the PCIE EQ parameters. When there is no specific optimization direction or special requirement, it can provide a reasonable and general reference benchmark for screening out the optimal equalization parameters that are suitable for most situations and enable the link to achieve the best performance, so as to ensure that when the subsequent device is started, the optimal equalization parameters screened based on this criterion can make the PCIE link operate with the best performance.

[0092] Further, in another feasible embodiment, the PCIE parameter optimization training method may further include the following implementation steps 1 to step 6.

[0093] Step 1. The device is powered on and initialized.

[0094] Step 2. During the UEFI BIOS PCIE device enumeration stage, detect whether the link status (i.e., link bandwidth) of the PCIE controller is the expected highest bandwidth, such as PCIE x16 GEN3? If so, update the number of passed tests and execute Step 3; otherwise, execute Step 4 and update the EQ parameters in the pbf.

[0095] Step 3. Determine whether the stable training times have been reached? If so, execute Step 4 and update the EQ parameters in the pbf; otherwise, restart and continue the PCIE device stability test.

[0096] Step 4. Have all EQ parameter combinations been enumerated? If so, execute Step 5; otherwise, update the EQ parameters in the pbf and execute Step 1.

[0097] Step 5. Complete the automatic training of the PCIE EQ parameters, print the training results, such as outputting all the required EQ parameter lists and giving the optimal EQ parameters.

[0098] Step 6. Release the official BIOS with the trained optimal EQ parameters. If the company's hardware conditions permit, then use an oscilloscope to test the PCIE eye diagram.

[0099] In summary, the PCIE parameter optimization training method proposed in this application uses a UEFI firmware-level EQ automatic enumeration module implemented by pure software, effectively solving the problems of high hardware cost, complex implementation, and low efficiency in traditional PCIE signal optimization technologies. The core technical effects are as follows: 1) Low cost: It does not rely on expensive hardware devices such as high-end oscilloscopes, and fully relies on software algorithms to optimize parameters, significantly reducing the R & D cost; 2) Easy to implement: It does not require hardware modification or cooperation of engineers in multiple fields. Only by building a board environment can the training be automatically completed through software, and finally the optimal EQ parameters are output, highly simplifying the operation process; 3) High efficiency: Based on the UEFI firmware, the PCIE link bandwidth is directly detected during the device enumeration stage. Combining with the dichotomy parameter enumeration algorithm, invalid parameter combinations are dynamically eliminated, greatly reducing the originally massive test tasks. Taking the Feiteng platform as an example, it only takes 15 seconds to complete parameter verification each time it boots. With 50 - 1000 times of stability tests, the PCIE link stability of a certain customer's FPGA product is finally successfully increased from 50% to 100%, realizing full-link stable operation at the PCIE GEN3 standard. Through the deep combination of algorithm optimization and firmware-level detection, this method provides an efficient, economical, and easy-to-popularize solution for PCIE device compatibility and signal quality optimization.

[0100] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the PCIE parameter optimization training method of this application. Based on this technical concept, more forms of simple transformations are within the protection scope of this application.

[0101] This application also provides a PCIE parameter optimization training device. The PCIE parameter optimization training device includes an acquisition module and a test training module. Please refer to Figure 3 ., the PCIE parameter optimization training controller includes:

[0102] An acquisition module H01, configured to acquire test equalization parameters corresponding to each PCIE differential line channel, and determine the device working state according to the link bandwidth of the PCIE controller during the device enumeration stage;

[0103] A test training module H02, configured to perform multiple rounds of stress test training on all the test equalization parameters according to the device working state being the parameter test state, and obtain the optimal equalization parameters.

[0104] Optionally, the acquisition module H01 may further include:

[0105] A detection unit, configured to detect whether the link bandwidth of the PCIE controller is a preset highest bandwidth threshold during the device enumeration stage;

[0106] A parameter test unit, configured to determine that the device working state is the parameter test state if the link bandwidth is the highest bandwidth threshold;

[0107] A parameter adjustment unit, configured to determine that the device operating state is a parameter adjustment state if the link bandwidth is not the highest bandwidth threshold.

[0108] Optionally, the acquisition module H01 may further include:

[0109] An update unit, configured to, in response to the device operating state being the parameter adjustment state, update the test equalization parameters being subjected to stress test training according to a preset parameter automatic training module.

[0110] Optionally, the test training module H02 may further include:

[0111] A response unit, configured to, in response to the device operating state being the parameter test state, perform a first round of stress test training on each of the test equalization parameters according to a preset first number of test times, record the number of consecutive passes of each of the test equalization parameters during the first round of stress test training, and use the test equalization parameters with the number of consecutive passes greater than the stable training number as relatively optimal equalization parameters;

[0112] A test unit, configured to perform multiple rounds of stress test training according to all the relatively optimal equalization parameters to obtain an optimal equalization parameter.

[0113] Optionally, the test training module H02 may further include:

[0114] A multiple-round test unit, configured to perform a second round of stress test training on each of the test equalization parameters according to a preset second number of test times, and perform a third round of stress test on the relatively optimal equalization parameters that are stable for the consecutive second number of test times according to a preset third number of test times to obtain a plurality of final training equalization parameters;

[0115] An optimal equalization parameter determination unit, configured to determine an optimal equalization parameter according to all the final training equalization parameters.

[0116] Optionally, the test training module H02 may further include:

[0117] A generation unit, configured to transmit each of the final training equalization parameters to a preset equalization parameter list in chronological order to form an equalization parameter training list, and generate a formal BIOS firmware according to the equalization parameter training list.

[0118] The PCIE parameter optimization training device provided by this application adopts the PCIE parameter optimization training method in the above-mentioned embodiment, and can solve the technical problem of poor effect in PCIE parameter optimization training. Compared with the prior art, the beneficial effects of the PCIE parameter optimization training device provided by this application are the same as those of the PCIE parameter optimization training method provided by the above-mentioned embodiment, and other technical features in the PCIE parameter optimization training device are the same as the features disclosed in the above-mentioned embodiment method, which will not be elaborated here.

[0119] This application provides a PCIE parameter optimization training device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the PCIE parameter optimization training method in the first embodiment above.

[0120] Refer to the following Figure 4 , which shows a schematic structural diagram of a PCIE parameter optimization training device suitable for implementing the embodiments of this application. The PCIE parameter optimization training device in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 4 The PCIE parameter optimization training device shown is only an example and should not impose any limitations on the functions and usage scope of the embodiments of this application.

[0121] As Figure 4As shown, the PCIe parameter optimization training device may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. In the RAM 1004, various programs and data required for the operation of the PCIe parameter optimization training device are also stored. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following devices may be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the PCIe parameter optimization training device to communicate with other devices wirelessly or wiredly to exchange data. Although the figure shows a PCIe parameter optimization training device having various devices, it should be understood that it is not required to implement or have all the shown devices. More or fewer devices can be alternatively implemented or had.

[0122] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program codes for executing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device, or installed from the storage device 1003, or installed from the ROM 1002. When the computer program is executed by the processing device 1001, the above functions defined in the methods of the embodiments disclosed in the present application are executed.

[0123] The PCIe parameter optimization training device provided by the present application adopts the PCIe parameter optimization training method in the above embodiment, and can solve the technical problem of poor effect of PCIe parameter optimization training. Compared with the prior art, the beneficial effects of the PCIe parameter optimization training device provided by the present application are the same as those of the PCIe parameter optimization training method provided by the above embodiment, and other technical features in the PCIe parameter optimization training device are the same as the features disclosed in the method of the previous embodiment, and will not be elaborated here.

[0124] It should be understood that each part disclosed in this application can be implemented by hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0125] As described above, the above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application, and all of them should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

[0126] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., computer programs) stored thereon, and the computer-readable program instructions are used to execute the PCIE parameter optimization training method in the above embodiments.

[0127] The computer-readable storage medium provided by this application can be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor devices, devices, or components, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this embodiment, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or combined with an instruction execution device, device, or component. The program code contained on the computer-readable storage medium can be transmitted by any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0128] The above computer-readable storage medium can be included in the PCIE parameter optimization training device; or it can exist separately without being assembled into the PCIE parameter optimization training device.

[0129] The above computer-readable storage medium carries one or more programs, and when the one or more programs are executed by the PCIE parameter optimization training device, the PCIE parameter optimization training device is caused to:

[0130] Obtain the initial text data to be processed, where the initial text data includes the initial text format and the processing format requirements;

[0131] Determine the processing mode according to the processing format requirements and the initial text format, where the processing mode includes a first processing mode for changing the text format and a second processing mode for not changing the text format;

[0132] When the processing mode is the first processing mode, perform text display according to the initial text format and the processing format requirements;

[0133] When the processing mode is the second processing mode, perform text display according to the initial text format.

[0134] Computer program code for performing the operations of the present application can be written in one or more programming languages or combinations thereof. The above-mentioned programming languages include object-oriented programming languages - such as Java, Smalltalk, C++, and also include conventional procedural programming languages - such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network - including a local area network (LAN: Local Area Network) or a wide area network (WAN: Wide Area Network), or can be connected to an external computer (for example, by using an Internet service provider to connect through the Internet).

[0135] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of devices, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and this module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based device for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0136] The modules involved in the embodiments of the present application can be implemented in software or in hardware. Among them, the name of the module does not constitute a limitation to the unit itself in some cases.

[0137] Referring to Figure 5 , Figure 5 FIG. is a schematic structural diagram of a storage medium related to the PCIE parameter optimization training method of the present application. The computer-readable storage medium provided by the present application stores computer-readable program instructions (i.e., computer programs, and this computer program is an over-the-top tracking program) for executing the above-mentioned PCIE parameter optimization training method, and can solve the technical problem of poor effect of PCIE parameter optimization training. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as those of the PCIE parameter optimization training method provided by the above embodiment, and will not be elaborated here.

[0138] The present application also provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the steps of the PCIE parameter optimization training method as described above.

[0139] The computer program product provided by the present application can solve the technical problem of poor effect of PCIE parameter optimization training. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as those of the PCIE parameter optimization training method provided by the above embodiment, and will not be elaborated here.

[0140] The above are only some embodiments of the present application, and do not limit the patent scope of the present application accordingly. All equivalent structural transformations made under the technical concept of the present application by using the content of the specification and drawings of the present application, or directly / indirectly applied to other related technical fields, are included in the patent protection scope of the present application.

Claims

1. A PCIE parameter optimization training method, characterized in that: The PCIE parameter optimization training method comprises: Obtain the test equalization parameters corresponding to each PCIE differential line channel, and determine the device working status according to the link bandwidth of the PCIE controller during the device enumeration phase; According to the device working state being a parameter test state, multiple rounds of stress test training are performed on all the test equalization parameters to obtain optimal equalization parameters.

2. The PCIE parameter optimization training method according to claim 1, characterized in that: The step of determining the working state of the device according to the link bandwidth of the PCIE controller during the device enumeration phase includes: During the device enumeration phase, it is detected whether the link bandwidth of the PCIE controller is the preset maximum bandwidth threshold; If the link bandwidth is the highest bandwidth threshold, determining that the device working state is a parameter test state; If the link bandwidth is not the highest bandwidth threshold, it is determined that the device operating state is a parameter adjustment state.

3. The PCIE parameter optimization training method according to claim 2, characterized in that: After the step of determining the device working state according to the link bandwidth of the PCIE controller in the device enumeration phase, the PCIE parameter optimization training method includes: In response to the device operating state being a parameter adjustment state, the test equalization parameters of the ongoing stress test training are updated according to a preset parameter automatic training module.

4. The PCIE parameter optimization training method according to claim 1, characterized in that: The step of performing multiple rounds of stress test training on all the test equalization parameters according to the device working state being a parameter test state to obtain the optimal equalization parameters includes: In response to the device operating state being a parameter test state, a first round of stress test training is performed on each of the test equalization parameters according to a preset first test number, and the number of consecutive test passes of each of the test equalization parameters during the first round of stress test training is recorded, and the test equalization parameter whose number of consecutive test passes is greater than the number of stable training times is taken as a better equalization parameter; Perform multiple rounds of stress test training based on all the better balancing parameters to obtain the optimal balancing parameters.

5. The PCIE parameter optimization training method according to claim 4, characterized in that: The step of performing multiple rounds of stress test training according to all the better equalization parameters to obtain the best equalization parameters includes: Perform a second round of stress test training on each of the test equalization parameters according to a preset second test number, and perform a third round of stress test on the better equalization parameters that have been tested stably for consecutive second test numbers according to a preset third test number, to obtain a plurality of final training equalization parameters; An optimal equalization parameter is determined according to all the final trained equalization parameters.

6. The PCIE parameter optimization training method according to claim 5, characterized in that: The step of determining the optimal equalization parameter according to all the final training equalization parameters comprises: The final training equalization parameters are transmitted to a preset equalization parameter list in chronological order to form an equalization parameter training list, and a formal BIOS firmware is generated according to the equalization parameter training list.

7. A PCIE parameter optimization training device, characterized in that: The PCIE parameter optimization training device comprises: An acquisition module is used to obtain the test equalization parameters corresponding to each PCIE differential line channel, and determine the device working status according to the link bandwidth of the PCIE controller during the device enumeration stage; The test training module is used to perform multiple rounds of stress test training on all the test equalization parameters according to the working state of the device being the parameter test state, so as to obtain the optimal equalization parameters.

8. A PCIE parameter optimization training device, characterized in that: The PCIE parameter optimization training device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the PCIE parameter optimization training method according to any one of claims 1 to 6.

9. A medium, the medium being a computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the PCIE parameter optimization training method according to any one of claims 1 to 6 are implemented.

10. A product, the product being a computer product, the computer product comprising a computer program, characterized in that: The computer program comprises computer program code means stored on a computer-readable medium or carrier wave, and the computer program code means is configured to implement the steps of the PCIE parameter optimization training method as claimed in any one of claims 1 to 6 when executed by a computer or a processor.

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