Server and topological structure determination method

Abstract

The invention provides a server and a topological structure determination method. The server comprises a first CPU, a second CPU, a first PCIe switching chip, a second PCIe switching chip, a first GPU cluster and a second GPU cluster. The second PCIe switching chip is used for acquiring a working mode; if the working mode shows that the AI string topological structure is adopted, the uplink of the second PCIe switching chip and the first PCIe switching chip is valid, the uplink of the second PCIe switching chip and the second CPU is invalid, and the AI string topological structure is obtained; and if the working mode shows that the HPC topological structure is adopted, the uplink of the second PCIe switching chip and the second CPU takes effect, the uplink of the second PCIe switching chip and the first PCIe switching chip fails, and the HPC topological structure is obtained. Through the technical scheme of the invention, various topological structures can be supported at the same time, such as an AI string topological structure and an HPC topological structure, so that the requirements of different artificial intelligence scenes can be met.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a server and a topology determination method. Background Art

[0002] With the advent of the AI (Artificial Intelligence) era, users have put forward higher requirements for the excellence of the design performance, the flexibility of the architecture, the scalability, and the reliability of GPU (Graphics Processing Unit) servers. The flexibility of the architecture can help users accurately switch different topological architectures according to business scenarios, and achieve the highest performance in application scenarios such as deep learning inference and high-performance computing.

[0003] A GPU server includes a CPU (Central Processing Unit) and multiple GPUs. The CPU and the multiple GPUs are interconnected through a PCIe (Peripheral Component Interconnect Express) switching chip to implement a topological architecture of CPU-PCIe switching chip-GPU. However, when the GPU server adopts the topological architecture of CPU-PCIe switching chip-GPU, it can only support one topological structure and cannot support multiple topological structures simultaneously. For example, a GPU server can only support an AI string topological structure or an HPC (High Performance Computing) topological structure, and cannot support both the AI string topological structure and the HPC topological structure simultaneously. Summary of the Invention

[0004] This application provides a server. The server includes a main board and a switching board. The main board includes a first CPU and a second CPU. The switching board includes a first PCIe switching chip, a second PCIe switching chip, a first GPU cluster, and a second GPU cluster. The first PCIe switching chip is connected to the first GPU cluster, and the second PCIe switching chip is connected to the second GPU cluster.

[0005] The first PCIe switching chip is connected to the first CPU, the second PCIe switching chip is connected to the second CPU, and the second PCIe switching chip is connected to the first PCIe switching chip.

[0006] The second PCIe switching chip is used to obtain the working mode. If the working mode indicates that the server adopts an AI string topology structure, the uplink between the second PCIe switching chip and the first PCIe switching chip is activated, and the uplink between the second PCIe switching chip and the second CPU is deactivated, obtaining an AI string topology structure. Wherein, under the AI string topology structure, AI computing is performed through the first GPU cluster and the second GPU cluster. The communication between the first GPU cluster and the second GPU cluster is forwarded through the first PCIe switching chip and the second PCIe switching chip.

[0007] If the working mode indicates that the server adopts an HPC topology structure, the uplink between the second PCIe switching chip and the second CPU is activated, and the uplink between the second PCIe switching chip and the first PCIe switching chip is deactivated, obtaining an HPC topology structure. Wherein, under the HPC topology structure, HPC computing is performed through the first GPU cluster and the second GPU cluster. The communication between the first GPU cluster and the second GPU cluster is forwarded through the first PCIe switching chip, the first CPU, the second CPU, and the second PCIe switching chip.

[0008] This application provides a method for determining the topology structure of a server. The server includes a motherboard and a switching board. The motherboard includes a first CPU and a second CPU. The switching board includes a first PCIe switching chip, a second PCIe switching chip, a first GPU cluster, and a second GPU cluster. The first PCIe switching chip is connected to the first GPU cluster, and the second PCIe switching chip is connected to the second GPU cluster. The first PCIe switching chip is connected to the first CPU, the second PCIe switching chip is connected to the second CPU, and the second PCIe switching chip is connected to the first PCIe switching chip. The method includes:

[0009] Obtain the working mode corresponding to the server.

[0010] If the working mode indicates the adoption of an AI string topology structure, the uplink between the second PCIe switching chip and the first PCIe switching chip is activated, and the uplink between the second PCIe switching chip and the second CPU is deactivated, obtaining an AI string topology structure. Wherein, under the AI string topology structure, AI computing is performed through the first GPU cluster and the second GPU cluster. The communication between the first GPU cluster and the second GPU cluster is forwarded through the first PCIe switching chip and the second PCIe switching chip.

[0011] If the working mode indicates the adoption of an HPC topology structure, the uplink between the second PCIe switching chip and the second CPU is enabled, and the uplink between the second PCIe switching chip and the first PCIe switching chip is disabled to obtain an HPC topology structure. Among them, in the HPC topology structure, HPC computing is performed through the first GPU cluster and the second GPU cluster. The communication between the first GPU cluster and the second GPU cluster is forwarded through the first PCIe switching chip, the first CPU, the second CPU, and the second PCIe switching chip.

[0012] The present application provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the topology structure determination method of the server described above.

[0013] The present application provides a server, including: a processor and a machine-readable storage medium. The machine-readable storage medium stores machine-executable instructions that can be executed by the processor. Among them, the processor is used to execute the machine-executable instructions to implement the topology structure determination method of the server in the above examples of the present application.

[0014] The present application provides a machine-readable storage medium, which stores machine-executable instructions that can be executed by a processor. Among them, the processor is used to execute the machine-executable instructions to implement the topology structure determination method of the server in the above examples of the present application.

[0015] As can be seen from the above technical solutions, in the embodiments of the present application, by connecting the second PCIe switching chip to the second CPU and connecting the second PCIe switching chip to the first PCIe switching chip, in this way, by enabling the uplink between the second PCIe switching chip and the first PCIe switching chip and disabling the uplink between the second PCIe switching chip and the second CPU, an AI string topology structure can be obtained. By enabling the uplink between the second PCIe switching chip and the second CPU and disabling the uplink between the second PCIe switching chip and the first PCIe switching chip, an HPC topology structure can be obtained. Obviously, when the GPU server adopts a topology architecture of CPU-PCIe switching chip-GPU, it can support multiple topology structures at the same time, such as supporting the AI string topology structure and the HPC topology structure at the same time, so as to meet the needs of different artificial intelligence scenarios. Without changing the hardware connection of the GPU server, users can flexibly adjust to the corresponding topology structure according to the actual application scenario, realize one-key switching between different topologies, meet the topology switching without changing the hardware connection, realize flexible switching of the topology, improve the switching efficiency and product competitiveness. In the AI string topology structure, the communication efficiency between GPUs is optimal, and in the HPC topology structure, the CPU computing power is higher. Brief Description of the Drawings

[0016] Figure 1 is a schematic structural diagram of a server in an embodiment of the present application;

[0017] Figure 2 is a schematic structural diagram of a server in an embodiment of the present application;

[0018] Figure 3 is a schematic diagram of an AI string topology structure in an embodiment of the present application;

[0019] Figure 4 is a schematic diagram of one - key topology switching in an embodiment of the present application;

[0020] Figure 5 is a schematic diagram of an HPC topology structure in an embodiment of the present application;

[0021] Figure 6 is a schematic flowchart of a method for determining the topology structure of a server in an embodiment of the present application;

[0022] Figure 7 is a hardware structure diagram of a server in an embodiment of the present application. Detailed Embodiment

[0023] In an embodiment of the present application, a server (such as a GPU server, etc.) is proposed. Refer to Figure 1 As shown, it is a schematic structural diagram of the server. The server may include a main board and a switching board. The main board includes a first CPU and a second CPU. The switching board includes a first PCIe switching chip, a second PCIe switching chip, a first GPU cluster, and a second GPU cluster. The first PCIe switching chip is connected to the first GPU cluster, and the second PCIe switching chip is connected to the second GPU cluster. The first PCIe switching chip is connected to the first CPU, the second PCIe switching chip is connected to the second CPU, and the second PCIe switching chip is connected to the first PCIe switching chip.

[0024] The second PCIe switching chip is used to obtain the working mode. If the working mode indicates that the server adopts the AI string topology structure, the uplink between the second PCIe switching chip and the first PCIe switching chip is enabled, and the uplink between the second PCIe switching chip and the second CPU is disabled, obtaining the AI string topology structure. Under the AI string topology structure, AI computing is performed through the first GPU cluster and the second GPU cluster. The communication (such as P2P communication) between the first GPU cluster and the second GPU cluster is forwarded by the first PCIe switching chip and the second PCIe switching chip, that is, the packets between the first GPU cluster and the second GPU cluster are forwarded by the first PCIe switching chip and the second PCIe switching chip. If the working mode indicates that the server adopts the HPC topology structure, the uplink between the second PCIe switching chip and the second CPU is enabled, and the uplink between the second PCIe switching chip and the first PCIe switching chip is disabled, obtaining the HPC topology structure. Under the HPC topology structure, HPC computing is performed through the first GPU cluster and the second GPU cluster. The communication (such as P2P communication) between the first GPU cluster and the second GPU cluster is forwarded by the first PCIe switching chip, the first CPU, the second CPU, and the second PCIe switching chip, that is, the packets between the first GPU cluster and the second GPU cluster are forwarded by the first PCIe switching chip, the first CPU, the second CPU, and the second PCIe switching chip.

[0025] In one example, the characteristics of the AI string topology structure are that the communication between GPU clusters does not need to cross CPU nodes, and the P2P communication bandwidth is the highest. It is suitable for large model inference and single machine training fine-tuning, and can also take into account multi-machine cluster training. The characteristics of the HPC topology structure are that the CPU utilization rate is maximized, the uplink bandwidth is high, and the P2P communication bandwidth is low. The HPC topology structure is suitable for HPC scenarios, image processing scenarios, and virtualization scenarios.

[0026] In one example, the motherboard may further include a BMC (Baseboard Management Controller) and a logic device; the logic device is connected to the second PCIe switching chip, and the BMC is connected to the logic device. The BMC is used to obtain topology description information (the topology description information is used to describe the topology structure that the customer wants to implement, that is, the information related to the topology structure), and determine whether the server adopts the AI string topology structure or the HPC topology structure based on the topology description information. If the server adopts the AI string topology structure, it sends the AI string topology structure enabling parameters to the logic device. The logic device is used to, if it receives the AI string topology structure enabling parameters, send a first control signal to the second PCIe switching chip, so that the second PCIe switching chip determines the working mode based on the first control signal, and the working mode indicates that the server adopts the AI string topology structure.

[0027] In one example, the BMC is further configured to send HPC topology enable parameters to the logic device if the server adopts an HPC topology; the logic device is further configured to send a second control signal to the second PCIe switch chip if it receives the HPC topology enable parameters, so that the second PCIe switch chip determines its working mode based on the second control signal, where the working mode indicates that the server adopts an HPC topology.

[0028] In one example, the BMC is further configured to write a first value into the register of the logic device if the server adopts an AI string topology, where the first value can represent AI string topology enable parameters; and write a second value into the register of the logic device if the server adopts an HPC topology, where the second value can represent HPC topology enable parameters. The logic device is further configured to determine that it has received AI string topology enable parameters if it reads the first value from the register; or determine that it has received HPC topology enable parameters if it reads the second value from the register.

[0029] In one example, the second PCIe switch chip includes a first serial boot record image and a second serial boot record image; the first serial boot record image stores a first uplink configuration corresponding to the uplink between the second PCIe switch chip and the first PCIe switch chip, and the second serial boot record image stores a second uplink configuration corresponding to the uplink between the second PCIe switch chip and the second CPU. The second PCIe switch chip is further configured to activate the uplink between the second PCIe switch chip and the first PCIe switch chip based on the first uplink configuration and deactivate the uplink between the second PCIe switch chip and the second CPU by starting the first serial boot record image, so as to obtain an AI string topology; or activate the uplink between the second PCIe switch chip and the second CPU based on the second uplink configuration and deactivate the uplink between the second PCIe switch chip and the first PCIe switch chip by starting the second serial boot record image, so as to obtain an HPC topology.

[0030] In one example, the first control signal includes a first starting address corresponding to the first serial boot record image, and the second PCIe switch chip is further configured to obtain the first starting address from the first control signal and start the first serial boot record image based on the first starting address; or the second control signal includes a second starting address corresponding to the second serial boot record image, and the second PCIe switch chip is further configured to obtain the second starting address from the second control signal and start the second serial boot record image based on the second starting address.

[0031] In one example, when the server adopts the AI string topology structure, the BMC is further configured to obtain the changed topology description information, determine that the server adopts the HPC topology structure based on the topology description information, and send the HPC topology structure enabling parameters to the logic device; the logic device is further configured to send a second control signal to the second PCIe switching chip; the second PCIe switching chip is further configured to determine the working mode based on the second control signal, and the working mode indicates that the server adopts the HPC topology structure; the second PCIe switching chip is further configured to activate the uplink between the second PCIe switching chip and the second CPU and deactivate the uplink between the second PCIe switching chip and the first PCIe switching chip to obtain the HPC topology structure. When the server adopts the HPC topology structure, the BMC is further configured to obtain the changed topology description information, determine that the server adopts the AI string topology structure based on the topology description information, and send the AI string topology structure enabling parameters to the logic device; the logic device is further configured to send a first control signal to the second PCIe switching chip; the second PCIe switching chip is further configured to determine the working mode based on the first control signal, and the working mode indicates that the server adopts the AI string topology structure; activate the uplink between the second PCIe switching chip and the first PCIe switching chip and deactivate the uplink between the second PCIe switching chip and the second CPU to obtain the AI string topology structure.

[0032] In one example, the first PCIe switching chip is connected to the first CPU through a first high-speed cable; the second PCIe switching chip is connected to the second CPU through a second high-speed cable (different from the first high-speed cable); the second PCIe switching chip is connected to the first PCIe switching chip through a third high-speed cable.

[0033] As can be seen from the above technical solutions, in the embodiments of the present application, by connecting the second PCIe switching chip to the second CPU and connecting the second PCIe switching chip to the first PCIe switching chip, in this way, by enabling the uplink of the second PCIe switching chip and the first PCIe switching chip and disabling the uplink of the second PCIe switching chip and the second CPU, an AI string topology structure can be obtained. By enabling the uplink of the second PCIe switching chip and the second CPU and disabling the uplink of the second PCIe switching chip and the first PCIe switching chip, an HPC topology structure can be obtained. Obviously, when the GPU server adopts the topology architecture of CPU-PCIe switching chip-GPU, it can support multiple topology structures at the same time, such as supporting the AI string topology structure and the HPC topology structure at the same time, so as to meet the requirements of different artificial intelligence scenarios. Without changing the hardware connection of the GPU server, users can flexibly adjust to the corresponding topology structure according to the actual application scenario, realize one-key switching between different topologies, meet the topology switching without changing the hardware connection, realize flexible switching of the topology, improve the switching efficiency and product competitiveness. In the AI string topology structure, the communication efficiency between GPUs is optimal, and in the HPC topology structure, the CPU computing power is higher.

[0034] The above technical solutions of the embodiments of the present application will be described below in conjunction with specific application scenarios.

[0035] In the embodiments of the present application, a server is proposed. The server can be a GPU server or other types of servers, and there is no limitation in this regard. Refer to Figure 2 As shown, it is a schematic structural diagram of the server.

[0036] The server may include a motherboard (MOTHER BOARD) and a switch board (SWITCH BOARD). The motherboard may include a BMC, logic devices, a first CPU (such as CPU1) and a second CPU (such as CPU2). Among them, the logic device may be a CPLD (Complex Programmable Logic Device), an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), etc. The BMC is connected to the logic device, and the first CPU is connected to the second CPU. For example, the first CPU and the second CPU may be connected through UPI (Ultra Path Interconnect) or other means.

[0037] The switching board may include a first PCIe switching chip (such as PCIe SW1, where SW stands for Switch, i.e., a data switching circuit chip), a second PCIe switching chip (such as PCIe SW2), a first GPU cluster, and a second GPU cluster. The first GPU cluster may include at least one GPU (such as multiple GPUs), Figure 2 Taking 4 GPUs as an example in Figure 2 , the number of GPUs is not limited. The second GPU cluster may include at least one GPU (such as multiple GPUs), Figure 2 Taking 4 GPUs as an example in Figure 2 , the number of GPUs is not limited.

[0038] See Figure 2 As shown in Figure 2 , the first PCIe switching chip is connected to the first GPU cluster, that is, multiple GPUs connected to the first PCIe switching chip form the first GPU cluster. The second PCIe switching chip is connected to the second GPU cluster, that is, multiple GPUs connected to the second PCIe switching chip form the second GPU cluster.

[0039] See Figure 2 As shown in Figure 2 , the first PCIe switching chip is connected to the first CPU, that is, the UPSTREAM1 (upstream) of the first PCIe switching chip is connected to the first CPU, and the first PCIe switching chip is connected to the first CPU through a first high-speed cable. The second PCIe switching chip is connected to the second CPU, that is, the UPSTREAM1 of the second PCIe switching chip is connected to the second CPU, and the second PCIe switching chip is connected to the second CPU through a second high-speed cable, and the second high-speed cable is different from the first high-speed cable. The second PCIe switching chip is connected to the first PCIe switching chip, that is, the UPSTREAM2 of the second PCIe switching chip is connected to the first PCIe switching chip, and the second PCIe switching chip is connected to the first PCIe switching chip through a third high-speed cable, and the third high-speed cable is different from the first high-speed cable, and the third high-speed cable is different from the second high-speed cable.

[0040] For the server, the UPSTREAM1 of the first PCIe switching chip, the UPSTREAM1 of the second PCIe switching chip, and the UPSTREAM2 of the second PCIe switching chip can all be achieved through high-speed cables. In this embodiment, the 3 groups of physical connections in hardware exist simultaneously, that is, the first high-speed cable, the second high-speed cable, and the third high-speed cable exist simultaneously. Based on this, the first PCIe switching chip is connected to the first CPU through the first high-speed cable, the second PCIe switching chip is connected to the second CPU through the second high-speed cable, and the second PCIe switching chip is connected to the first PCIe switching chip through the third high-speed cable.

[0041] See Figure 2As shown, the logic device can be connected to the second PCIe switching chip, and the logic device can send a MODE_SEL signal to the second PCIe switching chip. The MODE_SEL signal can be a control signal used to select different operating modes, and its function can be referred to the subsequent embodiments.

[0042] For Figure 2 the server shown, the server can support both the AI string topology structure and the HPC topology structure. The following describes how the server supports the AI string topology structure and the HPC topology structure.

[0043] First, the server supports the AI string topology structure. In the AI string topology structure, the uplink between the second PCIe switching chip and the first PCIe switching chip can be enabled, and the uplink between the second PCIe switching chip and the second CPU can be disabled. Refer to Figure 3 shown, which is a schematic diagram of the AI string topology structure.

[0044] In one example, the BMC can obtain topology description information, which indicates that the server adopts the AI string topology structure or the server adopts the HPC topology structure. The BMC can determine whether the server adopts the AI string topology structure or the HPC topology structure based on the topology description information. Taking the server adopting the AI string topology structure as an example, the BMC can send the AI string topology structure enabling parameter to the logic device.

[0045] For example, when the server is in the S5 state, the user can send the topology description information to the BMC. If the user hopes that the server adopts the AI string topology structure, the topology description information indicates that the server adopts the AI string topology structure, that is, the topology description information is the description information for the AI string topology structure. The server being in the S5 state means that the hardware such as the CPU, system, BIOS (Basic Input Output System), and peripherals of the server do not work, and only the BMC and the logic device work.

[0046] Since the topology description information indicates that the server adopts the AI string topology structure or the HPC topology structure, the BMC can determine whether the server adopts the AI string topology structure or the HPC topology structure.

[0047] Taking the server adopting the AI string topology structure as an example, the BMC can send the AI string topology structure enabling parameter to the logic device. For example, the BMC sends an AI string topology structure enabling command to the logic device. The AI string topology structure enabling command includes the AI string topology structure enabling parameter. For example, the AI string topology structure enabling command carries a first value (such as 0), and the first value represents the AI string topology structure enabling parameter.

[0048] For example, the logic device may include a register, and the BMC may write a first value (such as 0) into the register of the logic device to represent the AI string topology enabling parameter through the first value.

[0049] In one example, if the logic device receives the AI string topology enabling parameter, it determines that the server adopts the AI string topology, and the logic device sends a first control signal to the second PCIe switching chip. The first control signal is used to enable the second PCIe switching chip to determine that the working mode represents that the server adopts the AI string topology.

[0050] For example, the logic device may receive the AI string topology enabling command sent by the BMC. If the AI string topology enabling command carries the first value, it determines that the AI string topology enabling parameter is received.

[0051] For example, the logic device may read the value of the register of this logic device. If the first value is read from the register of this logic device, it determines that the AI string topology enabling parameter is received.

[0052] For example, if the logic device receives the AI string topology enabling parameter, it sends a first control signal to the second PCIe switching chip. The first control signal may be the MODE_SEL signal. The first control signal may carry the working mode information, and the working mode information represents that the server adopts the AI string topology.

[0053] In one example, the second PCIe switching chip may obtain the working mode. For example, if the second PCIe switching chip receives the first control signal, it obtains the working mode information from the first control signal and determines the working mode of the server based on the working mode information. Among them, if the working mode information represents that the server adopts the AI string topology, it determines that the working mode represents that the server adopts the AI string topology.

[0054] When the working mode represents that the server adopts the AI string topology, the second PCIe switching chip may activate the uplink between the second PCIe switching chip and the first PCIe switching chip and deactivate the uplink between the second PCIe switching chip and the second CPU to obtain the AI string topology. See Figure 3 As shown, it is a schematic diagram of the AI string topology. Obviously, in the AI string topology, the second PCIe switching chip and the first PCIe switching chip may be connected, and the second PCIe switching chip and the second CPU may not be connected.

[0055] For example, the second PCIe switching chip includes a first serial boot record image and a second serial boot record image. The first serial boot record image can store a first uplink configuration corresponding to the uplink of the second PCIe switching chip and the first PCIe switching chip, and the second serial boot record image can store a second uplink configuration corresponding to the uplink of the second PCIe switching chip and the second CPU.

[0056] The first uplink configuration may include information such as the uplink bandwidth, downlink bandwidth, slot number of each GPU in the first GPU cluster, the uplink bandwidth, downlink bandwidth, slot number of each GPU in the second GPU cluster, and the PCIe rate. Based on the first uplink configuration, the uplink between the second PCIe switching chip and the first PCIe switching chip can be made effective, and the second GPU cluster attached to the second PCIe switching chip and the first GPU cluster attached to the first PCIe switching chip can communicate through this uplink. The content of the first uplink configuration is not limited, as long as the second GPU cluster and the first GPU cluster can communicate through this uplink.

[0057] The second uplink configuration may include information such as the uplink bandwidth, downlink bandwidth, slot number of each GPU in the first GPU cluster, the uplink bandwidth, downlink bandwidth, slot number of each GPU in the second GPU cluster, and the PCIe rate. Based on the second uplink configuration, the uplink between the second PCIe switching chip and the second CPU can be made effective, and the second GPU cluster attached to the second PCIe switching chip and the first GPU cluster attached to the first PCIe switching chip can communicate through this uplink. The content of the first uplink configuration is not limited, as long as the second GPU cluster and the first GPU cluster can communicate through this uplink.

[0058] For example, when the second PCIe switching chip determines that the working mode of the server indicates that the server adopts an AI string topology structure, the second PCIe switching chip can start the first serial boot record image. Since the first serial boot record image stores the first uplink configuration corresponding to the uplink of the second PCIe switching chip and the first PCIe switching chip, by starting the first serial boot record image, the uplink between the second PCIe switching chip and the first PCIe switching chip can be made effective based on the first uplink configuration, that is, the second GPU cluster and the first GPU cluster communicate through the uplink between the second PCIe switching chip and the first PCIe switching chip. On the basis of the uplink between the second PCIe switching chip and the first PCIe switching chip becoming effective, since one uplink corresponding to the second PCIe switching chip becomes effective, the uplink between the second PCIe switching chip and the second CPU is made ineffective. In this way, the Figure 3 shown AI string topology structure can be obtained.

[0059] For example, when the logic device sends a first control signal (such as the MODE_SEL signal) to the second PCIe switching chip, the first control signal may include a first starting address corresponding to the first serial boot record image. That is, the first starting address represents the working mode information, and the working mode information indicates that the server adopts the AI string topology structure. Based on this, the second PCIe switching chip can obtain the first starting address from the first control signal and start the first serial boot record image based on the first starting address. For example, the second PCIe switching chip finds the first starting address and starts the first serial boot record image from the first starting address.

[0060] For example, referring to Figure 4 As shown, it is a schematic diagram of one-key topology switching. The second PCIe switching chip may include an SBR (Serial Boot Record) area. The SBR area may include 6 partition images, and these 6 partition images are used as 6 SBR images (serial boot record images), which are respectively called SBR IMAGE 0, SBR IMAGE 1, SBR IMAGE2, SBR IMAGE 3, SBR IMAGE 4, and SBR IMAGE 5. On this basis, 2 SBR images are selected from the 6 SBR images, and these 2 SBR images are used as the first serial boot record image and the second serial boot record image. For example, SBR IMAGE 0 can be used as the first serial boot record image, and SBR IMAGE 1 can be used as the second serial boot record image. SBR IMAGE 0 can be used as the first serial boot record image, and SBR IMAGE 4 can be used as the second serial boot record image. SBR IMAGE 3 can be used as the first serial boot record image, and SBR IMAGE 1 can be used as the second serial boot record image. There is no limit to this.

[0061] For each SBR image, the SBR image corresponds to a starting address. For example, SBR IMAGE 0 corresponds to the starting address 0x00 (0400 represents the length of the SBR image), SBR IMAGE 1 corresponds to the starting address 0x04, SBR IMAGE 2 corresponds to the starting address 0x08, SBR IMAGE 3 corresponds to the starting address 0x0C, SBR IMAGE 4 corresponds to the starting address 0x10, and SBR IMAGE 5 corresponds to the starting address 0x14.

[0062] If SBR IMAGE 0 is used as the first serial boot record image, when the logic device sends a first control signal to the second PCIe switching chip, the first control signal may include the first starting address 0x00 corresponding to SBR IMAGE 0. The second PCIe switching chip may obtain the first starting address 0x00 from the first control signal and start SBR IMAGE 0 based on the first starting address 0x00. By starting SBR IMAGE0, the uplink between the second PCIe switching chip and the first PCIe switching chip can be activated.

[0063] In the design process of the server, the GPIO (General Purpose Input Output) of the logic device (such as CPLD) can be connected to the configuration pins of the second PCIe switching chip, and the loading partition of the SBR can be configured through the GPIO to achieve topology switching. For example, the BMC controls the CPLD to output the MODE_SEL signal to select the uplink of the second PCIe switching chip for topology switching, that is, the BMC can control the CPLD to output 0x00 (that is, the MODE_SEL signal is 0x00), so that the second PCIe switching chip starts SBR IMAGE 0 based on the first starting address 0x00, thereby activating the uplink between the second PCIe switching chip and the first PCIe switching chip.

[0064] In one example, in the AI string topology structure, a 1:8 hanging ratio between the CPU and the GPU can be achieved, that is, 1 CPU corresponds to 8 GPUs. See Figure 3 In the shown AI string topology structure, the first CPU is connected to 4 GPUs through the first PCIe switching chip, and the first CPU is connected to 4 GPUs through the first PCIe switching chip and the second PCIe switching chip. In this way, the first CPU can correspond to 8 GPUs.

[0065] Obviously, in the AI string topology structure, the uplink of the second PCIe switching chip is connected to the first PCIe switching chip, the uplink of the first PCIe switching chip is connected to the first CPU, all 8 GPUs communicate through the PCIe switching chip, and the mounting ratio between the CPU and the GPU is 1:8, and the communication efficiency between the GPUs is optimal.

[0066] In the AI string topology structure, AI computing can be performed through the first GPU cluster and the second GPU cluster. For example, AI computing such as deep learning model training and deep learning inference can be achieved through the first GPU cluster and the second GPU cluster. The process of this AI computing is not limited in this embodiment.

[0067] In the AI string topology structure, the communication between the first GPU cluster and the second GPU cluster is forwarded through the first PCIe switching chip and the second PCIe switching chip, that is, the communication between the first GPU cluster and the second GPU cluster is not forwarded through the CPU. Obviously, during the AI computing process, the PCIe switching chip can be used to implement message forwarding without passing through the CPU, saving the computing resources of the CPU and making full use of the GPU resources. The GPU can undertake more AI computing, making the communication efficiency between GPUs optimal.

[0068] Second, the server supports the HPC topology structure. In the HPC topology structure, the uplink between the second PCIe switching chip and the second CPU can be enabled, and the uplink between the second PCIe switching chip and the first PCIe switching chip can be disabled. See Figure 5 shown in the schematic diagram of the HPC topology structure.

[0069] In an example, the BMC can obtain topology description information, which indicates that the server adopts the AI string topology structure or the server adopts the HPC topology structure. The BMC can determine that the server adopts the AI string topology structure or the HPC topology structure based on the topology description information. Taking the example that the server adopts the HPC topology structure, the BMC can send HPC topology structure enabling parameters to the logic device.

[0070] For example, the BMC sends an HPC topology structure enabling command to the logic device. The HPC topology structure enabling command includes HPC topology structure enabling parameters. For example, the HPC topology structure enabling command carries a second value (such as 1), and the HPC topology structure enabling parameters are represented by the second value.

[0071] For example, the logic device may include a register, and the BMC can write a second value (such as 1) into the register of the logic device, and the HPC topology structure enabling parameters are represented by the second value.

[0072] In an example, if the logic device receives the HPC topology structure enabling parameters, it determines that the server adopts the HPC topology structure. The logic device sends a second control signal to the second PCIe switching chip, and the second control signal is used to enable the second PCIe switching chip to determine that the working mode represents that the server adopts the HPC topology structure.

[0073] For example, the logic device can receive the HPC topology structure enabling command sent by the BMC. If the HPC topology structure enabling command carries a second value, it determines that it has received the HPC topology structure enabling parameters.

[0074] For example, a logic device can read the value of the register of this logic device. If the second value is read from the register of this logic device, it is determined that the HPC topology enable parameter is received.

[0075] For example, if a logic device receives the HPC topology enable parameter, it sends a second control signal to the second PCIe switching chip. The second control signal can be a MODE_SEL signal. The second control signal can carry working mode information, and this working mode information indicates that the server adopts the HPC topology.

[0076] In one example, the second PCIe switching chip can obtain the working mode. For example, if the second PCIe switching chip receives the second control signal, it obtains the working mode information from the second control signal and determines the working mode of the server based on this working mode information. Among them, if this working mode information indicates that the server adopts the HPC topology, it is determined that this working mode indicates that the server adopts the HPC topology.

[0077] When this working mode indicates that the server adopts the HPC topology, the second PCIe switching chip can activate the uplink between the second PCIe switching chip and the second CPU and deactivate the uplink between the second PCIe switching chip and the first PCIe switching chip to obtain the HPC topology. See Figure 5 shown, which is a schematic diagram of the HPC topology. Obviously, in the HPC topology, the second PCIe switching chip can be connected to the second CPU, and the second PCIe switching chip and the first PCIe switching chip can be not connected.

[0078] For example, the second PCIe switching chip includes a first serial boot record image and a second serial boot record image. The first serial boot record image can store the first uplink configuration corresponding to the uplink between the second PCIe switching chip and the first PCIe switching chip, and the second serial boot record image can store the second uplink configuration corresponding to the uplink between the second PCIe switching chip and the second CPU.

[0079] For example, when the second PCIe switching chip determines that the operating mode of the server indicates that the server adopts an HPC topology structure, the second PCIe switching chip can start the second serial boot record image. Since the second serial boot record image stores the second uplink configuration corresponding to the uplink between the second PCIe switching chip and the second CPU, by starting the second serial boot record image, the uplink between the second PCIe switching chip and the second CPU can be enabled based on the second uplink configuration, that is, the second GPU cluster and the first GPU cluster communicate through the uplink between the second PCIe switching chip and the second CPU. On the basis of enabling the uplink between the second PCIe switching chip and the second CPU, the uplink between the second PCIe switching chip and the first PCIe switching chip is disabled, so that the Figure 5 shown HPC topology structure can be obtained.

[0080] For example, when the logic device sends a second control signal (such as the MODE_SEL signal) to the second PCIe switching chip, the second control signal includes the second starting address corresponding to the second serial boot record image, that is, the second starting address represents the operating mode information, and the operating mode information indicates that the server adopts an HPC topology structure. Based on this, the second PCIe switching chip obtains the second starting address from the second control signal and starts the second serial boot record image based on the second starting address. For example, if SBR IMAGE 1 is used as the second serial boot record image, when the logic device sends a second control signal to the second PCIe switching chip, the second control signal includes the second starting address 0x04 corresponding to SBR IMAGE 1. The second PCIe switching chip obtains the second starting address 0x04 from the second control signal and starts SBR IMAGE 1 based on the first starting address 0x04. By starting SBR IMAGE 1, the uplink between the second PCIe switching chip and the second CPU is enabled.

[0081] During the design process of the server, the GPIO of the logic device (such as CPLD) can be connected to the configuration pins of the second PCIe switching chip, so that the loading partition of the SBR can be configured through the GPIO to realize the topology switching. For example, the BMC can be used to control the CPLD to output 0x04 (that is, the MODE_SEL signal is 0x04), so that the second PCIe switching chip starts SBR IMAGE 1 based on the first starting address 0x04, thereby enabling the uplink between the second PCIe switching chip and the second CPU.

[0082] In one example, in the HPC topology structure, a 1:4 connection ratio between the CPU and the GPU can be achieved, that is, 1 CPU corresponds to 4 GPUs. See Figure 5In the HPC topology shown, the first CPU is connected to 4 GPUs through the first PCIe switching chip, and the second CPU is connected to 4 GPUs through the second PCIe switching chip. In this way, the first CPU can correspond to 4 GPUs, and the second CPU can correspond to 4 GPUs.

[0083] Obviously, in the HPC topology, the upstream of the second PCIe switching chip is connected to the second CPU, and the upstream of the first PCIe switching chip is connected to the first CPU. In this way, every 4 GPUs (i.e., a GPU cluster) are mounted under the same 1 CPU, and two GPU clusters can be mounted under two CPUs. The mounting ratio between the CPU and the GPU is 1:4, which can achieve load balancing and the CPU has high computing power.

[0084] For example, in the HPC topology, HPC computing can be performed through the first GPU cluster and the second GPU cluster. The process of this HPC computing is not limited in this embodiment.

[0085] In the HPC topology, the communication between the first GPU cluster and the second GPU cluster is forwarded through the first PCIe switching chip, the first CPU, the second CPU, and the second PCIe switching chip, that is, the communication between the first GPU cluster and the second GPU cluster is forwarded through the first CPU and the second CPU. Obviously, during the HPC computing process, the CPU can be used to implement packet forwarding, so as to make full use of the computing resources of the CPU. The CPU can undertake more HPC computing, making the computing power of the CPU higher.

[0086] In one example, when the server adopts the AI string topology, the BMC can also obtain the changed topology description information. If it is determined that the server adopts the HPC topology based on the topology description information, the BMC sends the HPC topology enabling parameter to the logic device. The logic device sends a second control signal to the second PCIe switching chip. The second PCIe switching chip determines the working mode based on the second control signal, and the working mode indicates that the server adopts the HPC topology. On this basis, the second PCIe switching chip can activate the upstream link between the second PCIe switching chip and the second CPU, and deactivate the upstream link between the second PCIe switching chip and the first PCIe switching chip to obtain the HPC topology. This process will not be repeated here.

[0087] For example, when the server adopts the AI string topology, in the S5 state of the server, the BMC can also obtain the changed topology description information and implement dynamic switching of the topology based on the changed topology description information, that is, dynamically switch from the AI string topology to the HPC topology, rather than dynamically switching from the AI string topology to the HPC topology when the PCIE switching chip is working.

[0088] In one example, when the server adopts an HPC topology structure, the BMC can also obtain the changed topology description information. If it is determined based on the topology description information that the server adopts an AI string topology structure, the BMC sends the AI string topology structure enabling parameters to the logic device. The logic device sends a first control signal to the second PCIe switching chip. The second PCIe switching chip determines the working mode based on the first control signal, and the working mode indicates that the server adopts an AI string topology structure. On this basis, the second PCIe switching chip can activate the uplink between the second PCIe switching chip and the first PCIe switching chip, and deactivate the uplink between the second PCIe switching chip and the second CPU to obtain the AI string topology structure. This process will not be repeated here.

[0089] For example, when the server adopts an HPC topology structure, in the S5 state of the server, the BMC can also obtain the changed topology description information and implement dynamic switching of the topology structure based on the changed topology description information, that is, dynamically switch from the HPC topology structure to the AI string topology structure, rather than dynamically switching from the HPC topology structure to the AI string topology structure when the PCIE switching chip is working.

[0090] As can be seen from the above technical solutions, in the embodiments of the present application, by connecting the second PCIe switching chip to the second CPU and connecting the second PCIe switching chip to the first PCIe switching chip, in this way, by activating the uplink between the second PCIe switching chip and the first PCIe switching chip and deactivating the uplink between the second PCIe switching chip and the second CPU, an AI string topology structure can be obtained. By activating the uplink between the second PCIe switching chip and the second CPU and deactivating the uplink between the second PCIe switching chip and the first PCIe switching chip, an HPC topology structure can be obtained. Obviously, when the GPU server adopts a CPU-PCIe switching chip-GPU topology architecture, it can support multiple topology structures at the same time, such as supporting the AI string topology structure and the HPC topology structure at the same time, so as to meet the requirements of different artificial intelligence scenarios. Without changing the hardware connection of the GPU server, users can flexibly adjust to the corresponding topology structure according to the actual application scenario, realize one-key switching between different topologies, meet the requirement of realizing topology switching without changing the hardware connection, realize flexible switching of the topology, improve the switching efficiency and product competitiveness. In the AI string topology structure, the communication efficiency between GPUs is optimal, and in the HPC topology structure, the CPU computing power is higher. It is possible to realize one-key topology switching of the server based on the BMC and the logic device, and realize one-key switching of the topology by writing to the logic device to control the second PCIe switching chip to load different SBRs. The hanging ratios of 1:4 and 1:8 between the CPU and the GPU can be realized, so as to meet the requirements of different artificial intelligence scenarios.

[0091] Based on the same application concept as the above solution, a method for determining the topology structure of a server is proposed in an embodiment of the present application. The server may include a main board and a switching board. The main board may include a first CPU and a second CPU. The switching board may include a first PCIe switching chip, a second PCIe switching chip, a first GPU cluster, and a second GPU cluster. The first PCIe switching chip is connected to the first GPU cluster, and the second PCIe switching chip is connected to the second GPU cluster. The first PCIe switching chip is connected to the first CPU, the second PCIe switching chip is connected to the second CPU, and the second PCIe switching chip is connected to the first PCIe switching chip.

[0092] See Figure 6 As shown, it is a schematic flowchart of the method, and the method may include:

[0093] Step 601, obtain the working mode corresponding to the server.

[0094] Step 602, if the working mode indicates adopting an AI string topology structure, activate the uplink of the second PCIe switching chip and the first PCIe switching chip, and deactivate the uplink of the second PCIe switching chip and the second CPU to obtain an AI string topology structure. Among them, in the AI string topology structure, AI computing can be performed through the first GPU cluster and the second GPU cluster; the communication between the first GPU cluster and the second GPU cluster can be forwarded through the first PCIe switching chip and the second PCIe switching chip.

[0095] Step 603, if the working mode indicates adopting an HPC topology structure, activate the uplink of the second PCIe switching chip and the second CPU, and deactivate the uplink of the second PCIe switching chip and the first PCIe switching chip to obtain an HPC topology structure. Among them, in the HPC topology structure, HPC computing is performed through the first GPU cluster and the second GPU cluster; the communication between the first GPU cluster and the second GPU cluster is forwarded through the first PCIe switching chip, the first CPU, the second CPU, and the second PCIe switching chip.

[0096] In one example, the second PCIe switching chip may include a first serial boot record image and a second serial boot record image; the first serial boot record image may store a first uplink configuration corresponding to the uplink of the second PCIe switching chip and the first PCIe switching chip, and the second serial boot record image may store a second uplink configuration corresponding to the uplink of the second PCIe switching chip and the second CPU.

[0097] On this basis, enable the uplink of the second PCIe switching chip and the first PCIe switching chip, and disable the uplink of the second PCIe switching chip and the second CPU, to obtain an AI string topology structure, which may include, but is not limited to: obtaining a first starting address corresponding to a first serial boot record image, and starting the first serial boot record image based on the first starting address, so as to enable the uplink of the second PCIe switching chip and the first PCIe switching chip based on the first uplink configuration, and disable the uplink of the second PCIe switching chip and the second CPU, to obtain an AI string topology structure. In addition, enable the uplink of the second PCIe switching chip and the second CPU, and disable the uplink of the second PCIe switching chip and the first PCIe switching chip, to obtain an HPC topology structure, which may include, but is not limited to: obtaining a second starting address corresponding to a second serial boot record image, and starting the second serial boot record image based on the second starting address, so as to enable the uplink of the second PCIe switching chip and the second CPU based on the second uplink configuration, and disable the uplink of the second PCIe switching chip and the first PCIe switching chip, to obtain an HPC topology structure.

[0098] In one example, when the server adopts an AI string topology structure, it is also possible to obtain the changed topology description information. If it is determined based on the topology description information that the server adopts an HPC topology structure, then enable the uplink of the second PCIe switching chip and the second CPU, and disable the uplink of the second PCIe switching chip and the first PCIe switching chip, to obtain an HPC topology structure. Or, when the server adopts an HPC topology structure, it is also possible to obtain the changed topology description information. If it is determined based on the topology description information that the server adopts an AI string topology structure, then enable the uplink of the second PCIe switching chip and the first PCIe switching chip, and disable the uplink of the second PCIe switching chip and the second CPU, to obtain an AI string topology structure.

[0099] In one example, the first PCIe switching chip can be connected to the first CPU through a first high-speed cable; the second PCIe switching chip can be connected to the second CPU through a second high-speed cable; the second PCIe switching chip can be connected to the first PCIe switching chip through a third high-speed cable.

[0100] Based on the same application concept as the above method, an embodiment of the present application proposes a server. Refer to Figure 7 As shown, the server may include: a processor 71 and a machine-readable storage medium 72. The machine-readable storage medium 72 stores machine-executable instructions that can be executed by the processor 71; the processor 71 is used to execute the machine-executable instructions to implement the topology structure determination method of the server disclosed in the above examples of the present application.

[0101] Based on the same application concept as the above method, an embodiment of the present application further provides a machine-readable storage medium, on which a number of computer instructions are stored. When the computer instructions are executed by a processor, the method for determining the topology structure of the server disclosed in the above examples of the present application can be implemented.

[0102] Among them, the above machine-readable storage medium can be any electronic, magnetic, optical or other physical storage device that can contain or store information, such as executable instructions, data, etc. For example, the machine-readable storage medium can be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drives (such as hard disk drives), solid-state drives, any type of storage disk (such as optical discs, DVDs, etc.), or similar storage media, or a combination thereof.

[0103] Based on the same application concept as the above method, an embodiment of the present application further provides a computer program product, which may include a computer program. When the computer program is executed by a processor, the method for determining the topology structure of the server disclosed in the above examples of the present application is implemented.

[0104] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0105] The above are only the embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A server, characterized in that: The server includes a mainboard and a switch board, the mainboard includes a first CPU and a second CPU, the switch board includes a first PCIe switch chip, a second PCIe switch chip, a first GPU cluster and a second GPU cluster; the first PCIe switch chip is connected to the first GPU cluster, and the second PCIe switch chip is connected to the second GPU cluster; The first PCIe switch chip is connected to the first CPU, the second PCIe switch chip is connected to the second CPU, and the second PCIe switch chip is connected to the first PCIe switch chip; The second PCIe switching chip is used to obtain the working mode; If the working mode indicates that the server adopts an AI string topology structure, the uplink between the second PCIe switching chip and the first PCIe switching chip is enabled, and the uplink between the second PCIe switching chip and the second CPU is disabled, thereby obtaining an AI string topology structure; wherein, under the AI ​​string topology structure, AI calculation is performed through the first GPU cluster and the second GPU cluster; and communication between the first GPU cluster and the second GPU cluster is forwarded through the first PCIe switching chip and the second PCIe switching chip; If the working mode indicates that the server adopts an HPC topology structure, the uplink between the second PCIe switching chip and the second CPU is enabled, and the uplink between the second PCIe switching chip and the first PCIe switching chip is disabled, thereby obtaining an HPC topology structure; wherein, under the HPC topology structure, HPC computing is performed through the first GPU cluster and the second GPU cluster; and communication between the first GPU cluster and the second GPU cluster is forwarded through the first PCIe switching chip, the first CPU, the second CPU, and the second PCIe switching chip.

2. The server according to claim 1, characterized in that: The mainboard further includes a BMC and a logic device; wherein the logic device is connected to the second PCIe switch chip, and the BMC is connected to the logic device; The BMC is used to obtain topology description information, and determine whether the server adopts an AI string topology structure or an HPC topology structure based on the topology description information; if the server adopts an AI string topology structure, an AI string topology structure enabling parameter is sent to the logic device; The logic device is used to send a first control signal to the second PCIe switching chip if the AI ​​string topology enable parameter is received, so that the second PCIe switching chip determines the working mode based on the first control signal, and the working mode indicates that the server adopts the AI ​​string topology.

3. The server according to claim 2, characterized in that: The BMC is further configured to send an HPC topology enabling parameter to the logic device if the server adopts an HPC topology; The logic device is further configured to send a second control signal to the second PCIe switch chip if the HPC topology enabling parameter is received, so that the second PCIe switch chip determines the working mode based on the second control signal, and the working mode indicates that the server adopts the HPC topology.

4. The server according to claim 3, characterized in that: The BMC is further configured to write a first value in a register of the logic device if the server adopts an AI string topology structure, the first value representing an AI string topology structure enabling parameter; and write a second value in the register if the server adopts an HPC topology structure, the second value representing an HPC topology structure enabling parameter; The logic device is further used to determine that the AI ​​string topology structure enabling parameter is received if the first value is read from the register; or to determine that the HPC topology structure enabling parameter is received if the second value is read from the register.

5. The server according to claim 1 or 3, characterized in that: The second PCIe switch chip includes a first serial boot record image and a second serial boot record image; The first serial boot record image stores a first uplink configuration corresponding to an uplink between the second PCIe switch chip and the first PCIe switch chip, and the second serial boot record image stores a second uplink configuration corresponding to an uplink between the second PCIe switch chip and the second CPU; The second PCIe switching chip is also used to start the first serial boot record image to validate the uplink between the second PCIe switching chip and the first PCIe switching chip based on the first uplink configuration, and disable the uplink between the second PCIe switching chip and the second CPU to obtain an AI string topology structure; or, start the second serial boot record image to validate the uplink between the second PCIe switching chip and the second CPU based on the second uplink configuration, and disable the uplink between the second PCIe switching chip and the first PCIe switching chip to obtain an HPC topology structure.

6. The server according to claim 5, characterized in that: The first control signal includes a first starting address corresponding to the first serial boot record image, and the second PCIe switch chip is further used to obtain the first starting address from the first control signal and start the first serial boot record image based on the first starting address; or, The second control signal includes a second starting address corresponding to the second serial boot record image. The second PCIe switching chip is further used to obtain the second starting address from the second control signal and start the second serial boot record image based on the second starting address.

7. The server according to claim 3, characterized in that: In the case where the server adopts an AI string topology structure, the BMC is further used to obtain the changed topology description information, determine that the server adopts an HPC topology structure based on the topology description information, and send an HPC topology structure enabling parameter to the logic device; the logic device is further used to send a second control signal to the second PCIe switching chip; the second PCIe switching chip is further used to determine a working mode based on the second control signal, and the working mode indicates that the server adopts an HPC topology structure; the uplink between the second PCIe switching chip and the second CPU is enabled, and the uplink between the second PCIe switching chip and the first PCIe switching chip is disabled, so as to obtain an HPC topology structure; In the case where the server adopts the HPC topology structure, the BMC is further used to obtain the changed topology description information, determine that the server adopts the AI ​​string topology structure based on the topology description information, and send the AI ​​string topology structure enable parameter to the logic device; the logic device is further used to send a first control signal to the second PCIe switching chip; the second PCIe switching chip is further used to determine a working mode based on the first control signal, and the working mode indicates that the server adopts the AI ​​string topology structure; the uplink between the second PCIe switching chip and the first PCIe switching chip is enabled, and the uplink between the second PCIe switching chip and the second CPU is disabled to obtain the AI ​​string topology structure.

8. The server according to any one of claims 1 to 4, characterized in that: The first PCIe switch chip is connected to the first CPU via a first high-speed cable; The second PCIe switch chip is connected to the second CPU via a second high-speed cable; The second PCIe switch chip is connected to the first PCIe switch chip through a third high-speed cable.

9. A method for determining a server topology structure, characterized in that: The server includes a mainboard and a switch board, the mainboard includes a first CPU and a second CPU, the switch board includes a first PCIe switch chip, a second PCIe switch chip, a first GPU cluster and a second GPU cluster; the first PCIe switch chip is connected to the first GPU cluster, and the second PCIe switch chip is connected to the second GPU cluster; the first PCIe switch chip is connected to the first CPU, the second PCIe switch chip is connected to the second CPU, and the second PCIe switch chip is connected to the first PCIe switch chip; the method includes: Obtaining the working mode corresponding to the server; If the working mode indicates that an AI string topology structure is adopted, the uplink between the second PCIe switching chip and the first PCIe switching chip is enabled, and the uplink between the second PCIe switching chip and the second CPU is disabled, thereby obtaining an AI string topology structure; wherein, under the AI ​​string topology structure, AI calculation is performed through the first GPU cluster and the second GPU cluster; and communication between the first GPU cluster and the second GPU cluster is forwarded through the first PCIe switching chip and the second PCIe switching chip; If the working mode indicates the use of an HPC topology structure, the uplink between the second PCIe switching chip and the second CPU is enabled, and the uplink between the second PCIe switching chip and the first PCIe switching chip is disabled, thereby obtaining an HPC topology structure; wherein, under the HPC topology structure, HPC computing is performed through the first GPU cluster and the second GPU cluster; and communication between the first GPU cluster and the second GPU cluster is forwarded through the first PCIe switching chip, the first CPU, the second CPU, and the second PCIe switching chip.

10. The method according to claim 9, characterized in that The second PCIe switch chip includes a first serial boot record image and a second serial boot record image; The first serial boot record image stores a first uplink configuration corresponding to an uplink between the second PCIe switch chip and the first PCIe switch chip, and the second serial boot record image stores a second uplink configuration corresponding to an uplink between the second PCIe switch chip and the second CPU; The uplink between the second PCIe switching chip and the first PCIe switching chip is enabled, the uplink between the second PCIe switching chip and the second CPU is disabled, and an AI string topology structure is obtained, including: obtaining a first starting address corresponding to the first serial boot record image, starting the first serial boot record image based on the first starting address, enabling the uplink between the second PCIe switching chip and the first PCIe switching chip based on the first uplink configuration, disabling the uplink between the second PCIe switching chip and the second CPU, and obtaining an AI string topology structure; The uplink between the second PCIe switch chip and the second CPU is enabled, and the uplink between the second PCIe switch chip and the first PCIe switch chip is disabled to obtain an HPC topology structure, including: obtaining a second starting address corresponding to the second serial boot record image, starting the second serial boot record image based on the second starting address, enabling the uplink between the second PCIe switch chip and the second CPU based on the second uplink configuration, disabling the uplink between the second PCIe switch chip and the first PCIe switch chip, and obtaining an HPC topology structure.

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