Chip first-in first-out queue automatic generation method, electronic equipment and medium

Abstract

The invention relates to the technical field of chips, in particular to a chip first-in first-out queue automatic generation method, electronic equipment and a medium, and the method comprises the following steps: S1, obtaining chip composition module combinations needing to be interconnected based on a Credit-Debit bus protocol in chips; step S2, inserting Credit-Debit bus protocol information Cn into the A < n >; s3, generating a corresponding sending end first-in FIFO module En with the depth Dn outside the An based on the Cn, and generating a receiving end FIFO module Fn with the depth Dn corresponding to the Bn outside the Bn; and S4, based on the Cn, interconnecting the output port of the An with the input port of the En, interconnecting the output port of the En with the input port of the Fn, and interconnecting the output port of the Fn with the input port of the Bn. According to the invention, the accuracy of FIFO generation of the chip composition module interconnected based on the Credit-Detail bus protocol is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular, to a method for automatically generating a chip first-in-first-out queue, an electronic device, and a medium. Background Art

[0002] In chip design, chip component modules can be interconnected based on the Credit-Debit bus protocol. The Credit-Debit bus protocol is a protocol for data transmission and communication on the bus inside or between chips. It controls the flow of data based on the credit and debit mechanisms to ensure the efficiency, reliability, and orderliness of data transmission. This protocol is similar to the accounting method of a bank account. The sender and receiver of data transmitted on the bus both have corresponding "credit limits" and "debit operations" for managing the sending and receiving of data. In two chip component modules interconnected based on the Credit-Debit bus protocol, a first-in-first-out queue (FIFO for short) with the same depth needs to be set respectively to record the number of requests and responses. During the chip design process, the depth of the FIFO is passed in as a parameter. Due to various factors, such as the two chip component modules being responsible for by different teams or parameter transmission errors, etc., the depths of the FIFOs set in the two chip component modules interconnected based on the Credit-Debit bus protocol are different, resulting in problems such as data overflow during operation. Due to the large scale of the chip, it is very difficult to debug. Therefore, how to improve the accuracy of FIFO generation of chip component modules interconnected based on the Credit-Debit bus protocol has become an urgent technical problem to be solved. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for automatically generating a chip first-in-first-out queue, an electronic device, and a medium, which improves the accuracy of FIFO generation of chip component modules interconnected based on the Credit-Debit bus protocol.

[0004] According to a first aspect of the present invention, there is provided a method for automatically generating a chip first-in-first-out queue, including: Step S1, obtaining the chip component module combinations {(A1, B1), (A2, B2),..., (A n , B n ),..., (A N , B N )} that need to be interconnected based on the Credit-Debit bus protocol in the chip, A nThe nth transmitting end chip component module in the chip that needs to be interconnected based on the Credit-Debit bus protocol, B n is A n The corresponding receiving module, where the value range of n is from 1 to N, and N is the total number of combinations of chip component modules in the chip that need to be interconnected based on the Credit-Debit bus protocol; Step S2, insert the Credit-Debit bus protocol information C n into A n , and C n contains the FIFO depth D n corresponding to A n and B n ; Step S3, based on C n generate a transmitting end first-in FIFO module E n with a depth of D n outside A n , and generate a receiving end FIFO module F n with a depth of D n corresponding to B n outside B n ; n ; Step S4, based on C n interconnect the output port of A n with the input port of E n , interconnect the output port of E n with the input port of F n , and interconnect the output port of F n with the input port of B n .

[0005] According to the second aspect of the present invention, there is provided an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the first aspect of the present invention.

[0006] According to the third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, and the computer instructions are used to execute the method described in the first aspect of the present invention.

[0007] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solutions, a method for automatically generating a chip first-in first-out queue, an electronic device, and a medium provided by the present invention can achieve considerable technical progressiveness and practicality, and have wide industrial utilization value. It has at least the following beneficial effects: In the present invention, by inserting Credit-Debit bus protocol information including the FIFO depth into each module composed of transmitting-end chips interconnected based on the Credit-Debit bus protocol, a FIFO with the FIFO depth is generated for the module composed of transmitting-end chips and the module composed of receiving-end chips based on the Credit-Debit bus protocol information in the module composed of transmitting-end chips, and an interconnection relationship is established. The present invention can ensure that the FIFOs generated by the module composed of transmitting-end chips and the module composed of receiving-end chips interconnected based on the Credit-Debit bus protocol have the same depth, improving the accuracy of FIFO generation for the module composed of chips interconnected based on the Credit-Debit bus protocol. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0009] Figure 1 It is a flowchart of a method for automatically generating a first-in-first-out queue of chips provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0010] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0011] An embodiment of the present invention provides a method for automatically generating a first-in-first-out queue of chips, as Figure 1 shown, including: Step S1, obtaining a combination of chip modules to be interconnected based on the Credit-Debit bus protocol in the chip {(A1, B1), (A2, B2),..., (A n , B n ),..., (A N , B N ),...,(A n is the nth module composed of transmitting-end chips in the chip that needs to be interconnected based on the Credit-Debit bus protocol, B n is the receiving module corresponding to A n , and the value range of n is from 1 to N, where N is the total number of combinations of chip modules to be interconnected based on the Credit-Debit bus protocol in the chip.

[0012] Among them, the Credit-Debit bus protocol is a protocol used for data transmission and communication on the bus inside or between chips. It controls the flow of data based on the Credit and Debit mechanisms to ensure the efficiency, reliability, and orderliness of data transmission. This protocol is similar to the accounting method of a bank account. Both the sender and receiver of data transmitted on the bus have corresponding "credit limits" and "debit operations" to manage the sending and receiving of data.

[0013] Step S2: Insert the Credit-Debit bus protocol information C n into A n , and C n contains the corresponding FIFO depth D n of A n and B n .

[0014] It should be noted that in the embodiments of the present invention, it is only necessary to insert the Credit-Debit bus protocol information into the sending-end chip component module. Both the sending-end chip component module and the corresponding receiving-end chip component module generate corresponding FIFO modules based on the Credit-Debit bus protocol information inserted in the sending-end chip component module.

[0015] As an embodiment, Cn further includes signal description information, timing diagram information, direction information, signal width information, reset value, and default value. Among them, the signal description information is used to describe the signal and can be used to generate documents. The direction information includes input, output, inout, which is configured according to the specific direction of the signal. The signal width information can be set as a fixed value or a configurable value. The reset value and default value are pre-configured according to the specific signal.

[0016] Step S3: Based on C n generate a corresponding sending-end FIFO module E n with a depth of D n outside A n , and generate a corresponding receiving-end FIFO module F n with a depth of D n outside B n for B n n .

[0017] ​It should be noted that in the prior art, corresponding FIFO modules are generated in the transmitting - end chip component module and the receiving - end chip component module respectively based on the parameters of the FIFO depth received by the transmitting - end chip component module and the receiving - end chip component module. However, in the present invention, corresponding FIFO modules are independently generated outside the transmitting - end chip component module and the receiving - end chip component module respectively based on the same FIFO depth, which can ensure that the FIFO module depths generated by the transmitting - end chip component module and the receiving - end chip component module are the same.

[0018] Step S4. Based on C n Connect the output port of A n to the input port of E n Connect the output port of E n to the input port of F n Connect the output port of F n to the input port of B n Connect them.

[0019] It should be noted that through step S4, the transmitting - end chip component module, the FIFO module corresponding to the transmitting - end chip component module, the receiving - end chip component module, and the FIFO module corresponding to the receiving - end chip component module are interconnected, ensuring that the transmitting - end chip component module and the transmitting - end chip component module interact based on the Credit - Debit bus protocol. The FIFO module corresponding to the transmitting - end chip component module is used to record the number of requests, and the receiving - end chip component module is used to record the number of responses.

[0020] As an embodiment, step S4 includes: Step S41. Set the input port name of E n to be the same as the output port name of A n Set them to the same port name.

[0021] Step S42. Set the output port name of E n and the input port name of F n to be the same port name.

[0022] Step S43. Set the output port name of F n and the input port name of B n to be the same port name.

[0023] Step S44. Connect the ports with the same port name based on the corresponding C n Establish an interconnection.

[0024] It should be noted that through steps S41 - S44, the output port of A n can be interconnected with the input port of E n Connect the output port of En 's output port is interconnected with the input port of F n , and the output port of F n is interconnected with the input port of B n . In the prior art, the output port of A n is directly interconnected with the input port of B n . The embodiment of the present invention is equivalent to inserting a FIFO module corresponding to the transmitting - end chip composition module and a FIFO module corresponding to the receiving - end chip composition module between the output port of A n and the input port of B n . Moreover, the FIFO module corresponding to the transmitting - end chip composition module and the FIFO module corresponding to the receiving - end chip composition module are generated based on the same depth, so they must have the same depth.

[0025] After the FIFO module corresponding to the transmitting - end chip composition module and the FIFO module corresponding to the receiving - end chip composition module are set up, when the number of cached data in the FIFO module reaches the corresponding depth, it reaches the first - in - first - out queue full (FIFO full) state, which will trigger the verification of the logic corresponding to the FIFO full state. However, due to various factors, many FIFO modules are released before reaching the FIFO full state, so many FIFOs never reach the FIFO full state during the entire verification process, resulting in many logics corresponding to the FIFO full state not being verified, and the chip verification coverage rate is low. Based on this, the embodiment of the present invention further proposes a solution. As an embodiment, after step S4, it further includes: Step S5: Set a corresponding virtual depth for the FIFO to be tested in the chip design. The virtual depth corresponding to the FIFO to be tested is less than or equal to the actual depth corresponding to the FIFO to be tested. The FIFO to be tested is E n or F n .

[0026] Step S6: When the depth of the currently stored information in the FIFO to be tested reaches the virtual depth corresponding to the FIFO to be tested, trigger the logic simulation of the full state of the FIFO to be tested.

[0027] As an embodiment, the method further includes: Step S0: Set a FIFO virtual - depth configuration file {F1, F2,..., F m ,..., F M} corresponding to the chip design. F m is the virtual - depth configuration information of the m - th FIFO to be tested in the chip design. F m = {F1 m , F2 m , F3m}, F1 m is F m The corresponding virtual depth configuration mode, and the virtual depth configuration mode includes a fixed mode and a random mode, F2 m is F m The corresponding time window, F m The corresponding time window is less than or equal to the chip simulation time. When F1 m is the fixed mode, F3 m is the fixed virtual depth value. When F1 m is the random mode, F3 m is the virtual depth range, and the maximum value of the virtual depth range is less than or equal to the actual depth corresponding to the FIFO to be measured.

[0028] It should be noted that through the fixed mode, the virtual depth of the FIFO can be set to a fixed value. Through the random mode, the virtual depth value of the FIFO can be reasonably set within the range of the virtual depth range. Through the time window, the time interval for setting the virtual depth can be controlled, so as to meet the different FIFO virtual depth configuration requirements of different FIFOs to be measured. If a part of the FIFO modules in the chip do not need to set the depth to verify the FIFO full state, the virtual depth configuration information of the FIFO can not be set for this part of the FIFO modules, and the actual depth corresponding to the FIFO can be used by default. That is, only the FIFO modules with the need to set the virtual depth in the embodiments of the present invention are used as the FIFOs to be measured.

[0029] As an embodiment, the step S5 includes: Step S51: If the depth configuration mode corresponding to the FIFO to be measured is the fixed mode, set the virtual depth corresponding to the FIFO to be measured to the corresponding fixed virtual depth value within the corresponding time window, and set the virtual depth corresponding to the FIFO to be measured to the actual depth of the FIFO to be measured at the time outside the corresponding time window.

[0030] It should be noted that based on {F1, F2,..., F m ,..., F M}, the {F1 m , F2 m , F3 m} corresponding to the FIFO to be measured can be determined, and step S51 is implemented based on {F1 m , F2 m , F3 m}.

[0031] As an embodiment, the step S5 includes: Step C51: If the depth configuration mode corresponding to the FIFO under test is the random mode, generate a random depth value within the corresponding virtual depth range in the time window as the virtual depth corresponding to the FIFO under test, and set the virtual depth corresponding to the FIFO under test to the actual depth corresponding to the FIFO under test at times outside the corresponding time window.

[0032] It should be noted that based on {F1, F2,..., F m ,..., F M}, the {F1 m , F2 m , F3 m} corresponding to the FIFO under test can be determined, and step C51 is implemented based on {F1 m , F2 m , F3 m}.

[0033] As an embodiment, the step S5 includes: Step E51: Set a corresponding interface module for the FIFO under test, and interconnect the FIFO under test with the interface module corresponding to the FIFO under test.

[0034] It should be noted that the FIFO under test is the FIFO set in the chip design. The FIFO under test and the interface module corresponding to the FIFO under test can be interconnected in a binding manner. Specifically, the interface module corresponding to the FIFO under test can be connected to the clock signal line, reset signal line, and full status signal line of the FIFO under test.

[0035] Step E52: Set the virtual depth corresponding to the FIFO under test in the interface module corresponding to the FIFO under test.

[0036] It should be noted that the size of the virtual depth corresponding to the FIFO under test depends on the specific situation of the FIFO under test. Step E52 is specifically implemented based on the interface module corresponding to the FIFO under test through step S51 or step C51.

[0037] As an implementation, the step S6 includes: Step S61: During the chip simulation process, if the depth of the information currently stored in the FIFO under test reaches the virtual depth corresponding to the FIFO under test, the interface module corresponding to the FIFO under test will force the full status signal corresponding to the FIFO under test to be high, triggering the logical simulation of the full status of the FIFO under test.

[0038] It should be noted that by setting the virtual depth corresponding to the FIFO under test and triggering the logical simulation of the full state of the FIFO under test when the depth of the currently stored information in the FIFO under test reaches the virtual depth corresponding to the FIFO under test, it is easier to verify the FIFO full state of the FIFO under test, improving the chip verification coverage rate.

[0039] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts depict the steps as sequential processes, many of the steps can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operations are completed, but it can also have additional steps not included in the figures. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0040] An embodiment of the present invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiments of the present invention.

[0041] An embodiment of the present invention also provides a computer-readable storage medium storing computer-executable instructions for executing the method described in the embodiments of the present invention.

[0042] In the embodiments of the present invention, by inserting Credit-Debit bus protocol information including the FIFO depth into each transmitting-end chip component module interconnected based on the Credit-Debit bus protocol, generating FIFOs with the FIFO depth for the transmitting-end chip component module and the receiving-end chip component module based on the Credit-Debit bus protocol information in the transmitting-end chip component module, and establishing an interconnection relationship, the present invention can ensure that the FIFOs generated by the transmitting-end chip component module and the receiving-end chip component module interconnected based on the Credit-Debit bus protocol have the same depth, improving the accuracy of FIFO generation for the chip component modules interconnected based on the Credit-Debit bus protocol.

[0043] The above are only preferred embodiments of the present invention and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to obtain equivalent embodiments with equivalent changes. However, as long as the content does not depart from the technical solution of the present invention, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for automatically generating a chip first-in-first-out queue, characterized in that, Comprising: Step S1. Obtain the combinations of chip component modules in the chip that need to be interconnected based on the Credit-Debit bus protocol {(A1, B1), (A2, B2),..., (A n , B n ),..., (A N , B N )}, where A n is the nth transmitting-end chip component module in the chip that needs to be interconnected based on the Credit-Debit bus protocol, and B n is the corresponding receiving module of A n . The value range of n is from 1 to N, and N is the total number of combinations of chip component modules in the chip that need to be interconnected based on the Credit-Debit bus protocol; Step S2. At A n Insert the Credit-Debit bus protocol information C n , where C n contains A n and B n corresponding FIFO depth D n ; Step S3, based on C n Outside A n External C n Generate a corresponding transmit - side FIFO module E with depth D n ; outside B n Generate a corresponding receive - side FIFO module F with depth D n External B n ; n n n ; Step S4, based on C n Connect the output port of A n to the input port of E n Connect the output port of E n to the input port of F n Connect the output port of F n to the input port of B n for interconnection.

2. The method according to claim 1, wherein C n It also includes signal description information, timing diagram information, direction information, signal width information, reset value, and default value.

3. The method according to claim 1, wherein The step S4 comprises: Step S41. Set the input port name of E n to be the same as the output port name of A n ; set the output port name of E Step S42: Set the output port name of E n to be the same as the input port name of F n ; Step S43: Set the output port name of F n to be the same as the input port name of B n ; Step S44: Interconnect the ports with the same port name based on the corresponding C n establish an interconnection.

4. The method according to claim 1, wherein After the step S4, it further comprises: Step S5: Set a corresponding virtual depth for the FIFO to be tested in the chip design. The virtual depth corresponding to the FIFO to be tested is less than or equal to the actual depth corresponding to the FIFO to be tested. The FIFO to be tested is E n or F n ; Step S6, when the depth of the information currently stored in the FIFO to be tested reaches the virtual depth corresponding to the FIFO to be tested, trigger the execution of the logic simulation of the full state of the FIFO to be tested.

5. The method according to claim 4, wherein The method further comprises: Step S0, set the FIFO virtual depth configuration file {F1, F2,..., F m ,..., F M} for the chip design. F m is the virtual depth configuration information of the m-th FIFO to be tested in the chip design. F m ={F1 m , F2 m , F3 m}. F1 m is the virtual depth configuration mode corresponding to F m . The virtual depth configuration mode includes a fixed mode and a random mode. F2 m is the time window corresponding to F m . The time window corresponding to F m is less than or equal to the chip simulation time. When F1 m is in the fixed mode, F3 m is a fixed virtual depth value. When F1 m is in the random mode, F3 m is a virtual depth interval, and the maximum value of the virtual depth interval is less than or equal to the actual depth corresponding to the FIFO to be tested.

6. The method according to claim 5, wherein The step S5 comprises: Step S51, if the depth configuration mode corresponding to the FIFO to be tested is the fixed mode, set the virtual depth corresponding to the FIFO to be tested to the corresponding fixed virtual depth value within the corresponding time window, and set the virtual depth corresponding to the FIFO to be tested to the actual depth of the FIFO to be tested at times outside the corresponding time window.

7. The method according to claim 5, wherein The step S5 comprises: Step C51, if the depth configuration mode corresponding to the FIFO to be tested is the random mode, generate a random depth value within the corresponding virtual depth range as the virtual depth corresponding to the FIFO to be tested within the corresponding time window, and set the virtual depth corresponding to the FIFO to be tested to the actual depth of the FIFO to be tested at times outside the corresponding time window.

8. An electronic device, characterized in that, Comprising: At least one processor; And a memory communicatively connected to the at least one processor; Wherein, the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method according to any one of the foregoing claims 1-7.

9. A computer-readable storage medium, characterized in that, Stores computer-executable instructions for executing the method according to any one of the foregoing claims 1-7.

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