8bit-ADC (Analog to Digital Converter) digital compensation circuit applied to FLASH storage calculation

Abstract

The invention discloses an 8bit-ADC (Analog to Digital Converter) digital compensation circuit applied to FLASH storage and calculation, and belongs to the field of digital integrated circuits. According to the invention, an error compensation selection switch is used for selecting a correction strategy of an ADC to be started; the gain error compensation module is used for correcting the linear gain error of the ADC; the bias error compensation module is used for correcting the bias error of the ADC; the piecewise error compensation module is used for correcting piecewise linear errors of the ADC and supports single-bit correction. According to the invention, the reliability of a calculation result can be remarkably improved, high-precision and low-delay ADC error compensation is realized through a lightweight digital correction algorithm on the premise of not needing an additional simulation module, and meanwhile, the energy efficiency advantage of a storage and calculation integrated framework is kept.

Description

Technical Field

[0001] The present invention relates to the technical field of digital integrated circuits, and particularly relates to an 8-bit ADC digital compensation circuit applied to FLASH computing-in-memory. Background Art

[0002] With the rapid development of technologies such as artificial intelligence and edge computing, the computing-in-memory (CIM) architecture has become one of the core technologies for realizing high-density parallel computing due to its high energy efficiency and low latency characteristics. As a typical implementation scheme of computing-in-memory, the FLAH computing-in-memory circuit directly completes analog-domain computing operations in storage units (such as FLASH memories), which can significantly reduce data transfer overhead and is suitable for scenarios such as low-power AI accelerators and Internet of Things terminals. However, in the FLAH computing-in-memory system, the accuracy of the analog-to-digital converter (ADC) directly affects the reliability of the computing results, and its error problem has become a key bottleneck restricting the system performance.

[0003] Existing ADC compensation schemes need to introduce additional analog circuits, resulting in an increase in chip area and power consumption. Moreover, software algorithms based on two-point calibration or multi-point piecewise linearization need to be pre-calibrated and are difficult to cope with real-time disturbances such as dynamic load changes and temperature drift in the computing-in-memory circuit. Summary of the Invention

[0004] The purpose of the present invention is to provide an 8-bit ADC digital compensation circuit applied to FLASH computing-in-memory to solve the problems in the background art.

[0005] To solve the above technical problems, the present invention provides an 8-bit ADC digital compensation circuit applied to FLASH computing-in-memory, including: An error compensation selection switch for selecting to enable the correction strategy of the ADC; A gain error compensation module for correcting the linear gain error of the ADC; A bias error compensation module for correcting the bias error of the ADC; A piecewise error compensation module for correcting the piecewise linear error of the ADC, supporting single-bit correction; wherein, In one embodiment, when the ADC error belongs to a linear error, the error compensation selection switch is configured as 2'b011, indicating that gain compensation and bias compensation are enabled; Two registers for configuring gain compensation. The register with a bit width of 16 bits is multiplied by the ADC input value in a multiplication form for correction, and the register with a bit width of 8 bits shifts the ADC input value to the right in a shift form for correction, and the corresponding values A and B are filled according to the coefficients fitted by software; Configure the register for offset compensation and fill in the corresponding value C according to the coefficient obtained by software fitting; At this time, the value input to the ADC is X, and after correction, a new value is obtained , and the Y value is the input value of the ADC after correction; In one embodiment, when the ADC error belongs to piecewise linear error, configure the error compensation selection switch to 2'b111, indicating that the gain compensation, offset compensation, and piecewise compensation functions are enabled; Configure two registers for gain compensation. The register with a bit width of 16 bits is multiplied by the ADC input value in a multiplicative form for correction, and the register with a bit width of 8 bits shifts the ADC input value to the right in a shift form for correction. Fill in the corresponding values A and B according to the coefficient obtained by software fitting; Configure the register for offset compensation and fill in the corresponding value C according to the coefficient obtained by software fitting; Configure the register for piecewise compensation. Each bit of the ADC input is multiplied by the value of each 16-bit register to correct the piecewise error; set the values of these 8 registers to D0, D1, D2, D3, D4, D5, D6, and D7 respectively; At this time, the value input to the ADC is X. Set each bit of it to X0, X1, X2, X3, X4, X5, X6, and X7. After correction, a new value is obtained , and the Y value is the input value of the ADC after correction.

[0006] In one embodiment, the error compensation selection switch includes a register with a 3-bit width. When the register value is 0, the ADC compensation function is not started; when the lowest bit is 1, the gain error compensation module is started; when the middle bit is 1, the offset error compensation module is started; when the highest bit is 1, the piecewise error compensation module is started; the error compensation selection switch starts a single type of compensation or, according to different situations, simultaneously enables multiple compensation functions.

[0007] In one embodiment, the gain error compensation module includes a register with a 16-bit width and a register with an 8-bit width, supporting a maximum amplification of 65535 times and a reduction correction of 2 255 times.

[0008] In one embodiment, the offset error compensation module includes a signed register with an 8-bit width, supporting a maximum offset compensation of plus or minus 128.

[0009] In one embodiment, the piecewise error compensation module is composed of 8 16-bit registers, corresponding to each bit input of the 8-bit ADC, and correcting each bit input accordingly.

[0010] In one embodiment, the segmented error compensation module is used in conjunction with the gain error compensation module. The segmented error compensation module corrects the input of the ADC, which expands the input value of the ADC, and then uses the shrinking function of the gain error compensation module to shrink the value of the ADC to a specified number of digits.

[0011] An 8-bit ADC digital compensation circuit for FLASH memory and computing provided by the present invention realizes high-precision and low-latency ADC error compensation through a lightweight digital correction algorithm without the need for an additional analog module. The present invention integrates the signal characteristics of the memory and computing system with the ADC non-linear model, and can effectively compensate for linear or non-linear errors of the ADC according to different configurations, significantly improving the reliability of the calculation results while maintaining the energy efficiency advantage of the memory and computing integrated architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic structural diagram of an 8-bit ADC digital compensation circuit for FLASH memory and computing provided by the present invention.

[0013] Figure 2 is a schematic diagram of the correction process when the ADC error is a linear error.

[0014] Figure 3 is a schematic diagram of the correction process when the ADC error is a segmented linear error. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] The following further details an 8-bit ADC digital compensation circuit for FLASH memory and computing proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0016] The present invention provides an 8-bit ADC digital compensation circuit for FLASH memory and computing, as Figure 1 shown, mainly including an error compensation selection switch, a gain error compensation module, an offset error compensation module, and a segmented error compensation module; the error compensation selection switch is used to select the correction strategy to be enabled for the ADC; the segmented error compensation module is used to correct the segmented linear error of the ADC and supports single-bit correction; the gain error compensation module is used to correct the linear gain error of the ADC; the offset error compensation module is used to correct the offset error of the ADC. Embodiment

[0017] First, the error curve of the ADC is fitted according to the software. When the ADC error is a linear error, the error compensation selection switch is configured as 2'b011, indicating that the gain compensation and offset compensation are enabled; Two registers for configuring gain compensation, including a register with a bit width of 16 bits and a register with a bit width of 8 bits. The first register with a bit width of 16 bits is multiplied by the ADC input value in a multiplicative form for correction, and the second register with a bit width of 8 bits shifts the ADC input value to the right in a displacement form for correction, where a maximum amplification of 65535 times and a reduction of 2 255 times are supported. Fill in the corresponding values A and B according to the coefficients fitted by the software.

[0018] Then configure the register for offset compensation, including a signed register with a bit width of 8 bits, which supports a maximum offset compensation of plus or minus 128. Fill in the corresponding value C according to the coefficients fitted by the software.

[0019] At this time, the value input to the ADC is X. After correction, a new value is obtained. The Y value is the input value of the ADC after correction, and the process is as Figure 2 shown. Embodiment

[0020] First, fit the error curve of the ADC according to the software. When the ADC error belongs to piecewise linear error, configure the error compensation selection switch to 2'b111, indicating that the gain compensation, offset compensation, and piecewise compensation functions are enabled; Two registers for configuring gain compensation, including a register with a bit width of 16 bits and a register with a bit width of 8 bits. The first register with a bit width of 16 bits is multiplied by the ADC input value in a multiplicative form for correction, and the second register with a bit width of 8 bits shifts the ADC input value to the right in a displacement form for correction, where a maximum amplification of 65535 times and a reduction of 2 255 times are supported. Fill in the corresponding values A and B according to the coefficients fitted by the software.

[0021] Then configure the register for offset compensation, including a signed register with a bit width of 8 bits, which supports a maximum offset compensation of plus or minus 128. Fill in the corresponding value C according to the coefficients fitted by the software.

[0022] Then configure the register for piecewise compensation, which consists of 8 registers with a bit width of 16 bits. For each bit input of the 8-bit ADC, each bit input of the ADC is multiplied by the value of each 16-bit register to correct the piecewise error. Set the values of these 8 registers to D0, D1, D2, D3, D4, D5, D6, and D7 respectively.

[0023] At this time, the value input to the ADC is X. Set each of its bits to X0, X1, X2, X3, X4, X5, X6, and X7. After correction, a new value is obtained. The Y value is the input value of the ADC after correction, and the process is asFigure 3 as shown

[0024] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art according to the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An 8-bit ADC digital compensation circuit applied to FLASH memory and computing, characterized in that Comprising: An error compensation selection switch for selecting to enable the correction strategy of the ADC; A gain error compensation module for correcting the linear gain error of the ADC; An offset error compensation module for correcting the offset error of the ADC; A segmented error compensation module for correcting the segmented linear error of the ADC, supporting single-bit correction; wherein, When the ADC error belongs to the linear error, configure the error compensation selection switch to 2'b011, indicating that the gain compensation and offset compensation are enabled; Configure two registers for gain compensation. The register with a bit width of 16 bits is multiplied by the ADC input value in a multiplicative form for correction, and the register with a bit width of 8 bits shifts the ADC input value to the right in a shift form for correction. Fill in the corresponding values A and B according to the coefficients fitted by the software; Configure the register for offset compensation, and fill in the corresponding value C according to the coefficients fitted by the software; At this time, the value input to the ADC is X, and after correction, a new value is obtained , and the value of Y is the input value of the ADC after correction; When the ADC error belongs to the segmented linear error, configure the error compensation selection switch to 2'b111, indicating that the gain compensation, offset compensation, and segmented compensation functions are enabled; Configure two registers for gain compensation. The register with a bit width of 16 bits is multiplied by the ADC input value in a multiplicative form for correction, and the register with a bit width of 8 bits shifts the ADC input value to the right in a shift form for correction. Fill in the corresponding values A and B according to the coefficients fitted by the software; Configure the register for offset compensation, and fill in the corresponding value C according to the coefficients fitted by the software; Configure the register for segmented compensation. Multiply each bit of the ADC input by the value of each 16-bit register to correct the segmented error; set the values of these 8 registers to D0, D1, D2, D3, D4, D5, D6, and D7 respectively; At this time, the value input to the ADC is X. Let each bit of it be X0, X1, X2, X3, X4, X5, X6, X7. After correction, a new value is obtained , and the Y value is the input value of the ADC after correction.

2. The 8-bit ADC digital compensation circuit applied to FLASH memory computing as described in claim 1, wherein The error compensation selection switch includes a register with a 3-bit width. When the register value is 0, the ADC compensation function is not started; when the lowest bit is 1, the gain error compensation module is started; when the middle bit is 1, the offset error compensation module is started; when the highest bit is 1, the segmented error compensation module is started; the error compensation selection switch starts a single type of compensation or, according to different situations, simultaneously enables multiple compensation functions.

3. The 8-bit ADC digital compensation circuit applied to FLASH memory and computing as described in claim 2, characterized in that, The gain error compensation module includes a register with a bit width of 16 bits and a register with a bit width of 8 bits, supporting a maximum amplification of 65,535 times and a correction of 255 downscaling by a factor of 2.

4. The 8-bit ADC digital compensation circuit applied to FLASH memory and computing as claimed in claim 3, wherein The offset error compensation module includes a signed register with a bit width of 8 bits, supporting a maximum offset compensation of plus or minus 128.

5. The 8-bit ADC digital compensation circuit applied to FLASH memory and computing as described in claim 4, wherein The segmented error compensation module is composed of 8 16-bit registers, corresponding to each bit of the 8-bit ADC input, and correcting each bit of the input accordingly.

6. The 8-bit ADC digital compensation circuit applied to FLASH memory computing according to claim 5, characterized in that, The segmented error compensation module is used in combination with the gain error compensation module. The correction of the ADC input by the segmented error compensation module will expand the ADC input value, and then use the reduction function of the gain error compensation module to reduce the ADC value to the specified number of digits.

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