Clock simulation method, device, equipment and medium

Abstract

The invention discloses a clock simulation method and device, equipment and a medium, relates to the technical field of integrated circuits, is applied to a prototype verification platform, and comprises the following steps: analyzing an original design file corresponding to a register transfer level circuit to obtain file topology information of an instantiated clock module; determining a to-be-adjusted clock module selected by the user side from the instantiated clock modules, and acquiring clock configuration information input by the user side, so as to generate a clock constraint file according to the clock configuration information; replacing a to-be-adjusted clock module in the original design file with a target clock module corresponding to the clock configuration information based on the file topology information to obtain an updated design file; and inputting the clock constraint file and the updated design file into a preset prototype development tool, and outputting a time sequence report after finishing time sequence analysis by utilizing the prototype development tool. Clock simulation under different scenes can be realized in an FPGA prototype verification platform, and the robustness of cross-clock domain transmission is verified.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a clock simulation method, device, equipment and medium. Background Art

[0002] With the continuous development and iteration of integrated circuit technology, the ability of a chip to process data and tasks is constantly enhanced, its functions and structures become more and more complex, and the chip power consumption will also increase sharply. Under this background, using traditional front-end verification methods for verification requires consuming a large amount of computing resources and designs, and it is very difficult to cover all usage scenarios, and it is impossible to fully guarantee the effectiveness of ASIC (Application Specific Integrated Circuit) design and meet the requirements of collaborative development with corresponding driver software.

[0003] To solve the above problems, an FPGA (Field Programmable Gate Array) prototype verification platform has emerged as the times require. The FPGA prototype verification platform helps designers verify the functions and performance of a chip by simulating the hardware environment of the ASIC design on the FPGA, and provides a real physical platform for software developers. The prototype verification platform can be used as a real physical platform to simulate more real usage scenarios by verifying the effectiveness and robustness of cross-clock domain processing under a large amount of data interaction through stress testing. However, the frequency selection module in the original clock often drives many sub-modules with gated clocks. If timing analysis is performed on all these modules at multiple frequencies, it will be extremely difficult to achieve timing convergence. Therefore, to facilitate timing convergence, the current FPGA prototype verification platforms usually simplify the complex clock structures in the original design, resulting in the inability to verify the effectiveness of cross-clock domain transmission under different frequency combinations. In addition, in most scenarios, users only care about whether the cross-clock domain data transmission between asynchronous modules that require a large amount of data interaction is reliable, and do not need to pay too much attention to other modules.

[0004] In summary, how to implement clock simulation in different scenarios in the FPGA prototype verification platform and verify the robustness of cross-clock domain transmission is a problem to be solved currently. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a clock simulation method, device, equipment and medium, which can implement clock simulation in different scenarios in the FPGA prototype verification platform and verify the robustness of cross-clock domain transmission. The specific solutions are as follows:

[0006] In a first aspect, the present application discloses a clock simulation method applied to a prototype verification platform, including:

[0007] Parse the original design file corresponding to the register transfer level circuit to obtain the file topology information of the instantiated clock module; the file topology information includes file location and hierarchical structure information;

[0008] Determine the clock module to be adjusted selected by the user from the instantiated clock module, and obtain the clock configuration information input by the user to generate a clock constraint file according to the clock configuration information;

[0009] Based on the file topology information, replace the clock module to be adjusted in the original design file with the target clock module corresponding to the clock configuration information to obtain the updated design file;

[0010] Input the clock constraint file and the updated design file into a preset prototyping tool to output a timing report after completing timing analysis using the prototyping tool.

[0011] Optionally, outputting a timing report after completing timing analysis using the prototyping tool includes:

[0012] Use the prototyping tool to determine the physical locations of each logic unit on the chip based on the updated design file and perform placement and routing operations to obtain the placed and routed design file;

[0013] Load the placed and routed design file and the clock constraint file, and traverse each timing path in the circuit to calculate the propagation delay of the signal on each timing path;

[0014] Judge whether the timing converges based on each propagation delay, and generate and output a timing report based on the judgment result.

[0015] Optionally, after outputting a timing report after completing timing analysis using the prototyping tool, it further includes:

[0016] Judge whether the current meets the preset test timing requirements based on the timing report; among them, the preset test timing requirements are the requirements corresponding to the clock configuration information;

[0017] If the preset test timing requirements are not met, then jump back to the step of using the prototyping tool to determine the physical locations of each logic unit on the chip based on the updated design file and perform placement and routing operations, or re-obtain the new clock configuration information input by the user to jump to the step of generating a clock constraint file according to the clock configuration information until the preset test timing requirements are met.

[0018] Optionally, after determining that the current meets the preset test timing requirements, it further includes:

[0019] Obtain the target instruction sent by the target host through the preset serial port to control the target clock module based on the target instruction; wherein, the target instruction includes the header information and tail information for identifying the instruction, the command information for determining whether to enable the target clock module, and the parameter information for controlling the counter in the target clock module.

[0020] Optionally, generate a clock constraint file according to the clock configuration information, including:

[0021] Read the configuration parameters in the clock configuration information and determine the preset constraint file format; wherein, the configuration parameters include any one or several of the clock frequency, clock source, duty cycle, clock interval period, clock jitter, and clock skew.

[0022] Generate a clock constraint file based on the configuration parameters and the constraint file format.

[0023] Optionally, obtain the clock configuration information input by the client, including:

[0024] Obtain the clock configuration information input by the client carrying clock signals with different duty cycles;

[0025] And / or, obtain the clock configuration information input by the client carrying clock signals with jitter;

[0026] And / or, obtain the clock configuration information input by the client carrying clock signals with variable clock interval periods.

[0027] Optionally, replace the clock module to be adjusted in the original design file with the target clock module corresponding to the clock configuration information based on the file topology information to obtain the updated design file, including:

[0028] Locate the clock module to be adjusted from the original design file based on the file topology information;

[0029] Replace the original process library equivalent behavior model in the clock module to be adjusted with the target clock module corresponding to the clock configuration information; wherein, the target clock module has a target process library equivalent behavior model, a user-expected clock generation module, and a clock switching and enabling module built in; the process library equivalent behavior model is an abstract description of the behavior of various standard cells in the process library, and the standard cells include logic gate cells and flip-flop cells; the target process library equivalent behavior model is functionally equivalent to the original process library equivalent behavior model; the user-expected clock generation module is used to generate the corresponding clock signal according to the clock configuration information input by the client, and the clock switching and enabling module is used to prevent glitches during clock switching and control the on / off of the clock.

[0030] Allocate address information to the target clock module and generate a control module at the top level of the hierarchy of the original design file, so that the control module can control the target clock module through hierarchical calls and based on the address information;

[0031] Obtain the updated design file including the target clock module and the control module.

[0032] In a second aspect, the present application discloses a clock simulation device applied to a prototype verification platform, including:

[0033] A parsing module for parsing the original design file corresponding to the register transfer level circuit to obtain the file topology information of the instantiated clock module; the file topology information includes file location and hierarchical structure information;

[0034] A file generation module for determining the clock module to be adjusted selected by the user from the instantiated clock module and obtaining the clock configuration information input by the user to generate a clock constraint file according to the clock configuration information;

[0035] A replacement module for replacing the clock module to be adjusted in the original design file with a target clock module corresponding to the clock configuration information based on the file topology information to obtain an updated design file;

[0036] A report acquisition module for inputting the clock constraint file and the updated design file into a preset prototype development tool to output a timing report after completing timing analysis by the prototype development tool.

[0037] In a third aspect, the present application discloses an electronic device, including:

[0038] A memory for storing a computer program;

[0039] A processor for executing the computer program to implement the steps of the clock simulation method disclosed above.

[0040] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the clock simulation method disclosed above are implemented.

[0041] It can be seen that in this application, the original design file corresponding to the register transfer level circuit is parsed through a prototype verification platform to obtain the file topology information of the instantiated clock module; the file topology information includes file location and hierarchical structure information; the clock module to be adjusted selected by the user from the instantiated clock module is determined, and the clock configuration information input by the user is obtained, so as to generate a clock constraint file according to the clock configuration information; based on the file topology information, the clock module to be adjusted in the original design file is replaced with a target clock module corresponding to the clock configuration information to obtain an updated design file; the clock constraint file and the updated design file are input into a preset prototype development tool to output a timing report after completing timing analysis using the prototype development tool.

[0042] Beneficial effects: In this application, first, the original design file corresponding to the register transfer level circuit is parsed to obtain the file topology information of the instantiated clock module, which may specifically include file location and hierarchical structure information, so as to accurately locate and operate the clock module in the design subsequently. This application can also determine the clock module to be adjusted selected by the user from the instantiated clock module and obtain the clock configuration information input by the user, that is, this application allows the user to customize the clock configuration, and subsequently, only the clock module selected and configured by the user can be tested to meet the requirements of different test scenarios. In addition, this application will also generate a clock constraint file according to the clock configuration information. By generating the clock constraint file, it is ensured that the design meets the timing requirements in hardware implementation, so as to verify the reliability of cross-clock domain transmission through timing analysis. Further, based on the file topology information, the clock module to be adjusted in the original design file is replaced with a target clock module corresponding to the clock configuration information to obtain an updated design file. By replacing the clock module, it is possible to simulate the clock situation under some abnormal conditions. Finally, the clock constraint file and the updated design file are input into a preset prototype development tool to output a timing report after completing timing analysis using the prototype development tool. In this way, this application can modify only the clock configuration of the clock module that needs to be tested according to the user's needs, thereby reducing the difficulty of timing convergence, being able to be used to verify the robustness and performance bottleneck of the code, and in addition, various unstable abnormal clocks can also be generated to meet the test requirements under some special scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0044] Figure 1 It is a flowchart of a clock simulation method disclosed in this application;

[0045] Figure 2 A hierarchical structure diagram implemented in hardware disclosed in this application;

[0046] Figure 3 A schematic diagram of clock module replacement disclosed in this application;

[0047] Figure 4 A flowchart of a specific clock simulation method disclosed in this application;

[0048] Figure 5 An interaction schematic diagram between a host and an FPGA disclosed in this application;

[0049] Figure 6 A schematic diagram of the format of an instruction disclosed in this application;

[0050] Figure 7 A specific example diagram of a target instruction disclosed in this application;

[0051] Figure 8 A schematic diagram of the structure of a clock simulation device disclosed in this application;

[0052] Figure 9 A structure diagram of an electronic device disclosed in this application. Detailed implementation manners

[0053] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0054] Currently, the prototype verification platform can serve as a real physical platform to verify the effectiveness and robustness of cross-clock domain processing under a large amount of data interaction through stress testing, so as to simulate a more realistic usage scenario. However, the frequency selection module in the original clock often drives many sub-modules with gated clocks. If timing analysis is performed on all these modules at multiple frequencies, it will be extremely difficult to achieve timing convergence. Therefore, to facilitate timing convergence, the current FPGA prototype verification platform usually simplifies the complex clock structure in the original design, resulting in the inability to verify the effectiveness of cross-clock domain transmission under different frequency combinations. In addition, in most scenarios, users only care about whether the cross-clock domain data transmission between asynchronous modules that require a large amount of data interaction is reliable, and do not need to pay excessive attention to other modules. For this reason, the embodiments of the present application disclose a clock simulation method, device, equipment, and medium, which can implement clock simulation in different scenarios in the FPGA prototype verification platform and verify the robustness of cross-clock domain transmission.

[0055] See Figure 1 and Figure 2 As shown, the embodiments of the present application disclose a clock simulation method, which is applied to a prototype verification platform. The method includes:

[0056] Step S11: Parse the original design file corresponding to the register transfer level circuit to obtain the file topology information of the instantiated clock module; the file topology information includes the file location and the hierarchical structure information.

[0057] In this embodiment, first, the original design file corresponding to the register transfer level (RTL) circuit is parsed to obtain the file topology information of the instantiated clock module, which may specifically include the file location and the hierarchical structure information, so as to accurately locate and operate the clock module in the design subsequently.

[0058] It should be noted that this step is specifically executed by the hierarchical structure parsing module. It can be understood that in the RTL stage of ASIC design, the behavioral models related to clocks are generally processed by dedicated process libraries provided by manufacturers. Therefore, this module mainly parses the instantiated structure hierarchy of these clock process libraries according to the list of the original design file in the top-down order, obtains the file location, hierarchical structure information, and related call file information of the instantiated clock module, and records them in the local dataset; the file location is convenient for finding the code, and the hierarchical structure helps to understand the module architecture association, providing a basis for subsequent operations.

[0059] Among them, the original design files may specifically include RTL code files, code files related to clock modules, clock constraint files, process library files, etc. The instantiated clock module refers to the process of calling and using a designed clock module as a sub-module in a larger design. By instantiating the clock module, the design of the same clock module can be reused in multiple different design projects, avoiding the need to redesign the clock circuit each time, improving the design efficiency, reducing the design cycle and cost. It also makes the design of the entire digital system more hierarchical and modular. By encapsulating the functions of clock generation and processing in an independent module, the structure of the main design becomes clearer, easier to understand and maintain. When other designers view the main design, they only need to focus on the input and output interfaces of the clock module, without having to delve into its internal complex clock generation and processing logic.

[0060] Step S12: Determine the clock module to be adjusted selected by the user terminal from the instantiated clock modules, and obtain the clock configuration information input by the user terminal to generate a clock constraint file according to the clock configuration information.

[0061] In this embodiment, this step is specifically executed by the clock selection and processing module. Specifically, the user can select the module whose clock needs to be adjusted according to the test requirements. Therefore, this module needs to determine the clock module to be adjusted selected by the user terminal from the instantiated clock modules, and obtain the clock configuration information input by the user terminal. That is, this application allows the user to customize the clock configuration, and subsequently, only the clock module selected and configured by the user can be tested to meet the requirements of different test scenarios.

[0062] After the user configures the clock information to be generated, the design implemented by the prototype verification platform may not necessarily meet such timing requirements. Therefore, it is also necessary to analyze the timing. At this time, this module will read in the clock configuration information and generate the required clock constraint analysis files under different configurations. That is, this application will also generate a clock constraint file according to the clock configuration information. By generating the clock constraint file, it is ensured that the design meets the timing requirements in the hardware implementation, so as to verify the reliability of cross-clock domain transmission through timing analysis.

[0063] In the specific implementation, obtaining the clock configuration information input by the client includes: obtaining the clock configuration information input by the client that carries clock signals with different duty cycles; and / or, obtaining the clock configuration information input by the client that carries clock signals with jitter; and / or, obtaining the clock configuration information input by the client that carries clock signals with variable clock interval periods. That is, the user can configure the abnormal and unstable clock information to be generated according to the test requirements, such as clock signals with different duty cycles, clock signals with jitter, and clock signals with variable clock interval periods. The abnormal clock here is relative to the characteristics of the clock that can be generated under normal conditions on the prototype platform.

[0064] Among them, the duty cycle refers to the ratio of the duration of the high level to the entire clock cycle within one clock cycle. It is usually expressed as a percentage. For example, if a clock cycle is 10 ns and the duration of the high level is 3 ns, the duty cycle is 30%. Clocks with different duty cycles are generated by changing the ratio of the duration of the high level to the low level to generate clock signals with specific duty cycles.

[0065] Clock jitter refers to the random change in the period of the clock signal, resulting in the instability of the clock edge. A clock with jitter is a clock signal artificially introduced with this characteristic of period instability. Jitter is usually measured in time units (such as picoseconds, nanoseconds), reflecting the degree to which the clock period deviates from the ideal value. In the specific implementation, the following methods can be adopted to generate a clock signal with jitter: 1. Random noise can be generated through a Gaussian noise model, superimposed on a stable clock signal, and the amplitude and frequency of the jitter can be controlled by adjusting the mean and variance of the noise; 2. A dedicated noise generator can be used to generate white noise, and then the generated white noise signal is passed through a low-pass filter to filter out high-frequency noise components to obtain a noise signal with an appropriate bandwidth. Subsequently, the noise signal is superimposed on the stable clock signal through an adder. Due to the randomness of the noise signal, the superimposed clock signal will generate jitter; 3. Digital signal processing algorithms can also be used to generate a clock signal with jitter. First, an ideal clock signal sequence is generated, such as a series of equally spaced rising edges or falling edges; then, the period of the clock signal is randomly adjusted through an algorithm. Specifically, a random number sequence can be generated using a pseudo-random number generator, and the values of this sequence are used to adjust the period of the clock signal. For example, according to the size of the random number, a certain time interval is added or subtracted to each clock cycle. This time interval can be determined by the clock resolution of the hardware. Then, the adjusted clock signal sequence is converted into an analog signal through a digital-to-analog converter (DAC), and then output after buffering and amplification to obtain a clock signal with jitter.

[0066] The variable clock interval period means that the time interval between two adjacent cycles of the clock signal is not a fixed value, but can be changed according to the setting. This kind of clock signal breaks the traditional mode of constant clock period and provides a more flexible way of time control.

[0067] In the specific implementation manner, a clock constraint file is generated according to the clock configuration information, including: reading the configuration parameters in the clock configuration information and determining the preset constraint file format; wherein, the configuration parameters include any one or several of the clock frequency, clock source, duty cycle, clock interval period, clock jitter, and clock offset; generating a clock constraint file based on the configuration parameters and the constraint file format.

[0068] That is to say, in this embodiment, it is necessary to clarify the configuration parameters in the clock configuration information, including but not limited to the clock frequency, clock source, duty cycle, clock interval period, clock jitter, and clock offset, etc. Further, it is also necessary to determine the preset constraint file format, such as whether it is a constraint file in the XDC (Xilinx Design Constraints) format or an SDC (Synopsys Design Constraints) format. Finally, a corresponding clock constraint file is generated based on these configuration parameters and the constraint file format.

[0069] Step S13: Replace the clock module to be adjusted in the original design file with the target clock module corresponding to the clock configuration information based on the file topology information to obtain the updated design file.

[0070] In this embodiment, this step is specifically executed by the design clock conversion module, which specifically needs to replace the clock module to be adjusted in the original design file with the target clock module corresponding to the clock configuration information to obtain the updated design file. By replacing the clock module, the clock situation in some abnormal situations can be simulated.

[0071] In a specific embodiment, the original clock module to be adjusted in the original design file is replaced with a target clock module corresponding to the clock configuration information based on the file topology information to obtain an updated design file, including: locating the clock module to be adjusted from the original design file based on the file topology information; replacing the original process library equivalent behavior model in the clock module to be adjusted with a target clock module corresponding to the clock configuration information; wherein, the target clock module incorporates a target process library equivalent behavior model, a user-expected clock generation module, and a clock switching and enabling module; the process library equivalent behavior model is an abstract description of the behaviors of various standard cells in the process library in the circuit, and the standard cells include logic gate cells and flip-flop cells; the target process library equivalent behavior model is functionally equivalent to the original process library equivalent behavior model; the user-expected clock generation module is used to generate a corresponding clock signal according to the clock configuration information input by the user side, and the clock switching and enabling module is used to prevent glitches from occurring during clock switching and control the on / off of the clock; allocating address information to the target clock module and generating a control module at the top layer of the hierarchical structure of the original design file, so that the control module controls the target clock module through hierarchical calls and based on the address information; obtaining the updated design file including the target clock module and the control module.

[0072] That is, as Figure 3 shown, the clock configuration information is read in by the design clock conversion module. First, the clock module to be adjusted is located from the original design file based on the file topology information, and the instantiated original process library equivalent behavior model in the original design file under the hierarchical path is replaced with a target clock module corresponding to the clock configuration information. The target clock module includes the following sub-modules: Process library equivalent behavior model: ensuring that the replaced module is functionally equivalent to the original module; User-expected clock generation module: generating an expected clock signal according to the clock information input by the user; Clock switching and enabling module: preventing glitches from occurring during clock switching and controlling the on / off of the clock. Among them, the process library equivalent behavior model is an abstract description of the behaviors of various standard cells in the process library in the circuit, and the standard cells include logic gate cells, flip-flop cells, and so on. Further, the present application also needs to allocate a unique address information to the target clock module and generate a control module at the top layer of the hierarchical structure of the original design file, so that the control module independently controls each target clock module through hierarchical calls and based on the address information. After the above steps are completed, the updated design file including the target clock module and the control module is obtained. Through the above process, the clock requirements expected by the user can be accurately implemented in the hardware design, while avoiding the glitch problem during clock switching, and improving the stability and reliability of the design.

[0073] Step S14: Input the clock constraint file and the updated design file into a preset prototype development tool to output a timing report after completing timing analysis by using the prototype development tool.

[0074] In this embodiment, the clock constraint file and the updated design file are input into a preset prototyping tool for placement and routing implementation, and after the timing analysis is completed by the prototyping tool, a timing report is output.

[0075] Furthermore, the present application also provides a clock conversion analysis module, which mainly analyzes the timing report output by the prototyping tool to determine whether the current hardware layout can reasonably generate the abnormal clock expected by the user, and outputs the analysis result to the user for subsequent configuration use.

[0076] It can be seen that the present application first parses the original design file corresponding to the register transfer level circuit to obtain the file topology information of the instantiated clock module, which may specifically include the file location and the hierarchical structure information, so as to accurately locate and operate the clock module in the design subsequently. The present application can also determine the clock module to be adjusted selected by the user from the instantiated clock module, and obtain the clock configuration information input by the user, that is, the present application allows the user to customize the clock configuration, and subsequently only the clock module selected and configured by the user can be tested to meet the requirements of different test scenarios. In addition, the present application also generates a clock constraint file according to the clock configuration information. By generating the clock constraint file, it is ensured that the design meets the timing requirements in the hardware implementation, so as to verify the reliability of cross-clock domain transmission through timing analysis. Furthermore, based on the file topology information, the present application replaces the clock module to be adjusted in the original design file with a target clock module corresponding to the clock configuration information to obtain an updated design file. By replacing the clock module, the clock situation under some abnormal conditions can be simulated. Finally, the clock constraint file and the updated design file are input into a preset prototyping tool to output a timing report after the timing analysis is completed by the prototyping tool. In this way, the present application can only modify the clock configuration of the clock module that needs to be tested according to the user's needs, thereby reducing the difficulty of timing convergence, and can be used to verify the robustness and performance bottleneck of the code. In addition, various unstable abnormal clocks can also be generated to meet the test requirements under some special scenarios.

[0077] See Figure 4 As shown in the figure, the embodiment of the present application discloses a specific clock simulation method. Compared with the previous embodiment, this embodiment further explains and optimizes the technical solution. Specifically, it includes:

[0078] Step S21: Parse the original design file corresponding to the register transfer level circuit to obtain the file topology information of the instantiated clock module; the file topology information includes the file location and the hierarchical structure information.

[0079] Step S22: Determine the clock module to be adjusted selected by the client from the instantiated clock modules, and obtain the clock configuration information input by the client, so as to generate a clock constraint file according to the clock configuration information.

[0080] Step S23: Based on the file topology information, replace the clock module to be adjusted in the original design file with the target clock module corresponding to the clock configuration information, so as to obtain the updated design file.

[0081] Step S24: Input the clock constraint file and the updated design file into a preset prototyping tool, so as to use the prototyping tool to determine the physical locations of each logic unit on the chip based on the updated design file, and perform placement and routing operations to obtain the placed and routed design file.

[0082] In this embodiment, after receiving the updated design file and the timing constraint file, the prototyping tool will start the placement and routing operations. This process is a key step in transforming the abstract design description into the actual physical circuit layout. Placement mainly refers to that the prototyping tool will determine the physical locations of each logic unit (such as gates, registers, etc.) on the chip based on the updated design file. For example, the logic units that often perform data interaction can be placed as close as possible to reduce the signal transmission delay. After the placement is completed, the tool will establish electrical connections between each logic unit, that is, perform routing. The routing process needs to follow the requirements in the timing constraint file to ensure that the signals can be accurately transmitted within the specified time. At the same time, it is also necessary to avoid interference and conflicts between signals to ensure the stability and reliability of the circuit. After the placement and routing are completed, the placed and routed design file can be obtained.

[0083] Step S25: Load the placed and routed design file and the clock constraint file, and traverse each timing path in the circuit to calculate the propagation delay of the signal on each timing path.

[0084] In this embodiment, load the placed and routed design file and the timing constraint file, traverse all the timing paths in the circuit, calculate the propagation delay of the signal on each timing path, and further check whether the timing parameters such as the clock frequency, setup time, and hold time meet the requirements, so as to generate a timing analysis report, including the delay information of the timing paths and the timing violation conditions.

[0085] Step S26: Determine whether the timing converges based on each propagation delay, so as to generate and output a timing report based on the judgment result.

[0086] In this embodiment, determine whether the timing converges based on each propagation delay, so as to generate and output a timing report based on the judgment result.

[0087] Further, after completing the timing analysis using the prototyping tool and outputting the timing report, it further includes: determining whether the current situation meets the preset test timing requirements based on the timing report; wherein, the preset test timing requirements are the requirements corresponding to the clock configuration information; if the preset test timing requirements are not met, then it jumps back to the step of using the prototyping tool to determine the physical positions of each logic unit on the chip based on the updated design file and performing the placement and routing operations, or re-obtaining the new clock configuration information input by the user terminal to jump to the step of generating the clock constraint file according to the clock configuration information until the preset test timing requirements are met.

[0088] It can be understood that according to the timing report, there will be two situations: 1. The current situation meets the preset test timing requirements: If the timing analysis result shows that various timing indicators such as the propagation delay of the signal meet the timing requirements of the design, it means that the current design and placement and routing strategy are feasible, and the subsequent test and verification work can be continued; 2. The current situation does not meet the preset test timing requirements: If the timing analysis result does not meet the requirements, corresponding measures need to be taken for adjustment. There are two specific adjustment methods as follows: One is to modify the placement and routing strategy: Return to modify the placement and routing strategy of the prototyping tool, such as adjusting the positions of the logic units, optimizing the routing path, etc., and then re-perform the placement and routing and timing analysis. By continuously trying different placement and routing schemes, an optimal scheme that can meet the timing requirements is found. The other is to re-obtain the new clock configuration information input by the user terminal, that is, because the initially set clock parameters are too strict, it is difficult to meet the timing requirements during the actual placement and routing process. Therefore, the requirements for timing can be reduced by adjusting parameters such as the clock period and duty cycle, and then the subsequent steps are performed again until the test timing requirements are met.

[0089] In addition, after determining that the current situation meets the preset test timing requirements, it further includes: obtaining the target instruction sent by the target host through the preset serial port to control the target clock module based on the target instruction; wherein, the target instruction includes the header information and tail information for identifying the instruction, the command information for determining whether to enable the target clock module, and the parameter information for controlling the counter in the target clock module.

[0090] It can be understood that as Figure 5 shown, when the hardware layout is completed and meets the preset test timing requirements, the user can control the target clock module through the serial port on the host side using instructions. The specific target instructions include the header information and tail information for identifying the instruction, the command information for determining whether to enable the target clock module, and the parameter information for controlling the counter in the target clock module. The format of the instruction is as Figure 6As shown, START and END therein are the packet header and packet tail for identifying instructions. CMD can indicate whether to enable the target clock module. When enabled, it generates a clock according to the user's definition, or can use the clock in the original design or turn off the clock. There are n counters in the target clock module. NUM indicates only the first NUM are selected. The three parameters HIGHm, LOWm, and CNTm (0 < m <= n) correspond to the mth counter. The clock of the module is pulled high when the mth counter counts to HIGHm and pulled low before LOWm, and it counts a total of CNTm. An example is as Figure 7 shown.

[0091] In addition, it should be noted that this embodiment mainly writes the target clock module in the Python language. It can automatically insert the target clock module into the specified sub-module according to user needs, generate a timing file, generate a control module at the top level of the design, and drive the abnormal clock modules in each sub-module through hierarchical calls to meet the requirements of special test scenarios or verify the robustness of the cross-clock domain transfer code.

[0092] Among them, for the more specific processing procedures of the above steps S21, S22, and S23, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated here.

[0093] It can be seen that considering the current prototype verification platform, due to resource limitations and for the convenience of timing convergence, the complex and complete clock structure in the original design is usually streamlined, and frequency switching cannot be performed, resulting in the inability to verify the effectiveness of cross-clock domain transfer under different frequency combinations, the stability under long-term stress tests, and the performance bottlenecks of the system under different frequency combinations. At the same time, in high-speed IP such as PCIe (Peripheral Component Interconnect Express, a high-speed peripheral component interconnect standard), it has the function of detecting the loss of the input clock and unstable clock cycles and reporting them. At this time, an unstable clock cycle also requires a method to be simulated. Therefore, this application discloses a clock simulation method more suitable for the prototype verification platform. It can modify only the clock frequency of the module to be tested according to user needs, reduce the difficulty of timing convergence, be used to verify the robustness and performance bottlenecks of the code, and can also generate various unstable abnormal clocks to meet the test requirements in some special scenarios.

[0094] See Figure 8 As shown, an embodiment of this application discloses a clock simulation device applied to a prototype verification platform. The device includes:

[0095] A parsing module 11 for parsing an original design file corresponding to a register transfer level circuit to obtain file topology information of the instantiated clock module; the file topology information includes file location and hierarchical structure information;

[0096] A file generation module 12 for determining a clock module to be adjusted selected by the user from the instantiated clock module and obtaining clock configuration information input by the user, so as to generate a clock constraint file according to the clock configuration information;

[0097] A replacement module 13 for replacing the clock module to be adjusted in the original design file with a target clock module corresponding to the clock configuration information based on the file topology information to obtain an updated design file;

[0098] A report acquisition module 14 for inputting the clock constraint file and the updated design file into a preset prototyping tool, and outputting a timing report after completing timing analysis by using the prototyping tool.

[0099] It can be seen that this application first parses the original design file corresponding to the register transfer level circuit to obtain the file topology information of the instantiated clock module, which can specifically include file location and hierarchical structure information, so as to accurately locate and operate the clock module in the design subsequently. This application can also determine the clock module to be adjusted selected by the user from the instantiated clock module and obtain the clock configuration information input by the user, that is, this application allows the user to customize the clock configuration, and subsequently only the clock module selected and configured by the user can be tested to meet the requirements of different test scenarios. In addition, this application will also generate a clock constraint file according to the clock configuration information. By generating the clock constraint file, it is ensured that the design meets the timing requirements in hardware implementation, so as to verify the reliability of cross-clock domain transmission through timing analysis. Further, this application replaces the clock module to be adjusted in the original design file with a target clock module corresponding to the clock configuration information to obtain an updated design file. By replacing the clock module, it is possible to simulate the clock situation under some abnormal conditions. Finally, the clock constraint file and the updated design file are input into a preset prototyping tool, and a timing report is output after completing timing analysis by using the prototyping tool. In this way, this application can only modify the clock configuration of the clock module that needs to be tested according to the user's needs, thereby reducing the difficulty of timing convergence, being able to be used to verify the robustness and performance bottleneck of the code, and in addition, various unstable abnormal clocks can also be generated to meet the test requirements under some special scenarios.

[0100] Since the embodiments of the device part correspond to the above embodiments, the embodiments of the device part are described with reference to the embodiments of the above method part and will not be elaborated here.

[0101] Figure 9A structural schematic diagram of an electronic device provided by an embodiment of the present application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the clock simulation method executed by the electronic device disclosed in any of the foregoing embodiments.

[0102] In this embodiment, the power supply 23 is used to provide a working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and no specific limitation is imposed on it here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.

[0103] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, and the AI processor is used to process computational operations related to machine learning.

[0104] In addition, the memory 22, as a carrier for resource storage, may be a read-only memory, a random access memory, a disk, or an optical disc, etc. The resources stored thereon include an operating system 221, a computer program 222, and data 223, etc., and the storage method may be short-term storage or permanent storage.

[0105] Among them, the operating system 221 is used to manage and control each hardware device on the electronic device 20 and the computer program 222, so as to enable the processor 21 to perform operations and processing on the massive data 223 in the memory 22. It can be Windows, Unix, Linux, etc. In addition to the computer program that can be used to complete the clock simulation method executed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs that can be used to complete other specific tasks. The data 223 may include not only the data transmitted by the external device received by the electronic device, but also the data collected by its own input / output interface 25, etc.

[0106] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium. When the computer program stored in the storage medium is loaded and executed by a processor, the steps of the clock simulation method disclosed in any of the foregoing embodiments are implemented.

[0107] Furthermore, an embodiment of the present invention also discloses a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of the clock simulation method disclosed in any of the foregoing embodiments are implemented.

[0108] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description of the method part.

[0109] Those skilled in the art can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0110] The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be implemented directly in hardware, in software modules executed by a processor, or in a combination thereof. The software modules may be located in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0111] Finally, it should also be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0112] The above has introduced in detail a clock simulation method, apparatus, device and storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation on the present invention.

Claims

1. A clock simulation method, characterized in that: Applied to prototype verification platform, including: Parsing the original design file corresponding to the register transfer level circuit to obtain file topology information of the instantiated clock module; the file topology information includes file location and hierarchical structure information; Determine a clock module to be adjusted selected by the user terminal from the instantiated clock modules, and obtain clock configuration information input by the user terminal to generate a clock constraint file according to the clock configuration information; Based on the file topology information, the clock module to be adjusted in the original design file is replaced with a target clock module corresponding to the clock configuration information to obtain an updated design file; The clock constraint file and the updated design file are input into a preset prototype development tool, so as to output a timing report after completing the timing analysis using the prototype development tool.

2. The clock simulation method according to claim 1, characterized in that: The method of outputting a timing report after completing the timing analysis using the prototype development tool includes: Determine the physical location of each logic unit on the chip based on the updated design file using the prototype development tool, and perform layout and routing operations to obtain a layout and routing design file; Loading the design file after layout and routing and the clock constraint file, and traversing each timing path in the circuit to calculate the propagation delay of the signal on each timing path; Whether the timing is converged is determined based on each of the propagation delays, so as to generate and output a timing report based on the determination result.

3. The clock simulation method according to claim 2, characterized in that: After the timing analysis is completed by the prototype development tool and a timing report is output, the method further includes: Determine whether a preset test timing requirement is currently met based on the timing report; wherein the preset test timing requirement is a requirement corresponding to the clock configuration information; If the preset test timing requirement is not met, the process jumps back to the step of using the prototype development tool to determine the physical location of each logic unit on the chip based on the updated design file and performing layout and routing operations, or reacquires the new clock configuration information input by the user end to jump to the step of generating a clock constraint file based on the clock configuration information until the preset test timing requirement is met.

4. The clock simulation method according to claim 3, characterized in that: After determining that the preset test timing requirement is currently met, the method further includes: Obtain a target instruction sent by a target host through a preset serial port to control the target clock module based on the target instruction; wherein the target instruction includes header information and tail information for identifying the instruction, command information for determining whether to enable the target clock module, and parameter information for controlling a counter in the target clock module.

5. The clock simulation method according to claim 1, characterized in that: The step of generating a clock constraint file according to the clock configuration information comprises: Reading configuration parameters in the clock configuration information and determining a preset constraint file format; wherein the configuration parameters include any one or more parameters of clock frequency, clock source, duty cycle, clock interval period, clock jitter and clock offset; A clock constraint file is generated based on the configuration parameters and the constraint file format.

6. The clock simulation method according to claim 1, characterized in that: The acquiring the clock configuration information input by the user terminal includes: Acquire clock configuration information of clock signals with different duty cycles input by the user end; and / or, obtaining clock configuration information of a clock signal with jitter input by the user end; And / or, acquiring clock configuration information of a clock signal with a variable clock interval period input by the user end.

7. The clock simulation method according to any one of claims 1 to 6, characterized in that: The step of replacing the to-be-adjusted clock module in the original design file with a target clock module corresponding to the clock configuration information based on the file topology information to obtain an updated design file includes: Locating the clock module to be adjusted from the original design file based on the file topology information; The original process library equivalent behavior model in the clock module to be adjusted is replaced with a target clock module corresponding to the clock configuration information; wherein the target clock module has a target process library equivalent behavior model, a user expected clock generation module and a clock switching and enabling module built in; the process library equivalent behavior model is an abstract description of the behavior of various standard units in the process library in the circuit, and the standard unit includes a logic gate unit and a trigger unit; the target process library equivalent behavior model is functionally equivalent to the original process library equivalent behavior model; the user expected clock generation module is used to generate a corresponding clock signal according to the clock configuration information input by the user end, and the clock switching and enabling module is used to prevent glitches during clock switching and control the switching of the clock; Allocating address information to the target clock module, and generating a control module at the top level of the hierarchy of the original design file, so that the control module controls the target clock module through hierarchical calling and based on the address information; An updated design file including the target clock module and the control module is obtained.

8. A clock simulation device, characterized in that: Applied to prototype verification platform, including: A parsing module, used for parsing the original design file corresponding to the register transfer level circuit to obtain file topology information of the instantiated clock module; the file topology information includes file location and hierarchical structure information; A file generating module, used for determining a clock module to be adjusted selected by the user terminal from the instantiated clock modules, and obtaining clock configuration information input by the user terminal, so as to generate a clock constraint file according to the clock configuration information; A replacement module, used to replace the clock module to be adjusted in the original design file with a target clock module corresponding to the clock configuration information based on the file topology information, so as to obtain an updated design file; The report acquisition module is used to input the clock constraint file and the updated design file into a preset prototype development tool, so as to output a timing report after completing the timing analysis using the prototype development tool.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the clock simulation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the steps of the clock simulation method according to any one of claims 1 to 7 are implemented.

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