Semiconductor device

Abstract

The purpose of the present invention is to reduce chip size and reduce power consumption. The semiconductor device includes: a control wiring connected to a gate of the first transistor; a second transistor having a first terminal to which a first voltage for turning on the first transistor is input, and a second terminal to which a first voltage for turning on the first transistor is input, the second transistor being connected to a first gate of the control wiring; a third transistor that has a third terminal connected to the second terminal, a fourth terminal for controlling the voltage of the control wiring, and a second gate, and that is turned on by a first control signal input to the second gate when the plurality of first transistors are turned on; a fourth transistor having a fifth terminal and a sixth terminal, and a third gate, and turned on by a second control signal input to the third gate when the third transistor is turned on; and a capacitor that, by capacitive coupling, boosts a second voltage output from the fourth terminal to a third voltage higher than the second voltage in a state in which the first transistor and the second transistor are turned on, and supplies the third voltage to the control wiring.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device. Background Art

[0002] With the development of high stacking of NAND flash memories, there is a tendency for the proportion of high breakdown voltage transistors for data writing to increase in chip size. In particular, with the development of high stacking, the area of the core circuit including the word line switching transistor that drives the word line and the control line, and the circuit that controls the gate voltage of the word line switching transistor increases, making it difficult to reduce the chip size. Prior Art Documents Patent Documents

[0003] Patent Document 1: U.S. Patent Publication No. 2017 / 0084335 Summary of the Invention

[0004] Here, one embodiment of the present invention provides a semiconductor device capable of reducing the chip size.

[0005] In order to solve the above technical problems, according to one embodiment of the present invention, there is provided a semiconductor device including: a control wiring connected to the gate of a first transistor; a second transistor having a first terminal and a second terminal respectively serving as a source or a drain, and a first gate connected to the control wiring, the first terminal being input with a first voltage for turning on the first transistor; a third transistor having a third terminal and a fourth terminal respectively serving as a source or a drain, and a second gate, the third terminal being connected to the second terminal, the fourth terminal controlling the voltage of the control wiring, the third transistor being turned on by a first control signal input to the second gate when the first transistor is turned on; a fourth transistor having a fifth terminal and a sixth terminal respectively serving as a source or a drain, and a third gate, the fourth transistor being turned on by a second control signal input to the third gate when the third transistor is turned on, and being turned off by the second control signal input to the third gate when the third transistor is turned off; and a capacitor that boosts, by capacitive coupling, a second voltage output from the fourth terminal in a state where the first transistor and the second transistor are turned on to a third voltage higher than the second voltage and supplies the third voltage to the control wiring. Brief Description of the Drawings

[0006] Figure 1 is a block diagram showing an example of the configuration of a storage system including the semiconductor storage device according to the embodiment. Figure 2 It is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the semiconductor memory device according to the embodiment. Figure 3 It is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device according to the embodiment. Figure 4 It is a circuit diagram showing an example of the configuration of a row decoder module, a driver module, and a memory cell array of the semiconductor memory device according to the embodiment. Figure 5 It is a circuit diagram showing an example of the configuration of a block decoder included in the semiconductor memory device according to the embodiment. Figure 6 It is a circuit diagram of the main part of the block decoder according to the first embodiment. Figure 7 It is a cross-sectional view in the case where a capacitor is formed of a MOS capacitor. Figure 8 It is a diagram showing the voltage change of the second voltage and the transfer gate line. Figure 9 It is a diagram showing the on-current characteristics of the transfer transistor according to the first embodiment. Figure 10 It is a top view and a cross-sectional view showing the structure of a diode. Figure 11 It is a cross-sectional view in the case where a diode is formed of a MOS transistor. Figure 12 It is a circuit diagram of the block decoder according to the first modification of the first embodiment. Figure 13 It is a cross-sectional view of two capacitors included in the block decoder according to the first modification. Figure 14 It is a circuit diagram of the block decoder according to the second modification of the first embodiment. Figure 15 It is a cross-sectional view of the capacitor according to the second modification. Figure 16 It is a circuit diagram of the block decoder according to the second embodiment. Figure 17 It is a cross-sectional view of the capacitor included in the block decoder according to the second embodiment. Figure 18 It shows Figure 17 a diagram of the voltage level change of the voltage. Figure 19 It is a diagram showing the on-current characteristics of the transfer transistor according to the second embodiment. Figure 20It is a block diagram showing the configuration on the transmission path of the voltage supplied to each block decoder. Figure 21 It is a diagram showing the path from the input of the second multiplexer to the word line for one control signal line. Figure 20 to the word line. Figure 22 It is a diagram showing the wiring path from the voltage supply circuit to the row decoder module. Figure 23 It is a block diagram showing the connection relationship between the voltage supply circuit and the local charge pump. Figure 24 It is a circuit diagram showing an example of the internal configuration of the local charge pump. Figure 25 It is a voltage waveform diagram of the signals input to and output from the local charge pump. Figure 26 It is a voltage waveform diagram of the block decoder according to the third embodiment. Detailed Embodiment

[0007] Hereinafter, embodiments of the semiconductor device will be described with reference to the drawings. Hereinafter, the description will be centered on the main components of the semiconductor device, but in the semiconductor device, there may be components or functions that are not shown or described. The following description does not exclude components or functions that are not shown or described.

[0008] (Outline Configuration of Storage System) Figure 1 It is a block diagram showing the outline configuration of a storage system including the semiconductor device according to the embodiment. In addition, in this specification, an example in which the semiconductor device according to the embodiment is applied to a semiconductor memory device will be mainly described.

[0009] The storage system 3 includes a semiconductor memory device 1 and a memory controller 2.

[0010] The storage system 3 is, for example, a memory card such as an SD TM card, UFS (universal flash storage), or SSD (solid state drive). The storage system 3 is configured to be connected to an external host device (not shown).

[0011] The memory controller 2 is constituted by an integrated circuit such as a SoC (system-on-a-chip). The memory controller 2 controls the semiconductor memory device 1 based on requests from the host device. Specifically, for example, the memory controller 2 writes data requested to be written from the host device into the semiconductor memory device 1. In addition, the memory controller 2 reads data requested to be read from the host device from the semiconductor memory device 1 and sends it to the host device.

[0012] The semiconductor memory device 1 is, for example, a NAND type flash memory. The semiconductor memory device 1 stores data non-volatilely. The semiconductor memory device 1 is connected to the memory controller 2 via the NAND bus B.

[0013] The NAND bus B is, for example, a bus based on an SDR (single data rate) interface, a Toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0014] (Internal Configuration of Semiconductor Memory Device) Hereinafter, with reference to Figure 1 the block diagram shown, the internal configuration of the semiconductor memory device 1 according to the embodiment will be described. The semiconductor memory device 1 includes, for example, a memory cell array 10 and a peripheral circuit PERI. The peripheral circuit PERI includes a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0015] The memory cell array 10 includes a plurality of blocks BLKO to BLKn (n is an integer of 1 or more). A block BLK is a set of a plurality of memory cell transistors that can store data non-volatilely and is used, for example, as an erasure unit for data. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. For example, one memory cell transistor is associated with one bit line and one word line.

[0016] The command register 11 holds the command CMD received by the semiconductor memory device 1 from the memory controller 2. The command CMD includes, for example, commands for causing the sequencer 13 to perform read operations, write operations, and erase operations.

[0017] The address register 12 holds the address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a page address PA, a block address BA, and a column address CA. For example, the page address PA, the block address BA, and the column address CA are used for the selection of word lines, blocks BLK, and bit lines, respectively.

[0018] The sequencer 13 controls the operation of the entire semiconductor memory device 1. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc. based on the command CMD held in the command register 11, and executes read operations, write operations, erase operations, etc.

[0019] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. And, for example, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line according to the page address PA held in the address register 12.

[0020] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 according to the block address BA held in the address register 12. Then, for example, the row decoder module 15 transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0021] The sense amplifier module 16 transfers data DAT between the memory controller 2 and the memory cell array 10. The data DAT includes write data and read data. More specifically, in the write operation, the sense amplifier module 16 transfers the write data received from the memory controller 2 to the memory cell array 10. In addition, in the read operation, the sense amplifier module 16 determines the data stored in the memory cell transistor according to the voltage of the bit line. Then, the sense amplifier module 16 transfers the result of the determination as read data to the memory controller 2.

[0022] (Circuit configuration of the memory cell array) Figure 2 It is a circuit diagram showing an example of the circuit configuration of the memory cell array 10 included in the semiconductor memory device according to the embodiment. In Figure 2 it, one block BLK of the plurality of blocks BLK included in the memory cell array 10 is shown. In Figure 2 the example shown, the block BLK includes, for example, five string units SU0 to SU4.

[0023] Each string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer greater than or equal to 1). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2. Each of the memory cell transistors MT0 to MT7 includes a control gate and a charge storage layer, and non-volatilely stores data. The selection transistors ST1 and ST2 are respectively used for selecting the string unit SU during various operations. In the following description, the memory cell transistors MT0 to MT7 are also respectively referred to as the memory cell transistor MT.

[0024] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. One end of the selection transistor ST1 is connected to the associated bit line BL, and the other end of the selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. One end of the selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The other end of the selection transistor ST2 is connected to the source line SL.

[0025] In the same block BLK, the control gates of the memory cell transistors MT0 to MT7 are respectively connected to the word lines WL0 to WL7. The gates of the selection transistors ST1 in the string units SU0 to SU4 are respectively connected to the selection gate lines SGD0 to SGD4. In contrast, the gates of the plurality of selection transistors ST2 are commonly connected to the selection gate line SGS. However, not limited thereto, the gates of the plurality of selection transistors ST2 may also be respectively connected to different multiple selection gate lines for each string unit SU. In the following description, when not distinguishing the word lines WL0 to WL7, they are simply referred to as the word line WL. In addition, when not distinguishing the selection gate lines SGD0 to SGD4, they are simply referred to as the selection gate line SGD.

[0026] Each of the bit lines BL0 to BLm is commonly connected to one NAND string NS included in each string unit SU in the plurality of blocks BLK. The word lines WL0 to WL7 are respectively provided for each block BLK. The source line SL is shared, for example, between the plurality of blocks BLK.

[0027] In one string unit SU, a set of a plurality of memory cell transistors MT connected to the common word line WL is, for example, referred to as a cell unit CU. For example, the storage capacity of the cell unit CU including the memory cell transistors MT each storing 1-bit data is defined as "1 page of data". Depending on the number of bits of data stored in the memory cell transistor MT, the cell unit CU may have a storage capacity of 2 pages of data or more.

[0028] In addition, the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 according to the embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT, and selection transistors ST1 and ST2 included in each NAND string NS can be designed to be any number respectively.

[0029] (Cross-sectional structure of semiconductor memory device) Next, Figure 3 the cross-sectional structure of the semiconductor memory device 1 according to the embodiment will be described. Figure 3 FIG. is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device according to the embodiment. In Figure 3 it, a cross-sectional structure including 2 out of 5 string units SU included in 1 block BLK is shown.

[0030] In addition, in the drawings referred to below, the X direction corresponds to the extending direction of the word line WL, the Y direction corresponds to the extending direction of the bit line BL, and the Z direction corresponds to the direction perpendicular to the surface of the semiconductor substrate forming the semiconductor memory device 1.

[0031] The memory cell array 10 includes conductor layers 21, 22, 24, and 25 provided above the semiconductor substrate 20, a plurality of conductor layers 23, and a plurality of memory posts MP (only 2 are shown in Figure 3 ). In addition, in the following description, the direction in which the memory cell array 10 is provided with respect to the semiconductor substrate 20 is taken as the upper direction. In addition, the opposite direction is taken as the lower direction.

[0032] A wiring layer region WR is disposed on the semiconductor substrate 20. The wiring layer region WR has a plurality of wiring layers D0, D1, D2 laminated via contacts C0, C1, C2. The periphery of the plurality of wiring layers D0, D1, D2 is covered with an insulator layer. In Figure 3 an example in which the wiring layer region has 3 wiring layers D0, D1, D2 is shown, but the number of wiring layers is arbitrary. At least a part of peripheral circuits such as a row decoder is disposed in the wiring layers D0, D1, D2.

[0033] Above the wiring layer region WR, a conductor layer 21 is stacked. The conductor layer 21 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 21 serves as a source line SL. The conductor layer 21 is made of a conductive material, and for example, an N-type semiconductor doped with impurities, or a metal material such as titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), a stacked film of tantalum nitride (TaN) and tantalum (Ta), a stacked film of titanium (Ti), titanium nitride (TiN), and tungsten (W), or a stacked film of titanium nitride (TiN) and tungsten silicide (WSi) is used. Additionally, the conductor layer 21 may also be, for example, a stacked structure of a semiconductor and a metal material such as a stacked film of titanium nitride (TiN), tungsten silicide (WSi), and polysilicon.

[0034] An insulator layer 31 is provided on the conductor layer 21. A conductor layer 22 is stacked on the insulator layer 31. The conductor layer 22 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 22 serves as a selection gate line SGS. The conductor layer 22 contains, for example, tungsten (W).

[0035] An insulator layer 32 is provided on the conductor layer 22. Eight conductor layers 23 and eight insulator layers 33 are alternately stacked layer by layer on the insulator layer 32. The conductor layer 23 is formed, for example, in a plate shape extending along the XY plane. The eight stacked conductor layers 23 are sequentially used as word lines WL0 to WL7 starting from the conductor layer 21 side. The conductor layer 23 contains, for example, tungsten (W).

[0036] On the uppermost insulator layer 33, a conductor layer 24 and an insulator layer 34 are stacked in sequence. The conductor layer 24 is formed, for example, in a plate shape extending along the XY plane. The stacked conductor layer 24 serves as a selection gate line SGD. The conductor layer 24 contains, for example, tungsten (W). The conductor layer 24 is electrically separated for each string unit SU by a slit SHE, for example.

[0037] An insulator layer 34 is provided on the conductor layer 24. A conductor layer 25 is provided above the insulator layer 34. The conductor layer 25 is formed, for example, in a linear shape extending along the Y direction and functions as a bit line BL. The conductor layer 25 contains, for example, copper (Cu).

[0038] A plurality of memory pillars MP are provided to extend along the Z direction below the conductor layer 25, passing through the conductor layers 22 and 24 and the plurality of conductor layers 23. Additionally, the bottom of each memory pillar MP is located below the insulator layer 31 and is in contact with the conductor layer 21.

[0039] Each memory pillar MP contains, for example, a core member 35, a semiconductor film 36, a tunnel insulating film 37, a charge storage film 38, a blocking insulating film 39, and a semiconductor portion 26.

[0040] The core member 35 is arranged to extend, for example, along the Z direction. The upper end of the core member 35 is included in the layer above the conductor layer 24, and the lower end of the core member 35 is included in the layer below the conductor layer 22. The core member 35 includes, for example, silicon dioxide (SiO2).

[0041] The semiconductor film 36 is arranged to cover the side surface and the lower surface of the core member 35. The upper end of the semiconductor film 36 reaches the same position as the upper end of the core member 35. The lower end of the semiconductor film 36 is in contact with the conductor layer 21. The semiconductor film 36 includes, for example, polysilicon.

[0042] The tunnel insulating film 37 covers the side surface of the semiconductor film 36. The tunnel insulating film 37 includes, for example, silicon dioxide (SiO2).

[0043] The charge storage film 38 covers the side surface of the tunnel insulating film 37. The charge storage film 38 includes, for example, an insulator capable of storing charges. This insulator is, for example, silicon nitride (SiN).

[0044] The blocking insulating film 39 covers the side surface of the charge storage film 38. The blocking insulating film 39 includes, for example, silicon dioxide (SiO2).

[0045] The semiconductor portion 26 is arranged to be in contact with the semiconductor film 36 and cover the upper end of the core member 35. At the upper end of the semiconductor portion 26, a conductor layer 27 that functions as a columnar contact CV is provided. The upper end of the conductor layer 27 is in contact with the conductor layer 25. The conductor layer 25 has a linear bit line BL extending in the Y direction. In the conductor layer 25, for example, Figure 3 a plurality of bit lines BL are arranged at a prescribed interval in the front-back direction. Each bit line BL is electrically connected to the corresponding memory pillar MP via the corresponding conductor layer 27.

[0046] Above the conductor layer 25, a conductor layer 28 is arranged with an insulator layer therebetween. Above the conductor layer 28, a conductor layer 29 is arranged with an insulator layer therebetween. In the conductor layers 28 and 29, at least a part of the peripheral circuit of the memory cell array 10, for example, is arranged. In Figure 3 the example shows two conductor layers 28 and 29 laminated above the conductor layer in which the bit lines are arranged, but the number of wiring layers is arbitrary. In this specification, the conductor layer 25 including the bit lines is sometimes referred to as the wiring layer M0, the conductor layer 28 above it is referred to as the wiring layer M1, and the conductor layer 29 above it is referred to as the wiring layer M2.

[0047] In the configuration of the memory pillar MP described above, the portion where the memory pillar MP intersects with the conductor layer 22 functions as the selection transistor ST2. Further, the portion where the memory pillar MP intersects with the conductor layer 23 functions as the memory cell transistor MT. Further, the portion where the memory pillar MP intersects with the conductor layer 24 functions as the selection transistor ST1. Further, the semiconductor film 36 functions as the channel of each of the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. Further, the charge storage film 38 functions as the charge storage layer of the memory cell transistor MT.

[0048] (Overall Configuration of Row Decoder Module) Next, a configuration example of the row decoder module 15 included in the peripheral circuit PERI will be described.

[0049] Use Figure 4 To describe the overall configuration of the row decoder module 15. Figure 4 It is a circuit diagram for illustrating an example of the configurations of the row decoder module, driver module, and memory cell array 10 of the semiconductor memory device according to the embodiment.

[0050] The row decoder module 15 includes row decoders RD0 to RDn. The row decoders RD0 to RDn are used for the selection of the blocks BLK. The row decoders RD0 to RDn are respectively associated with BLK0 to BLKn.

[0051] Each row decoder RD includes, for example, a block decoder BD, and transfer transistors TW0 to TW7, TS, and TD0 to TD4. The transfer transistors TW0 to TW7, TS, and TD0 to TD4 are, for example, high breakdown voltage N-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). The transfer transistors TW0 to TW7 are respectively associated with the word lines WL0 to WL7. Further, in the following description, when not distinguishing between the transfer transistors TW0 to TW7, they are simply referred to as the transfer transistor TW. The transfer transistors TS and TD0 to TD4 are respectively associated with the selection gate lines SGS and SGD0 to SGD4. Further, in the following description, when not distinguishing between the transfer transistors TD0 to TD4, they are simply referred to as the transfer transistor TD. Further, a high breakdown voltage MOSFET means a MOSFET having a physical film thickness of the gate insulating film of 10 nm or more. The voltage between the gate and source of the high breakdown voltage N-channel MOSFET can be, for example, a voltage of 10 V or more.

[0052] The block decoder BD decodes the block address BA. For example, based on the result of this decoding, the block decoder BD applies a voltage of "H (High)" level and a voltage of "L (Low)" level to the transfer gate line BLKSEL. In this specification, the transfer gate line BLKSEL is sometimes simply referred to as the control wiring.

[0053] The transfer transistors TW0 to TW7, TS, and TD0 to TD4 respectively connect the driver module 14 to the corresponding block BLK via the signal lines CG0 to CG7, CGS, and CGD0 to CGD4. Additionally, in the following description, without distinguishing between the signal lines CG0 to CG7, CGS, and CGD0 to CGD4, they are simply referred to as the signal line CG.

[0054] More specifically, in each row decoder RD, the gate of each transfer transistor TD is connected to the transfer gate line BLKSEL. The first end of each transfer transistor TD is connected to the driver module 14 via the corresponding signal line CG among the signal lines CGD0 to CGD4. The second end of the transfer transistor TD is connected to the corresponding selection gate line SGD among the selection gate lines SGD0 to SGD4.

[0055] The gates of the transfer transistors TW are each connected to the transfer gate line BLKSEL. The first end of each transfer transistor TW is connected to the driver module 14 via the corresponding signal line CG among the signal lines CG0 to CG7. The second end of each transfer transistor TW is connected to the corresponding word line WL among the word lines WL0 to WL7.

[0056] The gate of the transfer transistor TS is connected to the transfer gate line BLKSEL. The first end of the transfer transistor TS is connected to the driver module 14 via the signal line CGS. The second end of the transfer transistor TS is connected to the selection gate line SGS.

[0057] When a voltage of "H" level is applied to the transfer gate line BLKSEL, the transfer transistors TW, TS, and TD become conductive states. As a result, the voltages of the respective signal lines CG0 to CG7, CGS, and CGD0 to CGD4 are each transmitted to the word lines WL0 to WL7, the selection gate line SGS, and the selection gate lines SGD0 to SGD4 via the transfer transistors TW0 to TW7, TS, and TD0 to TD4. When a voltage of "L" level is applied to the transfer gate line BLKSEL, the transfer transistors TW, TS, and TD become cutoff states.

[0058] (Basic Structure of Block Decoder BD) Use Figure 5 The structure of the multiple block decoders BD included in each row decoder RD will be described. Figure 5This is a circuit diagram showing the basic configuration of a block decoder BD included in a semiconductor memory device according to an embodiment.

[0059] As Figure 5 shown, the block decoder BD includes a logic circuit LC, a logical AND circuit AND, inverters INV1 and INV2, and transistors T1, T2, T3, and T4. Transistors T1, T2, and T4 are, for example, N-channel MOSFETs. Transistor T3 is, for example, a P-channel MOSFET. Transistors T2, T3, and T4 are high-voltage MOSFETs having a physical film thickness of the gate insulating film thicker than that of transistor T1. The physical film thickness of the gate insulating film of each of transistors T2, T3, and T4 is, for example, 10 nm or more. In addition, the gate-source voltage of each of transistors T2, T3, and T4 can be, for example, a voltage of 10 V or more. On the other hand, the physical film thickness of the gate insulating film of transistor T1 is, for example, thinner than 10 nm. In addition, the gate-source voltage of transistor T1 is, for example, a voltage lower than 10 V. In this specification, transistor T4 is sometimes referred to as the second transistor, transistor T3 is sometimes referred to as the third transistor, and transistor T2 is sometimes referred to as the fourth transistor. In addition, sometimes the Figure 4 transistors TD0 to TD4, TW0 to TW7, and TS are collectively referred to as the first transistor.

[0060] The block address BA is input from the address register 12 to the first input section of the logic circuit LC. The second input section of the logic circuit LC is, for example, applied with the power supply voltage VDD. The logic circuit LC is driven by the power supply voltage VDD. A signal based on this block address BA is output from the output section of the logic circuit LC. When the block address BA input to the logic circuit LC is the block address BA assigned to the block BLK corresponding to this logic circuit LC, a signal of "H" level is output from the output section of the logic circuit LC. When the block address BA input to the logic circuit LC is not the block address BA assigned to the block BLK corresponding to this logic circuit LC, a signal of "L" level is output from the output section of the logic circuit LC.

[0061] The first input section of the logical AND circuit AND is connected to the first output section of the logic circuit LC. The second input section of the logical AND circuit AND is, for example, applied with the power supply voltage VDD. The logical AND circuit AND is driven by the power supply voltage VDD. A signal of a logical AND operation based on the signal output from the output section of the logic circuit LC is output from the output section of the logical AND circuit AND.

[0062] The first input of the inverter INV1 is connected to the output of the logic AND circuit AND. The second input of the inverter INV1 is applied with the power supply voltage VDD, for example. The inverter INV1 is driven by the power supply voltage VDD. The output of the inverter INV1 is connected to the node N1. The output of the inverter INV1 outputs an inverted signal of the signal output from the output of the logic AND circuit AND.

[0063] The first input of the inverter INV2 is connected to the node N1. The power supply voltage VDD is applied to the second input of the inverter INV2, for example. The inverter INV2 is driven by the power supply voltage VDD. The output of the inverter INV2 outputs an inverted signal of the signal output from the output of the inverter INV1.

[0064] The first terminal (eg, drain) of the transistor T1 is connected to the output of the inverter INV2. The power supply voltage VDD is applied to the gate of the transistor T1. The second terminal (eg, source) of the transistor T1 is connected to the first terminal (eg, drain) of the transistor T2.

[0065] The first terminal of the transistor T2 is connected to the second terminal (eg, source) of the transistor T1. The power supply voltage VDD is applied to the gate of the transistor T2. The second terminal of the transistor T2 is connected to the transmission gate line BLKSEL.

[0066] A first terminal (eg, drain) of transistor T3 is connected to the transmission gate line BLKSEL. A gate of transistor T3 is connected to node N1. A second terminal (eg, source) of transistor T3 is connected to transistor T4 together with a back gate of transistor T3.

[0067] The first end (e.g., source) of transistor T4 is connected to the second end of transistor T3 and the back gate of transistor T3. The gate of transistor T4 is connected to the transmission gate line BLKSEL. The second end (e.g., drain) of transistor T4 is applied with voltage VRDEC. The second end of transistor T4 is applied with a high voltage set as follows: by transmitting the high voltage to the transmission gate line BLKSEL via transistors T3 and T4, the transmission transistors TW, TS, and TD can transmit the voltage supplied to the corresponding signal line CG to the word line WL, the selection gate line SGS, and the selection gate line SGD, respectively.

[0068] The transistor T4 switches whether to boost the voltage of the gate connected to the transmission gate line BLKSEL according to the voltage VRDEC for boosting the transmission gate line BLKSEL. The transistor T3 is turned on when boosting the transmission gate line BLKSEL, and is turned off otherwise. The transistor T2 sets the selected transmission gate line BLKSEL to a high level. The transistor T2 is turned on or off in conjunction with the transistor T3.

[0069] According to the above configuration, when the corresponding block BLK is selected, the block decoder BD outputs a signal with an "H" level to the transmission gate line BLKSEL. When the corresponding block BLK is not selected, the block decoder BD outputs a signal with an "L" level to the transmission gate line BLKSEL.

[0070] As Figure 1 and Figure 4 shown, each row decoder RD in the row decoder module 15 has a plurality of block decoders BD, and each block decoder BD is associated with a certain block. As Figure 5 shown, each block decoder BD uses the corresponding transmission gate line BLKSEL to switch and control the conduction or cutoff of the corresponding transmission transistors TW0 to TW7, TS, and TD0 to TD4. In this specification, the transmission transistors TW0 to TW7, TS, and TD0 to TD4 are sometimes collectively referred to as the switch circuit group or word line switch (fourth transistor) WLSW. Each row decoder RD has a plurality of switch circuit groups (word line switches) WLSW corresponding to the plurality of block decoders BD.

[0071] (First Embodiment) The semiconductor device according to the first embodiment has a block decoder BD with a configuration different from that of Figure 5 the block decoder BD. Figure 6 is a circuit diagram of the main part of the block decoder BD according to the first embodiment. In Figure 6 it, the same reference numerals are assigned to the components common to Figure 5 and the following description will focus on the differences. The block decoder BD according to the first embodiment has the same logic circuit LC, logic AND circuit AND, inverters INV1 and INV2, and transistor T1 as Figure 5 but are omitted in Figure 6 .

[0072] As Figure 6 shown, the block decoder BD according to the first embodiment uses the first voltage VRDEC generated by the driver module 14 and the like to control the voltage of the transmission gate line BLKSEL. The block decoder BD according to the first embodiment has a capacitor Ca1 and a rectifier circuit 4 in addition to the transistors T1 to T4.

[0073] The capacitor Ca1 boosts the voltage of the transmission gate line BLKSEL through capacitive coupling. The capacitor Ca1 can be implemented in various ways such as a MOS capacitor or an inter-wiring capacitance as described later. Additionally, the inter-wiring capacitance can be formed by, for example, MIM (Metal-Insulator-Metal) or MOM (Metal-Oxide-Metal).

[0074] The rectifying circuit 4 prevents the current from flowing backward between the drain and source of the transistor T3 due to the boosted voltage of the transmission gate line BLKSEL. The rectifying circuit 4 is composed of one or more diodes. Additionally, the diode can also be formed by short-circuiting the drain and gate of a MOS transistor. In the first embodiment, an example in which the rectifying circuit 4 is composed of two diodes (first diode, second diode) DD1 and DD2 connected in series is described. The anode of the diode DD1 is connected to the drain of the transistor T3. The cathode of the diode DD1 is connected to the anode of the diode DD2. The cathode of the diode DD2 is connected to the transmission gate line BLKSEL.

[0075] The transmission gate line BLKSEL is set to a voltage level corresponding to the voltage at one end of the capacitor Ca1. A second voltage Vz whose voltage level can be changed is applied to one end of the capacitor Ca1. The second voltage Vz is generated in the driver module 14 or elsewhere. The other end of the capacitor Ca1 is connected to an intermediate node Va that connects the cathode of the diode DD1 and the anode of the diode DD2.

[0076] Figure 7 This is a cross-sectional view in the case where the capacitor Ca1 is composed of a MOS capacitor. An N-type well region 6 is disposed on a P-type silicon substrate 5, and two diffusion regions 7a and 7b connected to one end of the capacitor Ca1 are disposed. Above the two diffusion regions 7a and 7b, a gate electrode layer 9 connected to the other end of the capacitor Ca1 is disposed with a gate insulating film 8 interposed therebetween. The gate electrode layer 9 can be a metal material or polysilicon. The thickness of the gate insulating film 8 is arbitrary. The transistors T2 to T4 in the block decoder BD are high-voltage transistors, and the gate insulating film 8 is thicker than that of the low-voltage transistor T1. Figure 7 The gate insulating film 8 of the MOS capacitor Ca1 shown can be the same as that of the high-voltage transistors T2 to T4, or can also be the same as that of the low-voltage transistor T1. By adjusting at least one of the film thickness or the material of the gate insulating film 8, the capacitance of the capacitor Ca1 can be adjusted. Thus, the gate insulating film 8 of the MOS capacitor Ca1 has, for example, a film thickness less than or equal to that of the transistors T1 to T3.

[0077] Figure 8 This is a diagram showing the voltage changes of the second voltage Vz and the transmission gate line BLKSEL. Figure 8The voltage waveforms of the second voltage Vz, the voltage of the intermediate node Va between the diodes DD1 and DD2, and the voltage Vy of the transmission gate line BLKSEL are shown.

[0078] At time t1, the transistor T1 is turned on, and the selected transmission gate line BLKSEL becomes high level. The voltage of the transmission gate line BLKSEL at this time becomes Vpgmh - 2Vfb. Vpgmh is the voltage VRDEC supplied from the outside to the transistor T4 in the block decoder BD. Since two diodes DD1 and DD2 are connected between the gate of the transistor T4 and the transmission gate line BLKSEL, the transmission gate line BLKSEL becomes a voltage level (Vpgmh - Vfb) obtained by subtracting the forward voltage Vfb of these diodes DD2 from the voltage Vpgmh. In this way, the intermediate node Va becomes a voltage higher than the forward voltage Vfb of the transmission gate line BLKSEL by the diode DD2.

[0079] At time t2, when the second voltage Vz rises, through the capacitive coupling of the capacitor Ca1, the voltage of the intermediate node Va rises to Vpgmh + α. At this time, the voltage of the transmission gate line BLKSEL becomes a voltage (Vpgmh + α - Vfb) lower than the voltage Vpgmh + α of the intermediate node Va by the forward voltage Vfb.

[0080] After that, at time t3 when the second voltage Vz drops, through the capacitive coupling of the capacitor Ca1, the voltage of the intermediate node Va also drops. The voltage of the intermediate node Va becomes a voltage lower than the voltage Vpgmh supplied from the outside to the transistor T4 by Vfb. At this time, the voltage Vy of the transmission gate line BLKSEL becomes a voltage lower than the voltage of the intermediate node Va by the forward voltage Vfb.

[0081] After that, at time t4 when the second voltage Vz rises, similar to time t2, as the voltage of the intermediate node Va rises, the voltage of the transmission gate line BLKSEL rises to (Vpgmh + α - Vfb).

[0082] For example, when the forward voltage Vfb of the diodes DD1 and DD2 is set to 0.8V, the transmission gate line BLKSEL can be boosted to a voltage 0.8V lower than the voltage rise amount of the intermediate node Va caused by the capacitive coupling of the capacitor Ca1.

[0083] In this way, by periodically raising and lowering the voltage level of the second voltage Vz applied to one end of the capacitor Ca1, the voltage level of the transmission gate line BLKSEL can be periodically boosted.

[0084] Figure 9It is a diagram showing the on-current characteristics of transfer transistors TW0 to TW7, TS, and TD0 to TD4 according to the first embodiment. Figure 9 The horizontal axis represents the gate voltage [V] of each transfer transistor (word line switch), and the vertical axis represents the on-current [A]. In Figure 9 , three curves w1, w2, and w3 showing the on-current characteristics are illustrated when the substrate bias Vbs of each transfer transistor TW0 to TW7, TS, and TD0 to TD4 is changed in three ways (Vbs = about -10V, about -15V, about -20V). Regardless of the substrate bias Vbs, the higher the gate voltage supplied by the transfer gate line BLK, the more the on-current tends to increase. For example, when the substrate bias Vbs = about -20V, if the second voltage Vz is increased from Vpgmh to Vpgmh + α, the on-current will change from Figure 9 curve p1 to curve p2. Thus, by increasing the second voltage Vz, the on-current can be increased.

[0085] Figure 10 It is a top view and a cross-sectional view showing the structures of diodes DD1 and DD2. Diodes DD1 and DD2 are each formed, for example, by joining a P-type diffusion region 42 and an N-type diffusion region 43 in an N-well region 41 disposed on a P-Si substrate 40. In Figure 10 example, the N-type diffusion region 43 is disposed so as to surround the periphery of the P-type diffusion region 42. The P-type diffusion region 42 is connected to the anode electrode, and the N-type diffusion region 43 is connected to the cathode electrode.

[0086] Diodes DD1 and DD2 may also have a structure in which the drain and gate of a MOS transistor are short-circuited. Figure 11 It is a cross-sectional view in the case where diodes DD1 and DD2 are formed of MOS transistors. In this case, the gate 46g and the drain 46d of a MOS transistor 46 in an N-well region 45 disposed on a P-type substrate 44 are short-circuited. Figure 11 It shows the cross-sectional structure of diode DD2. The short-circuited gate 46g and drain 46d are applied with a voltage Va. Since the source 46s is connected to the transfer gate line BLKSEL, it becomes voltage Vy. A capacitor Ca1 having the gate insulating film 47 of the MOS transistor 46 as a dielectric layer is disposed. One electrode 48 of the capacitor Ca1 is connected to a P-type diffusion region 49 disposed near the MOS transistor 46. This electrode 48 is applied with a voltage Vz. The other electrode 50 of the capacitor Ca1 is connected to the gate 46g and the drain 46d of the MOS transistor 46 connected in a diode configuration.

[0087] Figure 12 It is a circuit diagram of a block decoder BD according to the first modification of the first embodiment. Figure 12The semiconductor device according to the first modification example shown in FIG. 1 is characterized in that Figure 6 The capacitor Ca1 of the block decoder BD is replaced by two capacitors Ca1a and Ca1b connected in parallel. By connecting the two capacitors Ca1a and Ca1b in parallel between the node to which the second voltage Vz is applied and the intermediate node Va, it is difficult for each capacitor Ca1a and Ca1b to cause insulation breakdown. Figure 6 In comparison, the area of ​​each capacitor Ca1a, Ca1b can be reduced.

[0088] Figure 13 It is a cross-sectional view of two capacitors Ca1a and Ca1b of the block decoder BD involved in the first variant. On the gate insulating film 55 arranged on the N-well region 54 on the P-Si substrate 53, an IPD (Inter-Poly Dielectric: inter-polysilicon dielectric) film 57 is arranged via a first conductive layer 56, and a second conductive layer 58 is arranged thereon. The first conductive layer 56 and the second conductive layer 58 can be polysilicon layers or metal layers. The first capacitor Ca1 is formed by sandwiching the IPD film 57 with the first conductive layer 56 and the second conductive layer 58. In addition, the second capacitor Ca1 connected in parallel with the first capacitor Ca1 is formed by sandwiching the gate insulating film 55 with the second conductive layer 58 and the source / drain diffusion layer 59.

[0089] Figure 14 It is a circuit diagram of a block decoder BD according to a second modification of the first embodiment. Figure 14 The semiconductor device according to the second modification example shown in FIG. 1 is characterized in that three or more capacitors Ca1 are connected in parallel between the node to which the second voltage Vz is applied and the intermediate node Va. Figure 12 In contrast, each capacitor Ca1 is less likely to cause insulation breakdown.

[0090] exist Figure 14 In FIG. 1 , three or more capacitors Ca1 are connected in parallel between the wiring to which the second voltage Vz is applied and the wiring of the intermediate node Va.

[0091] Figure 15 2 is a cross-sectional view of a capacitor Ca1 according to a second modification. The capacitor Ca1 according to the second modification is arranged at Figure 3In the wiring layer region WR shown. In the wiring layer region WR, wiring layers D0 and D1 are stacked. For example, in the wiring layer D1, the wiring layer D1a to which the voltage Vy is applied and the wiring layer D1b to which the second voltage Vz is applied are alternately arranged. The wiring layer D1a to which the voltage Vy is applied is the wiring layer connected to the transfer gate line BLKSEL. A capacitor Ca1 is arranged between the wiring layer D1a to which the voltage Vy is applied and the wiring layer D1b to which the second voltage Vz is applied that are adjacent in the substrate surface direction. Thus, by connecting the capacitor Ca1 between two adjacent wiring layers D1a and D1b in the substrate surface direction, the number of capacitors Ca1 can be increased with a small area, and the dielectric breakdown of each capacitor Ca1 can be prevented.

[0092] Figure 15 An example of arranging a plurality of transfer transistors 63 in a P-type well region 62 arranged in a part of an N-type well region 61 arranged on a P-type silicon substrate 60 is shown. Two transfer transistors 63 adjacent in the substrate surface direction share a drain region 63d or a source region 63s. The drain region 63d and the source region 63s of each transfer transistor 63 are each connected to different electrodes provided in the wiring layer D0 via a contact 64.

[0093] Thus, in the block decoder BD according to the first embodiment, the second voltage Vz whose voltage level changes periodically is applied to one end of the capacitor Ca1, and the other end of the capacitor Ca1 is connected to an intermediate node Va of two diodes DD1 and DD2 connected in series between the drain of the transistor T3 and the transfer gate line BLKSEL. Thus, through the capacitive coupling of the capacitor Ca1, the voltage level of the transfer gate line BLKSEL can be periodically increased. Therefore, the voltage level of the transfer gate line BLKSEL can be boosted corresponding to the timing of writing data into the NAND string.

[0094] According to the present embodiment, since the periodic boosting operation of the transfer gate line BLKSEL can be performed only by the capacitor Ca1, the circuit configuration of the block decoder BD can be simplified. In addition, since the boosting is performed by capacitive coupling, the switching of the voltage level of the transfer gate line BLKSEL can be quickly performed with low power consumption.

[0095] In addition, since the diodes DD1 and DD2 are connected between the drain of the transistor T3 and the transfer gate line BLKSEL, even when the transfer gate line BLKSEL is boosted, current does not flow from the transfer gate line BLKSEL to the drain of the transistor T3, and the operation when the transfer gate line BLKSEL is boosted can be stabilized.

[0096] (Second Embodiment) Figure 16This is a circuit diagram of the block decoder BD according to the second embodiment. In Figure 16 the same reference numerals are assigned to the components common to Figure 6 and the following description will focus on the differences.

[0097] Figure 16 The block decoder BD according to the second embodiment shown has a capacitor Ca2 connected at a position different from that of Figure 6 . In addition, the block decoder BD according to the second embodiment is different from Figure 6 in that one diode DD1 is connected between the drain of the transistor T3 and the transfer gate line BLKSEL.

[0098] The block decoder BD according to the second embodiment has a capacitor Ca2 connected to the gate of the transfer transistor 63. One end CG2 of the capacitor Ca2 is applied with a second voltage Vz, and the other end CG1 of the capacitor Ca2 is connected to the gate of the transfer transistor 63. As Figure 4 shown, the transfer gate line BLKSEL is connected to the gates of the plurality of transfer transistors 63. The gates of the plurality of transfer transistors 63 are individually connected to the capacitor Ca2 described above. That is, the capacitor Ca2 is provided for each of the plurality of transfer transistors 63. More specifically, the plurality of transfer transistors are transfer transistors TW0 to TW7, TS, and TD0 to TD4, etc.

[0099] Figure 17 This is a cross-sectional view of the capacitor Ca2 included in the block decoder BD according to the second embodiment. Figure 17 This shows a cross-sectional view of the transfer transistor 63 having a gate to which the other end of the capacitor Ca2 is connected. The transfer transistor 63 is provided in a plurality of P-type well regions 62 arranged in a part of the N-type well region 61 on the P-type silicon substrate 60. A gate insulating film 65 is disposed above the P-type well region 62, and a first polysilicon layer 66 is disposed thereon. An IPD film 67 is disposed above the first polysilicon layer 66, and a second polysilicon layer 68 is disposed thereon.

[0100] The capacitor Ca2 has a structure in which the IPD film 67 is sandwiched between the first polysilicon layer 66 and the second polysilicon layer 68. The transfer transistor 63 uses the first polysilicon layer 66 as a gate. A gate electrode CG1 is connected to the first polysilicon layer 66. An electrode CG2 is connected to the second polysilicon layer 68. The gate electrode CG1 is connected to the transfer gate line BLKSEL and is applied with a voltage Vy. The electrode CG2 is applied with a second voltage Vz.

[0101] When the voltage level of the second voltage Vz increases, due to the capacitive coupling of the capacitor Ca2, the gate voltage CG1 of the transfer transistor 63 increases. Since the transfer gate line BLKSEL is connected to the gate of the transfer transistor 63, when the gate voltage of the transfer transistor 63 rises, the voltage Vy of the transfer gate line BLKSEL also rises. A diode is connected between the drain of the transistor T3 and the transfer gate line BLKSEL. Therefore, even when the voltage Vy of the transfer gate line BLKSEL rises, it is possible to prevent current from flowing from the transfer gate line BLKSEL to the drain of the transistor T3.

[0102] Figure 18 is a diagram showing Figure 17 the changes in the voltage levels of the voltages CG1 and CG2. As described above, the voltage CG1 is the voltage Vy of the transfer gate line BLKSEL. The voltage CG2 is the second voltage Vz applied to one end of the capacitor Ca2.

[0103] When the voltage level of the voltage CG2 (second voltage Vz) rises at time t1, due to the capacitive coupling of the capacitor Ca2, the voltage level of the voltage CG1 (transfer gate line BLKSEL) also rises. After that, when the voltage level of the voltage CG1 further rises at time t2, due to the capacitive coupling of the capacitor Ca2, the voltage level of the voltage CG1 further rises.

[0104] Figure 19 is a diagram showing the on-current characteristics of the transfer transistor 63 according to the second embodiment. Figure 19 The horizontal axis of is the gate voltage [V] of each transfer transistor 63 (word line switch), and the vertical axis is the on-current [A]. In Figure 19 it, the curves w4, w5, and w6 showing the on-current characteristics are illustrated for the case where the substrate bias Vbs of each of the transfer transistors TW0 to TW7, TS, and TD0 to TD4 is changed in three ways. Regardless of the substrate bias Vbs, the higher the gate voltage, the more the on-current tends to increase. For example, when the substrate bias Vbs = 24V, if the second voltage Vz is increased from Vpgmh to Vpgmh + α, the on-current will increase as shown by the curve p3 to the curve p4 in Figure 19 .

[0105] Thus, in the second embodiment, by connecting the capacitor Ca2 to the gate of each transfer transistor 63 and increasing the voltage CG1 (second voltage Vz) applied to one end of the capacitor Ca2, it is possible to rapidly increase the gate voltage of each transfer transistor 63. As a result, it is possible to raise the voltage level of the transfer gate line BLKSEL without complicating the configuration of the block decoder BD.

[0106] (Third Embodiment) In contrast to generating the boost voltage for the transfer gate line BLKSEL by using the capacitive coupling of the capacitors Ca1 and Ca2 inside the block decoder BD in the above-described first and second embodiments, the third embodiment is characterized in that the boost voltage is generated on the front stage side of the row decoder RD in which the block decoder BD is incorporated.

[0107] Figure 20 FIG. is a block diagram showing the configuration on the transmission path of the voltage VRDEC supplied to each block decoder BD. A voltage supply circuit (first boost circuit) 71, a first multiplexer 72, a second multiplexer 73, a local charge pump (second boost circuit) 74, and a row decoder module 15 are connected on the above-described transmission path. The voltage supply circuit 71, the first multiplexer 72, the second multiplexer 73, the local charge pump 74, and the row decoder RD are incorporated in the driver module 14, for example.

[0108] The voltage supply circuit 71 generates a voltage of a specified voltage level. The first multiplexer 72 divides the voltage generated by the voltage supply circuit 71 into a plurality of systems. The second multiplexer 73 further divides each of the plurality of systems divided by the first multiplexer 72 into a plurality of systems. Each system divided by the second multiplexer 73 is, for example, for each block decoder BD.

[0109] The local charge pump 74 is provided, for example, for Figure 4 each row decoder module 15, and boosts the voltage VRDEC applied to the corresponding block decoder BD as needed.

[0110] The block decoder BD according to the third embodiment is configured Figure 5 in the same manner. The local charge pump 74 generates the voltage VRDEC and supplies it to the corresponding block decoder BD. The local charge pump 74 raises the voltage level of the voltage VRDEC as needed. Specifically, the voltage level of the voltage VRDEC is boosted during data writing. The voltage VRDEC generated by the local charge pump 74 is applied to Figure 5 the drain of the transistor T4. The block decoder BD supplies the voltage corresponding to the voltage VRDEC to the transfer gate line BLKSEL. Thus, since each block decoder BD according to the third embodiment does not have the boost circuit of the block decoder BD according to the first and second embodiments, the circuit scale of the block decoder BD can be reduced compared with the first and second embodiments.

[0111] Figure 21 FIG. shows, for one control signal line CGN, the signal from Figure 20Diagram of the path from the input of the second multiplexer 73 to the word lines. As described above, each row decoder RD within the row decoder module 15 has a plurality of switch circuit groups (word line switches) WLSW respectively corresponding to a plurality of block decoders BD.

[0112] As Figure 21 shown, the word lines located in the same layer among the word lines of all blocks are respectively connected to one control signal line CGI. The number of control signal lines CGI is equal to the number of word lines of one block BLK. The plurality of control signal lines CGI correspond to one control signal line CGN output from the first multiplexer 72. The second multiplexer 73 has a plurality of second multiplexer units 73a, and each of the plurality of second multiplexer units 73a selects whether to supply the voltage transmitted by one control signal line CGN to the control signal line CGI corresponding to a certain word line.

[0113] In Figure 21 it, an example is shown in which there are 9 control signal lines CGI, 9 blocks, and 9×9 = 81 word lines WL for one control signal line CGN. Typically, for several to dozens of control signal lines CGN, dozens to hundreds of control signal lines CGI, thousands of blocks, and tens of thousands or more word lines are provided. Therefore, the typical magnitude relationship of the number of control signal lines CGN, CGI, and word lines WL is CGN < CGI < WL. The same applies to the other control signal lines SGDN, SGDI, SGD, SGSN, SGSI, SGS. For example, the number of the other control signal lines is SGDN < SGDI < SGD, SGSN < SGSI < SGS. Hereinafter, the control signal lines CGN, SGDN, and SGSN are collectively referred to as control signal lines GN.

[0114] Figure 22 is a diagram showing the wiring path from the voltage supply circuit 71 to the row decoder module 15. In addition, for the plurality of control signal lines GN, numbers are marked after GN for distinction. In Figure 22 an example with 8 control signal lines GN is shown, but the number of control signal lines GN is arbitrary.

[0115] The second multiplexer 73 has a switch group SW10 to SW17 including a plurality of switches. Each of the switch groups SW10 to SW17 has the same configuration. A control signal line GN0 is commonly connected to the input terminals of the switches in the switch group SW10. The output terminals of the switches in the switch group SW10 are respectively connected to the control signal lines SGDI, CGI, and SGSI. The switch group SW10 determines to which control signal line the voltage supplied via the control signal line GN0 is supplied. For example, when the read voltage VCGRV is transmitted through the control signal line GN0, the switch group SW10 controls each switch to supply the voltage VCGRV to the control signal line CGI corresponding to the word line WL to be read.

[0116] Similarly, as Figure 22 shown, the input terminals of the switches in the switch groups SW10 to SW17 are respectively connected to the control signal lines GN0 to GN7. In addition, as Figure 22 shown, the output terminals of the switch groups SW10 to SW17 are respectively connected to the control signal lines SGDI, CGI, and SGSI.

[0117] The switch groups SW10 to SW17 control each switch in such a way that the voltages transmitted by the control signal lines GN0 to GN7 are supplied to the control signal lines SGDI, CGI, and SGSI corresponding to the control signal lines SGD, WL, and SGS in the storage cell array 10 to be supplied. In this way, the voltages corresponding to the control signal lines SGDI, SGSI, and CGI are supplied from the second multiplexer 73. For example, during a write operation, each switch is controlled so that the switch group that has transmitted the voltage VPASS through the control signal line GN supplies the voltage VPASS to a plurality of control signal lines CGI corresponding to non-selected word lines.

[0118] Figure 23 FIG. is a block diagram showing the connection relationship between the voltage supply circuit 71 and the local charge pump 74. The voltage supply circuit 71 has a main charge pump 75, a first voltage generation unit 76, and a second voltage generation unit 77.

[0119] The main charge pump 75 generates a voltage VPGMH supplied to the plurality of first voltage generation units 76 and the plurality of second voltage generation units 77, and a voltage VPGM supplied to the first multiplexer 72.

[0120] The first voltage generation unit 76 and the second voltage generation unit 77 are provided in association with each row decoder module 15, that is, a plurality of block decoders BD within the row decoder module 15. That is, each of the plurality of first voltage generation units 76 generates a voltage VRDEC_PB for the corresponding block decoder BD. Similarly, each of the plurality of second voltage generation units 77 generates a voltage VRDEC_HVSW for the corresponding block decoder BD. The voltage VRDEC_VSW generated by each of the plurality of second voltage generation units 77 is input to the gates of the transistors of the first multiplexer 72 and the second multiplexer 73.

[0121] The local charge pump 74 uses the voltage VRDEC_PB generated by the first voltage generation unit 76 to generate a voltage VRDEC for boosting the transmission gate line of the corresponding block decoder BD.

[0122] Figure 24 It is a circuit diagram showing an example of the internal configuration of the local charge pump 74. As Figure 24 shown, the local charge pump 74 includes first to fourth transistors Q1 to Q4, and first and second capacitors Ca11 and C12. The first to fourth transistors Q1 to Q4 are all NMOS transistors. The drain of the first transistor Q1 and the drain of the third transistor Q3 are connected to the input voltage node VIN. The source of the first transistor Q1 is connected to the drain of the second transistor Q2, and the source of the second transistor Q2 is connected to the output voltage node VOUT. The source of the third transistor Q3 is connected to the drain of the fourth transistor Q4, and the source of the fourth transistor Q4 is connected to the output voltage node VOUT. The gate of the first transistor Q1 is connected to the source of the third transistor Q3 and the drain of the fourth transistor Q4. The gate of the fourth transistor Q3 is connected to the source of the first transistor Q1 and the drain of the second transistor Q2. The first electrode of the first capacitor Ca11 is input with an inverted clock signal KLC, and the second electrode of the first capacitor Ca11 is connected to the gate of the third transistor Q3, the source of the first transistor Q1, and the drain of the second transistor Q2. The first electrode of the second capacitor Ca12 is input with a clock signal CLK, and the second electrode of the first capacitor Ca11 is connected to the gate of the first transistor Q1, the source of the third transistor Q3, and the drain of the fourth transistor Q4. The input voltage node VIN is applied with the voltage VRDEC_PB generated by the first voltage generation unit 76.

[0123] In addition, Figure 24 This is just an example of the internal configuration of the local charge pump 74. The local charge pump 74 may adopt an internal configuration different from Figure 24 this.

[0124] Figure 25 It is a voltage waveform diagram of the signals input to and output from the local charge pump 74. Figure 25The figure shows the voltage waveforms of the clock signal CLK, the inverted clock signal KLC, the voltage VRDEC_PB input to the input voltage node, the voltage NN1 at the second electrode of the first capacitor Ca11, the voltage NN2 at the second electrode of the second capacitor Ca11, and the voltage VOUT output from the output voltage node. As Figure 25 shown, as the number of clocks of the clock signal CLK increases, the voltage VOUT gradually rises.

[0125] Figure 26 is a voltage waveform diagram of the block decoder BD according to the third embodiment. In Figure 26 it, the voltage waveforms w1 when the voltage of the transfer gate line BLKSEL in the Figure 23 block decoder BD is boosted by the local charge pump 74, the voltage waveform w2 when not boosted, the voltage waveforms w3a, w3b after boosting the word lines connected to the word line switch WLSW, and the voltage waveforms w4a, w4b before boosting are shown. The voltage waveforms w3a, w4a show the voltage waveforms of the word lines near the block decoder BD, and the voltage waveforms w3b, w4b show the voltage waveforms of the word lines far from the block decoder BD.

[0126] As Figure 26 shown, when the voltage VRDEC is boosted by the Figure 23 local charge pump 74, the voltage of the transfer gate line BLKSEL in the block decoder is boosted by about 1 V, and the voltage level of the word line is also boosted.

[0127] Thus, in the third embodiment, since the local charge pump 74 for boosting the voltage supplied to each block decoder BD in the row decoder module 15 is provided on the front stage side of the row decoder module 15, it is possible to reduce the overall circuit size of the semiconductor memory device without having each block decoder BD have an additional boosting function.

[0128] [Supplementary Note] [Item 1] A semiconductor device, comprising: a control wiring connected to the gate of the first transistor; a second transistor having a first terminal and a second terminal respectively serving as a source or a drain, and a first gate connected to the control wiring, the first voltage for turning on the first transistor being input to the first terminal; a third transistor having a third terminal and a fourth terminal respectively serving as a source or a drain, and a second gate, the third terminal being connected to the second terminal, the fourth terminal controlling the voltage of the control wiring, the third transistor being turned on by a first control signal input to the second gate when the first transistor is turned on; A fourth transistor having a fifth terminal and a sixth terminal respectively serving as a source or a drain, and a third gate, the fourth transistor being turned on by a second control signal input to the third gate when the third transistor is turned on, and being turned off by the second control signal input to the third gate when the third transistor is turned off; and A capacitor that boosts, by capacitive coupling, a second voltage output from the fourth terminal in a state where the first transistor and the second transistor are turned on to a third voltage higher than the second voltage, and supplies the third voltage to the control wiring. [Item 2] The semiconductor device according to Item 1, wherein A rectifying circuit is provided to prevent a current caused by the boosted voltage of the control wiring from flowing between the drain and source of the third transistor. [Item 3] The semiconductor device according to Item 2, wherein The second transistor and the fourth transistor are N-type MOS (Metal Oxide Semiconductor) transistors, The third transistor is a P-type MOS transistor, The rectifying circuit is disposed between the drain of the P-type MOS transistor and the control wiring. [Item 4] The semiconductor device according to Item 2 or 3, wherein The rectifying circuit is a diode having an anode connected to the drain of the third transistor and a cathode connected to the control wiring, or a MOS transistor connected in a diode configuration. [Item 5] The semiconductor device according to Item 4, wherein The rectifying circuit has a first diode and a second diode connected in series between the drain of the third transistor and the control wiring, The capacitor boosts, by capacitive coupling, the voltage level of an intermediate node connecting the cathode of the first diode and the anode of the second diode. [Item 6] The semiconductor device according to Item 5, wherein One end of the capacitor is connected to the intermediate node, The other end of the capacitor is applied with a second voltage whose voltage level can be changed. [Item 7] The semiconductor device according to any one of Items 1 to 6, wherein The control wiring is at a voltage level corresponding to the voltage of one end of the capacitor, One end of the capacitor is applied with a second voltage whose voltage level can be changed. [Item 8] The semiconductor device according to Item 7, wherein, the second voltage is a clock signal whose voltage level changes periodically, the control wiring is repeatedly boosted in synchronization with the period of the clock signal. [Item 9] The semiconductor device according to Item 7 or 8, wherein, a plurality of the capacitors are provided in parallel between the control wiring and the application node of the second voltage. [Item 10] The semiconductor device according to any one of Items 1 to 9, wherein, the capacitor is a MOS capacitor having a gate insulating film with a film thickness less than or equal to the film thickness of the gate insulating films of the second to fourth transistors. [Item 11] The semiconductor device according to any one of Items 1 to 10, wherein, a plurality of fifth transistors are provided, and the gates of the plurality of fifth transistors are connected to the control wiring, when the control wiring is boosted, each of the plurality of fifth transistors has a larger on-current flowing between the drain and the source than in the case where it is not boosted. [Item 12] The semiconductor device according to any one of Items 1 to 4, wherein, comprises: a fifth transistor whose gate is connected to the control wiring; and a dielectric layer and a conductive layer stacked on the gate of the fifth transistor, the capacitor includes the gate of the fifth transistor, the dielectric layer, and the conductive layer, the conductive layer is applied with a second voltage whose voltage level can be changed, the gate voltage of the fifth transistor is variably controlled by capacitive coupling of the capacitor. [Item 13] The semiconductor device according to any one of Items 1 to 12, wherein, a decoder is provided which selects the control wiring to be boosted from a plurality of control wirings, the decoder has the second transistor, the third transistor, the fourth transistor, and the capacitor for each of the plurality of control wirings. [Item 14] The semiconductor device according to Item 13, wherein, comprises: a plurality of memory strings, each of the plurality of memory strings having a plurality of memory cell transistors and control transistors connected in series; A plurality of first wirings, each of the plurality of first wirings being connected to each gate of the plurality of memory cell transistors and control transistors; and A plurality of transfer transistors, the plurality of transfer transistors switching whether to drive the plurality of first wirings, The decoder switches whether to drive each gate line of the plurality of transfer transistors in the selected memory string as the control wiring. [Item 15] A semiconductor device, comprising: A voltage supply circuit that generates a first voltage commonly used when boosting a plurality of control wirings; A boosting circuit that is provided corresponding to the plurality of control wirings and generates a second voltage higher than the first voltage based on the first voltage; and A plurality of decoders that control whether to boost the corresponding control wiring based on the second voltage. [Item 16] The semiconductor device according to Item 15, wherein It includes: A plurality of memory strings, each of the plurality of memory strings having a plurality of memory cell transistors and control transistors connected in series; and A memory cell array that erases data for each of a plurality of blocks each having the plurality of memory strings, The plurality of decoders are provided in association with the plurality of blocks. [Item 17] The semiconductor device according to Item 16, wherein Each of the plurality of decoders has: A first transistor that switches whether to boost the voltage of the gate connected to the corresponding control wiring based on the corresponding second voltage; A second transistor that conducts when boosting the corresponding control wiring; and A third transistor that cuts off when boosting the corresponding control wiring. [Item 18] The semiconductor device according to any one of Items 1 to 14, or Item 17, wherein The first transistor, the second transistor, and the third transistor are high-voltage withstand transistors. The embodiments of the present disclosure are not limited to the above-described respective embodiments, and also include various modifications that can be conceived by those skilled in the art. The effects of the present disclosure are not limited to the above content. That is, various additions, changes, and partial deletions can be made without departing from the conceptual ideas and gists of the present disclosure derived from the content defined in the claims and their equivalents. [Description of Reference Numerals]

[0129] 1 Semiconductor memory device, 2 Memory controller, 3 Storage system, 4 Rectifier circuit, 5 P-type silicon substrate, 6 N-type well region, 7a Diffusion region, 7b Diffusion region, 8 Gate insulating film, 9 Gate electrode layer, 10 Memory cell array, 11 Command register, 12 Address register, 13 Sequencer, 14 Driver module, 15 Row decoder module, 16 Sense amplifier module, 20 Semiconductor substrate, 21 - 25 Conductor layers, 26 Semiconductor portion, 27 - 29 Conductor layers, 28 Conductor layer, 29 Conductor layer, 31 - 34 Insulator layers, 35 Core member, 36 Semiconductor film, 37 Tunnel insulating film, 38 Charge storage film, 39 Blocking insulating film, 40 P-Si substrate, 41 N well region, 42 P-type diffusion region, 43 N-type diffusion region, 44 P-type substrate, 45 N well region, 46 MOS transistor, 46d Drain, 46g Gate, 46s Source, 47 Gate insulating film, 48 Electrode, 49 P-type diffusion region, 50 Electrode, 53 P-Si substrate, 54 N well region, 55 Gate insulating film, 56 First conductive layer, 57 IPD film, 58 Second conductive layer, 59 Drain diffusion layer, 60 P-type silicon substrate, 61 N-type well region, 62 P-type well region, 63 Transfer transistor, 63d Drain region, 63s Source region, 64 Contact, 65 Gate insulating film, 66 First polysilicon layer, 67 IPD film, 68 Second polysilicon layer, 71 Voltage supply circuit, 72 First multiplexer, 73 Second multiplexer, 73a Second multiplexer section, 74 Local charge pump, 75 Main charge pump, 76 First voltage generation section, 77 Second voltage generation section.

Claims

1. A semiconductor device comprising: a control wiring connected to the gate of the first transistor; a second transistor having a first terminal and a second terminal as a source or a drain, respectively, and a first gate connected to the control wiring, the first terminal being input with a first voltage for turning on the first transistor; a third transistor having a third terminal and a fourth terminal as a source or a drain, respectively, and a second gate, the third terminal being connected to the second terminal, the fourth terminal controlling a voltage of the control wiring, the third transistor being turned on by a first control signal input to the second gate when the first transistor is turned on; a fourth transistor having a fifth terminal and a sixth terminal as a source or a drain, respectively, and a third gate, the fourth transistor being turned on by a second control signal input to the third gate when the third transistor is turned on, and being turned off by a second control signal input to the third gate when the third transistor is turned off; as well as The capacitor boosts the second voltage output from the fourth terminal when the first transistor and the second transistor are in an on state to a third voltage higher than the second voltage through capacitive coupling, and supplies the voltage to the control wiring.

2. The semiconductor device according to claim 1, wherein A rectifying circuit is provided for preventing a current caused by the boosted voltage of the control wiring from flowing between the drain and the source of the third transistor.

3. The semiconductor device according to claim 2, wherein: The second transistor and the fourth transistor are N-type MOS transistors, The third transistor is a P-type MOS transistor, The rectifying circuit is arranged between the drain of the P-type MOS transistor and the control wiring.

4. The semiconductor device according to claim 2, wherein: The rectifying circuit is a diode having an anode connected to the drain of the third transistor and a cathode connected to the control wiring, or a diode-connected MOS transistor.

5. The semiconductor device according to claim 4, wherein: The rectifying circuit includes a first diode and a second diode connected in series between the drain of the third transistor and the control wiring. The capacitor boosts a voltage level of an intermediate node connecting a cathode of the first diode and an anode of the second diode through capacitive coupling.

6. The semiconductor device according to claim 5, wherein: One end of the capacitor is connected to the intermediate node, A second voltage whose voltage level can be changed is applied to the other end of the capacitor.

7. The semiconductor device according to claim 1, wherein The control wiring has a voltage level corresponding to the voltage at one end of the capacitor, A second voltage whose voltage level can be changed is applied to one end of the capacitor.

8. The semiconductor device according to claim 7, wherein: The second voltage is a clock signal whose voltage level changes periodically, The control wiring is repeatedly boosted in synchronization with a cycle of the clock signal.

9. The semiconductor device according to claim 7, wherein: A plurality of the capacitors connected in parallel are provided between the control wiring and the node to which the second voltage is applied.

10. The semiconductor device according to claim 1, wherein The capacitor is a MOS capacitor having a gate insulating film having a thickness less than that of gate insulating films of the second to fourth transistors.

11. The semiconductor device according to claim 1, wherein A plurality of the first transistors are provided, each of which has a gate connected to the control wiring, When the voltage of the control wiring is boosted, a larger on-current flows between the drain and the source of each of the plurality of first transistors than when the voltage is not boosted.

12. The semiconductor device according to claim 1, wherein A dielectric layer and a conductive layer stacked on the gate of the first transistor are provided, The capacitor includes a gate of the first transistor, the dielectric layer, and the conductive layer, A second voltage capable of changing the voltage level is applied to the conductive layer, The gate voltage of the first transistor is variably controlled by capacitive coupling of the capacitor.

13. The semiconductor device according to claim 1, wherein A decoder is provided for selecting a control wiring to be boosted from a plurality of control wirings, The decoder includes the second transistor, the third transistor, the fourth transistor, and the capacitor for each of the plurality of control wirings.

14. The semiconductor device according to claim 13, wherein: have: a plurality of memory strings, each of the plurality of memory strings having a plurality of memory cell transistors and a control transistor connected in series; a plurality of first wirings, the plurality of first wirings being respectively connected to the gates of the plurality of memory cell transistors and the control transistor; as well as a plurality of transfer transistors for switching whether to drive the plurality of first wirings; The decoder switches whether to drive each gate line of the plurality of transfer transistors in the selected memory string as the control wiring.

15. A semiconductor device comprising: a voltage supply circuit that generates a first voltage commonly used when boosting a plurality of control wirings; a boost circuit provided corresponding to the plurality of control wirings and configured to generate a second voltage higher than the first voltage based on the first voltage; and A plurality of decoders control whether to boost the corresponding control wiring according to the second voltage.

16. The semiconductor device according to claim 15, wherein: have: a plurality of memory strings, each of the plurality of memory strings having a plurality of memory cell transistors and a control transistor connected in series; as well as A memory cell array is configured to erase data in each of a plurality of blocks each having the plurality of memory strings. The plurality of decoders are provided in association with the plurality of blocks.

17. The semiconductor device according to claim 16, wherein: Each of the plurality of decoders has: a first transistor that switches whether to boost a voltage of a gate connected to the corresponding control wiring according to the corresponding second voltage; a second transistor that is turned on when the corresponding control wiring is boosted; as well as The third transistor is turned off when the corresponding control wiring is boosted.

18. The semiconductor device according to claim 1, wherein The first transistor, the second transistor, and the third transistor are high withstand voltage transistors.

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