Multilayer electronic component

Abstract

The present disclosure provides a multilayer electronic component. The multilayer electronic component may include: a body including a plurality of capacitance forming portions including first dielectric layers and internal electrodes alternately arranged in a first direction, and an intermediate layer disposed between adjacent capacitance forming portions and including second dielectric layers, the main body comprises a first surface and a second surface which are opposite to each other in a first direction, a third surface and a fourth surface which are connected to the first surface and the second surface and are opposite to each other in a second direction, and a fifth surface and a sixth surface which are connected to the first surface to the fourth surface and are opposite to each other in a third direction; and an external electrode disposed on the body and connected to the internal electrode, and the first dielectric layer and the second dielectric layer may include a plurality of crystal grains and holes, and an average crystal grain size of the first dielectric layer may be smaller than an average crystal grain size of the second dielectric layer, and a porosity of the first dielectric layer may be lower than a porosity of the second dielectric layer.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0195311, filed with the Korean Intellectual Property Office on December 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a multi-layer electronic component. Background Art

[0003] A multi-layer ceramic capacitor (MLCC), which is a type of multi-layer electronic component, is a chip capacitor that is mounted on a printed circuit board of various types of electronic products (such as image display devices including liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, and mobile phones) and is used for charging or discharging.

[0004] Multi-layer ceramic capacitors can be used as components in various electronic devices because they have a small size, ensure a high capacitance, and are easy to install. With the miniaturization of various electronic devices such as computers and mobile devices and the realization of high output power, the demand for miniaturization and high capacitance of multi-layer ceramic capacitors is also increasing.

[0005] Generally, an MLCC has a structure with the same width and thickness. To achieve a high capacitance, it is necessary to increase the number of layers by thinning the dielectric layer and the internal electrodes. However, due to technical limitations in thinning the dielectric layer and the internal electrodes, it may not be easy to achieve a high number of layers in a structure where the chip has the same width and thickness. Therefore, a high-profile ceramic capacitor (HPCC) product has been developed to achieve a high stacking number of layers by increasing the thickness of the chip.

[0006] Since the HPCC has a structure in which its thickness T is greater than its width W, the HPCC can increase the number of layers and can easily achieve a high capacitance compared to a general MLCC having the same width and thickness.

[0007] However, since the HPCC has a structure in which its thickness T is greater than its width W, there may be a problem that the shape of the chip may be easily deformed due to stress generated during the pressing and cutting processes. Summary of the Invention

[0008] One aspect of the present disclosure is to provide a multi-layer electronic component having excellent reliability.

[0009] One aspect of the present disclosure is to prevent defects in the shape deformation of the main body.

[0010] One aspect of the present disclosure is to provide a multi-layer electronic component having a compact structure and excellent capacitance.

[0011] However, aspects of the present disclosure are not limited to the above, and can be more easily understood during the process of describing specific embodiments of the present disclosure.

[0012] A multilayer electronic component according to an exemplary embodiment of the present disclosure may include: a body including a plurality of capacitor-forming portions and an intermediate layer, the plurality of capacitor-forming portions including a first dielectric layer and an inner electrode alternately arranged in a first direction, the intermediate layer being disposed between adjacent capacitor-forming portions and including a second dielectric layer, and the body including a first surface and a second surface facing each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and facing each other in a second direction, and a fifth surface and a sixth surface connected to the first surface to the fourth surface and facing each other in a third direction; and an external electrode disposed on the body and connected to the inner electrode, and the first dielectric layer and the second dielectric layer may include a plurality of grains and pores, and an average grain size of the first dielectric layer may be smaller than an average grain size of the second dielectric layer, and a porosity of the first dielectric layer may be lower than a porosity of the second dielectric layer.

[0013] A multilayer electronic component according to an exemplary embodiment of the present disclosure may include: a first capacitor-forming portion and a second capacitor-forming portion, each including a first inner electrode and a second inner electrode, a first dielectric layer being disposed between the first inner electrode and the second inner electrode; and an intermediate layer including a second dielectric layer disposed between the first capacitor-forming portion and the second capacitor-forming portion, wherein an average grain size of the first dielectric layer is smaller than an average grain size of the second dielectric material, and a ratio of an average thickness t1 of the intermediate layer to an average thickness td of the first dielectric layer is greater than or equal to 7.

[0014] One of the various effects of the present disclosure is to provide a multilayer electronic component having excellent reliability.

[0015] One of the various effects of the present disclosure is to provide a multilayer electronic component configured to suppress shape deformation defects of the body.

[0016] One of the various effects of the present disclosure is to provide a multilayer electronic component having a compact structure and excellent capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a schematic perspective view of a multilayer electronic component according to an exemplary embodiment of the present disclosure; Figure 2 is along Figure 1 sectional view taken along line I-I'; Figure 3 is a cross-sectional view taken along line II-II' of Figure 1 ; Figure 4 is an exploded perspective view schematically showing a main body of a multi-layer electronic component; Figure 5 is Figure 3 an enlarged view of region K1 of Figure 6 is Figure 3 an enlarged view of region K2 of Figure 7 a cross-sectional view showing deformation of the main body; and Figure 8 is a view corresponding to Figure 2 of a multi-layer electronic component according to another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to specific exemplary embodiments and the drawings. However, the exemplary embodiments of the present disclosure can be illustrated in many different forms and should not be construed as being limited to the specific embodiments set forth herein. The exemplary embodiments disclosed herein are provided to better explain the present disclosure to those skilled in the art. Therefore, in the drawings, for clarity, the shapes and sizes of elements may be exaggerated, and the same reference numerals will always be used to denote the same elements.

[0019] In addition, to clearly describe the present disclosure in the drawings, content unrelated to the description is omitted, and since the dimensions (e.g., thickness) of each component shown in the drawings are arbitrarily shown for ease of description, the present disclosure is not limited thereto. In addition, for components having the same function within the same concept range, the same reference numerals are used for description. Throughout the specification, when a certain component "includes" or "comprises" another component, unless otherwise stated, it means that other components are not excluded and other components may be further included.

[0020] In the drawings, the first direction may be defined as the thickness direction, the second direction may be defined as the length direction, and the third direction may be defined as the width direction.

[0021] Figure 1 is a schematic perspective view of a multi-layer electronic component according to an exemplary embodiment of the present disclosure.

[0022] Figure 2 is taken along Figure 1 line I-I' of

[0023] Figure 3 is taken along Figure 1 line II-II' of

[0024] Figure 4 is an exploded perspective view schematically showing a main body of a multilayer electronic component.

[0025] Figure 5 is Figure 3 an enlarged view of region K1 of

[0026] Figure 6 is Figure 3 an enlarged view of region K2 of

[0027] Referring to Figures 1 to 6 FIG. 18, a multilayer electronic component 100 according to an exemplary embodiment of the present disclosure may include: a main body 110 including a plurality of capacitor forming portions Ac1 and Ac2 and an intermediate layer 140, the capacitor forming portions Ac1 and Ac2 including first dielectric layers 111 and inner electrodes 121 and 122 alternately arranged in a first direction, the intermediate layer 140 being disposed between adjacent capacitor forming portions Ac1 and Ac2 and including a second dielectric layer 112, and the main body 110 including a first surface 1 and a second surface 2 opposite to each other in the first direction, a third surface 3 and a fourth surface 4 connected to the first surface and the second surface and opposite to each other in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first surface to the fourth surface and opposite to each other in a third direction; and outer electrodes 131 and 132 disposed on the main body and connected to the inner electrodes, and the first dielectric layer and the second dielectric layer including a plurality of grains G1 and G2 and holes P1 and P2, and an average grain size of the first dielectric layer being smaller than an average grain size of the second dielectric layer, and a porosity of the first dielectric layer may be smaller than a porosity of the second dielectric layer.

[0028] As described above, since a high-profile ceramic capacitor (HPCC) product that realizes a high stacking number by increasing the thickness of a multilayer electronic component has a structure in which its thickness T is larger than its width W, compared with a general MLCC having the same width and thickness, the HPCC product can increase the stacking number, thereby easily realizing a high capacitance.

[0029] However, since the HPCC has a structure in which the thickness T is larger than the width W, there may be a problem that the sheet shape may be easily deformed due to stress generated during the pressing and cutting processes. Therefore, there is a limit to increasing the stacking number to a level greater than or equal to a specific number.

[0030] On the other hand, the multi-layer electronic component 100 according to an exemplary embodiment of the present disclosure may include an intermediate layer 140 disposed between adjacent capacitance forming portions Ac1 and Ac2 and including a second dielectric layer 112, and the average grain size of the first dielectric layer included in the capacitance forming portions Ac1 and Ac2 may be smaller than the average grain size of the second dielectric layer 112, and the porosity of the first dielectric layer 111 may be smaller than the porosity of the second dielectric layer 112, thereby suppressing defects in the shape deformation of the main body and further increasing the number of stacked layers.

[0031] Hereinafter, each component included in the multi-layer electronic component 100 according to an exemplary embodiment of the present disclosure will be described.

[0032] There is no particular limitation on the specific shape of the main body 110, but as Figure 1 shown, the main body 110 may have a hexahedron shape or a shape similar thereto. Due to the shrinkage of the ceramic powder particles included in the main body 110 during the sintering process, the main body 110 may not have a completely straight hexahedron shape, but may have a substantially hexahedron shape.

[0033] The main body 110 may have a first surface 1 and a second surface 2 that are opposite to each other in a first direction, a third surface 3 and a fourth surface 4 that are connected to the first surface 1 and the second surface 2 and are opposite to each other in a second direction, and a fifth surface 5 and a sixth surface 6 that are connected to the first surface to the fourth surface and are opposite to each other in a third direction.

[0034] The main body 110 may include a plurality of capacitance forming portions Ac1 and Ac2, in which capacitances are formed by including first dielectric layers 111 alternately arranged in a first direction and inner electrodes 121 and 122. The adjacent capacitance forming portions Ac1 and Ac2 may be arranged in the first direction. For example, the intermediate layer 140 is interposed therebetween.

[0035] In a state where the first dielectric layers 111 forming the capacitance forming portions Ac1 and Ac2 are sintered, the adjacent first dielectric layers 111 may be integrated so that it is difficult to identify the boundary therebetween without using a scanning electron microscope (SEM).

[0036] The first dielectric layer 111 may be formed by preparing a ceramic slurry containing ceramic powder particles, an organic solvent, and a binder, coating and drying the ceramic slurry on a carrier film to prepare a green sheet, and then sintering the green sheet. There is no particular limitation on the ceramic powder particles as long as sufficient electrostatic capacitance can be obtained therefrom. For example, barium titanate (BaTiO3)-based powder particles may be used as the ceramic powder particles. For a more specific example, the ceramic powder particles may be BaTiO3, (Ba 1-x Ca x)TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1) and Ba(Ti 1-y Zr y )O3 (0 < y < 1) or more of them.

[0037] The average thickness td of the first dielectric layer 111 is not particularly limited. For example, the average thickness td of the first dielectric layer 111 can be from 0.1 μm to 10 μm. Additionally, the average thickness td of the first dielectric layer 111 can be from 0.1 μm to 0.6 μm to achieve miniaturization and high capacitance of the multilayer electronic component.

[0038] Here, the average thickness td of the first dielectric layer 111 can refer to the average thickness of the first dielectric layer 111 disposed between the inner electrodes 121 and 122. The average thickness td of the first dielectric layer 111 can be measured by scanning images of the cross-sections of the main body 110 in the first direction and the second direction with a scanning electron microscope (SEM) at a magnification of 10,000 times. More specifically, the average thickness td of the first dielectric layer 111 can be obtained by measuring its thickness at multiple points (e.g., 30 points equally spaced from each other in the second direction) of one first dielectric layer 111 in the scanned image and calculating their average value. Thirty points equally spaced from each other can be specified in the capacitance forming portions Ac1 and Ac2. Additionally, when the average value measurement is extended to 10 first dielectric layers 111 to calculate the average value, the average thickness of the first dielectric layer 111 can be further generalized.

[0039] The inner electrodes 121 and 122 can be alternately arranged with the first dielectric layer 111, and can be arranged, for example, in such a way that a pair of electrodes (the first inner electrode 121 and the second inner electrode 122) with different polarities face each other and the first dielectric layer 111 is interposed therebetween. The plurality of first inner electrodes 121 and the plurality of second inner electrodes 122 can be electrically isolated from each other by the first dielectric layer 111 interposed therebetween.

[0040] The inner electrodes 121 and 122 can be spaced apart from the fifth surface 5 and the sixth surface 6 of the main body 110, and can be connected to the third surface 3 or the fourth surface 4. For example, the plurality of first inner electrodes 121 can be respectively spaced apart from the fourth surface 4, the fifth surface 5, and the sixth surface 6, and can be exposed to the third surface 3. Additionally, the plurality of second inner electrodes 122 can be respectively spaced apart from the third surface 3, the fifth surface 5, and the sixth surface 6, and can be exposed to the fourth surface 4.

[0041] The conductive metal included in the internal electrodes 121 and 122 may be one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and their alloys, and the present disclosure is not limited thereto.

[0042] The internal electrodes 121 and 122 can be formed by coating a conductive paste for the internal electrode including a conductive metal on a green ceramic sheet with a predetermined thickness and sintering the conductive paste. Additionally, the capacitor forming portions Ac1 and Ac2 can be formed by stacking and sintering green ceramic sheets coated with the conductive paste for the internal electrode. The method of printing the conductive paste for the internal electrode can use a screen printing method or a gravure printing method, and the present disclosure is not limited thereto.

[0043] The average thickness of the internal electrodes 121 and 122 does not need to be particularly limited. In this case, the thickness of the internal electrodes 121 and 122 can represent the dimension of the internal electrodes 121 and 122 in the first direction. For example, the average thickness of the internal electrodes 121 and 122 can be 0.1 μm to 5 μm. Additionally, in order to achieve miniaturization and high capacitance of the multilayer electronic component, the average thickness of the internal electrodes 121 and 122 can be 0.1 μm to 0.8 μm.

[0044] Here, the average thickness of the internal electrodes 121 and 122 can be measured by scanning the cross-sections of the main body 110 in the first direction and the second direction with a scanning electron microscope (SEM) at a magnification of 10,000 times. More specifically, the average thickness of the internal electrodes 121 and 122 can be obtained by measuring the thicknesses at multiple points (e.g., 30 points equally spaced from each other in the second direction) of one of the internal electrodes 121 or 122 in the scanned image and calculating their average value. Thirty points equally spaced from each other can be specified in the capacitor forming portions Ac1 and Ac2. Additionally, when the average value measurement is extended to 10 internal electrodes 121 and 122 to calculate the average value, the average thickness of the internal electrodes 121 and 122 can be further generalized.

[0045] The main body 110 may include cover portions 113 and 114 provided on the internal electrodes 121 and 122 disposed in the outermost portions based on the first direction. For example, the cover portions 113 and 114 may include a first cover portion 113 and a second cover portion 114. The first cover portion 113 is provided on the internal electrode 121 or 122 disposed in the uppermost portion based on the first direction, and the second cover portion 114 is provided on the internal electrode 121 or 122 disposed in the lowermost portion based on the first direction. The cover portions 113 and 114 can be mainly used to prevent damage to the internal electrodes due to physical stress or chemical stress. Except that the cover portions 113 and 114 do not include internal electrodes, the cover portions 113 and 114 can have the same structure as the first dielectric layer 111.

[0046] The average thickness tc of the cover parts 113 and 114 does not need to be particularly limited. However, in order to achieve miniaturization and high capacitance of the multilayer electronic component 100, the average thickness tc of the cover parts 113 and 114 can be less than or equal to 20 μm. Here, the average thickness tc of the cover parts 113 and 114 refers to the average thickness of each of the first cover part 113 and the second cover part 114.

[0047] The average thickness tc of the cover parts 113 and 114 can refer to the average dimension of the cover parts 113 and 114 in the first direction, and can be the average value of the first direction dimensions measured at five points that are equally spaced from each other in the second direction in the cross-sections of the main body 110 in the first direction and the second direction.

[0048] The main body 110 can include edge parts 115 and 116 provided on two surfaces of the capacitance forming parts Ac1 and Ac2 in the third direction. That is to say, the edge parts 115 and 116 can refer to the regions between the two ends of the inner electrodes 121 and 122 in the third direction and the outer surface of the main body 110 in the cross-section obtained by cutting the main body 110 in the first direction and the third direction. In this case, the edge parts 115 and 116 can include a first edge part 115 provided on one surface of the capacitance forming parts Ac1 and Ac2 in the third direction and a second edge part 116 provided on the other surface of the capacitance forming parts Ac1 and Ac2 in the third direction.

[0049] Except that the edge parts 115 and 116 do not include the inner electrodes 121 and 122, the edge parts 115 and 116 can include the same material as the material of the first dielectric layer 111 of the capacitance forming parts Ac1 and Ac2.

[0050] The edge parts 115 and 116 can be mainly used to prevent damage to the inner electrodes 121 and 122 due to physical stress or chemical stress.

[0051] The edge parts 115 and 116 can be formed by not coating the conductive paste for the inner electrodes in the regions outside the regions on the green sheet where the inner electrodes are to be formed.

[0052] The average thickness of the edge parts 115 and 116 does not need to be particularly limited. However, in order to achieve miniaturization and high capacitance of the multilayer electronic component 100, the average thickness of the edge parts 115 and 116 can be less than or equal to 20 μm. Here, the average thickness of the edge parts 115 and 116 refers to the average thickness of each of the first edge part 115 and the second edge part 116.

[0053] The average thickness of the edge portions 115 and 116 may refer to the average dimension of the edge portions 115 and 116 in the third direction, and may be a value obtained by averaging the third-direction dimensions measured at five points that are equally spaced from each other in the first direction in a cross-section of the main body 110 in the first and third directions.

[0054] The outer electrodes 131 and 132 may be provided on the third surface 3 and the fourth surface 4 of the main body 110, and may extend to a part of each of the first surface 1, the second surface 2, the fifth surface 5, and the sixth surface 6. The outer electrodes 131 and 132 may include a first outer electrode 131 and a second outer electrode 132 that are respectively connected to a plurality of first inner electrodes 121 and a plurality of second inner electrodes 122.

[0055] The outer electrodes 131 and 132 may be formed of any material as long as the outer electrodes have conductivity (such as a metal), and the specific material may be determined considering electrical characteristics, structural stability, etc., and the outer electrodes 131 and 132 may further have a multilayer structure. For example, the outer electrodes 131 and 132 may include a conductive metal, and the conductive metal included in the outer electrodes 131 and 132 may include copper (Cu), nickel (Ni), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), lead (Pb), and / or an alloy including copper (Cu), nickel (Ni), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), lead (Pb).

[0056] The outer electrodes 131 and 132 may include a first electrode layer 131a and 132a provided on the third surface 3 and the fourth surface 4 of the main body 110 and connected to the inner electrodes 121 and 122, and a second electrode layer 131b and 132b provided on the first electrode layer 131a and 132a.

[0057] The first electrode layer 131a and 132a may be formed by dipping the third surface 3 and the fourth surface 4 of the main body 110 into a conductive paste for the outer electrode including a conductive metal and glass and then sintering the conductive paste. Alternatively, the first electrode layer 131a and 132a may be formed by transferring a sheet including a conductive metal and glass. Therefore, the first electrode layer 131a and 132a may be a sintered electrode including a conductive metal and glass.

[0058] In addition, the first electrode layer 131a and 132a may be, for example, a resin-based electrode including a conductive metal and a resin. The first electrode layer 131a and 132a may be formed by coating and curing a paste including a conductive metal and a resin.

[0059] The conductive metals included in the first electrode layers 131a and 132a may include copper (Cu), nickel (Ni), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), lead (Pb), and / or alloys including copper (Cu), nickel (Ni), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), lead (Pb), but the present disclosure is not limited thereto.

[0060] The second electrode layers 131b and 132b may improve the mounting characteristics. The types of the second electrode layers 131b and 132b are not particularly limited, and the second electrode layers 131b and 132b may be plating layers including nickel (Ni), tin (Sn), palladium (Pd), and / or alloys including (Ni), tin (Sn), palladium (Pd), and may be formed of multiple layers. The second electrode layers 131b and 132b may be, for example, nickel (Ni) plating layers or tin (Sn) plating layers, and may have a form in which the nickel (Ni) plating layer and the tin (Sn) plating layer are formed in sequence. Additionally, the second electrode layers 131b and 132b may include multiple nickel (Ni) plating layers and / or multiple tin (Sn) plating layers.

[0061] The drawings illustrate a structure in which the multilayer electronic component 100 has two external electrodes 131 and 132, but the present disclosure is not limited thereto, and the number or shape of the external electrodes may be changed according to the shape of the internal electrodes or other purposes.

[0062] The multilayer electronic component 100 according to an exemplary embodiment of the present disclosure may include an intermediate layer 140 disposed between adjacent capacitance forming portions Ac1 and Ac2 and including a second dielectric layer 112, and the average grain size of the first dielectric layer included in the capacitance forming portions Ac1 and Ac2 may be smaller than the average grain size of the second dielectric layer 112, and the porosity of the first dielectric layer 111 may be smaller than the porosity of the second dielectric layer 112.

[0063] The intermediate layer 140 may be used to disperse the stress generated during the pressing and cutting processes of the stacked body, thereby suppressing the shape deformation of the main body. Since the intermediate layer 140 may have a smaller capacitance contribution than the first dielectric layer 111, the capacitance of the multilayer electronic component 100 may be lower than that of a multilayer electronic component having the same thickness and not having the intermediate layer 140. However, since the main body 110 includes the intermediate layer 140, the shape deformation of the main body may be suppressed, so that the number of stacked layers may be increased, and since the thickness of the main body may be made thicker, it may be easier to ensure a high capacitance.

[0064] Refer to Figure 5 and Figure 6 , Figure 5 illustrates the microstructure of the first dielectric layer 111, Figure 6The microstructure of the second dielectric layer 112 is shown. The first dielectric layer 111 may include a plurality of first grains G1 and first holes P1, and the second dielectric layer 112 may include a plurality of second grains G2 and second holes P2. The average size of the first grains G1 of the first dielectric layer 111 may be smaller than the average size of the second grains G2 of the second dielectric layer 112, and the porosity of the first dielectric layer 111 may be lower than the porosity of the second dielectric layer 112, such that the intermediate layer 140 can be used to disperse the stress generated during the pressing and cutting processes of the stack.

[0065] When the average grain size of the first dielectric layer 111 is defined as Gs1 and the average grain size of the second dielectric layer 112 is defined as Gs2, Gs2 / Gs1 does not need to be specifically limited. However, when 1.05 < Gs2 / Gs1 < 1.50 is satisfied, the stress dispersion effect of the intermediate layer 140 can be further improved to further suppress the deformation phenomenon of the main body, and the number of stacked layers can be increased while minimizing the capacitance reduction caused by the intermediate layer 140, so it is more beneficial to ensure a high capacitance.

[0066] When the porosity of the first dielectric layer 111 is defined as Ps1 and the porosity of the second dielectric layer 112 is defined as Ps2, Ps2 / Ps1 does not need to be specifically limited. However, when 1.05 < Ps2 / Ps1 < 1.40 is satisfied, the stress dispersion effect of the intermediate layer 140 can be further improved, such that the deformation phenomenon of the main body can be further suppressed, and the number of stacked layers can be increased while minimizing the capacitance reduction caused by the intermediate layer 140, thereby being more beneficial to ensure a high capacitance.

[0067] The average grain size and porosity can be measured by analyzing images of cross-sectional scans in the first and second directions cut from the center of the third direction of the main body at a magnification of 50,000 times using a SEM manufactured by ZEISS. The Feret diameter of the grains can be measured from the scanned images using Zootos, a grain size measurement software, to obtain the average size of each of the grains G1 and G2. Additionally, since there are significant differences in brightness between the grains G1 and G2 and the holes P1 and P2, the area ratio of the holes P1 in the first dielectric layer 111 and the area ratio of the holes P2 in the second dielectric layer 112 can be measured from the scanned images of the SEM using an image analysis program to obtain their respective porosities.

[0068] The second dielectric layer 112 can be formed by fabricating a ceramic slurry including ceramic powder particles, an organic solvent, and a binder, coating and drying the ceramic slurry on a carrier film to prepare a green ceramic sheet, and then sintering the green ceramic sheet. There is no particular limitation on the ceramic powder particles as long as sufficient electrostatic capacitance can be obtained using them. For example, barium titanate (BaTiO3) powder particles can be used as the ceramic powder particles. For more specific examples, the ceramic powder particles can be one or more of BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), and Ba(Ti 1-y Zr y )O3 (0 < y < 1). Additionally, there is no particular limitation on the method for controlling the average grain size and porosity of the first dielectric layer 111 and the second dielectric layer 112. For example, the binder content included in the green ceramic sheet for forming the second dielectric layer 112 can be made higher than the binder content included in the green ceramic sheet for forming the first dielectric layer 111 to control the porosity. Additionally, the size of the dielectric powder particles included in the green ceramic sheet for forming the second dielectric layer 112 can be made larger than the size of the dielectric powder particles included in the green ceramic sheet for forming the first dielectric layer 111 to control the average grain size. However, the present disclosure is not limited thereto, and the average grain size and porosity of the first dielectric layer and the second dielectric layer can be controlled by changing the additive content, the type of ceramic powder particles, etc.

[0069] The intermediate layer 140 can be formed by stacking one or more layers of the second dielectric layer 112. The intermediate layer 140 can be formed by stacking and sintering one or more green ceramic sheets for forming the second dielectric layer.

[0070] More specifically, one or more green ceramic sheets for forming the first dielectric layer can be stacked to form the second cover portion 114, and a plurality of green ceramic sheets for forming the first dielectric layer coated with a conductive paste for the inner electrode can be stacked to form the second capacitor forming portion Ac2. Then, one or more green ceramic sheets for forming the second dielectric layer can be stacked to form the intermediate layer 140. Then, a plurality of green ceramic sheets for forming the first dielectric layer coated with a conductive paste for the inner electrode can be stacked to form the first capacitor forming portion Ac1, and one or more green ceramic sheets for forming the first dielectric layer can be stacked to form the first cover portion 113, thereby preparing a stacked body.

[0071] In an exemplary embodiment, when the average thickness of the main body in the first direction is defined as T and the average thickness of the intermediate layer in the first direction is defined as t1, 0.0002 < t1 / T ≤ 0.06 can be satisfied. Accordingly, the stress dispersion effect of the intermediate layer 140 can be further improved to further suppress the deformation phenomenon of the main body, and the number of stacked layers can be increased while minimizing the capacitance reduction caused by the intermediate layer 140, which is more conducive to ensuring a high capacitance. The average thickness of the main body may be the average distance Ta between the top surface of the upper cover portion and the bottom surface of the lower cover portion.

[0072] In an exemplary embodiment, the outer electrodes 131 and 132 may include a first outer electrode and a second outer electrode respectively disposed on the third surface and the fourth surface, and the inner electrodes 121 and 122 may include a first inner electrode 121 connected to the first outer electrode 131 on the third surface and a second inner electrode 122 connected to the second outer electrode 132 on the fourth surface.

[0073] In an exemplary embodiment, when the average thickness of the main body 110 in the first direction is defined as T and the distance from the point where the extension line E6 of the sixth surface meets the extension line E1 of the first surface to the point where the extension line E6 of the sixth surface meets the extension line E2 of the second surface is defined as Tr, 0.996 ≤ T / Tr ≤ 1 can be satisfied. In the case where T / Tr is less than 0.996, it may be difficult to increase the number of stacked layers. Additionally, although T / Tr being 1 is ideal, when considering errors in the manufacturing process, etc., 0.996 ≤ T / Tr < 1 can be satisfied.

[0074] Referring to Figure 7 , a cross-sectional view showing the deformation of the main body, the thickness of the main body 110 in the first direction may be the length of the vertical line segment from the extension line E1 of the first surface to the extension line E2 of the second surface. And Tr may be the length of the line segment from the point where the extension line E6 of the sixth surface intersects the extension line E1 of the first surface to the point where the extension line E6 of the sixth surface intersects the extension line E2 of the second surface.

[0075] In an exemplary embodiment, when the average thickness of the main body in the first direction is defined as T, the average length of the main body in the second direction is defined as L, and the average width of the main body in the third direction is defined as W, L > T > W can be satisfied. Accordingly, the capacitance of the multi-layer electronic component can be easily improved.

[0076] The size of the multilayer electronic component does not need to be particularly limited. However, generally, as the size of the multilayer electronic component decreases, the possibility of the main body deformation phenomenon increases. According to the present disclosure, when the intermediate layer is provided between the capacitor forming portions, even if the multilayer electronic component is compact, the deformation phenomenon of the main body can be effectively suppressed. Specifically, the effect of suppressing the deformation phenomenon of the main body according to the present disclosure can be significant in a chip of 0603 size or smaller. Therefore, in an exemplary embodiment, when the average thickness of the main body in the first direction is defined as T, the average length of the main body (capacitor forming portion) in the second direction is defined as L, and the average width of the main body (capacitor forming portion) in the third direction is defined as W, T>W, T≤0.55 mm, L≤0.66 mm, and W≤0.33 mm can be satisfied.

[0077] T and W can be measured in the first direction and third direction cross-sections cut from the center of the second direction of the main body. The average value of the first direction dimensions of the main body measured at five points spaced apart from each other at equal intervals in the third direction can be defined as T, and the average value of the third direction dimensions of the main body measured at five points spaced apart from each other at equal intervals in the first direction can be defined as W. L can be measured in the first direction and second direction cross-sections cut from the center of the third direction of the main body. The average value of the second direction dimensions of the main body measured at five points spaced apart from each other at equal intervals in the first direction can be defined as L.

[0078] In an exemplary embodiment, when the average thickness of the main body in the first direction is defined as T and the average width of the main body in the third direction is defined as W, 1.1<T / W<1.8 can be satisfied. When T / W is less than or equal to 1.1, it may be difficult to ensure a high capacitance. When T / W is greater than or equal to 1.8, the thickness of the main body may increase significantly relative to its width, making it difficult to mount the multilayer electronic component on the substrate.

[0079] In an exemplary embodiment, the main body 110 includes cover portions 113 and 114 provided on the inner electrodes disposed at the outermost portions based on the first direction. When the average thickness of the intermediate layer 140 is defined as t1, the average thickness of the cover portions 113 and 114 is defined as tc, and the average thickness of the first dielectric layer 111 is defined as td, td<tc<t1 can be satisfied.

[0080] In addition, in an exemplary embodiment, when the average thickness of the intermediate layer 140 is defined as t1 and the average thickness of the first dielectric layer 111 is defined as td, 7≤t1 / td can be satisfied. The upper limit of t1 / td does not need to be particularly limited and can be, for example, 100 or less. Therefore, the stress dispersion effect of the intermediate layer 140 can be further improved to further suppress the deformation phenomenon of the main body, and the number of stacked layers can be increased while minimizing the capacitance reduction caused by the intermediate layer 140, which is more beneficial for ensuring a high capacitance.

[0081] The average thickness t1 of the intermediate layer 140 may refer to the average dimension of the intermediate layer 140 in the first direction. The thickness of the intermediate layer 140 may refer to the first-direction distance between the two inner electrodes 121 and 122 closest to the intermediate layer 140. Additionally, the average thickness t1 of the intermediate layer 140 may be the average of the first-direction dimensions measured at five points spaced equidistantly from each other in the second direction in an image of a cross-section of the main body 110 in the first and second directions measured by a scanning electron microscope (SEM). Additionally, when multiple intermediate layers 140 are provided, the average thickness t1 may refer to the average thickness of each of the multiple intermediate layers 140.

[0082] Figure 8 is a diagram corresponding to a multi-layer electronic component according to another exemplary embodiment of the present disclosure Figure 2 of.

[0083] Referring to Figure 8 , the main body 210 of the multi-layer electronic component 200 according to another exemplary embodiment of the present disclosure may include three capacitance-forming portions Ac1, Ac2, and Ac3 and two intermediate layers 140' provided between the adjacent capacitance-forming portions Ac1, Ac2, and Ac3.

[0084] In the exemplary embodiment, the number of the multiple capacitance-forming portions Ac1, Ac2, and Ac3 may be three or more, and the number of the intermediate layers 140' may be two or more. There is no particular limitation on the upper limit of the number of the intermediate layers 140', and it may be, for example, ten or less.

[0085] In the exemplary embodiment, the multiple capacitance-forming portions Ac1, Ac2, and Ac3 may be provided in the first direction.

[0086] In the case of the multi-layer electronic component 200 according to another exemplary embodiment of the present disclosure, since multiple intermediate layers 140' are provided, the stress distribution effect may be further improved through the intermediate layers 140', thereby further suppressing the deformation of the main body.

[0087] Although the exemplary embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above embodiments and drawings, but is limited by the appended claims. Therefore, those of ordinary skill in the art may make various substitutions, modifications, or changes without departing from the scope of the present disclosure defined by the appended claims, and these substitutions, modifications, or changes should be construed as being included within the scope of the present disclosure.

[0088] In addition, the expression "exemplary embodiment" used in this disclosure does not denote the same embodiment and is provided to emphasize and explain different unique features. However, the embodiments presented above do not preclude the implementation in combination with the features of another embodiment. For example, although an item described in a particular embodiment is not described in another embodiment, unless there is a description in the other embodiment that is contrary to or inconsistent with that item, that item can be understood as being related to the description in the other embodiment.

Claims

1. A multilayer electronic component comprising: a body including a plurality of capacitance forming parts and an intermediate layer, the plurality of capacitance forming parts including first dielectric layers and inner electrodes alternately arranged in a first direction, the intermediate layer being provided between adjacent capacitance forming parts and including a second dielectric layer, and the body including a first surface and a second surface opposite to each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in the second direction, and a fifth surface and a sixth surface connected to the first surface to the fourth surface and opposite to each other in a third direction; as well as an outer electrode disposed on the body and connected to the inner electrode, wherein the first dielectric layer and the second dielectric layer include a plurality of grains and holes, and An average grain size of the first dielectric layer is smaller than an average grain size of the second dielectric layer, and a porosity of the first dielectric layer is lower than a porosity of the second dielectric layer.

2. The multilayer electronic component according to claim 1, wherein When the average grain size of the first dielectric layer is defined as Gs1 and the average grain size of the second dielectric layer is defined as Gs2, 1.05<Gs2 / Gs1<1.50 is satisfied.

3. The multilayer electronic component according to claim 1, wherein: When the porosity of the first dielectric layer is defined as Ps1 and the porosity of the second dielectric layer is defined as Ps2, 1.05 is satisfied. <Ps2 / Ps1<1.40。 4. The multilayer electronic component according to claim 1, wherein: When the average thickness of the main body in the first direction is defined as T and the average thickness of the intermediate layer in the first direction is defined as t1, 0.0002 is satisfied. <t1 / T≤0.06。 5. The multilayer electronic component according to claim 1, wherein The external electrodes include first and second external electrodes disposed on the third surface and the fourth surface, respectively, and The internal electrodes include a first internal electrode connected to the first external electrode on the third surface, and a second internal electrode connected to the second external electrode on the fourth surface.

6. The multilayer electronic component according to claim 5, wherein: When the average thickness of the body in the first direction is defined as T and the distance from the point where the extension line of the fifth surface intersects with the extension line of the first surface to the point where the extension line of the fifth surface intersects with the extension line of the second surface is defined as Tr, Satisfies 0.996≤T / Tr≤1.

7. The multilayer electronic component according to claim 6, wherein: T and Tr satisfy 0.996≤T / Tr<1.

8. The multilayer electronic component according to any one of claims 1 to 5, wherein: When the average thickness of the body in the first direction is defined as T, the average length of the body in the second direction is defined as L, and the average width of the body in the third direction is defined as W, Satisfies L>T>W.

9. The multilayer electronic component according to any one of claims 1 to 5, wherein: When the average thickness of the body in the first direction is defined as T, the average length of the body in the second direction is defined as L, and the average width of the body in the third direction is defined as W, Satisfy T>W, T≤0.55mm, L≤0.66mm and W≤0.33mm.

10. The multilayer electronic component according to any one of claims 1 to 5, wherein: When the average thickness of the body in the first direction is defined as T and the average width of the body in the third direction is defined as W, Satisfies 1.1<T / W<1.

8.

11. The multilayer electronic component according to claim 1, wherein The main body includes a cover portion provided on an inner electrode disposed at the outermost portion in the first direction, and when the average thickness of the intermediate layer is defined as t1, the average thickness of the cover portion is defined as tc, and the average thickness of the first dielectric layer is defined as td, td < tc < t1 is satisfied.

12. The multilayer electronic component according to claim 1, wherein When the average thickness of the intermediate layer is defined as t1 and the average thickness of the first dielectric layer is defined as td, 7 ≤ t1 / td is satisfied.

13. The multilayer electronic component according to claim 1, wherein The number of the plurality of capacitor forming portions is three or more, and the number of the intermediate layers is two or more.

14. The multilayer electronic component according to claim 13, wherein: The plurality of capacitor forming portions are arranged in the first direction.

15. A multilayer electronic component, comprising: a first capacitor forming portion and a second capacitor forming portion, each including a first inner electrode and a second inner electrode, with a first dielectric layer disposed between the first inner electrode and the second inner electrode; and an intermediate layer including a second dielectric layer, disposed between the first capacitor forming portion and the second capacitor forming portion, wherein the average grain size of the first dielectric layer is smaller than the average grain size of the second dielectric layer, and the ratio of the average thickness t1 of the intermediate layer to the average thickness td of the first dielectric layer is greater than or equal to 7.

16. The multilayer electronic component according to claim 15, wherein The first capacitor forming portion is disposed above the second capacitor forming portion in the thickness direction, and the intermediate layer is interposed between the first capacitor forming portion and the second capacitor forming portion, wherein the multilayer electronic component further includes an upper cover portion disposed above the first capacitor forming portion in the thickness direction and a lower cover portion disposed below the second capacitor forming portion, and wherein the average thickness tc of the upper cover portion and the lower cover portion satisfies td < tc < t1.

17. The multilayer electronic component according to claim 16, wherein: The average distance Ta between the top surface of the upper cover portion and the bottom surface of the lower cover portion is greater than the width W of the capacitor forming portion and less than the length L of the capacitor forming portion.

18. The multilayer electronic component according to claim 17, wherein: 1.1 < Ta / W < 1.

8.

19. The multilayer electronic component according to claim 16, the multilayer electronic component further comprising: a first outer electrode contacting the first inner electrode and spaced apart from the second inner electrode in the length direction; and a second outer electrode contacting the second inner electrode and spaced apart from the first inner electrode in the length direction.

20. The multilayer electronic assembly of claim 16, wherein: 0.0002 < t1 / Ta ≤ 0.06, wherein Ta is the average distance between the top surface of the upper cover portion and the bottom surface of the lower cover portion.

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