Suppression of dopant hydride precipitation in epitaxial films in integrated circuit (IC) fabrication

Abstract

Embodiments of the present disclosure relate to suppression of dopant hydride precipitation in epitaxial films in integrated circuit (IC) fabrication. A method of fabricating an integrated circuit (IC) (400) device is disclosed. A doped epitaxial layer (404) may be formed over a substrate (402), including forming a surface segregation layer (SSL) (406) including a dopant species that is not incorporated into the doped epitaxial layer (404). Thereafter, the SSL (406) may be removed in an in-situ operation, where a portion of the doped epitaxial layer (404) may be removed based on removal selectivity.

Description

Technical Field

[0001] The disclosed embodiments generally relate to the field of integrated circuits (ICs) and IC manufacturing. More specifically, but not exclusively, the disclosed embodiments relate to an IC device that includes one or more doped epitaxial films that inhibit dopant hydride precipitation. Background Art

[0002] Epitaxy is used in semiconductor manufacturing to create a suitable crystalline base layer on which semiconductor devices are built, to deposit crystalline films with engineered electrical properties, and / or to modify the mechanical properties of the underlying layer in a way that improves the underlying conductivity. In some cases, the epitaxial layer can be doped during deposition by adding impurities to the source gas in order to obtain the desired electrical properties of the epitaxial layer. Summary of the Invention

[0003] A simplified summary is presented below in order to provide a basic understanding of some examples of the present disclosure. This summary of the invention is not an extensive overview of the examples and is not intended to identify key or critical elements of the examples or to delineate their scope. Indeed, the primary purpose of the summary of the invention is to present some concepts of the present disclosure in a simplified form as a prelude to the more detailed description presented later in this document.

[0004] In one example, a method of manufacturing an IC device is disclosed. The method can particularly include: placing a semiconductor substrate in a working volume of a semiconductor processing tool; forming a doped epitaxial layer over the semiconductor substrate, including forming a surface segregation layer (SSL) that includes dopant species not incorporated into the doped epitaxial layer; removing the SSL; and removing the semiconductor substrate from the working volume. In some arrangements, the SSL can be removed using a selective etching process. In some arrangements, the SSL can be removed using a non-selective etching process.

[0005] In one example, an IC device is disclosed that can particularly include: a semiconductor substrate; a doped epitaxial layer over the semiconductor substrate, the doped epitaxial layer having a first dopant concentration; and a surface conditioning layer over the doped epitaxial layer, the surface conditioning layer including silicon or germanium having a second dopant concentration less than the first dopant concentration.

[0006] In one example, an IC manufacturing tool is disclosed, which may particularly include: at least one main chamber; a first processing chamber coupled to the at least one main chamber; and the first processing chamber is configured to form a doped epitaxial layer over a substrate, wherein the first processing chamber may also be configured to remove a surface segregation layer (SSL) formed over the doped epitaxial layer, wherein the SSL may contain unincorporated dopant atoms. In another variant, the IC manufacturing tool may include a separate processing chamber (e.g., a second processing chamber) coupled to the at least one main chamber, wherein the second processing chamber may be configured to remove the SSL using a series of etching chemistries. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the figures of the drawings, embodiments of the present disclosure are illustrated by way of example and not limitation. Different references to "an" or "one" embodiment in the present disclosure do not necessarily refer to the same embodiment, and such references may mean at least one. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, such feature, structure, or characteristic is operable in connection with other embodiments whether or not explicitly described.

[0008] To illustrate one or more exemplary embodiments of the present disclosure, the drawings are incorporated into and form a part of the specification. The various advantages and features of the present disclosure will be understood from the following detailed description taken in conjunction with the appended claims and with reference to the drawings, in which:

[0009] Figure 1A and 1B A flowchart depicting an IC manufacturing method according to some examples of the present disclosure;

[0010] Figure 2 A generally schematic configuration of a wafer processing tool depicting a wafer processing tool that can be used for epitaxial processing and suppressing dopant hydride precipitation according to some examples of the present disclosure, which can be deployed in association with one or more processing stages of a wafer manufacturing process;

[0011] Figure 3 A representative chemical reaction depicting the formation of a surface segregation layer (SSL) containing elemental dopants that can be generated in a doped epitaxial process in some examples; and

[0012] Figures 4A - 4D A cross-sectional view of an IC device depicting an IC device in various formation stages that can suppress dopant hydride precipitation according to some examples of the present disclosure. DETAILED DESCRIPTION

[0013] The examples of the present disclosure are described with reference to the accompanying drawings, in which like reference numerals generally refer to like elements throughout. The figures are not drawn to scale, and are provided only to illustrate the examples. Many specific details, relationships, and methods are set forth below in order to provide an understanding of one or more examples. However, it should be understood that some examples may be practiced without such specific details. In other examples, well-known subsystems, components, structures, and techniques have not been shown in detail so as not to obscure the understanding of the examples. Thus, the examples of the present disclosure may be practiced without such specific components.

[0014] Additionally, terms such as "coupled" and "connected" and their derivatives may be used in the following detailed description, the appended claims, or both. It should be understood that these terms are not necessarily intended as synonyms for each other. "Coupled" may be used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, cooperate or interact with each other. "Connected" may be used to indicate the establishment of communication between two or more elements that are coupled to each other, i.e., a communication relationship. Further, in one or more examples set forth herein, generally speaking, if an element can be programmed to perform or otherwise be structurally arranged to perform a certain function, the element, component, or module can be configured to perform the function.

[0015] Non-limitingly, examples of IC devices having a doped epitaxial film and techniques for suppressing the precipitation of dopant hydrides in the doped epitaxial film of an IC device are set forth below in the context of doped epitaxy using group V dopants.

[0016] Epitaxy (the prefix epi- means "on top of" and taxis means "ordered") refers to a type of crystal growth or material deposition in which a new crystalline layer is formed with one or more well-defined orientations relative to an underlying substrate that can act as a crystallization seed layer. The deposited crystalline film is called an epitaxial film or an epitaxial layer. The relative orientation of the epitaxial layer with respect to the seed layer can be defined according to the orientation of the lattice of each material. For most epitaxial growths, the new layer is typically crystalline, where each crystalline domain of the overlying layer has a well-defined orientation with respect to the substrate crystal structure. Generally speaking, single-domain epitaxy, i.e., the growth of an overlying layer crystal having one well-defined orientation with respect to the substrate crystal, is preferred.

[0017] One of the main commercial applications of epitaxial growth is in the semiconductor industry, where doped or undoped semiconductor films are grown epitaxially on a substrate having a specific crystalline orientation defined by its Miller index. Several epitaxial techniques can be used to fabricate epitaxial layers comprising various semiconductor materials, e.g., including but not limited to metalorganic vapor phase epitaxy (MOVPE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), and atomic layer epitaxy (ALE), among others. Depending on the implementation, the epitaxial process can involve various complex interactions of different materials, typically present in multiple phases (e.g., gas phase, liquid phase, and / or solid phase), which can occur in a dedicated chamber used to grow the epitaxial layer one layer at a time (e.g., atoms or molecules of a single layer, referred to as a monolayer) above the substrate. Broadly speaking, the epitaxial process can include the following steps and / or phenomena: transporting reactants to the substrate in the reaction chamber, diffusing the reactants to the substrate surface, adsorbing the reactants on the substrate, surface processes such as incorporating reaction and adsorption layers, desorbing products and / or by-products, transferring the products / by-products to the main transport medium (e.g., gas), and exhausting / removing the gas and other by-products from the reaction chamber.

[0018] Epitaxial films doped with an n-type dopant comprising a Group VA element (or synonymously, Group 5A or simply Group V) are used in the fabrication of many IC devices, as N-P-N and P-N-P junctions are the basis of semiconductor device design and operation. The manufacturing processes used to produce such epitaxial films rely on the use of appropriate n-type source precursor molecules, which typically include Group V hydrides when fabricating various IC products, including high-volume manufacturing (HVM) process flows deployed at advanced technology nodes. Arsenic (As) and phosphorus (P) are the most common n-type dopants, which are typically incorporated into the epitaxial film at concentrations ranging from ppm levels (usually diluted in H2) to 100% pure form using arsine (AsH3) and phosphine (PH3) gas sources as precursors.

[0019] Group 5A hydrides, such as NH3 (ammonia), PH3 (phosphine), AsH3 (arsine), and SbH3 (stibine), are toxic to humans. Arsine and phosphine are of particular importance, both being generally colorless and applied in gaseous form, which can cause various diseases depending on the duration and concentration of the exposure involved. Arsine is an odorless gas known to cause massive hemolysis, leading to anemia, jaundice, hemoglobinuric renal failure, and other conditions. Phosphine is a flammable gas with a fishy or garlic odor, known to cause restlessness and fatigue, speech, vision, and gait disturbances, nausea, abdominal pain, vomiting, and diarrhea, headache, thirst, and chills. In more severe cases, respiratory disorders can include dyspnea, chest tightness, and delayed pulmonary edema, followed by seizures and coma, and ultimately death from heart failure. Generally, the intensity and duration of hydride exposure, as well as any pre-existing conditions of the exposed person, can affect the onset time and severity of the disease.

[0020] Since both arsine and phosphine are highly toxic, various measures have been taken in the semiconductor manufacturing industry to safeguard personnel in IC manufacturing plants and facilities (also known as foundries). The safeguards commonly employed in foundries can include dedicated gas cabinets that vent to appropriate facilities and sensitive detectors configured to monitor the release of toxic gases, high-integrity gas distribution systems that conduct sensitive monitoring at potential leak points contained within enclosures, and general monitoring of trace amounts of AsH3 and PH3 within the manufacturing cleanroom environment. Such measures have proven sufficient to safely use n-type dopant gases in most cases, particularly when maintaining the integrity of the atmospheric barrier throughout the manufacturing phase. However, in certain situations, there is another gas source that is often overlooked - the wafers, which themselves have epitaxial films doped with As and / or P and, upon post-processing, may need to be transported in dedicated wafer containers to additional manufacturing stages for further processing.

[0021] For the purposes of this disclosure, and without limitation, it is herein assumed that an epitaxial film growth process involving the use of AsH3 and PH3 precursors generally results in surface segregation of dopant species (e.g., P and As) during the growth process. It is further assumed that the segregated dopant species can exist in an unincorporated form, e.g., not as interstitial dopants or incorporated as substitutional species in the Si lattice in a grid structure, whereby the dopant species can "float" to the top surface of the epitaxial layer during epitaxial layer growth. Under certain conditions, the floating dopant species, also referred to as elemental dopant species, can form a surface segregation layer (SSL) above the epitaxial layer, where the SSL can comprise one or several monolayers consisting essentially of dopant species not incorporated in the grid structure. In contrast, the n-doped thin film layer below the SSL contains P and As atoms that are formally bonded (e.g., covalently) into the film crystalline structure or interstitially filled before becoming available as electrically active dopants. While the processing conditions in the reaction chamber are tightly controlled to minimize ambient oxygen (O2) and moisture (H2O) such that not only high-quality crystalline material can be grown in the epitaxial thin film growth process but also the risk of gas evolution reactions that could lead to the unintended release of arsine / phosphine gases is reduced. However, when the processed wafers are subsequently exposed to ambient conditions containing O2 and H2O, the presence of the unincorporated dopants in the SSL film above the epitaxial layer continues to pose a threat of arsine / phosphine evolution (e.g., as outgassing). In cases involving patterned wafers and blanket film growth (non-selective epitaxy), the situation becomes even more complex and potentially dangerous because non-single-crystalline materials with a higher surface area relative to the single-crystalline surface can produce an SSL with a higher surface concentration of unincorporated dopants that may be more prone to outgassing.

[0022] Although gas evolution reactions involving doped epitaxial films can be complex, it is herein assumed, without limitation, that such reactions can involve the oxidation and surface kinetics of the SSL film when exposed to humid air, where the unincorporated dopants can react with water (H2O) to form harmful gaseous by-products. Depending on the surface coverage of the As and P species and the surface area of the wafers involved, this outgassing can lead to the accumulation of AsH3 and / or PH3 in the wafer carriers deployed to transport the processed wafers in the overall fab manufacturing environment (e.g., "FOUP" or "front-opening unified pod"), thus leading to potentially hazardous situations at different foundry locations, especially in high-volume manufacturing (HVM) facilities with very high wafer throughput.

[0023] Some baseline practices for dealing with the generation of AsH3 and PH3 in an HVM environment are included in the wafer handling operations of transferring processed n-type epitaxial wafers into a FOUP, using an inert ambient gas (usually N2), maintaining the FOUP in an N2 environment to prevent or slow oxidation, and controlling additional oxidation reactions in dedicated equipment configured to remove toxic gases for proper and safe elimination. Although effective, such methods require a large amount of infrastructure to implement and additional logic control related to the state of the post-epitaxy wafers, thus adding significant costs to the overall manufacturing process. Some examples also use an oxide "capping layer" over the doped epitaxial layer to mitigate the risk of dopant hydride precipitation. While capping layers of intrinsic silicon and silicon dioxide can be effective, these capping layers add an additional layer to the top surface of the intentionally doped epitaxial layer, which may not meet device requirements and / or performance. In addition, the use of an oxide capping layer requires transporting the processed wafers to a separate tool to perform oxidation and thus requires additional safeguards during transportation, similar to the previously mentioned issues.

[0024] Examples of the present disclosure recognize these and related challenges and thus provide technical solutions for manufacturing IC devices including doped epitaxial layers, where various post-epitaxy removal processes are provided for suppressing, reducing, and / or eliminating or otherwise mitigating the risk of dopant hydride precipitation in a semiconductor fab environment. Depending on the implementation, examples herein may include several classes of removal processes, for example, in the same reaction chamber or in the same tool used for epitaxial processing, where selective or non-selective etching operations may be implemented to remove SSL from the doped epitaxial layer. Some examples may also include one or more post-removal surface modulation (PRSM) processing options for conditioning the doped epitaxial layer to improve any undesirable effects caused by and / or remaining after the removal operation, as will be elaborated further below. While it is expected that such examples and variations reduce the incidence of harmful gas precipitation in the manufacturing environment without significantly increasing costs, unless explicitly recited in a particular claim, the present disclosure does not claim a particular result other than potentially reducing manufacturing defects that may otherwise reduce the yield, reliability, or electrical performance of the product.

[0025] Turning to Figure 1A and 1B, which depicts a flowchart of an IC manufacturing method according to some examples of the present disclosure, where the illustrated steps, blocks, actions, or operations can be combined in various ways. Example method 100A may begin with growing a doped epitaxial layer (or simply "epitaxial layer") over a substrate placed in the working volume or reactor chamber of a semiconductor processing tool, where the doped epitaxial layer may include an n-type dopant, as set forth at block 102. As previously mentioned, various epitaxial processes and / or techniques can be used to form the doped epitaxial layer, but are not limited thereto. According to an embodiment, the substrate may include a semiconductor substrate having a specific crystal orientation and may include any suitable semiconductor material, for example, silicon doped appropriately in some arrangements as the substrate material. In additional and / or alternative examples, other semiconductor materials such as Ge, SiGe, GaAs, SiC, GaN, other III-V materials, etc. may be used as the substrate in some embodiments, where one or more doped epitaxial layers or single crystal layers may be formed or provided in some arrangements. In other variations, the substrate may include single crystal material, polycrystalline material, amorphous material, silicon-on-insulator (SOI) material, or dielectric material. In some arrangements, the doped epitaxial layer may be grown as a homoepitaxial layer or a heteroepitaxial layer, where a selective epitaxial growth (SEG) process (also referred to as selective area epitaxy or SAE) or a non-selective epitaxial growth process may be used.

[0026] Depending on the implementation, the doped epitaxial layer may have a first thickness (e.g., on the order of tens or hundreds of nanometers), which in some arrangements may be reduced to a second thickness, as will be seen further below. The doped epitaxial layer may have a surface segregation layer (SSL), which may include one or more monolayers of unincorporated dopant species (e.g., As, P, etc., as previously mentioned). At block 104, the SSL film containing the n-type dopant may be removed using a suitable etchant under selective process conditions (e.g., selective temperature and pressure, flow rate of reactants, etchant composition, and selectivity rate, etc.). Depending on the implementation, the SSL removal may be performed in a selective manner (so as to substantially not etch the doped epitaxial layer and / or substrate material (e.g., with a high selectivity ratio)) or a non-selective manner (which may remove at least a portion of the doped epitaxial layer, e.g., greater than 1% of the material in some arrangements). As will be seen further below, for the purposes of the examples herein, various halogen-based chemistries may be provided, which may be deployed in-situ, e.g., in the same reactor chamber or working volume and / or in the same cluster tool (e.g., in different working volumes of the tool), so as not to disrupt the integrity of the atmosphere barrier with respect to epitaxial layer growth and subsequent SSL removal. At block 106, one or more optional post-etch / removal surface modification / modulation (PRSM) processing operations may be performed depending on the type of epitaxial growth (e.g., selective vs. non-selective), the initial thickness of the doped epitaxial layer, the desired target thickness of the doped epitaxial layer, the type of halogen-based etching for SSL removal (e.g., self-limiting vs. non-self-limiting), the location of SSL removal (e.g., same reaction chamber vs. same process tool), etc.

[0027] Figure 1B Depicts additional steps of method 100B that may be combined with at least a portion of the foregoing process according to some examples herein. At block 120, the SSL formed over the doped epitaxial layer may be removed according to various in-situ etch flows, thereby exposing the top surface of the doped epitaxial layer. In one arrangement, a surface conditioning layer of silicon and / or germanium may be formed over the top surface of the doped epitaxial layer (block 122), where suitable silane / germane precursors may be used. Additionally and / or alternatively, several variants of surface conditioning may be implemented according to some examples herein, as will be further elaborated below. At block 124, additional dopants may be added to the doped epitaxial layer, optionally with or without a surface conditioning layer, where the additional dopants may include boron, phosphorus, indium, antimony, and / or any combination thereof, but are not limited thereto.

[0028] Several example SSL removal processes and optional surface conditioning / modification treatments will now be elaborated in additional detail below by way of illustration, but there is no restriction and no significance to the order or priority in the following description unless specifically stated otherwise. In one arrangement, the example SSL removal process can be implemented after the desired film thickness of the doped epitaxial layer has been achieved, thereby advantageously overcoming the safety issues caused by post-epitaxial dopant hydride precipitation, which can be determined using a suitable in-situ metrology device (e.g., an ellipsometer configured to operate with the epitaxial chamber). Additionally, the examples herein can be implemented without using an oxide capping layer, thus reducing and / or eliminating safety risks without compromising the device design. In some examples, an in-situ etching reaction as previously described can be used to remove dopant species in the SSL. In some forms of this arrangement, the required etchant source may already be provided as part of the reactor system. Thus, no additional hardware components or gas sources need to be added to the reactor system.

[0029] In another example of the present disclosure, multiple steps can be employed to reduce and / or eliminate surface dopant species through an in-situ etching reaction, followed by reacting the etched surface with a silane source precursor (Si n H 2n+2 ) and / or a germane source precursor (Ge n H 2n+2 ) to perform surface conditioning as previously mentioned. In a variant of this example where a halogen-based chemistry is used for etching, such surface conditioning or reconditioning can be employed to reduce and / or eliminate a surface layer of chemisorbed halogen that may be generated through the etching process, thereby mitigating the risk of HX precipitation (where X is a halogen) upon subsequent exposure to air. In some arrangements, the germane source precursor may be preferred to achieve a lower temperature reaction scheme for removing the halogen surface layer that can be produced as a by-product of SSL etching. In some arrangements, the in-situ etching reaction can be configured as a self-limiting process (e.g., a selective etching process) by, for example, choosing the etchant species and / or the in-situ etching process conditions. By way of illustration, the selectivity of the SSL etching reaction can be on the order of ten percent or one part per thousand, such that the selected etchant can remove the SSL material more easily than the doped epitaxial material or the substrate. In such scenarios, the SSL etching reaction can be configured to substantially not cause removal of the doped epitaxial material.

[0030] In some arrangements, the reaction of silane and / or germane source precursors for surface (re)conditioning can also be configured as a self-limiting or non-self-limiting process by selecting the silane and / or germane source precursors and subsequent reaction conditions. For the purposes of some examples, it is assumed that modifying / modulating the top surface of an initially grown film (exposed after removal of the unincorporated dopants in the SSL layer) using a silane and / or germane source deposition precursor can result in the formation of a surface layer predominantly of hydrogen and / or dangling bonds (depending on the temperature of the surface modification step) prior to unloading the wafer from the reactor chamber or cluster chamber, depending on the tool configuration. Depending on the process conditions, the hydrogen or dangling bond surface layer can be used to mask underlying n-type dopants during the formation of a native oxide above the top surface of the doped epitaxial layer when exposed to air. Although the Si / Ge-based surface conditioning layer can be undoped in some arrangements, additional dopants can be added using appropriate dopant source precursors in some arrangements as previously mentioned, where in some examples, the dopant concentration can be in the range of 1×10 15 atoms / cm 3 to 1×10 21 atoms / cm 3 .

[0031] Suitable etchant sources for SSL removal can include, but are not limited to, halogen-containing gases and / or vapors compatible with the epitaxial growth chamber and / or cluster fabrication tool. Depending on the implementation, the halogen-based etchant can include iodine (I), bromine (Br), and chlorine (Cl), where in some examples, chlorine is preferred. Fluorine (F) can also be considered within the scope of the present disclosure, but is generally less preferred because the epitaxial growth chambers for silicon-containing epitaxial film growth typically include quartz (SiO2) components that can be eroded by fluorine. Suitable halogen-containing gases and / or vapors can include, but are not limited to, any volatile halogen-containing source that can be delivered to the reactor chamber and thermally activated to drive an in-situ etching reaction of the n-type dopant surface layer formed during / after epitaxial film growth. In some arrangements, the halogen-containing gas and / or vapor can include, but are not limited to, X2, where X = I, Br, Cl, and combinations thereof. In some arrangements, hydrogen halides can also be used as etchants, for example, having a composition of HX, where X = I, Br, Cl, and combinations thereof. In some arrangements, the etchant can include a composition of M n Z 2n+2Saturated alkanes and / or their analogues, where M = C, Si, and / or Ge or combinations thereof, and Z = I, Br, Cl, or H and combinations thereof, but not limited thereto. Combinations of any of the foregoing chemical substances are also within the scope of the present disclosure. Additionally, any of the foregoing gases and / or vapors can be used in pure or diluted form and / or mixtures, depending on the implementation. For example, halogen-containing gases can include Cl2 delivered as a mixture with a carrier gas, where the carrier gas can include H2, N2, inert gases (e.g., helium (He), neon (Ne), argon (Ar), and / or xenon (Xe)), and / or any suitable combination thereof.

[0032] Various suitable etching process conditions can be employed, e.g., largely depending on the nature of the etchant to be used and the degree of selectivity of the etching process. As previously mentioned, an example SSL etching process can be configured to have high selectivity, e.g., relative to an underlying doped epitaxial film. In some arrangements, selective etching of the surface-segregated dopant layer can be achieved through process optimization (e.g., as a self-limiting etching process), where different conditions such as the temperature of the etching process, the flow rate and partial pressure of the etchant, the flow rate of any carrier gas co-introduced with the etchant, and the pressure at which the etching reaction occurs can be modulated.

[0033] In a specific example, HCl can be used as an etchant, where the n-type dopant is arsenic (As). In a first step, Si2H6 with a flow rate of about 200 standard cubic centimeters per minute (sccm) and AsH3 (1% in H2) with a flow rate of about 500 sccm diluted in H2 with a flow rate of about 50 standard liters per minute (slm) can be used to non-selectively grow an epitaxial silicon thin film with a doping concentration of about 1×10 21 atoms / cm 3 . The epitaxial growth can be carried out at a temperature of about 600 °C and a pressure of about 8 kilopascals (kPa) for a duration sufficient to grow an epitaxial film about 30 nm thick. The As-doped epitaxial silicon film can have a segregated surface layer of As, which is generated by As segregation during the epitaxial growth process. In a second step, the in-situ thermal HCl etching carried out at the epitaxial film growth temperature (about 600 °C) can be used to remove the surface-segregated As layer from the surface of the epitaxial film. The etching process can be carried out at a pressure of about 5300 Pa with a HCl flow rate of about 300 sccm diluted in ultra-pure H2 with a flow rate of about 50 slm. The etching process can continue for a time sufficient to substantially completely remove the As layer segregated from the top surface of the As-doped silicon film from the entire surface of the wafer, which is about 60 seconds in this non-limiting example.

[0034] In some instances, different modifications / modulations can be used to optimize process conditions to remove substantially all of the surface-segregated As in a minimum amount of time. Since the etch process conditions can be focused below the temperature at which HCl can etch silicon, the example process can be configured to be self-limiting with respect to the epitaxially doped As silicon located below the surface-segregated As layer.

[0035] In a third step, the pressure in the reactor chamber can be increased to about 55 kPa with an ultra-pure H2 carrier gas flow rate of about 40 slm, while reducing the temperature from about 600 °C to about 530 °C and stabilizing it for about 30 seconds. After the stabilization time has elapsed, SiH4 with a flow rate of about 400 sccm is introduced into the reactor system, while continuing to flow the ultra-pure H2 carrier gas (at about 40 slm) for a period of time sufficient to produce approximately a monolayer of chemisorbed SiH3 groups on the surface of the As-doped epitaxial silicon film, which period of time is about 12 seconds in this non-limiting example. In some instances, additional modulations can be used to optimize process conditions to deposit substantially a monolayer of surface-adsorbed SiH3 groups in a minimum amount of time. The reactor can then return to standard unloading conditions, and the wafer can be unloaded from the chamber and transferred through the various transfer compartments, chambers, etc. of the cluster tool platform in transfer order until the wafer is placed in the batch load lock of the cluster tool platform.

[0036] In another arrangement, an example SSL etch reaction can be performed in a separate chamber that is attached to a cluster tool platform in a suitable configuration (e.g., in-situ tool etch as compared to in-situ chamber etch), which also avoids exposing the wafer surface to external environmental conditions prior to performing the etch reaction to remove the SSL dopant material from the surface of the wafer. Depending on the implementation, this arrangement can provide the advantage of reduced impact on overall throughput and cost of ownership. Additionally, this enables the use of other types of SSL etch processes and / or etchants based on appropriate material selection and / or chamber design, such as fluorine-containing etchant materials, plasma-type etch processes, etc. In an example implementation, a dedicated chamber can be configured to use thermal and / or plasma etching to remove the SSL material containing unincorporated dopants. Plasma processes covered within the scope of the present disclosure can include in-situ plasma, remote plasma, and / or combinations thereof. In some arrangements, the appropriate etchant, carrier gas, and deposition precursors can be the same as those described with respect to the in-situ chamber etch scenario. In a specific example involving a dedicated chamber that is clustered with an epitaxial reactor chamber, a plasma process using H2 as an etchant source gas can be employed to remove the surface-segregated n-type dopant layer, and the plasma process provides a hydrogen-based surface termination / passivation of the top surface of the initially grown n-type doped epitaxial film. Additional modulation can be performed to identify process conditions that result in the removal of substantially all of the segregated n-type dopant layer and provide appropriate surface termination / passivation of the top surface of the doped epitaxial film while substantially not changing or changing minimally the thickness of the initially grown epitaxial film (e.g., based on selectivity), similar to other SSL etch processes described previously.

[0037] Some general chemical reactions that can represent etch processes employed for some examples herein are set forth below:

[0038] (A) At the growth temperature (T) or at a different T, a halogen-containing etchant + segregated n-type surface layer {n-type}X3(g) (non-self-limiting), X = halogen;

[0039] (B) At the growth T or at a different T, a halogen-containing etchant + segregated n-type surface layer {n-type}X3(g) (having a significantly high selectivity with respect to the n-type doped film, e.g., self-limiting), X = halogen;

[0040] (C) At the in-situ etch reaction temperature, reaction (A) + silane and / or germane source precursors (combination of self-limiting or non-self-limiting growth and non-self-limiting halogen etch); and

[0041] (D) At the in-situ etch reaction temperature, reaction (B) + silane and / or germane source precursors (combination of self-limiting or non-self-limiting growth and self-limiting halogen etch).

[0042] As previously mentioned, suitable etching conditions can depend on the type of etching process (thermal and / or plasma, where exemplary plasma processes can involve in-situ or remote plasma sources and different species), the selected etchant species, and whether the process is self-limiting for unwanted SSL materials versus beneficial doped epitaxial films (e.g., having varying degrees of selectivity). In some non-limiting examples involving chlorine-based etchants, for a self-limiting etch reaction, the temperature can be maintained at less than about 750 °C, while for a non-self-limiting etch reaction, the temperature can be greater than about 750 °C. For plasma processes, in some embodiments, the temperature can be in the range of -50 °C to 600 °C. The etching process pressure can be in the range of 100 kPa to about 145 kPa. The etchant flow rate can be in the range of 1 sccm to about 20 slm, and the carrier gas flow rate can be in the range of 0 sccm to about 200 slm, independent of the type of etchant gas mixture and / or carrier gas mixture that can be used in some example embodiments.

[0043] In some arrangements involving plasma, additional etchant sources within the scope of the present disclosure can include ultra-high purity H2 (99.9998% ALPHAGAZ TM Grade 2), where the target etch byproduct is {n-type dopant}H3(g).

[0044] Generally, different etching processes can be optimized for different dopant applications and reactor / tool configurations in accordance with the teachings herein. In some specific examples, the etching process can be configured or otherwise optimized such that the byproducts of the etch reaction for removing SSL dopant species are volatile substances having low melting and / or boiling points to ensure they are effectively removed from the reactor chamber and transported to the exhaust pump and associated abatement systems that have been incorporated as part of the reactor / tool system. Some representative etch byproducts and their properties are illustrated in the table below, where some examples can include compounds that decompose at temperatures before reaching their standard boiling points:

[0045] Compound Melting point (°C) Boiling point (°C) <![CDATA[AsF3]]> -8.5 60.4 <![CDATA[AsCl3]]> 16.2 130.2 <![CDATA[AsBr3]]> 31.1 221 <![CDATA[Asl3]]> 146 403 <![CDATA[pf3]]> -151.5 -101.8 <![CDATA[PCl3]]> -93.6 76.1 <![CDATA[PB3]]> -41.5 173.2 <![CDATA[Pl3]]> 61.2 200 (decomposes)

[0046] In non-limiting examples, an IC manufacturing method in accordance with the teachings herein can include the following steps:

[0047] (A) Completing an epitaxial growth process at a desired thickness and doping concentration target;

[0048] (B) When necessary, adjusting the temperature and flow conditions to achieve self-limiting in-situ etching of an SSL layer containing unincorporated / elemental n-type dopant species, e.g., by using HCl (for etching the SSL / elemental layer down to the film surface with H and Cl and terminating the surface);

[0049] (C) When necessary, adjust the temperature and flow conditions by introducing a silane and / or germane source deposition precursor to achieve self-limiting removal of the chemisorbed Cl layer generated during etching with substantially no change in film thickness, and provide a hydrogen-based surface termination to replace the n-type dopant top surface; and

[0050] (D) Remove / unload the wafer from the tool, where the risk of AsH3 and / or PH3 gas evolution is reduced or negligible.

[0051] Now turning to Figure 2 , which depicts a generally schematic configuration of a wafer processing tool 200 that can be used for epitaxial processing and suppressing dopant hydride evolution according to some examples of the present disclosure. The wafer processing tool can be deployed in association with one or more processing stages of a wafer manufacturing process flow. By way of illustration, the processing tool 200 can be implemented as a configurable tool for deployment in a processing stage where a doped epitaxial layer can be formed over a suitable substrate using any known or heretofore unknown epitaxial technique in one or more reactor chambers or processing chambers 205-1, 205-2. In some arrangements, chambers 205-1 and / or 205-2 can be adapted to a working volume to perform various SSL etching operations as described above (e.g., designated herein as in-situ chamber etching operations). Additionally, according to some examples, the processing tool 200 can additionally and / or alternatively include one or more dedicated chambers or working volumes configured to perform one or more SSL etching operations (e.g., designated herein as in-situ tool etching operations) within the tool.

[0052] In some arrangements, the processing tool 200 can be configured as a multi-functional tool system, also referred to as a cluster tool system, which allows for the automatic transfer of semiconductor processing wafers (also referred to as semiconductor wafers, processing wafers, or simply wafers in some examples) between different reactor chambers configured to implement different processes or to process similar layers in parallel without exposing the wafer to air between process steps. Thus, in such arrangements, one or more processing chambers can be provided that can serve as corresponding working volumes, each processing chamber being adapted to implement corresponding process steps, operations, and / or recipes associated with a wide range of wafer manufacturing techniques, including but not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) including atomic layer deposition (ALD) and plasma-enhanced CVD (PECVD), and rapid thermal processing (RTP) and rapid thermal annealing (RTA) stages for dopant activation, pre-cleaning / post-cleaning processes, degassing operations, surface conditioning / modulation, etc. As Figure 2As illustrated, the example process chambers 203-1, 203-2, the pre-clean chamber 206 (e.g., using RF or plasma), and the degassing chambers 208-1, 208-2 represent such chambers that may be provided in the process tool 200 (e.g., a cluster tool system). In some arrangements, it may be necessary to monitor and control various properties and characteristics associated with a semiconductor process wafer during the processing stage, such as film thickness, sheet resistance, temperature-dependent resistance, etc. Thus, one or more sensor / metrology chambers 207 may also be provided as part of an example cluster tool system (e.g., the process tool 200).

[0053] Depending on the implementation, the process tool 200 may be configured to include a plurality of main chambers 202A, 202B, and the foregoing process chambers and sensing / metrology chambers may be detachably coupled to the plurality of main chambers. In one arrangement, the first main chamber (e.g., the main chamber 202A) may be configured as a buffer chamber with robotic wafer handling capabilities for assisting in the loading and / or unloading of semiconductor process wafers using the load lock chambers 212A and 212B coupled to the front-end assembly and interface 211, which is adapted to cooperate with a dedicated wafer carrier system such as a FOUP. The main chamber 202A may also be used as a transfer chamber to assist in transferring process wafers between different process chambers coupled to the main chamber. Similarly, the second main chamber (e.g., the main chamber 202B) may also be configured as a transfer chamber, which may also include a robotic wafer handling system for assisting in transferring wafers from one process chamber to another according to the process flow. In some examples, the robotic wafer handling system may include a robotic arm that is adapted to rotate about a vertical axis and a horizontal axis and travel in any plane within the 3D space enclosed by the main chambers 202A, 202B. One or more transfer passages or conduits 210-1, 210-2 may be coupled between the main chambers 202A and 202B for assisting in transferring process wafers between the two main chambers 202A and 202B. In some arrangements, a suitable cooling chamber (not specifically shown in this figure) may be provided for cooling / conditioning the temperature of the process wafer before or after the processing stage.

[0054] Depending on the implementation and / or process flow requirements, the various process chambers, load lock chambers, sensor / metrology chambers, any additional / extended chambers, and the main chambers 202A, 202B may be pressurized (depressurized) to different levels using a suitable gas (e.g., argon, nitrogen, etc.) in combination with one or more servo mechanism vacuum pumps and associated hardware (e.g., cryopumps, turbopumps, rotary vane pumps, etc., not specifically shown in this figure). Thus, a suitable mechanical coupling may be provided between the main chambers 202A, 202B and the other chambers to facilitate chamber detachability while maintaining vacuum integrity during operation.

[0055] In one arrangement, a suitable communication interface may include various processing chambers and sensor / metrology chambers, which may be coupled to a data acquisition (DAQ) unit 216 for collecting sensor data and transmitting the data to a host computer 220 via a local network and / or a remote network 218 using any known or heretofore unknown data collection / transmission protocol. For example, interfaces 214-1, 214-2, and 214-3 are provided with respect to the epitaxial chambers 205-1 / 205-2, the sensor / metrology chamber 207, and the SSL etch chamber 204, respectively. In addition to data collection, monitoring, and processing, according to examples herein, the host computer 220 may be configured to execute appropriate processing software or programs for implementing and / or controlling various process recipes, e.g., various process recipes regarding doped epitaxial growth processes, SSL removal processes, post-removal surface conditioning, etc. Depending on the implementation, the host computer 220 may be deployed as a local or remote host, or deployed at a cloud-based data center associated with an IC manufacturing facility, which may include one or more processors that operate under program control to implement sensing processes and process recipes, data analysis, report generation, etc.

[0056] Figure 3 Depicts a general chemical reaction illustrating the formation of a surface segregation layer (SSL) containing elemental or unincorporated dopants that may be generated in a doped epitaxial process in some examples. Reference numeral 300A represents the application of dopant precursor molecules 304, e.g., AsH3, onto the surface 306 of a substrate 302. In some arrangements, the dopant may be introduced into the substrate at a concentration greater than the solid solubility parameter of the substrate. For example, chemisorption surface reaction kinetics is a type of adsorption that may initially occur near the surface 306, where adjacent dopant precursors in a local region of the substrate 302 may form bonds between dopant atoms by eliminating hydrogen (e.g., As-As bonds), as represented by reference numeral 300B. This process may continue to occur throughout the duration of the epitaxial growth, whereby successive chemisorption kinetics may produce local "surface clusters" 310 of dopant atoms that are not incorporated into the underlying substrate lattice. Depending on the dopant concentration and epitaxial process conditions involved, the clusters 310 of unincorporated dopant atoms may form an adjacent thin layer or layer over the majority of the growing / grown epitaxial layer formed over the substrate, thereby serving as an SSL capable of causing detrimental outgassing, as previously set forth in this disclosure. In a factory environment, such surface clusters and / or segregation layers over the doped epitaxial layer may be detected by suitable instrumentation such as, for example, an energy-dispersive X-ray (EDX) device.

[0057] Figures 4A - 4D Depicts a cross-sectional view of an IC device in various formation stages that may suppress the precipitation of dopant hydrides according to teachings herein. Figure 4AReference numeral 400 in the figure refers to an IC device including a semiconductor substrate 402, such as a silicon substrate having a suitable crystal orientation such as

[100] ,

[110] ,

[111] , etc., but not limited thereto. As previously described, the IC device 400 may represent an IC in an early manufacturing stage of a process for manufacturing any type of IC product, which may be based on various semiconductor technologies, such as bipolar junction transistor (BJT) technology, heterojunction bipolar transistor (HBT) technology, metal oxide semiconductor (MOS) technology, complementary metal oxide semiconductor (CMOS) technology, double-diffused metal oxide semiconductor (DMOS) technology, etc., including analog, digital, and / or mixed-signal device designs. In some instances, a combination of semiconductor technologies may be implemented, where different technologies suitable for corresponding types of product designs may be integrated within the same chip or IC device, such as linear BiCMOS or LBC (a bipolar CMOS combination technology where bipolar technology may be used for analog functions and CMOS may be used for digital logic design), BCD (a bipolar CMOS-DMOS combination technology where DMOS may be integrated within the IC device for power and high-voltage portions that also have analog and digital parts), etc. Thus, without being limited to a specific implementation, the semiconductor substrate 402 may include a portion of a semiconductor process wafer (e.g., an IC die), which may be in a stage without any patterning or in a stage with patterned structures or layers thereon, where the IC device 400 may have been processed to include any combination of epitaxial layers, buried layers, laterally diffused extensions, N-wells, P-wells, deep wells, shallow wells, reduced surface field (RESURF) layers formed above the dielectric layer of a SOI substrate, etc. Additionally, an example semiconductor substrate 402 may include various isolation structures for dielectrically isolating constituent layers, regions, well structures, etc. using various isolation techniques (e.g., shallow trench isolation (STI), local oxidation of silicon (LOCOS), etc.), which may be formed during a process flow not explicitly shown in the figures herein.

[0058] A suitably thick n-doped epitaxial film 404 may be formed above the substrate 402 using any epitaxial technique, where the growth may be selective or non-selective. A SSL 406 having a thickness of one or several monolayers and including dopants (e.g., As, P, etc.) segregated at the surface that are not incorporated into the doped epitaxial film 404 may be formed above the doped epitaxial film 404 as previously described. An example in-situ etching process may be performed, for example, in the same epitaxial reactor chamber, using a halogen-containing gas and / or vapor, with or without a carrier gas, whereby the SSL 406 may be removed from the IC device 400, as Figure 4BAs previously described, the etching process may be a non-limiting process (e.g., the process may also etch the doped epitaxial film 404, thereby removing a top portion thereof) or a self-limiting process (e.g., having a high degree of selectivity, wherein the process may not substantially etch the doped epitaxial film 404). Some general chemical reaction mechanisms involving halogen-based etching chemistries as contemplated herein are set forth as follows:

[0059] (A) Using HCl (g) in H2 (carrier gas):

[0060] 3HCl(g)+1{SSL n-type dopant atom}→{n-type}Cl3(g)+H2(g)

[0061] (B) Using Cl2(g) in H2(carrier gas):

[0062] 3Cl2(g)+2{SSL n-type dopant atom}→2{n-type}Cl3(g)

[0063] In some examples, the Cl2 etch may be performed at a temperature range lower than the temperature range used for the HCl etch (e.g., about 100° C. to 150° C. lower). Although the thickness of the doped epitaxial film 404 may not be substantially changed during the selective etch process, in some examples, the initial thickness may be brought to a target thickness in a separate process after the SSL removal. Furthermore, any surface chlorine remaining after the SSL removal may be removed by depositing Si and / or Ge using a suitable precursor such as silane / germane in a post-etch deposition step, as previously mentioned.

[0064] Figure 4C Illustrating another example where a non-selective etch may be configured to remove portion 410 of doped epitaxial film 404, where a Cl 2 etch or a HCl etch may be performed as mentioned above. Figure 4D A subsequent stage is described in which in some instances a secondary doped film 412 may be regrown over the initial doped epitaxial film 404 to obtain an overall target thickness. Depending on the type of dopant and / or dopant concentration used in the secondary doped film 412, it is expected that the effects of toxic outgassing due to the secondary doped film 412 may be minimized. In some arrangements, a different n-type dopant (e.g., phosphorus) may be used instead of arsenic, which is more toxic than phosphorus, thereby mitigating the risk of hydride precipitation. In some arrangements, a lower concentration of dopant may be used in the secondary doped film 412 than in the initial doped epitaxial film 404 in order to minimize the risk. As previously mentioned, various (optional) post-removal surface modulation / modification processes may be provided that may be integrated with any of the aforementioned manufacturing flows.

[0065] Although various examples of the present disclosure have been described above, the examples are presented by way of example and not limitation. Numerous changes may be made to the disclosed examples in accordance with the disclosure herein without departing from the spirit or scope of the present disclosure. Accordingly, the breadth and scope of the present disclosure should not be limited by any of the examples described above. Indeed, the scope of the present disclosure should be defined in accordance with the appended claims and their equivalents.

[0066] Additionally, in at least some additional or alternative embodiments, the functions / actions described in the blocks may not occur in the order shown in the flowcharts. For example, depending on the functionality / action involved, two consecutively presented blocks may actually be executed substantially simultaneously or the blocks may sometimes be executed in the reverse order. Further, the functionality of a given block of a flowchart and / or block diagram may be divided into multiple blocks, and / or the functionality of two or more blocks of a flowchart and / or block diagram may be at least partially integrated. Also, some blocks in the flowchart may optionally be omitted. Additionally, although some of the figures contain arrows on communication paths to show the primary direction of communication, it should be understood that communication may occur in the direction opposite to that depicted by the arrows. Finally, other blocks may be added / inserted between the illustrated blocks.

[0067] The order or sequence of actions, steps, functions, components, or blocks illustrated in any of the flowcharts and / or block diagrams depicted in the drawings of the present disclosure may be modified, changed, replaced, customized, or otherwise rearranged within a particular flowchart or block diagram, including the deletion or omission of a particular action, step, function, component, or block. Additionally, the actions, steps, functions, components, or blocks illustrated in a particular flowchart may be intermixed with or otherwise arranged or rearranged with the actions, steps, functions, components, or blocks illustrated in another flowchart so as to effect additional changes, modifications, and configurations relative to one or more processes for the purpose of practicing the teachings of the present disclosure. Similarly, although various examples have been set forth herein, not all features of a particular example are necessarily limited thereto and / or required therefor.

[0068] At least some of the foregoing descriptions may include certain directional terms, such as "upper", "lower", "top", "bottom", "left", "right", "front", "back", "vertical", "horizontal", etc., which may be used with reference to the orientation of some of the figures described or their illustrative elements. Since the components of some examples may be positioned in multiple different orientations, the directional terms are used for illustrative purposes and are in no way restrictive. Similarly, references to features referred to as "first", "second", etc. do not indicate any particular order, importance, etc., and such references may be interchanged depending on the context, embodiment, etc. Additionally, unless otherwise specifically noted, the features of the examples described herein may be combined with each other.

[0069] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. The above detailed description should not be considered as meaning that any particular component, element, step, act, or function is essential such that it must be included within the scope of the claims. In cases where a phrase such as "at least one of A and B" or a similar meaning phrase is recited or described, such a phrase should be understood to mean "only A, only B, or both A and B". References to an element in the singular form are not intended to mean "one and only one" unless expressly stated as such, but rather "one or more". In a similar manner, depending on the context, phrases such as "a plurality" or "multiple" may mean "one or more" or "at least one". All structural and functional equivalents of the elements of the embodiments described above are expressly incorporated herein by reference and are intended to be covered by the appended claims.

Claims

1. A method for manufacturing an integrated circuit IC, comprising: placing a semiconductor substrate in a semiconductor process tool working volume; forming a doped epitaxial layer over the semiconductor substrate, including forming a surface segregation layer SSL including a dopant species not incorporated into the doped epitaxial layer; removing the SSL; as well as The semiconductor substrate is removed from the working volume. 2 . The method of claim 1 , wherein the SSL is removed by selectively etching the SSL without substantially removing the doped epitaxial layer.

3. The method of claim 1, wherein the SSL is removed using a non-selective etch, the non-selective etch comprising removing a portion of the doped epitaxial layer.

4. The method of claim 1, wherein the SSL is removed using a halogen-based etchant, the halogen-based etchant comprising at least one of iodine (I), chlorine (Cl), bromine (Br), and any combination thereof.

5. The method of claim 1, wherein the SSL is removed using a hydride halogen etchant, the hydride halogen etchant comprising at least one of hydrogen iodide (HI), hydrogen chloride (HCl), hydrogen bromide (HBr), and any combination thereof.

6. The method of claim 1, wherein using comprises having M n Z 2n+2 The SSL is removed using an etchant of a saturated alkane or the like composed of: wherein M includes at least one of C, Si, Ge, and any combination thereof, and Z includes at least one of I, Br, Cl, H, and any combination thereof.

7. The method according to claim 1 further comprises forming a surface adjustment layer on the doped epitaxial layer, wherein the surface adjustment layer is made of silane (Si n H 2n+2 ) precursor, germanium (Ge n H 2n+2 ) precursors and any combination thereof. 8 . The method according to claim 7 , wherein the surface adjustment layer is doped with at least one of boron (B), indium (In), phosphorus (P), and antimony (Sb).

9. The method of claim 1, wherein the SSL is removed in an operation using the working volume for forming the doped epitaxial layer.

10. The method of claim 1, wherein the SSL is removed in an operation using a different working volume of the semiconductor process tool.

11. The method of claim 1 , wherein the doped epitaxial layer comprises a Group V dopant species.

12. An integrated circuit IC, comprising: Semiconductor substrate; a doped epitaxial layer over the semiconductor substrate, the doped epitaxial layer having a first dopant concentration; as well as A surface adjustment layer is above the doped epitaxial layer, the surface adjustment layer comprising silicon or germanium having a second dopant concentration less than the first dopant concentration.

13. The IC of claim 12, wherein the doped epitaxial layer comprises a Group V dopant species.

14. The IC of claim 13, wherein the surface conditioning layer is doped with at least one of boron (B), indium (In), phosphorus (P), and antimony (Sb).

15. An integrated circuit (IC) manufacturing tool, comprising: at least one main chamber; a first process chamber coupled to the at least one main chamber, the first process chamber configured to form a doped epitaxial layer over a semiconductor substrate; as well as A second process chamber is coupled to the at least one main chamber, the second process chamber being configured to remove a surface segregation layer SSL formed on the doped epitaxial layer. 16 . The IC manufacturing tool of claim 15 , wherein the first processing chamber is further configured to form a surface conditioning layer over the doped epitaxial layer after removing the SSL, the surface conditioning layer comprising at least one of silicon and germanium. 17 . The IC manufacturing tool of claim 15 , wherein the second processing chamber is configured to remove the SSL using an etchant in a selective etch or a non-selective etch.

18. The IC manufacturing tool of claim 17, wherein the etchant comprises a halogen-based etchant comprising at least one of iodine (I), chlorine (Cl), bromine (Br), and any combination thereof.

19. The IC manufacturing tool of claim 17, wherein the etchant comprises a hydride halogen etchant comprising at least one of hydrogen iodide (HI), hydrogen chloride (HCl), hydrogen bromide (HBr), and any combination thereof.

20. The IC manufacturing tool according to claim 17, wherein the etchant comprises n Z 2n+2 A saturated alkane or the like composed of, wherein M includes at least one of C, Si, Ge, and any combination thereof, and Z includes at least one of I, Br, Cl, H, and any combination thereof.

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