Chip packaging method and chip structure
By using a heat-dissipating carrier plate with an interface heat-dissipating material layer and a bonded chip frame in the chip package, the problem of high stress on the connection chip is solved and the yield of the chip structure is improved.
Patent Information
- Application Number
- CN202311861198.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-31
- Publication Date
- 2025-07-01
AI Technical Summary
In the existing multi-chip packaging methods, the connecting chip is subjected to high stress, resulting in dielectric layer damage and affecting the yield of the chip structure.
Using a chip packaging method, by preparing a heat dissipation carrier plate with an interface heat dissipation material layer, and bonding the first chip and the second chip thereon, forming a first chip frame, then flip the connecting chip onto the chip frame, and flip the chip frame onto the substrate, so that the connecting chip is accommodated in the accommodation space, and finally planting a ball on the back of the substrate to form a solder ball.
By pre-preparing the chip frame and substrate, the stress on the connecting chip is reduced, deformation is avoided, and the yield of the chip structure is improved.
Smart Images
Figure CN120237022A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip packaging technology, and particularly to a chip packaging method and a chip structure. Background Art
[0002] In today's high-tech field, the rapid development of chip technology poses challenges to meeting the growing demands for chip performance and functions. To address these challenges, researchers are actively exploring low-cost and high-performance multi-chip interconnection technologies, which are considered to be the necessary direction for future chip design.
[0003] In existing multi-chip packaging methods, connection chips are generally buried in a substrate or encapsulant, which can subject the connection chips to significant stress, leading to dielectric layer damage. Summary of the Invention
[0004] In view of this, this application provides a chip packaging method and a chip structure to reduce the stress on the connection chips and improve the yield of the chip structure.
[0005] In a first aspect of this application, a chip packaging method is provided, and the method includes:
[0006] Preparing a first chip frame; wherein, the first chip frame includes a heat dissipation carrier plate with an interfacial heat dissipation material layer, a first chip with first type bumps for connecting to a substrate and second type bumps for connecting to a connection chip on a first surface, a second chip with first type bumps for connecting to the substrate and second type bumps for connecting to the connection chip on a first surface, and a connection chip; the first chip and the second chip are bonded to the heat dissipation carrier plate with their second surfaces facing the interfacial heat dissipation material layer, and the second type bumps of the first chip and the second type bumps of the second chip are opposite to each other; the connection chip is flip-chip bonded to the second type bumps of the first chip and the second type bumps of the second chip;
[0007] Preparing a substrate; wherein, a receiving space for accommodating the connection chip is provided on the substrate;
[0008] In a manner that the connection chip faces the receiving space, the first chip frame is flip-chip mounted on the substrate so that the connection chip is accommodated in the receiving space;
[0009] Bumping balls on the back surface of the substrate facing away from the first chip frame to form solder balls.
[0010] Optionally, the receiving space is a groove.
[0011] Optionally, the receiving space is a through hole; after the first chip frame is flip-chip mounted on the substrate, the method further includes:
[0012] Cover a heat dissipation cover on the back of the connection chip facing away from the first chip frame; wherein, the heat dissipation cover is also connected to the substrate.
[0013] Optionally, the preparation of the first chip frame includes:
[0014] Prepare a heat dissipation carrier plate; wherein, one side of the heat dissipation carrier plate has an interface heat dissipation material layer; the interface heat dissipation material layer constitutes a chip fixing area;
[0015] Prepare first type bumps and second type bumps on the first surfaces of the first chip and the second chip respectively;
[0016] Bond the first chip and the second chip to the chip fixing area with the second surfaces facing the interface heat dissipation material layer; wherein, the second type bumps of the first chip and the second type bumps of the second chip are opposite to each other;
[0017] Flip-chip bond the connection chip on the second type bumps of the first chip and the second type bumps of the second chip to form the first chip frame.
[0018] Optionally, the bonding of the first chip and the second chip to the chip fixing area with the second surfaces facing the interface heat dissipation material layer includes:
[0019] Weld the first chip and the second chip to the chip fixing area respectively.
[0020] Optionally, the height of the first type bumps on the first chip and the height of the first type bumps on the second chip are equal to a first specified value; the height of the first type bumps on the first chip and the height of the second type bumps on the second chip are equal to a second specified value;
[0021] The first specified value is equal to the second specified value; or, the first specified value is less than the second specified value; or the first specified value is greater than the second specified value.
[0022] Optionally, the back of the connection chip is lower than the back of the substrate; the heat dissipation cover is a convex-shaped heat dissipation cover with one protruding part and two flush parts, the protruding part is received in the through hole and covers the back of the connection chip, and the flush parts are connected to the back of the substrate.
[0023] Optionally, the back of the connection chip is flush with the back of the substrate; the heat dissipation cover is a flat heat dissipation cover, the flat heat dissipation cover covers the through hole to cover the back of the connection chip, and is connected to the back of the substrate.
[0024] Optionally, the thickness of the heat dissipation cover is greater than the thickness of the connection chip.
[0025] Optionally, after forming the first chip frame, the method further includes:
[0026] Filling the area of the connection chip opposite to the first chip and the area of the connection chip opposite to the second chip.
[0027] The second aspect of the present application provides a chip structure, which is prepared by using any one of the chip packaging methods provided in the first aspect of the present application. The chip structure includes a first chip frame and a substrate having an accommodation space; wherein,
[0028] Wherein, the first chip frame includes a heat dissipation carrier plate with an interface heat dissipation material layer, a first chip having a first type of bump for connecting to the substrate and a second type of bump for connecting to the connection chip on the first surface, a second chip having a first type of bump for connecting to the substrate and a second type of bump for connecting to the connection chip on the first surface, and a connection chip; the first chip and the second chip are bonded to the heat dissipation carrier plate with the second surface facing the interface heat dissipation material layer, and the second type of bumps of the first chip and the second type of bumps of the second chip are opposite; the connection chip is flip-chip bonded to the second type of bumps of the first chip and the second type of bumps of the second chip;
[0029] The first chip frame is flip-chip bonded to the substrate, and the connection chip is accommodated in the accommodation space;
[0030] The back surface of the substrate facing away from the first chip frame has solder balls.
[0031] Optionally, the accommodation space is a groove.
[0032] The chip packaging method provided by this application includes preparing a first chip frame. The first chip frame includes a heat dissipation carrier plate with an interface heat dissipation material layer, a first chip with a first type of bumps for connecting to a substrate and a second type of bumps for connecting to a connecting chip on its first surface, a second chip with a first type of bumps for connecting to the substrate and a second type of bumps for connecting to the connecting chip on its first surface, and a connecting chip. The first chip and the second chip are bonded to the heat dissipation carrier plate with their second surfaces facing the interface heat dissipation material layer, and the second type of bumps of the first chip and the second type of bumps of the second chip are opposite to each other. The connecting chip is flip-chip bonded to the second type of bumps of the first chip and the second type of bumps of the second chip. Then, a substrate is prepared, and a receiving space for accommodating the connecting chip is provided on the substrate. Further, the first chip frame is flip-chip mounted on the substrate with the connecting chip facing the receiving space, so that the connecting chip is accommodated in the receiving space. Finally, balls are implanted on the back surface of the substrate facing away from the first chip frame to form solder balls. In this way, by preparing the first chip frame in advance and then flip-chip mounting the connecting chip on the substrate, since the heat dissipation carrier plate has a certain hardness, the generation of deformation can be avoided, the stress of the connecting chip can be reduced, and the yield of the chip structure can be improved. Description of the Drawings
[0033] Figure 1 It is a flowchart of the first embodiment of the chip packaging method provided by this application;
[0034] Figure 2 It is a cross-sectional view of the first chip frame shown in an exemplary embodiment of this application;
[0035] Figure 3 It is a plan view of the first chip frame shown in an exemplary embodiment of this application;
[0036] Figure 4 It is a schematic structural diagram of the first chip shown in an exemplary embodiment of this application;
[0037] Figure 5 It is a schematic structural diagram of the second chip shown in an exemplary embodiment of this application;
[0038] Figure 6 It is a schematic structural diagram of the prepared substrate shown in an exemplary embodiment of this application;
[0039] Figure 7A It is a schematic diagram of the implementation principle of flip-chip mounting the first chip frame on the substrate shown in an exemplary embodiment of this application;
[0040] Figure 7B It is a schematic diagram of the implementation principle of flip-chip mounting the first chip frame on the substrate shown in another exemplary embodiment of this application;
[0041] Figure 7C Schematic diagram of ball planting on the back surface of the substrate facing away from the first chip frame shown in an exemplary embodiment of the present application;
[0042] Figure 8A Schematic diagram of covering a heat dissipation cover on the side of the chip facing away from the first chip frame shown in an exemplary embodiment of the present application;
[0043] Figure 8B Schematic diagram of covering a heat dissipation cover on the side of the chip facing away from the first chip frame shown in another exemplary embodiment of the present application;
[0044] Figure 8C Schematic diagram of covering a heat dissipation cover on the side of the chip facing away from the first chip frame shown in another exemplary embodiment of the present application;
[0045] Figure 8D Schematic diagram of covering a heat dissipation cover on the side of the chip facing away from the first chip frame shown in another exemplary embodiment of the present application.
[0046] Figure 9 Schematic diagram of the chip structure shown in an exemplary embodiment of the present application;
[0047] Figure 10 Flow chart of the second embodiment of the chip packaging method provided by the present application;
[0048] Figure 11 Schematic diagram of the heat dissipation carrier shown in an exemplary embodiment of the present application;
[0049] Figure 12 Schematic diagram of the heat dissipation carrier shown in another exemplary embodiment of the present application;
[0050] Figure 13 Schematic diagram of bonding the first chip and the second chip to the chip fixing area shown in an exemplary embodiment of the present application;
[0051] Figure 14 Schematic diagram of filling shown in an exemplary embodiment of the present application;
[0052] Figure 15 Flow chart of the third embodiment of the chip packaging method provided by the present application;
[0053] Figure 16 Schematic diagram of the solder paste capsule film shown in an exemplary embodiment of the present application;
[0054] Figure 17 Schematic diagram of attaching the solder paste capsule film to the product to be packaged shown in an exemplary embodiment of the present application;
[0055] Figure 18 Schematic diagram of an intermediate product formed after attaching a solder paste capsule film to a product to be encapsulated, shown in an exemplary embodiment of the present application;
[0056] Figure 19 Schematic diagram of formed solder balls, shown in an exemplary embodiment of the present application.
[0057] Description of reference numerals:
[0058] 100: First chip frame;
[0059] 1: Heat dissipation carrier board;
[0060] 2: First chip;
[0061] 21: First side of the first chip;
[0062] 22: Second side of the first chip;
[0063] 211: First type of bumps on the first chip;
[0064] 212: Second type of bumps on the first chip;
[0065] 3: Second chip;
[0066] 31: First side of the second chip;
[0067] 32: Second side of the second chip;
[0068] 311: First type of bumps on the second chip;
[0069] 312: Second type of bumps on the second chip;
[0070] 4: Connecting chip;
[0071] 41: Back side of the connecting chip facing away from the first chip frame;
[0072] 5: Substrate;
[0073] 51: Accommodating space;
[0074] 52: Back side of the substrate facing away from the first chip frame
[0075] 6: Heat dissipation cover;
[0076] 7: Solder paste capsule film;
[0077] 71: Carrier film;
[0078] 72: Pattern film;
[0079] 721: First pattern
[0080] 73: Protective film
[0081] 74: Solder paste;
[0082] 8: Product to be encapsulated. Detailed implementation manners
[0083] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.
[0084] The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The singular forms "a", "the", and "said" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0085] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".
[0086] The following specific embodiments are given to introduce the technical solutions of the present application in detail.
[0087] Figure 1 It is a flowchart of the first embodiment of the chip encapsulation method provided by the present application. Please refer to Figure 1 , and the method includes:
[0088] S101. Prepare the first chip frame. The first chip frame includes a heat dissipation carrier plate with an interface heat dissipation material layer, a first chip with a first type of bumps for connecting to a substrate and a second type of bumps for connecting to a connecting chip on a first surface, a second chip with a first type of bumps for connecting to the substrate and a second type of bumps for connecting to the connecting chip on a first surface, and a connecting chip. The first chip and the second chip are bonded to the heat dissipation carrier plate with their second surfaces facing the interface heat dissipation material layer, and the second type of bumps of the first chip and the second type of bumps of the second chip are opposite to each other. The connecting chip is flip-chip bonded to the second type of bumps of the first chip and the second type of bumps of the second chip.
[0089] Figure 2 It is a cross-sectional view of the first chip frame shown in an exemplary embodiment of the present application. Figure 3 It is a plan view of the first chip frame shown in an exemplary embodiment of the present application. Please refer to Figure 2 and Figure 3 simultaneously. The first chip frame 100 includes a heat dissipation carrier plate 1, a first chip 2, a second chip 3, and a connecting chip 4.
[0090] Specifically, the heat dissipation carrier plate 1 is the basic part of the first chip frame 100, and it is a heat dissipation carrier plate with an interface heat dissipation material layer on one surface. This interface heat dissipation material layer is used for heat dissipation, that is, to effectively conduct the generated heat out to ensure that the temperature of the chip is within an acceptable range.
[0091] Specifically, in a possible implementation, the interface heat dissipation material layer can be made of materials such as nickel, tin, copper, gold, aluminum, silver, etc.; or, further, in another possible implementation, the interface heat dissipation material layer can be made of an alloy of nickel, tin, copper, gold, aluminum, and silver; further, in yet another possible implementation, the interface heat dissipation material layer can be made of graphene.
[0092] It should be noted that the heat dissipation carrier plate 1 is a high thermal conductivity plate-like structure with a certain thickness and a certain hardness, and it is not easily deformed, which can provide support for the first chip 2, the second chip 3, and the connecting chip 4 thereon to prevent the first chip 2, the second chip 3, and the connecting chip 4 from being deformed or damaged. Specifically, in a possible implementation, the heat dissipation carrier plate can be copper with nickel or gold plating on the surface, or, further, in another possible implementation, the heat dissipation carrier plate can be silicon, silicon carbide, diamond, etc. with titanium, nickel, or gold plating on the surface, which are high thermal conductivity materials.
[0093] Optionally, the heat dissipation carrier plate 1 can be a planar heat dissipation carrier plate with an interface heat dissipation material layer on one surface, or the heat dissipation carrier plate 1 is a groove-shaped heat dissipation carrier plate with grooves for accommodating chips; the grooves have an interface heat dissipation material layer.
[0094] It should be noted that Figure 4 is a schematic structural diagram of the first chip shown in an exemplary embodiment of the present application; please refer to Figure 4 , there are two types of bumps on the first surface 21 of the first chip 2, and these two types of bumps include the first type of bumps 211 for connecting to the substrate and the second type of bumps 212 for connecting to the connecting chip 4.
[0095] Similarly, Figure 5 is a schematic structural diagram of the second chip shown in an exemplary embodiment of the present application. Please refer to Figure 5 , the second chip 3 is similar to the first chip 2, and there are also two types of bumps on its first surface 31, and these two types of bumps include the first type of bumps 311 for connecting to the substrate and the second type of bumps 312 for connecting to the connecting chip 4.
[0096] Among them, the height of the first type of bumps 211 on the first chip 2 and the height of the first type of bumps 311 on the second chip 3 are equal to the first specified value; the height of the second type of bumps 212 on the first chip 2 and the height of the second type of bumps 312 on the second chip 3 are equal to the second specified value; the first specified value is equal to the second specified value; or, the first specified value is less than the second specified value; or the first specified value is greater than the second specified value.
[0097] It should be noted that the pitch and size of the second type of bumps may be different from those of the first type of bumps. For example, in a possible implementation, in one implementation, the pitch of the first type of bumps is 100 microns and the size is 80 microns, while the pitch of the second type of bumps is 40 microns and the size is 30 microns.
[0098] It should be noted that the first chip 2 and the second chip 3 are bonded to the heat dissipation carrier 1 in a manner that the second surface faces the interface heat dissipation material layer, and the second type of bumps 212 of the first chip 2 and the second type of bumps 312 of the second chip 3 are opposite to each other.
[0099] Specifically, referring to Figure 2 and Figure 3 , the first chip 2 is bonded to the heat dissipation carrier 1 in a manner that the second surface 22 faces the interface heat dissipation material layer, and the second chip 3 is also bonded to the heat dissipation carrier 1 in a manner that the second surface 32 faces the interface heat dissipation material layer, and the second type of bumps 212 of the first chip 2 and the second type of bumps of the second chip are opposite to each other.
[0100] It should be noted that, referring to the previous description, the heat dissipation carrier 1 has a certain thickness and hardness. Bonding the first chip 2 and the second chip 3 to the heat dissipation carrier 1 can not only avoid damage to the first chip 2 and the second chip 3, but also prevent deformation of the first chip 2 and the second chip 3, ensuring that the first chip 2 and the second chip 3 are in the same plane. In this way, the connection chip 4 can be flip-chip bonded to the first chip 2 and the second chip 3 conveniently and quickly, improving the efficiency of chip packaging. In addition, the stress on the connection chip 4 can also be reduced, improving the yield of the chip structure.
[0101] In addition, after the first chip and the second chip are bonded to the heat dissipation carrier in such a way that the second surface faces the interface heat dissipation material layer, a metal bonding interface can be formed. This metal bonding interface not only plays a role in fixing the chip but also has a heat conduction function.
[0102] Among them, the connection chip 4 is a key component for connecting between the first chip 2 and the second chip 3. It is flip-chip bonded (flip-chip bonding can be achieved by soldering or other connection methods) to the second type of bumps 212 of the first chip 2 and the second type of bumps 312 of the second chip 3 to form an electrical connection, realizing the electrical connection between these two chips.
[0103] It should be noted that the connection chip 4 can be a low-power chip or a high-power chip. In this embodiment, it is not limited thereto. The method provided in this embodiment can use either a high-power chip or a low-power chip as the connection chip, with wider adaptability.
[0104] It should be noted that flip-chip refers to the flip-chip technology of the chip, which means operating with the connection points of the chip facing down. For example, flip-chip bonding means connecting the chip with the connection points facing down to a substrate, carrier, circuit board, another chip, etc. (for example, the connection points of the chip can be connected to the connection points of other chips). Among them, the connection points can also be called pins, and bumps are a typical type of pins. In this article, flip-chip bonding refers to connecting the connection points of the connection chip 4 facing down to the second type of bumps 212 of the first chip 2 and the second type of bumps 312 of the second chip 3.
[0105] S102. Prepare a substrate; wherein, the substrate is provided with a receiving space for accommodating the connection chip.
[0106] Figure 6 This is a schematic structural diagram of the prepared substrate shown in an exemplary embodiment of the present application. Please refer to Figure 6 , a receiving space 51 is provided on the substrate. The receiving space 51 can be a through hole or a groove, and the size of the receiving space 51 matches the size of the connection chip 4.
[0107] Specifically, the substrate 5 generally refers to a high-density printed circuit board (Substrate) or a similar electronic component support structure. Various electronic components are carried on the substrate 5, including chips, connectors, and other circuit components, which are used to build the circuit of an electronic device. The substrate 5 is usually made of an insulating material, such as fiberglass-reinforced resin. The accommodation space 51 can be a through-hole or a groove formed on the substrate 5.
[0108] Furthermore, the size of the accommodation space 51 matches the size of the connection chip 4 for accommodating the connection chip into the accommodation space 51.
[0109] It should be noted that in this embodiment, the execution sequence of steps S101 and S102 is not limited. In one possible implementation, they can be executed simultaneously.
[0110] S103: In a manner that the connection chip faces the accommodation space, flip the first chip frame onto the substrate so that the connection chip is accommodated in the accommodation space.
[0111] Figure 7A FIG. [X] is a schematic diagram showing the implementation of flipping the first chip frame onto the substrate according to an exemplary embodiment of the present application. Figure 7B FIG. [Y] is a schematic diagram showing the implementation of flipping the first chip frame onto the substrate according to another exemplary embodiment of the present application; please refer to Figure 7A and Figure 7B simultaneously. Since the size of the pre-set accommodation space 51 matches the size of the connection chip 4, after flipping the first chip frame onto the substrate, it can be ensured that the connection chip 4 is accommodated in the accommodation space 51.
[0112] It should be noted that referring to Figure 7A and Figure 7B simultaneously, after flipping the first chip frame 100 onto the substrate 5, the first type of bumps on the first chip and the second type of bumps on the second chip are respectively connected to the substrate 5.
[0113] S104: Solder balls are implanted on the back surface of the substrate facing away from the first chip frame to form solder balls.
[0114] Figure 7C FIG. [Z] is a schematic diagram showing the implementation of implanting solder balls on the back surface of the substrate facing away from the first chip frame according to an exemplary embodiment of the present application. Please refer to Figure 7C simultaneously. Solder balls are implanted on the back surface 52 of the substrate 5 facing away from the first chip frame to form solder balls. It should be noted that the solder balls can be spheres, cylinders, or pads.
[0115] The chip packaging method provided by this application includes preparing a first chip frame. The first chip frame includes a heat dissipation carrier plate with an interface heat dissipation material layer, a first chip with a first type of bumps for connecting to a substrate and a second type of bumps for connecting to a connecting chip on its first surface, a second chip with a first type of bumps for connecting to the substrate and a second type of bumps for connecting to the connecting chip on its first surface, and a connecting chip. The first chip and the second chip are bonded to the heat dissipation carrier plate with their second surfaces facing the interface heat dissipation material layer, and the second type of bumps of the first chip and the second type of bumps of the second chip face each other. The connecting chip is flip-chip bonded to the second type of bumps of the first chip and the second type of bumps of the second chip. Then, a substrate is prepared, and a receiving space for accommodating the connecting chip is provided on the substrate. Further, the first chip frame is flip-chip mounted on the substrate with the connecting chip facing the receiving space, so that the connecting chip is accommodated in the receiving space. Finally, balls are implanted on the back surface of the substrate facing away from the first chip frame to form solder balls. In this way, by preparing the first chip frame in advance and then flip-chip mounting the connecting chip onto the substrate, since the heat dissipation carrier plate has a certain hardness, the generation of deformation can be avoided, the stress of the connecting chip can be reduced, and the yield of the chip structure can be improved.
[0116] Optionally, in a possible implementation manner of this application, the receiving space is a through hole. After step S103, the method further includes:
[0117] Covering a heat dissipation cover on the back surface of the connecting chip facing away from the first chip frame; wherein, the heat dissipation cover is also connected to the substrate.
[0118] Figure 8A This is the schematic diagram of the implementation of covering a heat dissipation cover on the side of the chip facing away from the first chip frame shown in an exemplary embodiment of this application; Figure 8B This is the schematic diagram of the implementation of covering a heat dissipation cover on the side of the chip facing away from the first chip frame shown in another exemplary embodiment of this application; Figure 8C This is the schematic diagram of the implementation of covering a heat dissipation cover on the side of the chip facing away from the first chip frame shown in another exemplary embodiment of this application; Figure 8D This is the schematic diagram of the implementation of covering a heat dissipation cover on the side of the chip facing away from the first chip frame shown in another exemplary embodiment of this application.
[0119] Please refer to Figures 8A to 8D simultaneously. Specifically, when the receiving space 51 on the substrate 5 is a through hole, a heat dissipation cover 6 can be covered on the back surface 41 of the connecting chip 4 facing away from the first chip frame 100.
[0120] It should be noted that the heat dissipation cover is an external covering for heat dissipation. It is usually made of a metal material with good heat conduction performance. The heat dissipation cover is placed on the back of the connection chip to effectively conduct and disperse the heat generated by the connection chip, maintain the temperature of the connection chip within a safe range, prevent overheating, and improve performance and reliability.
[0121] The method provided in this embodiment can effectively improve the heat dissipation performance of the connection chip by covering the heat dissipation cover on the back of the connection chip, thereby improving the performance and reliability of the connection chip. In addition, it can also enable the connection chip to be either a low-power chip or a high-power chip, improving adaptability.
[0122] Referring to the previous description, the height of the first type of bumps 211 on the first chip 2 and the height of the first type of bumps 311 on the second chip 3 are equal to the first specified value; the height of the second type of bumps 212 on the first chip 2 and the height of the second type of bumps 312 on the second chip 3 are equal to the second specified value; the first specified value is equal to the second specified value; or, the first specified value is less than the second specified value; or the first specified value is greater than the second specified value.
[0123] Please refer to Figure 8A , in Figure 8A the illustrated embodiment, the first specified value (the height of the first type of bumps) is equal to the second specified value (the height of the second type of bumps), and in Figure 8A the illustrated example, the back surface 41 of the connection chip 4 is lower than the back surface 52 of the substrate 5; the heat dissipation cover 6 is a convex-shaped heat dissipation cover having one protruding portion and two flush portions, the protruding portion is received in the through hole and covers the back surface 41 of the connection chip 4, and the flush portions are connected to the back surface 52 of the substrate 5.
[0124] It should be noted that by connecting the flush portion of the heat dissipation cover to the substrate (this connection is a reliable mechanical connection), in this way, the heat dissipation cover 6 not only has a heat dissipation effect, but also is used to support and hold the connection chip 4, limit the connection chip 4 in its initial position, and restrict the displacement of the connection chip 4 due to heat, thereby avoiding the problem that the connection between the connection chip 4 and the first chip and the second chip is disconnected due to the displacement of the connection chip 4. In this way, the stability and lifespan of the chip structure can be improved.
[0125] Please refer to Figure 8B , in Figure 8BIn the illustrated example, the first specified value is greater than the second specified value, and the connection chip 4 is close to the first chip 2 and the second chip 3. In this way, not only can the distances between the connection chip 4 and the first chip 2 and the second chip 3 be shortened to achieve short-distance signal transmission, but also the heat dissipation cover 6 can be made thicker to improve its heat dissipation performance (the thicker the heat dissipation cover, the better its heat dissipation performance).
[0126] Please continue to refer to Figure 8C , in Figure 8C the illustrated example, the first specified value is less than the second specified value. At this time, the connection chip 4 is slightly away from the first chip 2 and the second chip 3. In this way, the heat dissipation cover 6 can be made thinner. For example, when the connection chip is a low-power chip, the heat dissipation cover can be made thinner to save costs while meeting the heat dissipation requirements.
[0127] Please continue to refer to Figure 8D , in Figure 8D the illustrated example, the first specified value is less than the second specified value. At this time, the connection chip 4 is away from the first chip 2 and the second chip 3. In addition, in Figure 8D the illustrated example, the back surface 41 of the connection chip 4 is flush with the back surface 52 of the substrate 5; the heat dissipation cover 6 is a planar heat dissipation cover, and the planar heat dissipation cover 6 covers the through hole 51 to cover the back surface 41 of the connection chip 4 and is connected to the back surface 52 of the substrate 5.
[0128] It should be noted that referring to the previous description, by setting the heights of the first type of bumps and the second type of bumps, not only can the size of the connection chip be adapted, but also based on the power consumption of the connection chip, by adjusting the heights of the first type of bumps and the second type of bumps, the heat dissipation cover with a corresponding thickness can be adapted, with wide adaptability and strong scalability.
[0129] It should be noted that the thickness of the heat dissipation cover 6 is greater than the thickness of the connection chip to ensure the heat dissipation effect of the connection chip 4.
[0130] Figure 9 This is a schematic diagram of the chip structure shown in an exemplary embodiment of the present application. Please refer to Figure 9 , in Figure 9 the illustrated example, the accommodation space is a through hole. At this time, a heat dissipation cover can be covered on the connection chip to meet the heat dissipation requirements.
[0131] It should be noted that when the accommodation space on the substrate is a through hole, when forming solder balls on the back surface of the substrate, the height of the solder balls is higher than the lower surface of the heat dissipation cover to leave enough heat dissipation space for the heat dissipation cover.
[0132] In specific implementation, the thickness of the heat dissipation cover can be set according to actual heat dissipation requirements. Further, the height of the solder balls is matched with the thickness of the heat dissipation cover to leave sufficient heat dissipation space for the heat dissipation cover. For example, in a possible implementation, the thicker the heat dissipation cover, the greater the height difference between the solder balls and the lower surface of the heat dissipation cover (i.e., the higher the solder balls), so as to leave an appropriate heat dissipation space for the heat dissipation cover.
[0133] The method provided in this embodiment can meet the heat dissipation requirements of high-power connection chips by setting the accommodation space as a through hole and then covering a heat dissipation cover on the connection chip. That is, either high-power connection chips or low-power connection chips can be selected, and the adaptability is relatively wide.
[0134] Figure 10 This is a flowchart of the second embodiment of the chip packaging method provided by this application. Please refer to Figure 10 , based on the above embodiment, the preparation of the first chip frame includes:
[0135] S1001. Prepare a heat dissipation carrier; wherein, one side of the heat dissipation carrier has an interfacial heat dissipation material layer; the interfacial heat dissipation material layer constitutes a chip fixing area.
[0136] It should be noted that one side of the heat dissipation carrier has an interfacial heat dissipation material layer. It should be noted that the interfacial heat dissipation material layer is a material that can effectively conduct heat and is usually applied to the surface of the heat dissipation carrier to ensure good heat dissipation of the chip and other components.
[0137] Among them, the interfacial heat dissipation material layer constitutes the chip fixing area, which is used to support, fix, and dissipate heat from the chip. Usually, there are multiple such areas on the heat dissipation carrier to accommodate and process multiple chips. In this way, it can ensure that the chip can effectively dissipate heat under high-power conditions, thereby improving the performance and reliability of the electronic device.
[0138] Further, for each chip fixing area, a unique label can be set to identify the coordinates of the chip fixing area on the heat dissipation carrier. Accordingly, through this label, the fixed position of each chip on the heat dissipation carrier can be determined. Figure 11 This is a schematic diagram of the heat dissipation carrier shown in an exemplary embodiment of this application, Figure 12 This is a schematic diagram of the heat dissipation carrier shown in another exemplary embodiment of this application. Please refer to both Figure 11 and Figure 12 .
[0139] The heat dissipation carrier 1 is a planar heat dissipation carrier with an interfacial heat dissipation material layer on one side, or the heat dissipation carrier 1 is a groove-shaped heat dissipation carrier with a groove for accommodating chips; the groove has an interfacial heat dissipation material layer.
[0140] Optionally, the interface heat dissipation material on the interface heat dissipation material layer can be tin, gold, nickel, copper, etc., which can not only play a role in fixing the chip, but also provide high heat dissipation efficiency.
[0141] Optionally, the heat dissipation carrier 1 can be prepared from any of the following materials: silicon, diamond, aluminum nitride, and silicon carbide.
[0142] S1002. Prepare the first type of bumps and the second type of bumps on the first surfaces of the first chip and the second chip respectively.
[0143] Please refer to Figure 4 and Figure 5 , preparing two different types of bumps on the first surfaces of the first chip 2 and the second chip 3 is to meet different connection or transmission requirements. Among them, the first type of bumps is used to connect the substrate, and the second type of bumps is used to connect the chips.
[0144] S1003. Bond the first chip and the second chip to the chip fixing area with the second surfaces facing the interface heat dissipation material layer; wherein, the second type of bumps of the first chip and the second type of bumps of the second chip face each other.
[0145] It should be noted that the chip is permanently bonded to the heat dissipation carrier, and the subsequent process does not require a debonding process to remove the carrier, which saves the process, improves the yield, and reduces the cost.
[0146] Figure 13 This is the schematic diagram of the implementation of bonding the first chip and the second chip to the chip fixing area shown in an exemplary embodiment of the present application. Please refer to Figure 13 , specifically in implementation, the first chip 2 and the second chip 3 can be respectively welded to the chip fixing area, wherein, the second type of bumps 212 of the first chip 2 and the second type of bumps 312 of the second chip 3 face each other. By flipping the first chip 2 and the second chip 3 and bonding them in the chip fixing area, reliable electrical connection between them can be achieved, and it can be ensured that they are located above the interface heat dissipation material layer to effectively dissipate heat and maintain an appropriate working temperature.
[0147] In addition, for the first chip 2 and the second chip 3, another material layer (such as tin, gold, silver, copper, nickel, etc. and their alloys) adapted to the interface heat dissipation material layer corresponding to the heat dissipation carrier can be prepared on the back surfaces of the first chip 2 and the second chip 3, so as to facilitate the subsequent fixing of the first chip 2 and the second chip 3 on the heat dissipation carrier.
[0148] Optionally, in a possible implementation of the present application, the first chip 2 and the second chip 3 can be respectively soldered to the chip fixing area. For example, metals or alloys such as tin, gold, silver, copper, nickel, etc. are used to solder the first chip 2 and the second chip 3 to the chip fixing area.
[0149] It should be noted that in the method provided in this embodiment, by directly soldering the first chip and the second chip to the heat dissipation carrier board, since the heat dissipation carrier board has a certain hardness and thickness, deformation or damage of the first chip and the second chip can be avoided.
[0150] S1004. Flip-chip bond the connecting chip to the second type of bumps of the first chip and the second type of bumps of the second chip to form the first chip frame.
[0151] It should be noted that in a possible implementation of the present application, after the first chip frame 100 is formed, the areas of the connecting chip 4 opposite to the first chip 2 and the areas of the connecting chip 4 opposite to the second chip 3 can be filled.
[0152] Figure 14 This is the schematic diagram of the implementation of the filling shown in an exemplary embodiment of the present application. Please refer to Figure 14 , a specific material (possibly an insulating material or a packaging material) can be used to inject the material into these areas to achieve insulation, protection, strengthening of the connection, or other specific functions. Specifically, the filling material can be selected according to specific application requirements.
[0153] In the chip packaging method provided in this embodiment, by preparing a heat dissipation carrier board, wherein one surface of the heat dissipation carrier board has an interface heat dissipation material layer, the interface heat dissipation material layer constitutes a chip fixing area, and first type of bumps and second type of bumps are respectively prepared on the first surfaces of the first chip and the second chip. Further, the first chip and the second chip are bonded to the chip fixing area with the second surfaces facing the interface heat dissipation material layer, wherein the second type of bumps of the first chip and the second type of bumps of the second chip face each other. Finally, the connecting chip is flip-chip bonded to the second type of bumps of the first chip and the second type of bumps of the second chip to form the first chip frame. In this way, by first bonding the first chip and the second chip to the heat dissipation carrier board, deformation of the first chip and the second chip can be avoided. Further, when the connecting chip is bonded to the first chip and the second chip, at this time, the first chip and the second chip are not easily deformed, and the connecting chip can be very conveniently bonded, which can improve the efficiency.
[0154] Figure 15 This is the flowchart of the third embodiment of the chip packaging method provided by the present application. Please refer to Figure 15 , the method includes:
[0155] S1501. Prepare a heat dissipation carrier board; wherein, one side of the heat dissipation carrier board has an interfacial heat dissipation material layer; the interfacial heat dissipation material layer constitutes a chip fixing area.
[0156] S1502. Prepare first type bumps and second type bumps on the first surfaces of the first chip and the second chip respectively.
[0157] S1503. Bond the first chip and the second chip to the chip fixing area with the second surfaces facing the interfacial heat dissipation material layer; wherein, the second type bumps of the first chip and the second type bumps of the second chip face each other.
[0158] S1504. Flip-chip bond a connecting chip on the second type bumps of the first chip and the second type bumps of the second chip to form the first chip frame.
[0159] S1505. Prepare a substrate; wherein, a through hole for accommodating the connecting chip is provided on the substrate.
[0160] S1506. Flip-chip the first chip frame onto the substrate with the connecting chip facing the through hole so that the connecting chip is accommodated in the through hole.
[0161] S1507. Cover a heat dissipation cover on the back surface of the connecting chip facing away from the first chip frame.
[0162] S1508. Solder balls are implanted on the back surface of the substrate facing away from the first chip frame to form solder balls.
[0163] For the effects of this embodiment, please refer to the description in the previous embodiments and will not be elaborated here.
[0164] Optionally, in a possible implementation manner of the present application, the process of implanting solder balls on the back surface of the substrate facing away from the first chip frame may include:
[0165] (1) Prepare a solder paste capsule film; wherein, the solder paste capsule film includes a carrier film, a pattern film and a protective film stacked in sequence; the pattern film has a first pattern in the shape of a groove; the first pattern matches the second pattern of the product to be encapsulated; the first pattern is filled with solder paste.
[0166] Specifically, Figure 16 is a schematic diagram of the solder paste capsule film shown in an exemplary embodiment of the present application. Please refer to Figure 16, for the prepared solder paste capsule film of the present application, the solder paste capsule film 7 includes a carrier film 71, a pattern film 72, and a protective film 73 stacked in sequence. The pattern film 72 has a groove-like first pattern 721; the first pattern 721 matches the second pattern of the product to be encapsulated; the first pattern 721 is filled with solder paste 74.
[0167] It should be noted that in this case, the product to be encapsulated is Figures 8A to 8D the product that needs to have balls implanted as shown, and the back surface 52 of its substrate 5 has a second pattern, and the second pattern identifies the positions where it needs to have balls implanted.
[0168] Specifically, the process of preparing the solder paste capsule film may include:
[0169] 1. Press the pattern film on the carrier film, and prepare a groove-like first pattern on the pattern film that matches the second pattern of the product to be encapsulated;
[0170] 2. Brush solder paste on the pattern film so that the solder paste fills the first pattern;
[0171] 3. Press the protective film on the pattern film so that the solder paste is sealed in the first pattern to form a solder paste capsule film.
[0172] (2) In the manner that the protective film faces the first surface of the product to be encapsulated, attach the starting point of the solder paste capsule film to this first surface, and starting from the starting point, while using a roller to make the solder paste capsule film contact with the first surface, peel off the protective film, so that the solder paste capsule film with the protective film peeled off fits with the first surface. The first surface of the product to be encapsulated is the surface that has the second pattern.
[0173] In this case, the first surface of the product to be encapsulated is the back surface of the substrate.
[0174] Figure 17 This is the schematic diagram of the implementation of attaching the solder paste capsule film to the product to be encapsulated shown in an exemplary embodiment of the present application.
[0175] When specifically implemented, turn the prepared solder paste capsule film 7 over and invert it, that is, make the protective film 73 face the first surface of the product to be encapsulated 8, first attach the protective film 73 at one end of the solder paste capsule film 7 to the first surface. Further, starting from this attachment point, while using a roller to make the solder paste capsule film 7 contact with the first surface, slowly peel off the protective film 73 of the solder paste capsule film 7 (press and peel at the same time), so that the solder paste capsule film with the protective film 73 peeled off fits with the first surface.
[0176] It should be noted that Figure 17 the product to be encapsulated in Figures 8A to 8D is only for illustrative purposes, and the product to be encapsulated can have the morphology as shown.
[0177] Figure 18 Schematic diagram of an intermediate product formed after attaching a solder paste capsule film to a product to be encapsulated, shown in an exemplary embodiment of the present application. Please refer to Figure 18 , after attaching the solder paste capsule film 7 to the first surface (in this case, the first surface is the back surface of the substrate), the groove-like first pattern 721 on the graphic film 72 coincides with the second pattern on the first surface, and the solder paste 74 in the solder paste capsule film 7 is filled into the second pattern.
[0178] (3) Transfer the solder paste to the second pattern on the first surface and remove the carrier film;
[0179] (4) Using a reflow soldering process, form solder balls on the second pattern on the first surface and remove the graphic film.
[0180] Figure 19 Schematic diagram of the formed solder balls, shown in an exemplary embodiment of the present application. Please refer to Figure 19 , using this method, ball planting can be performed on the back surface of the substrate, and the formed solder balls are relatively uniform.
[0181] The method provided in this embodiment prepares a solder paste capsule film and finally forms solder balls using the solder paste capsule film. In this way, the first pattern in the graphic film can be used to uniformly form solder balls on the second pattern on the product to be encapsulated, which can improve the uniformity of the solder balls.
[0182] It should be noted that the solder balls on the front surface of the substrate and the solder balls connecting the front surface of the chip can also be formed by ball planting through the above method. In this embodiment, no detailed introduction will be given.
[0183] Corresponding to the foregoing embodiment of a chip packaging method, the present application also provides an embodiment of a chip structure. Please continue to refer to Figure 7C and Figure 9 , the chip structure includes a first chip frame 100 and an accommodation space for accommodating the connection chip;
[0184] Among them, the first chip frame 100 includes a heat dissipation carrier 1 having an interface heat dissipation material layer, a first chip 2 having a first type of bump for connecting to the substrate 5 and a second type of bump for connecting to the connecting chip 4 on the first surface, a second chip 3 having a first type of bump for connecting to the substrate 5 and a second type of bump for connecting to the connecting chip 4 on the first surface, and a connecting chip 4; the first chip 2 and the second chip 3 are bonded to the heat dissipation carrier in a manner that the second surfaces face the interface heat dissipation material layer, and the second type of bumps 212 of the first chip 2 and the second type of bumps 312 of the second chip 3 are opposite to each other; the connecting chip 4 is flip-chip bonded to the second type of bumps 212 of the first chip 2 and the second type of bumps 312 of the second chip 3;
[0185] The first chip frame 100 is flip-chip mounted on the substrate 5, and the connecting chip 4 is accommodated in the accommodation space 51;
[0186] The side of the substrate 5 away from the first chip frame 100 has solder balls.
[0187] Optionally, the height of the first type of bumps on the first chip and the height of the first type of bumps on the second chip are equal to a first specified value; the height of the first type of bumps on the first chip and the height of the second type of bumps on the second chip are equal to a second specified value;
[0188] The first specified value is equal to the second specified value; or, the first specified value is less than the second specified value; or the first specified value is greater than the second specified value.
[0189] Optionally, the heat dissipation carrier is a planar heat dissipation carrier with an interface heat dissipation material layer on one side, or the heat dissipation carrier is a groove-shaped heat dissipation carrier having a groove for accommodating chips, and the groove has an interface heat dissipation material layer.
[0190] Optionally, referring to Figure 7C , the accommodation space is a groove.
[0191] Optionally, referring to Figure 9 , the accommodation space is a through hole, and the chip structure further includes a heat dissipation cover, where,
[0192] The heat dissipation cover covers the connecting chip and is connected to the substrate.
[0193] Optionally, the back surface of the connecting chip is lower than the back surface of the substrate; the heat dissipation cover is a convex-shaped heat dissipation cover having one protruding portion and two flush portions, the protruding portion is accommodated in the through hole and covers the back surface of the connecting chip, and the flush portions are connected to the back surface of the substrate.
[0194] Optionally, the back surface of the connection chip is flush with the back surface of the substrate; the heat dissipation cover is a planar heat dissipation cover, and the planar heat dissipation cover covers the through hole to cover the back surface of the connection chip and is connected to the back surface of the substrate.
[0195] Optionally, the thickness of the heat dissipation cover is greater than the thickness of the connection chip.
[0196] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the scope of protection of the present application.
Claims
1. A chip packaging method, characterized in that, The method includes: Preparing a first chip frame; wherein, the first chip frame includes a heat dissipation carrier plate having an interface heat dissipation material layer, a first chip having a first type of bumps for connecting to a substrate and a second type of bumps for connecting to a connecting chip on a first surface, a second chip having a first type of bumps for connecting to the substrate and a second type of bumps for connecting to the connecting chip on a first surface, and a connecting chip; the first chip and the second chip are bonded to the heat dissipation carrier plate with a second surface facing the interface heat dissipation material layer, and the second type of bumps of the first chip and the second type of bumps of the second chip are opposite; the connecting chip is flip-chip bonded to the second type of bumps of the first chip and the second type of bumps of the second chip; Preparing a substrate; wherein, a receiving space for receiving the connecting chip is provided on the substrate; In a manner that the connecting chip faces the receiving space, flipping the first chip frame onto the substrate so that the connecting chip is received in the receiving space; Ball mounting on the back surface of the substrate facing away from the first chip frame to form solder balls.
2. The method according to claim 1, wherein The receiving space is a groove.
3. The method according to claim 1, characterized in that, The receiving space is a through hole; after flipping the first chip frame onto the substrate, the method further includes: Covering a heat dissipation cover on the back surface of the connecting chip facing away from the first chip frame; wherein, the heat dissipation cover is also connected to the substrate.
4. The method according to claim 1, characterized in that, The preparing the first chip frame includes: Preparing a heat dissipation carrier plate; wherein, one surface of the heat dissipation carrier plate has an interface heat dissipation material layer; the interface heat dissipation material layer constitutes a chip fixing area; Preparing a first type of bumps and a second type of bumps on the first surfaces of the first chip and the second chip respectively; Bonding the first chip and the second chip to the chip fixing area with a second surface facing the interface heat dissipation material layer; wherein, the second type of bumps of the first chip and the second type of bumps of the second chip are opposite; Flip-chip bonding a connecting chip to the second type of bumps of the first chip and the second type of bumps of the second chip to form the first chip frame.
5. The method according to claim 4, characterized in that The bonding the first chip and the second chip to the chip fixing area with a second surface facing the interface heat dissipation material layer includes: Welding the first chip and the second chip to the chip fixing area respectively.
6. The method according to claim 1, characterized in that, The heights of the first type of bumps on the first chip and the first type of bumps on the second chip are equal to a first specified value; the height of the first type of bumps on the first chip and the height of the second type of bumps on the second chip are equal to a second specified value; The first specified value is equal to the second specified value; or, the first specified value is less than the second specified value; Or the first specified value is greater than the second specified value.
7. The method according to claim 3, characterized in that, The back surface of the connecting chip is lower than the back surface of the substrate; the heat dissipation cover is a convex-shaped heat dissipation cover having one protruding portion and two flush portions, the protruding portion is received in the through hole and covers the back surface of the connecting chip, and the flush portions are connected to the back surface of the substrate.
8. The method according to claim 3, wherein The back surface of the connection chip is flush with the back surface of the substrate; the heat dissipation cover is a planar heat dissipation cover, and the planar heat dissipation cover covers the through hole to cover the back surface of the connection chip and is connected to the back surface of the substrate.
9. The method according to claim 7 or 8, characterized in that, The thickness of the heat dissipation cover is greater than the thickness of the connection chip.
10. A chip structure, characterized in that, The chip structure is prepared by using the chip packaging method according to any one of claims 1-9, and the chip structure includes a first chip frame and a substrate having an accommodation space; Wherein, Wherein, the first chip frame includes a heat dissipation carrier plate having an interface heat dissipation material layer, a first chip having a first type of bump for connecting to the substrate and a second type of bump for connecting to the connection chip on the first surface, a second chip having a first type of bump for connecting to the substrate and a second type of bump for connecting to the connection chip on the first surface, and a connection chip; the first chip and the second chip are bonded to the heat dissipation carrier plate with the second surface facing the interface heat dissipation material layer, and the second type of bumps of the first chip and the second type of bumps of the second chip are opposite; the connection chip is flip-chip bonded to the second type of bumps of the first chip and the second type of bumps of the second chip; The first chip frame is flip-chip mounted on the substrate, and the connection chip is accommodated in the accommodation space; The back surface of the substrate facing away from the first chip frame has solder balls.