Method for manufacturing multilayer wiring chip and superconducting quantum chip

Abstract

The invention discloses a manufacturing method of a multi-layer wiring chip and a superconducting quantum chip. The manufacturing method comprises the steps of providing a substrate; sequentially forming a superconducting grounding layer, a first superconducting layer and a second superconducting layer on the surface of the substrate; forming a dielectric structure wrapped with at least one superconducting wiring layer on the second superconducting layer, wherein the superconducting wiring layer is located above the predetermined area of the substrate; etching and removing the dielectric structure outside the predetermined region by adopting a first etching process taking the second superconducting layer as an etching cut-off layer to obtain a wiring structure; and etching and removing the second superconducting layer outside the wiring structure by adopting a second etching process taking the first superconducting layer as an etching cut-off layer to obtain the multi-layer wiring chip. According to the invention, the grounding superconducting metal on the lower layer can be prevented from being etched in the medium etching process.

Description

Technical Field

[0001] The present invention relates to the technical field of superconducting quantum chip manufacturing, and particularly to a manufacturing method of a multi-layer wiring chip and a superconducting quantum chip. Background Art

[0002] At present, the number of superconducting qubits integrated on a superconducting quantum chip is increasing, and the number of various transmission lines for superconducting qubits also increases accordingly, which may lead to more and more serious crosstalk between the transmission lines. In order to increase the number of transmission lines and reduce crosstalk at the same time, the industry proposes to perform multi-layer wiring locally, bury some transmission lines in the dielectric layer, and place the dielectric layer on the grounded superconducting metal plane.

[0003] However, in the actual process, after the dielectric layer is formed, the excess dielectric needs to be etched away. In order to ensure that the dielectric is etched cleanly, there will be a certain amount of over-etching, which will inevitably etch the underlying grounded superconducting metal, resulting in phenomena such as thinning of the thickness of the grounded superconducting metal, change in roughness, and plasma damage, thus affecting the performance of the superconducting quantum chip and even causing performance failure. Summary of the Invention

[0004] The purpose of the present invention is to provide a manufacturing method of a multi-layer wiring chip and a superconducting quantum chip to solve the problem that the underlying grounded superconducting metal is easily etched in the prior art, and to avoid the etching of the underlying grounded superconducting metal during the dielectric etching process.

[0005] To solve the above technical problems, the present invention provides a manufacturing method of a multi-layer wiring chip, including:

[0006] Providing a substrate;

[0007] Successively forming a superconducting grounding layer, a first superconducting layer, and a second superconducting layer on the surface of the substrate;

[0008] Forming a dielectric structure wrapped with at least one superconducting wiring layer on the second superconducting layer, and the superconducting wiring layer is located above a predetermined area of the substrate;

[0009] Using a first etching process with the second superconducting layer as the etching stop layer to etch away the dielectric structure outside the predetermined area to obtain a wiring structure;

[0010] Using a second etching process with the first superconducting layer as the etching stop layer to etch away the second superconducting layer outside the wiring structure to obtain a multi-layer wiring chip.

[0011] Preferably, the surface of the substrate has grooves, and the predetermined area is located within the range where the grooves are located.

[0012] Preferably, the step of sequentially forming a superconducting ground layer, a first superconducting layer, and a second superconducting layer on the substrate surface includes:

[0013] Forming a superconducting ground layer on the substrate surface by electron beam evaporation;

[0014] Forming a first superconducting layer on the surface of the superconducting ground layer by magnetron sputtering;

[0015] Forming a second superconducting layer on the surface of the first superconducting layer by electron beam evaporation.

[0016] Preferably, the number of the superconducting wiring layers is one, and the step of forming a dielectric structure wrapped with at least one superconducting wiring layer on the second superconducting layer includes:

[0017] Forming a base dielectric layer on the surface of the second superconducting layer by electron beam evaporation;

[0018] Forming a superconducting wiring layer on the base dielectric layer by lift-off process;

[0019] Forming a sealing dielectric layer wrapping the superconducting wiring layer on the base dielectric layer by electron beam evaporation to obtain a dielectric structure.

[0020] Preferably, the number of the superconducting wiring layers is multiple, and the step of forming a dielectric structure wrapped with at least one superconducting wiring layer on the second superconducting layer includes:

[0021] Forming a base dielectric layer on the surface of the second superconducting layer by electron beam evaporation;

[0022] Forming a superconducting wiring layer on the base dielectric layer by lift-off process;

[0023] Forming a sealing dielectric layer wrapping the superconducting wiring layer on the base dielectric layer by electron beam evaporation;

[0024] Taking the sealing dielectric layer as a new base dielectric layer, repeating the step of forming a superconducting wiring layer on the base dielectric layer by lift-off process until the number of layers of the superconducting wiring layer reaches a preset value to obtain a dielectric structure.

[0025] Preferably, the step of etching away the dielectric structure outside the predetermined area by a first etching process using the second superconducting layer as an etching stop layer to obtain a wiring structure includes:

[0026] Forming a photoresist layer on the surface of the dielectric structure;

[0027] Performing photolithography on the photoresist layer to form a mask pattern exposing the area outside the predetermined area;

[0028] Use a first etching process with the second superconducting layer as the etching stop layer to etch away the dielectric structure exposed by the mask pattern, obtaining a wiring structure.

[0029] Preferably, the first etching process is a dry etching process, the etching gas used in the first etching process is a fluorine-based gas, the second etching process is a wet etching process, and the etching solution used in the second etching process is a mixed solution of phosphoric acid, nitric acid, and acetic acid.

[0030] Preferably, the manufacturing method further includes:

[0031] Form a third superconducting layer on the outer surface of the wiring structure, so that the third superconducting layer and the second superconducting layer below the wiring structure form a shielding cavity.

[0032] Preferably, the material of the first superconducting layer is TiN, Ta, Nb, or NbTiN, the materials of the superconducting ground layer, the superconducting wiring layer, and the second superconducting layer are aluminum, and the material of the dielectric structure is α-Si, SIO2, or Ge.

[0033] To solve the above technical problems, the present invention also provides a superconducting quantum chip, including a first chip and a second chip connected in a flip-chip manner. The first chip is a multi-layer wiring chip obtained by using the manufacturing method of the multi-layer wiring chip according to any one of the foregoing. The wiring structure of the first chip faces the second chip, and the second chip is electrically connected to the first chip through the first superconducting layer outside the predetermined area.

[0034] Different from the prior art, the manufacturing method of the multi-layer wiring chip provided by the present invention forms two superconducting layers on the superconducting ground layer, and disposes the dielectric structure wrapped with the superconducting wiring layer on the superconducting layer. When etching the dielectric structure, the uppermost superconducting layer serves as an etching stop layer to protect the underlying grounding superconducting layer, thereby avoiding etching of the underlying grounding superconducting metal during the dielectric etching process.

[0035] The superconducting quantum chip provided by the present invention uses the multi-layer wiring chip obtained by the manufacturing method of the multi-layer wiring chip described above, which belongs to the same inventive concept as the manufacturing method of the multi-layer wiring chip, and thus has the same beneficial effects, which will not be elaborated here. Description of the Drawings

[0036] Figure 1 It is a schematic flow chart of the manufacturing method of the multi-layer wiring chip provided by an embodiment of the present invention.

[0037] Figures 2a to 2e It is a schematic process diagram of the manufacturing method of the multi-layer wiring chip according to an embodiment of the present invention.

[0038] Figure 3 Schematic diagram of the structure of a superconducting quantum chip provided by another embodiment of the present invention. Specific embodiments

[0039] The specific embodiments of the present invention will be described in more detail below with reference to the schematic diagrams. The advantages and features of the present invention will be clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0040] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0041] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0042] As the number of superconducting qubits integrated on a superconducting quantum chip increases, the distribution of transmission lines on the superconducting quantum chip tends to be dense. However, the increase in the number of transmission lines leads to an increase in crosstalk between the transmission lines, which may seriously affect the performance and reliability of the superconducting qubits. To reduce the negative impact caused by crosstalk between transmission lines and solve the problem of the increase in chip size as the number of transmission lines increases, current superconducting quantum chips usually perform multi-layer wiring in a local area. Specifically, part of the transmission lines are buried in the dielectric layer and are on different layers from other transmission lines (such as the most common grounded superconducting metal), and then the dielectric layer is selectively etched to form a multi-layer wiring structure in the local area. However, when etching the dielectric layer, in order to completely remove the dielectric, there will be a certain amount of over-etching, which inevitably causes etching of the grounded superconducting metal below the dielectric layer.

[0043] Please refer to Figure 1 , an embodiment of the present invention provides a manufacturing method for a multi-layer wiring chip, and the manufacturing method includes the following steps:

[0044] S1: Provide a substrate.

[0045] Among them, the substrate can be selected from low-loss high-resistance materials, such as silicon, sapphire, etc.

[0046] S2: Form a superconducting ground layer, a first superconducting layer, and a second superconducting layer on the substrate surface in sequence.

[0047] Among them, the superconducting ground layer, the first superconducting layer, and the second superconducting layer are all superconducting metals. Exemplarily, as Figure 2a shown, it is a cross-sectional structure diagram after forming the superconducting ground layer, the first superconducting layer, and the second superconducting layer on the substrate. A stacked metal structure of a superconducting ground layer 20, a first superconducting layer 30, and a second superconducting layer 40 is formed on the substrate 10 in sequence.

[0048] S3: Form a dielectric structure wrapped with at least one superconducting wiring layer on the second superconducting layer, and the superconducting wiring layer is located above a predetermined area of the substrate.

[0049] Among them, the material of the dielectric structure is a dielectric with characteristics such as low loss, excellent insulation performance, thermal stability, and chemical stability, and the superconducting wiring layer is located inside the dielectric structure. In an actual application, the thickness of the superconducting wiring layer can be set to 100 nm. Exemplarily, as Figure 2b shown, it is a cross-sectional structure diagram after forming the dielectric structure on the second superconducting layer. The dielectric structure 50 is formed on the second superconducting layer 40, the superconducting wiring layer 60 is located above a predetermined area C of the substrate 10, and the dielectric structure 50 wraps the superconducting wiring layer 60 inside. If there are multiple superconducting wiring layers 60, then the multiple superconducting wiring layers 60 are located on different layers, that is, different superconducting wiring layers 60 are separated by the dielectric.

[0050] In this embodiment, the material of the first superconducting layer is TiN, Ta, Nb, or NbTiN, the materials of the superconducting ground layer, the superconducting wiring layer, and the second superconducting layer are aluminum, and the material of the dielectric structure is α-Si, SIO2, or Ge.

[0051] S4: Use a first etching process with the second superconducting layer as the etching stop layer to etch away the dielectric structure outside the predetermined area to obtain a wiring structure.

[0052] Among them, the first etching process can use any etching process that is easy to etch the dielectric structure and resistant to etching the second superconducting layer. For example, the first etching process is a dry etching process, and the etching gas used in the first etching process is a fluorine-based gas. When the material of the dielectric structure is α-Si and the material of the second superconducting layer is aluminum, the etching rate of the fluorine-based gas on aluminum is very slow. Therefore, as long as the thickness of the second superconducting layer is sufficient, it can protect the underlying metal from being etched. In an actual application, the thickness of the second superconducting layer is 100 nm, and the thickness of the dielectric structure is 6 um. Exemplarily, as Figure 2cAs shown in the figure, it is a cross-sectional structure diagram of etching a dielectric structure to obtain a wiring structure. The part of the dielectric structure 50 outside the predetermined area C is etched away, thereby exposing the second superconducting layer 40, and a wiring structure 70 is obtained within the preset area C. The second superconducting layer 40 will be etched more or less during the etching process of the dielectric structure 50, but the second superconducting layer 40 will not affect the performance of the superconducting quantum chip, and even if the second superconducting layer 40 is etched, there is no need to consider it.

[0053] S5: Use a second etching process with the first superconducting layer as the etching stop layer to etch away the second superconducting layer outside the wiring structure to obtain a multi-layer wiring chip.

[0054] Among them, the second etching process can adopt any etching process that is easy to etch the second superconducting layer and resistant to etching the first superconducting layer, which requires different materials for the first superconducting layer and the second superconducting layer. For example, when the second etching process is a wet etching process, the etching solution used in the second etching process is a mixed solution of phosphoric acid, nitric acid, and acetic acid, the material of the first superconducting layer is TiN, and the material of the second superconducting layer is aluminum, the mixed solution hardly reacts with the first superconducting layer. Therefore, the first superconducting layer can protect the underlying metal from being etched. In a practical application, the thickness of the first superconducting layer is 50 nm. Exemplarily, as Figure 2d As shown in the figure, it is a cross-sectional structure diagram after etching the second superconducting layer to obtain a multi-layer wiring chip. The second superconducting layer 40 outside the coverage area of the wiring structure 70 is etched away, but the second superconducting layer 40 within the coverage range of the wiring structure 70 is protected and will not be etched. The part of the dielectric structure 50 outside the predetermined area C is etched away, thereby exposing the second superconducting layer 40, and thus exposing the first superconducting layer 30 outside the coverage area of the wiring structure 70. The superconducting wiring layer 60 and the ground superconducting layer 20 are distributed on different layers, thereby obtaining a multi-layer wiring chip.

[0055] Since the multi-layer wiring chip has an exposed first superconducting layer, the first superconducting layer can be selectively etched to obtain or other transmission lines, resonators, etc. can be further fabricated on the first superconducting layer.

[0056] In order to further avoid the multi-layer wiring chip from being affected by external electromagnetic fields, in this embodiment, the manufacturing method further includes:

[0057] S6: Form a third superconducting layer on the outer surface of the wiring structure, so that the third superconducting layer and the second superconducting layer below the wiring structure form a shielding cavity.

[0058] Exemplarily, as Figure 2eAs shown, it is a cross-sectional structure diagram after forming a third superconducting layer on the outer surface of the wiring structure. If the cross-sectional shape of the wiring structure 70 is a regular rectangle, then the third superconducting layer 80 is formed on the top surface and two side surfaces of the wiring structure 70. The third superconducting layer 80 is basically formed by a deposition process. Due to the continuity of the coating, the third superconducting layer 80 will be connected to the second superconducting layer 40 covered by the wiring structure 70. Thus, the third superconducting layer 80 and the second superconducting layer 40 below the wiring structure 70 form a shielding cavity to electromagnetically isolate the superconducting wiring layer 60 by using the shielding cavity.

[0059] Since the wiring structure is only formed in a partial area of the multi-layer wiring chip, there is a height difference between the substrate surface and the wiring structure, and this height difference may affect the subsequent processes. For example, when a photoresist needs to be coated on the substrate surface to form other structures later, this height difference will cause problems such as uneven coating of the photoresist. In order to reduce the height difference, in some other embodiments of the present application, the substrate surface has grooves, and the predetermined area is within the range where the grooves are located.

[0060] Exemplarily, as Figures 2a to 2e shown, the substrate 10 surface has grooves 11, the predetermined area C is within the range where the grooves 11 are located, the wiring structure 70 is within the grooves 11, and the superconducting wiring layer 60 is also within the grooves 11. Since the wiring structure 70 is at the bottom of the grooves 11, the height difference between the wiring structure 70 and the substrate 10 surface can be reduced, thereby reducing or avoiding the influence on the subsequent processes. In order to facilitate the superconducting ground layer, the first superconducting layer, and the second superconducting layer to better cover the substrate surface, the side surface of the grooves 11 can be set as an inclined surface, that is, the grooves 11 are of a structure that is wider at the top and narrower at the bottom.

[0061] The superconducting ground layer, the first superconducting layer, and the second superconducting layer are all superconducting metals and can be prepared by a deposition process. Specifically, the steps of sequentially forming the superconducting ground layer, the first superconducting layer, and the second superconducting layer on the substrate surface, that is, step S2: include;

[0062] S21: Form a superconducting ground layer on the substrate surface by an electron beam evaporation process;

[0063] S22: Form a first superconducting layer on the surface of the superconducting ground layer by a magnetron sputtering process;

[0064] S23: Form a second superconducting layer on the surface of the first superconducting layer by an electron beam evaporation process.

[0065] The number of superconducting wiring layers can be set according to actual needs, and can be one layer or multiple layers.

[0066] When the number of superconducting wiring layers is one layer, the steps of forming a dielectric structure wrapped with at least one superconducting wiring layer on the second superconducting layer, that is, step S3, include:

[0067] S31A: Form a base dielectric layer on the surface of the second superconducting layer by using an electron beam evaporation process;

[0068] S32A: Form a superconducting wiring layer on the base dielectric layer by using a lift-off process;

[0069] S33A: Form a sealing dielectric layer that wraps the superconducting wiring layer on the base dielectric layer to obtain a dielectric structure.

[0070] Among them, the base dielectric layer and the sealing dielectric layer are made of the same material, and are formed by using the same process. Moreover, the thicknesses of both can also be the same. For example, the thicknesses are both 3 μm, so as to form a dielectric structure with a thickness of 6 μm.

[0071] When the number of superconducting wiring layers is multiple, the step of forming a dielectric structure that wraps at least one layer of superconducting wiring layer on the second superconducting layer, that is, step S3, includes:

[0072] S31B: Form a base dielectric layer on the surface of the second superconducting layer by using an electron beam evaporation process;

[0073] S32B: Form a superconducting wiring layer on the base dielectric layer by using a lift-off process;

[0074] S33B: Form a sealing dielectric layer that wraps the superconducting wiring layer on the base dielectric layer by using an electron beam evaporation process;

[0075] S34B: Take the sealing dielectric layer as the new base dielectric layer, and repeatedly use the lift-off process to form a superconducting wiring layer on the base dielectric layer until the number of layers of the superconducting wiring layer reaches a preset value to obtain a dielectric structure.

[0076] Among them, assuming that the superconducting wiring layer is 2 layers, then S32B and S33B need to be carried out twice, so that there are 2 layers of sealing dielectric layers. The first superconducting wiring layer is wrapped between the base dielectric layer and the first sealing dielectric layer, and the second superconducting wiring layer is wrapped between the first sealing dielectric layer and the second sealing dielectric layer.

[0077] In this embodiment, the wiring structure can be obtained by combining a photolithography process and a first etching process. Specifically, the step of using a first etching process with the second superconducting layer as an etching stop layer to etch away the dielectric structure outside a predetermined area to obtain a wiring structure, that is, step S4 includes:

[0078] S41: Form a photoresist layer on the surface of the dielectric structure;

[0079] S42: Perform photolithography on the photoresist layer to form a mask pattern that exposes the area outside the predetermined area;

[0080] S43: Use a first etching process with the second superconducting layer as the etching stop layer to etch away the dielectric structure exposed by the mask pattern, obtaining a wiring structure.

[0081] Among them, after the photoresist layer is lithographed, only the photoresist above the predetermined area remains, and the photoresist in the area outside the predetermined area is removed, thereby forming a mask pattern that exposes the area outside the predetermined area. When etching using the first etching process, the dielectric structure protected by the mask pattern will not be etched, and only the exposed dielectric structure is etched away, thereby obtaining a wiring structure.

[0082] In the above manner, the manufacturing method of the multi-layer wiring chip in this embodiment first forms a first superconducting layer and a second superconducting layer on the grounded superconducting layer, and then forms a dielectric structure wrapped with at least one superconducting wiring layer on the second superconducting layer. When etching the dielectric structure to obtain a wiring structure, the second superconducting layer serves as the etching stop layer and can protect the grounded superconducting layer. When etching the wiring structure, the first superconducting layer serves as the etching stop layer and can protect the grounded superconducting layer, thereby avoiding the etching of the underlying grounded superconducting metal during the dielectric etching process.

[0083] Please refer to Figure 3 , another embodiment of the present invention further provides a superconducting quantum chip. The superconducting quantum chip includes a first chip 100 and a second chip 200 connected in a flip-chip manner. The first chip 100 is a multi-layer wiring chip obtained by using the manufacturing method of the multi-layer wiring chip in the foregoing embodiment. The wiring structure of the first chip 100 faces the second chip 200, and the second chip 200 is electrically connected to the first chip 100 through the first superconducting layer 30 outside the predetermined area C. For example, indium pillars 101 for electrical connection are provided on the first superconducting layer 30.

[0084] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example" or "specific example" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0085] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art within the technical field, without departing from the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present invention, all of which belong to the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A manufacturing method of a multi-layer wiring chip, characterized in that, Including: Providing a substrate; Successively forming a superconducting ground layer, a first superconducting layer, and a second superconducting layer on the surface of the substrate; Forming a dielectric structure wrapped with at least one superconducting wiring layer on the second superconducting layer, the superconducting wiring layer being located above a predetermined area of the substrate; Using a first etching process with the second superconducting layer as an etching stop layer to etch away the dielectric structure outside the predetermined area to obtain a wiring structure; Using a second etching process with the first superconducting layer as an etching stop layer to etch away the second superconducting layer outside the wiring structure to obtain a multi-layer wiring chip.

2. The manufacturing method according to claim 1, wherein The surface of the substrate has grooves, and the predetermined area is located within the range where the grooves are located.

3. The manufacturing method according to claim 1, wherein The step of successively forming a superconducting ground layer, a first superconducting layer, and a second superconducting layer on the surface of the substrate includes: Forming a superconducting ground layer on the surface of the substrate using an electron beam evaporation process; Forming a first superconducting layer on the surface of the superconducting ground layer using a magnetron sputtering process; Forming a second superconducting layer on the surface of the first superconducting layer using an electron beam evaporation process.

4. The manufacturing method according to claim 1, characterized in that, The number of the superconducting wiring layers is one layer. The step of forming a dielectric structure wrapped with at least one superconducting wiring layer on the second superconducting layer includes: Forming a base dielectric layer on the surface of the second superconducting layer using an electron beam evaporation process; Forming a superconducting wiring layer on the base dielectric layer using a lift-off process; Forming a sealing dielectric layer wrapping the superconducting wiring layer on the base dielectric layer using an electron beam evaporation process to obtain a dielectric structure.

5. The manufacturing method according to claim 1, characterized in that, The number of the superconducting wiring layers is multiple layers. The step of forming a dielectric structure wrapped with at least one superconducting wiring layer on the second superconducting layer includes: Forming a base dielectric layer on the surface of the second superconducting layer using an electron beam evaporation process; Forming a superconducting wiring layer on the base dielectric layer using a lift-off process; Forming a sealing dielectric layer wrapping the superconducting wiring layer on the base dielectric layer using an electron beam evaporation process; Taking the sealing dielectric layer as a new base dielectric layer, repeating the step of forming a superconducting wiring layer on the base dielectric layer using the lift-off process until the number of layers of the superconducting wiring layer reaches a preset value to obtain a dielectric structure.

6. The manufacturing method according to claim 1, characterized in that, The step of using a first etching process with the second superconducting layer as an etching stop layer to etch away the dielectric structure outside the predetermined area to obtain a wiring structure includes: Forming a photoresist layer on the surface of the dielectric structure; Performing photolithography on the photoresist layer to form a mask pattern exposing the area outside the predetermined area; Using a first etching process with the second superconducting layer as an etching stop layer to etch away the dielectric structure exposed by the mask pattern to obtain a wiring structure.

7. The manufacturing method according to claim 1, wherein The first etching process is a dry etching process, the etching gas used in the first etching process is a fluorine-based gas, the second etching process is a wet etching process, and the etching solution used in the second etching process is a mixed solution of phosphoric acid, nitric acid, and acetic acid.

8. The manufacturing method according to claim 1, characterized in that, The manufacturing method further includes: Forming a third superconducting layer on the outer surface of the wiring structure, so that the third superconducting layer and the second superconducting layer below the wiring structure form a shielding cavity.

9. The manufacturing method according to any one of claims 1 to 8, characterized in that, The material of the first superconducting layer is TiN, Ta, Nb or NbTiN, the materials of the superconducting ground layer, the superconducting wiring layer and the second superconducting layer are aluminum, and the material of the dielectric structure is α-Si, SIO2 or Ge.

10. A superconducting quantum chip, characterized in that, It includes a first chip and a second chip connected in a flip-chip manner. The first chip is a multi-layer wiring chip obtained by using the manufacturing method of the multi-layer wiring chip according to any one of claims 1 to 9. The wiring structure of the first chip faces the second chip, and the second chip is electrically connected to the first chip through the first superconducting layer outside the predetermined area.

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