Methods of forming interconnect structures and related semiconductor processing systems and structures

Abstract

A method for forming an interconnect structure and a semiconductor processing system for forming an interconnect structure are disclosed. The disclosed method includes forming a conductive element in a conductive layer and forming a passivation layer on the conductive element. The disclosed method further includes removing the passivation layer prior to forming the low dielectric constant layer in the trench to prevent process-induced damage in the low dielectric constant layer. The disclosed semiconductor processing system includes first, second and third reaction chambers and a transfer module for forming an interconnect structure.

Description

Technical Field

[0001] The present disclosure generally relates to the fields of semiconductor processing methods, related structures, and semiconductor processing systems, as well as the fields of device and integrated circuit fabrication. More specifically, the present disclosure generally relates to methods for forming interconnect structures including low dielectric constant layers suitable for fabricating electronic devices, semiconductor processing systems for forming interconnect structures, and related structures including interconnect structures. Background Art

[0002] During the fabrication of devices (such as semiconductor devices), it is generally desirable to deposit a low dielectric constant (low-k) material layer, such as to fill features (such as trenches or gaps) on the surface of a substrate. For example, low-k materials can be used as intermetal dielectric layers, gap fillers during the back-end-of-line process, insulating layers, or for other applications.

[0003] During device fabrication processing, such as during the fabrication of interconnect structures, low dielectric constant layers are susceptible to process-induced damage. Process-induced damage to the low dielectric constant layers in the interconnect structures can cause an undesired shift in the dielectric constant of the material.

[0004] Accordingly, there is a general need for methods of forming interconnect structures including low dielectric constant layers that are free or substantially free of process-induced damage.

[0005] Any discussion set forth in this section, including discussions of problems and solutions, has been included in the present disclosure solely to provide background for the present disclosure and should not be construed as an admission that any or all of the discussion was known at the time the invention was made or constitutes prior art. Summary of the Invention

[0006] This summary of the invention introduces some concepts in a simplified form that will be further described in detail below. This summary of the invention is not necessarily intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0007] Various embodiments of the present disclosure relate to methods for forming interconnect structures including low dielectric constant layers, and semiconductor processing systems configured and arranged to form interconnect structures including low dielectric constant layers. As will be described in more detail below, the methods described herein are capable of forming interconnect structures including low dielectric constant layers that are free or substantially free of process-induced damage.

[0008] In one aspect, a method of forming an interconnect structure on a substrate including a conductive layer is disclosed. The method includes forming a plurality of trenches in the conductive layer, the trenches extending through the conductive layer to the substrate, thereby forming a plurality of conductive elements, forming a passivation layer on the plurality of conductive elements, transferring the substrate from a first semiconductor processing system to a second semiconductor processing system, removing the passivation layer and filling the plurality of trenches with a low dielectric constant layer.

[0009] In some embodiments, the steps of forming a plurality of trenches in the conductive layer and forming a passivation layer are performed in a first semiconductor processing system.

[0010] In some embodiments, the step of forming a passivation layer is performed in a first semiconductor processing system.

[0011] In some embodiments, after forming the passivation layer, the substrate is transferred from a first semiconductor processing system to a second semiconductor processing system.

[0012] In some embodiments, the steps of removing the passivation layer and filling the plurality of trenches with a low dielectric constant layer are performed in a second semiconductor processing system.

[0013] In some embodiments, the steps of removing the passivation layer and filling the plurality of trenches with a low dielectric constant layer are performed in a single reaction chamber.

[0014] In some embodiments, the passivation layer is deposited sealingly on the plurality of trenches and the plurality of conductive elements, thereby sealing the plurality of trenches and the plurality of conductive elements.

[0015] In some embodiments, the passivation layer is selected from elemental metals such as tungsten, molybdenum, ruthenium or tantalum, nitrides such as silicon nitride, titanium nitride or tantalum nitride, oxides such as silicon oxide or aluminum oxide, or carbides such as titanium carbide or tantalum carbide.

[0016] In one aspect, a method of forming an interconnect structure on a substrate including a device region is disclosed. The method includes depositing a conductive layer on the substrate, etching a plurality of trenches in the conductive layer, the trenches extending through the conductive layer to the substrate, thereby forming a non-planar surface including a plurality of conductive elements and a plurality of trenches, depositing a passivation layer on the non-planar surface, transferring the substrate from a first semiconductor processing system to a second semiconductor processing system, etching the passivation layer to remove the passivation layer and expose the non-planar surface, and depositing a low dielectric constant layer directly on the non-planar surface to fill the plurality of trenches with the low dielectric constant layer.

[0017] In some embodiments of forming the interconnect structure, the step of depositing a passivation layer is performed in a first semiconductor processing system.

[0018] In some embodiments of forming the interconnect structure, after forming the passivation layer, the substrate is transferred from a first semiconductor processing system to a second semiconductor processing system.

[0019] In some embodiments of forming an interconnect structure, the steps of etching a passivation layer and depositing a low dielectric constant layer are performed in a second semiconductor processing system.

[0020] In some embodiments of forming an interconnect structure, the steps of etching a passivation layer and depositing a low dielectric constant layer are performed in a single reaction chamber.

[0021] In another aspect, a semiconductor processing system is disclosed. The semiconductor processing system includes: a first reaction chamber configured and arranged to etch a passivation layer disposed on a non-planar surface of a substrate, the non-planar surface including a plurality of conductive elements and a plurality of trenches; a second reaction chamber configured and arranged to perform a pre-treatment process on the non-planar surface before depositing a low dielectric constant layer on the non-planar surface; a third reaction chamber configured and arranged to deposit a low dielectric constant layer on the non-planar surface; a transfer module configured and arranged to move the substrate between the first reaction chamber, the second reaction chamber, and the third reaction chamber while maintaining the substrate in a vacuum or inert gas environment; one or more precursor / reactant sources operably coupled to each of the first reaction chamber, the second reaction chamber, and the third reaction chamber; and a controller configured and arranged to cause the semiconductor processing system to form an interconnect structure.

[0022] In some embodiments of the semiconductor processing system, the first reaction chamber and the third reaction chamber include a single reaction chamber configured and arranged to etch a passivation layer and deposit a low dielectric constant layer.

[0023] In some embodiments, the semiconductor processing system further includes a metrology chamber configured and arranged to inspect the substrate after etching the passivation layer and / or after depositing the low dielectric constant layer.

[0024] In yet another aspect, a method of forming an interconnect structure on a substrate including a device region is disclosed. The method includes depositing a conductive layer on the substrate, forming a patterned masking material on a top surface of the conductive layer to form a plurality of masking regions and a plurality of unmasked regions, etching exposed regions of the conductive layer through the plurality of unmasked regions to form a plurality of trenches in the conductive layer, the trenches extending through the conductive layer to the substrate, thereby forming a non-planar surface including a plurality of conductive elements and a plurality of trenches, depositing a passivation layer on the non-planar surface, transferring the substrate from a first semiconductor processing system to a second semiconductor processing system, etching the passivation layer to remove the passivation layer, and depositing a low dielectric constant layer on the non-planar surface to fill the plurality of trenches with the low dielectric constant layer.

[0025] In some embodiments of forming an interconnect structure, the passivation layer and the patterned masking material can be etched by substantially the same chemical.

[0026] In some embodiments of forming an interconnect structure, the step of etching the passivation layer further includes etching any remaining patterned masking material.

[0027] In some embodiments of forming an interconnect structure, the steps of performing a pre-treatment process to remove any remaining patterned masking material and etching the passivation layer are performed in a single reaction chamber of a second semiconductor processing system.

[0028] To summarize the present invention and the advantages achieved over the prior art, certain objects and advantages of the present invention have been described above. Of course, it should be understood that not all of these objects or advantages may be achieved in accordance with any particular embodiment of the present invention. Thus, for example, those skilled in the art will recognize that the present invention may be implemented or carried out in a manner that achieves or optimizes one advantage or a group of advantages taught or suggested herein, without necessarily achieving other objects or advantages taught or suggested herein.

[0029] All of these embodiments are within the scope of the present invention disclosed herein. From the following detailed description of certain embodiments with reference to the accompanying drawings, these and other embodiments will become apparent to those skilled in the art, and the present invention is not limited to any particular embodiment disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] To facilitate the discussion of any particular element or action, the most significant digit in the reference numeral refers to the figure number in which that element is first introduced.

[0031] A more complete understanding of the embodiments of the present disclosure can be obtained by reference to the detailed description and the claims when considered in conjunction with the following illustrative drawings.

[0032] Figure 1 An exemplary method for forming an interconnect structure including a low dielectric constant layer in accordance with one or more embodiments of the present disclosure is shown.

[0033] Figure 2 A structure including a substrate and a conductive layer in accordance with one or more embodiments of the present disclosure is shown.

[0034] Figure 3 A structure including a plurality of trenches and a plurality of conductive elements in accordance with one or more embodiments of the present disclosure is shown.

[0035] Figure 4 A structure including a passivation layer in accordance with one or more embodiments of the present disclosure is shown.

[0036] Figure 5 An additional structure including a plurality of trenches and a plurality of conductive elements in accordance with one or more embodiments of the present disclosure is shown.

[0037] Figure 6Shows a structure including a low dielectric constant layer according to one or more embodiments of the present disclosure.

[0038] Figure 7 Shows a structure including a planarized low dielectric constant layer according to one or more embodiments of the present disclosure.

[0039] Figure 8 Shows an exemplary semiconductor processing system according to one or more embodiments of the present disclosure.

[0040] It should be understood that the elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help improve understanding of the illustrated embodiments of the present disclosure. Detailed Description

[0041] The following description of exemplary embodiments of the methods and compositions provided is merely exemplary and for illustrative purposes only. The following description is not intended to limit the scope of the present disclosure or the claims. In addition, the recitation of multiple embodiments having the noted features or steps is not intended to exclude other embodiments having additional features or steps, or other embodiments incorporating different combinations of the recited features or steps.

[0042] As used herein, the term "substrate" can refer to any one or more underlying materials that can be used to form or on which devices, circuits, or films can be formed by a method according to embodiments of the present invention. The substrate can include bulk materials such as silicon (e.g., single-crystalline silicon), other Group IV materials such as germanium, or other semiconductor materials such as Group II-VI or Group III-V semiconductor materials, and can include one or more layers covering or underlying the bulk material. Additionally, the substrate can include various features such as depressions, protrusions, etc. formed within or on at least a portion of the substrate layer. For example, the substrate can include a bulk semiconductor material and an insulating or dielectric material layer covering at least a portion of the bulk semiconductor material. Further, the term "substrate" can refer to any one or more underlying materials that can be used or on which devices, circuits, or films can be formed. The "substrate" can be continuous or discontinuous; rigid or flexible; solid or porous. The "substrate" can be in any form such as powder, plate, or workpiece. The plate-like substrate can include wafers of various shapes and sizes. The substrate can be made of materials such as silicon, silicon germanium, silicon oxide, gallium arsenide, gallium nitride, and silicon carbide. The continuous substrate can extend beyond the boundaries of the processing chamber where the deposition process occurs and can be moved through the processing chamber such that the process continues until the end of the substrate is reached. The continuous substrate can be provided by a continuous substrate supply system that allows the continuous substrate to be fabricated and output in any suitable form. Non-limiting examples of continuous substrates can include sheets, non-woven membranes, rolls, foils, meshes, flexible materials, a bundle of continuous filaments or fibers (i.e., ceramic fibers or polymer fibers). The continuous substrate can also include a carrier or sheet on which a discontinuous substrate is mounted. For example, the substrate can include a semiconductor material. The semiconductor material can include or be used to form one or more of the source, drain, or channel regions of a device. The substrate can also include an interlayer dielectric (e.g., silicon oxide) and / or a high-k dielectric material layer covering the semiconductor material. In this document, a high-k dielectric material (or high-k dielectric) is a material having a dielectric constant greater than that of silicon oxide.

[0043] As used herein, the terms "film" and / or "layer" can be used interchangeably and can refer to any continuous or discontinuous structure and material, such as a material deposited by a method disclosed herein. For example, a layer can include two-dimensional materials, three-dimensional materials, nanoparticles, partial or complete molecular layers, or partial or complete atomic layers, or atomic and / or molecular clusters. The layer can be composed, in part or in whole, of a plurality of dispersed atoms on the surface of the substrate and / or embedded within the substrate and / or embedded within a device fabricated on the substrate. The layer can include a material or layer having pinholes and / or islands. The layer can be at least partially continuous. The layer can be patterned, e.g., subdivided, and can be composed of a plurality of semiconductor devices.

[0044] As used herein, the term "low dielectric constant layer" or "low-k layer" may refer to a layer of material having a dielectric constant less than that of silicon dioxide or less than 4.0, less than 3.5, less than 3.0, less than 2.5, less than 2.0, less than 1.5, or between 1.5 and 4.0.

[0045] As used herein, the term "structure" may refer to a partially or fully fabricated device structure. For example, a structure may be a substrate or a substrate including one or more layers and / or features formed thereon.

[0046] In the present disclosure, any two numbers of a variable may constitute a viable range of that variable, and any range indicated may or may not include the endpoints. Additionally, any value of a variable indicated (whether or not denoted by "about") may refer to an exact value or an approximate value and include equivalents, and in some embodiments may refer to an average value, a median value, a representative value, a majority value, etc. Further, in the present disclosure, the terms "comprising," "consisting of," and "having" may, in some embodiments, independently refer to "generally or broadly comprising," "including," "substantially consisting of," or "consisting of." In the present disclosure, the meaning of any defined term does not necessarily exclude the ordinary and customary meaning in some embodiments. In some cases, the percentages referred to herein may be relative or absolute percentages.

[0047] In the presently disclosed embodiments, a number of exemplary materials are given. It should be noted that the chemical formulas given for each exemplary material should not be construed as restrictive, and the non-limiting exemplary materials given should not be limited by the exemplary stoichiometries given.

[0048] In the specification, it should be understood that the terms "on" or "above" may be used to describe a relative positional relationship. Another element, film, or layer may be directly on the layer, or another layer (intermediate layer) or element may be interposed therebetween, or a layer may be disposed on the layer but not completely cover the surface of the layer. Thus, unless the term "directly" is used alone, the terms "on" or "above" will be construed as relative concepts. Similarly, it should be understood that the terms "under," "below," or "beneath" will be construed as relative concepts.

[0049] Various embodiments of the present disclosure relate to methods for forming interconnect structures including low dielectric constant layers and related structures and semiconductor processing systems configured and arranged to form such interconnect structures. As will be elaborated in more detail below, the methods of the present disclosure form interconnect structures including low dielectric constant layers that have no or substantially no process-induced damage, thereby maintaining the low dielectric constant of the low-k layer, which would otherwise shift to a higher k value in the presence of process-induced damage.

[0050] Common methods for forming an interconnect structure including a low dielectric constant layer include a "damascene" type process. For example, a damascene type process can include depositing a low dielectric constant layer on a substrate, and subsequently etching trenches in the low dielectric constant layer to enable deposition of a conductive layer within the trenches. The conductive layer is then planarized, resulting in a large number of conductive elements (such as conductive lines and conductive vias) being embedded in the low dielectric constant layer. However, as a result of the etching process, such existing methods often result in process-induced damage in the low dielectric constant layer, which typically employs a plasma-excited fluorine- and / or chlorine- and / or oxygen-containing etching species, which may cause damage in the low dielectric constant layer.

[0051] According to various embodiments of the present disclosure, the interconnect structure is achieved at least in part by performing an etching process and a subsequent passivation process before forming the low dielectric constant layer of the interconnect structure, thereby reducing process-induced damage in the low dielectric constant layer and enabling the fabrication of an interconnect structure including a low dielectric constant layer having an improved dielectric constant (e.g., less than 2.5).

[0052] Turning now to the drawings, Figure 1 an exemplary method 100 for forming an interconnect structure including a damage-free low dielectric constant layer according to an embodiment of the present disclosure is shown. Briefly, method 100 includes forming a plurality of trenches in a conductive layer on a substrate, the plurality of trenches extending through the conductive layer to the substrate, thereby forming a plurality of conductive elements (step 102). Method 100 also includes optionally preprocessing the substrate (step 104). For example, an optional preprocessing step can be performed on the substrate after forming the plurality of conductive elements. Method 100 also includes forming a passivation layer on the plurality of conductive elements (step 106). Method 100 also includes optionally inspecting the substrate (step 108). Method 100 also includes transferring the substrate from a first semiconductor processing system to a second semiconductor processing system (i.e., transferring to a different reaction chamber in a different system) (step 110). Method 100 also includes removing the passivation layer (step 112), and subsequently filling the plurality of trenches with a low dielectric constant layer (step 114). Method 100 may also include planarizing the low dielectric constant layer (step 116).

[0053] Referring below to Figure 1 method 100 and also referring to Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 the processing steps of method 100 are described in more detail, which Figure 1 show the related structures formed during the process of performing the steps of method 100, as well as additional steps that may be included as part of method 100.

[0054] More specifically, according to an example of the present disclosure, method 100 ( Figure 1 ) includes step 102, which includes forming a plurality of trenches in a conductive layer on a substrate. According to an example of the present disclosure, Figure 2 Structure 200 including substrate 202 is shown. In such an example, substrate 202 may include at least one of the materials and structures described above, such as a single-crystal semiconductor layer at least on the surface of substrate 202.

[0055] According to an example of the present disclosure, substrate 202 may include a device region 204, where one or more devices (not shown) are formed on / in substrate 202. In such an example, device region 204 may include devices such as transistors, diodes, imaging sensors, resistors, capacitors, inductors, memory cells, or combinations thereof. In some embodiments, the device is a transistor, such as a planar field effect transistor (FET), FinFET, nanostructure transistor, or other suitable transistor. The nanostructure transistor may include a nanosheet transistor, a nanowire transistor, a gate-all-around (GAA) transistor, a multi-bridge-channel (MBC) transistor, or any transistor having a gate electrode surrounding the channel.

[0056] According to an example of the present disclosure, structure 200 includes a conductive layer 206, which will become a plurality of conductive elements that are part of an interconnect structure in subsequent processing steps, as described in more detail below.

[0057] According to an example of the present disclosure, conductive layer 206 includes one or more of a metal, a metal alloy, a conductive metal nitride, a silicide, or a mixture thereof. In some embodiments, the conductive layer is selected from Cu, Co, Ru, Mo, Cr, W, Mn, Rh, Ir, Ni, Pd, Pt, Ag, Au, Al, FeAl, FeCo, and their alloys. In some embodiments, conductive layer 206 is deposited on substrate 202 and on the devices within device region 204. In such an embodiment, conductive layer 206 is deposited on substrate 202 by placing substrate 202 in a reaction chamber and employing one or more deposition processes, including but not limited to physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), electrochemical plating (ECP), or combinations thereof.

[0058] After forming the conductive layer on the substrate, method 100 includes forming a plurality of trenches in the conductive layer (step 102). Figure 3A structure 300 is shown that includes a plurality of trenches 302. According to an example of the present disclosure, the plurality of trenches 302 extend through the conductive layer 206 to the underlying substrate 202, thereby forming a plurality of conductive elements 304. In such an example, the plurality of trenches 302 separate the plurality of conductive elements 304 from each other as the trenches 302 extend to the underlying substrate 202. In such an example, each of the plurality of trenches 302 has a trench base 306 that is free of conductive material of the conductive layer 206. In such an example, the formation of the plurality of trenches 302 in the conductive layer 206 forms a non-planar surface 308 that includes a top surface of the conductive element, a sidewall surface of the conductive element, and a trench base surface at the bottom of the trench.

[0059] According to an example of the present disclosure, by removing ( Figure 2 The plurality of conductive elements 304 formed from selected areas of the conductive layer 206 of the substrate 202 are arranged to provide electrical pathways to various devices disposed in the device region 204 of the underlying substrate 202. In such examples, the plurality of conductive elements 304 provide vertical electrical routing from the device region 204 (and the devices therein) to the conductive elements 304, as well as horizontal electrical routing between the plurality of conductive elements 304 themselves. In such examples, the plurality of conductive elements 304 include conductive lines and conductive vias.

[0060] According to an example of the present disclosure, a plurality of grooves 302 are formed by patterning the surface of the conductive layer 206 with a masking material (not shown) and one or more etching processes. In such an example, the masking material (e.g., an organic layer, a metal oxide, etc.) can be formed and patterned using any suitable process (e.g., a photolithography process). In such an example, a plasma etching process is used, such as a plasma deep reactive ion etching (DRIE) process using an organic gas as an etchant. For example, the plasma DRIE process can use an inductively coupled plasma (ICP) having a power ranging from about 100W to about 1500W, a bias voltage ranging from about 0V to about 300V, and an organic etchant such as CH3COOH, CH3OH, CH3CH2OH or a combination thereof. In another example, the ICP plasma DRIE process can have a power ranging from about 100 W to about 1500 W, a bias voltage ranging from about 0 V to about 500 V, and an etchant such as CF4, CHF3, CH3F, CH2F2, C4F8, C4F6, N2, O2, Ar, or a combination thereof. In yet another example, the plasma DRIE process can have a power ranging from about 100 W to about 2000 W, a bias voltage ranging from about 0 V to about 500 V, and an etchant such as Cl2, SiCl4, BCl3, CF4, CHF3, CH2F2, C4F8, C4F6, N2, O2, Ar, or a combination thereof.

[0061] After forming a plurality of conductive elements, method 100( Figure 1 ) includes forming a passivation layer on the plurality of conductive elements (step 106). According to an example of the present disclosure, after removing any possible etch residues on the conductive elements, a passivation layer is formed on the exposed surfaces of the plurality of conductive elements to seal the conductive elements. In such an example, the passivation layer can prevent corrosion of the conductive elements.

[0062] Figure 4 A structure 400 including a passivation layer 402 is shown, where the passivation layer 402 is disposed on the plurality of conductive elements 304 and on each trench substrate 306 of the plurality of trenches 302. Once in a suitable reaction chamber configured and arranged to deposit a passivation layer on a substrate, the step of forming the passivation layer 402 on the plurality of conductive elements 304 is performed.

[0063] According to an example of the present disclosure, the passivation layer is formed by a deposition process. In some embodiments, the deposition process is a cyclic deposition process. In some embodiments, the cyclic deposition process is an atomic layer deposition (ALD) process. In some embodiments, the cyclic deposition process is a cyclic chemical vapor deposition process (CCVD). In some embodiments, the cyclic deposition process is a hybrid ALD / CCVD process. In some embodiments, the passivation layer 402 conformally deposits directly on the non-planar surface 308 with a conformality of at least 80%, or 85%, or 90%, or 95% or higher. As used herein, the term "conformality" may refer to the ratio of the average thickness of the passivation layer 402 on the top surface of the plurality of conductive elements 304 to the average thickness of the passivation layer 402 deposited on the sidewall surfaces of the plurality of conductive elements 304. In some embodiments, the passivation is deposited by a non-conformal deposition process.

[0064] According to an example of the present disclosure, the passivation layer is formed at a deposition temperature (e.g., substrate temperature) less than 300 °C, less than 250 °C, less than 200 °C, less than 150 °C or less than 100 °C. In such an example, the passivation is deposited at a deposition temperature between 100 °C and 300 °C. In such an example, the deposition temperature of the passivation layer can depend at least in part on the material of the conductive layer. In some embodiments, the deposition temperature is below the temperature at which the conductive elements may deform.

[0065] According to an example of the present disclosure, the passivation layer 402 is a sealing layer. In such an example, the passivation layer 402 seals the underlying plurality of conductive elements 304 and the trench substrate 306 regions between the conductive elements. In such an example, the passivation layer 402 does not extend into the voids of the underlying plurality of conductive elements 304 from the surface of the passivation layer, thereby enabling the sealing of the plurality of conductive elements 304. According to an example of the present disclosure, the passivation layer 402 is an impermeable layer. In such an example, the passivation layer is deposited hermetically on the plurality of trenches and the plurality of conductive elements, thereby sealing the plurality of trenches and the plurality of conductive elements.

[0066] According to an example of the present disclosure, the passivation layer 402 is a continuous layer. In some embodiments, the passivation layer 402 is deposited with an average layer thickness of less than 5 nm, less than 4 nm, less than 3 nm, less than 2 nm, or less than 1 nm. In some embodiments, the passivation layer 402 is deposited to have an average layer thickness between 1 nm and 5 nm. In some embodiments, the passivation layer 402 is deposited to have an average layer thickness greater than 5 nm, greater than 8 nm, greater than 10 nm, greater than 13 nm, greater than 15 nm, or between 5 nm and 15 nm. In some embodiments, the passivation layer 402 is deposited as a closed continuous film with an average layer thickness between 1 nm and 5 nm and a conformality greater than 90%.

[0067] According to an example of the present disclosure, the passivation layer 402 includes at least one of a metal, a semiconductor, a dielectric, or a polymer. In such an example, the passivation layer 402 is selected from elemental metals such as tungsten, molybdenum, ruthenium, or tantalum, nitrides such as silicon nitride, titanium nitride, or tantalum nitride, oxides such as silicon oxide or aluminum oxide, or carbides such as silicon carbide. In some embodiments, the passivation layer 402 includes silicon. In some embodiments, the passivation layer 402 includes nitrogen. In some embodiments, the passivation layer 402 includes carbon. In some embodiments, the passivation layer 402 includes oxygen. In some embodiments, the passivation layer 402 is selected from silicon oxide, silicon nitride, aluminum oxide, tungsten, molybdenum, ruthenium, titanium nitride, tantalum. In some embodiments, the passivation layer 402 includes at least one of a metal oxide or a metal nitride.

[0068] In some embodiments, the passivation layer comprises an organic material. In some embodiments, the passivation layer comprises an organic polymer, consisting of or consisting essentially of the same. In some embodiments, the passivation layer comprises polyimide, consisting of or consisting essentially of the same. In some embodiments, the passivation layer comprises polyamic acid, consisting of or consisting essentially of the same. In some embodiments, the passivation layer is deposited by atomic layer deposition. In some embodiments, the passivation layer is deposited at a temperature below 190 °C and subsequently heat treated (annealed) at a temperature of about 190 °C or higher (e.g., from about 200 °C to about 500 °C) to increase the ratio of the organic polymer from polyamic acid to polyimide. Other examples of deposited organic polymers include dimers, trimers, polyurethanes, polythioureas, polyesters, polyimides, other polymeric forms, or mixtures of the above materials. In some embodiments, the deposited organic polymer is exposed to plasma-generated reactive species. In embodiments where the organic polymer is used as the passivation material, this can improve the passivation performance of the organic polymer. For example, reactive species generated by a plasma containing hydrogen and argon can be used. The organic polymer can be exposed to the plasma for about 1 second to about 1 minute, such as about 1 second to about 30 seconds, or about 5 seconds to about 30 seconds, or about 1 second to about 15 seconds, or about 3 seconds to about 20 seconds.

[0069] According to an example of the present disclosure, the passivation layer 402 comprises a selectively removable material. In such an example, the passivation layer 402 is a material having an etch selectivity (compared to the material of the plurality of conductive elements 304) greater than 100%, greater than 200%, greater than 300%, greater than 500%, greater than 1000%, or greater.

[0070] Without limiting the present disclosure to any particular theory, a favorable passivation layer can be a sealing layer (i.e., preventing or at least reducing oxygen from entering the substrate surface). In addition, a favorable passivation layer can be formed on the substrate at a low temperature, such as by deposition. The low temperature for forming the passivation layer can be, for example, below 250 °C or below 200 °C. Another favorable feature of the passivation layer may be that it is easily removable before further processing of the substrate.

[0071] According to a further example of the present disclosure, before forming a passivation layer on a plurality of conductive elements (step 106), the plurality of conductive elements may optionally be subjected to one or more pre-treatment processes (step 104). For example, in such an embodiment, the pre-treatment process (step 104) may remove any undesirable residues remaining on the surface of the plurality of conductive elements to enhance the adhesion of the passivation layer to the plurality of conductive elements. As a non-limiting example, a pre-treatment process may be performed before forming the passivation layer to remove any remaining portions of the masking material employed during the formation of the plurality of trenches. In such an example, the one or more pre-treatment processes (step 104) may include thermal and / or chemical processes. In some embodiments, the pre-treatment includes removing etch residues from the substrate surface. In some embodiments, the pre-treatment includes reducing or removing oxides on the surface. For example, the pre-treatment may include treating the substrate with a plasma, such as a plasma containing H2 and / or NH3. In other examples, the optional pre-treatment step (step 104) may be repeated or employed before subsequent steps of method 100, as described in detail below.

[0072] According to a further example of the present disclosure, the substrate may optionally be inspected (step 108). In some embodiments, after forming a passivation layer on the conductive elements, i.e., after performing step 106 of method 100 ( Figure 1 ), the substrate may be inspected. In such an example, the substrate may be inspected to determine whether the dimensions of the plurality of conductive elements 304 and the plurality of trenches 302 having the passivation layer disposed thereon are within the expected range of values. The inspection process may include observing the substrate surface with a metrology tool to determine that the critical dimensions of the plurality of conductive elements 304 and the plurality of trenches 302 (on which the passivation layer is disposed) are within the expected range.

[0073] According to an example of the present disclosure, the optional inspection process (step 108) may be performed by removing the substrate from the semiconductor processing system used to form the passivation layer and inspecting the critical dimensions of the substrate off-site, such as using a metrology tool separate from the semiconductor processing system.

[0074] According to other examples of the present disclosure, an optional inspection process (step 108) can be performed within the same semiconductor processing system used to form the passivation layer. In such an embodiment, for example, a metrology tool is used within the same semiconductor processing system used to form the passivation layer to perform in-situ inspection of the critical dimensions of the substrate. In such an example, the step of forming the passivation layer (step 106) is performed in a first reaction chamber, while the step of inspecting the substrate (step 108) is performed in a second chamber (i.e., the metrology chamber), which is configured and arranged to inspect the critical dimensions of the substrate. In such an example, a transfer module can be employed to transfer the substrate, which is configured and arranged to move the substrate between the first reaction chamber (e.g., for depositing) the passivation layer and the second chamber (i.e., the metrology chamber), while maintaining the substrate in a vacuum or inert gas environment.

[0075] Method 100( Figure 1 ) further includes a step of removing the passivation layer (step 112). According to an example of the present disclosure, the passivation layer is removed before forming the low dielectric constant layer, as discussed in more detail below. In such an example, the passivation layer 402 protects the non-planar surface 308 of the substrate 202( Figure 4 ) before forming the low dielectric constant layer and is removed before forming the low dielectric constant layer to enable the direct formation of the low dielectric constant layer on the non-planar surface 308. According to an example of the present disclosure, the passivation layer hermetically engages the underlying plurality of conductive elements. In such an example, the passivation layer prevents corrosion of the plurality of conductive elements. In such an example, when the substrate (including the conductive elements) is queued for subsequent processing steps, and / or the substrate is transferred between different semiconductor processing systems, and / or the substrate is transferred between different reaction chambers of a semiconductor processing system, and / or the substrate is transferred to a metrology chamber to perform an inspection process, the passivation layer prevents corrosion of the plurality of conductive elements.

[0076] Figure 5 The structure 500 after removing the passivation layer 402 is shown. Once in a suitable reaction chamber configured and arranged to remove the passivation layer on the substrate, the step of removing the passivation layer 402 from the plurality of conductive elements 304 (step 112) is performed. In such an example, the passivation layer 402 is completely removed during the removal step 112 to expose the non-planar surface 308.

[0077] According to an example of the present disclosure, the passivation layer 402 is removed by one or more etching processes. In some embodiments, the passivation layer is removed by a chemical vapor etching process. In such embodiments, the substrate is heated to a temperature below 300°C, below 250°C, below 200°C, below 150°C, below 100°C, or between 100°C and 300°C, and a vapor etchant is introduced into the reaction chamber to remove the passivation layer. In some embodiments, the vapor etchant is a selective etchant. In such embodiments, the selective etchant selectively removes the passivation without etching or significantly etching the underlying materials (such as the conductive element 304 and the substrate 202). As a non-limiting example, the passivation layer may include a silicon dioxide layer, and the silicon dioxide passivation layer is removed by a chemical vapor etching process of heating the substrate to a temperature below 300°C and introducing hydrofluoric acid vapor into the reaction chamber. In other examples, the passivation layer 402 is removed by a plasma etching process.

[0078] According to an example of the present disclosure, the steps of forming the passivation layer (step 106) and removing the passivation layer (step 112) are performed in different semiconductor processing systems. In such an example, the step of forming the passivation layer (step 106) is performed in a first semiconductor processing system, and the step of removing the passivation layer (step 112) is performed in a second semiconductor processing system (different from the first reaction chamber).

[0079] According to an example of the present disclosure, a method of forming an interconnect structure on a substrate including a device region is disclosed. The method includes depositing a conductive layer on the substrate, forming a patterned masking material on the top surface of the conductive layer to form a plurality of masking regions and a plurality of unmasked regions, and etching the exposed regions of the conductive layer through the plurality of unmasked regions to form a plurality of trenches in the conductive layer, wherein the trenches extend through the conductive layer to the substrate, thereby forming a non-planar surface including a plurality of conductive elements and a plurality of trenches. The method further includes depositing a passivation layer on the non-planar surface, transferring the substrate from a first semiconductor processing system to a second semiconductor processing system, etching the passivation layer to remove the passivation layer, and depositing a low dielectric constant layer on the non-planar surface to fill the plurality of trenches with the low dielectric constant layer.

[0080] In some embodiments, the passivation layer and the patterned masking material may be etched by substantially the same chemical. In some embodiments, the passivation layer and the patterned masking material may be etched by the same chemical. In some embodiments, the passivation layer and the patterned masking material have substantially the same or the same etching contrast with the material of the non-planar surface 308.

[0081] In some embodiments, the step of etching the passivation layer further includes etching any remaining patterned masking material. In other words, etching the passivation layer can be performed at least partially concurrently with etching the patterned masking material. In some embodiments, the passivation layer is etched in the same reaction chamber as the remaining patterned masking material.

[0082] In some embodiments, the method further includes performing a pre-treatment process to remove any remaining patterned masking material. In some embodiments, the steps of performing a pre-treatment process to remove any remaining patterned masking material and etching the passivation layer are performed in a single reaction chamber of a second semiconductor processing system. In some embodiments, the pre-treatment includes contacting the surface with a reducing agent or a gas that is intended to modify the surface termini for further processing.

[0083] Method 100( Figure 1 ) further includes a step (step 114) of filling the plurality of trenches with a low dielectric constant layer. In some embodiments, step 114 includes depositing a low dielectric constant layer directly on the non-planar surface of the substrate to fill the plurality of trenches with the low dielectric constant layer.

[0084] Figure 6 Structure 600 is shown after a low dielectric constant layer 602 has been formed on the non-planar surface 308 of substrate 202 to fill the plurality of trenches 302. Once in a suitable reaction chamber configured and arranged for forming the low dielectric constant layer 602, the step of forming the low dielectric constant layer 602 on the non-planar surface 308 of substrate 202 to fill the plurality of trenches 302 (step 112) is performed. In such an example, the low dielectric constant layer 602 fills the plurality of trenches 302 and covers the top surfaces of the plurality of conductive elements 304.

[0085] According to an example of the present disclosure, the low dielectric constant layer 602 is a layer having a dielectric constant less than that of silicon dioxide (e.g., less than 4.0). In such an example, the low dielectric constant layer 602 can include at least one of doped silicon dioxide (e.g., fluorine-doped SiO2), silicon oxycarbide (SiOC), organosilicate glass, porous silicon dioxide, porous organosilicate glass, porous silicon oxycarbide, polymer dielectrics, or a combination thereof. In a further example, the low dielectric constant layer 602 can include air gaps. According to an example of the present disclosure, the low dielectric constant layer 602 can be formed by one or more deposition methods, including but not limited to spin coating methods, chemical vapor deposition, flowable chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, plasma-enhanced atomic layer deposition, and physical vapor deposition.

[0086] According to an example of the present disclosure, the low dielectric constant layer 602 formed in the plurality of trenches 302 has no or substantially no process-induced damage. In such an example, the low dielectric constant layer 602 retains the dielectric constant it had when deposited. In such an example, the low dielectric constant layer 602 has a dielectric constant less than 3.9, less than 3.5, less than 3.0, less than 2.5, less than 2.0, less than 1.5, or between 1.5 and 3.9.

[0087] According to another example of the present disclosure, an optional step of preprocessing the substrate (step 104) may be performed before forming the low dielectric constant layer 602. In such an example, before filling the plurality of trenches with the low dielectric constant layer (step 114), the plurality of conductive elements may optionally be subjected to one or more preprocessing processes (step 104). In such an embodiment, for example, the optional preprocessing process (step 104) may remove any undesirable residues remaining on the surfaces of the plurality of trenches to enhance the adhesion of the low dielectric constant layer in the plurality of trenches. As a non-limiting example, a preprocessing process may be performed before forming the low dielectric constant layer to remove any remaining portions of the masking material used during the formation of the plurality of trenches. In such an example, if the substrate is not preprocessed before forming the passivation layer, an optional preprocessing of the substrate (step 104) may be performed.

[0088] According to an example of the present disclosure, the steps of removing the passivation layer (step 112), preprocessing the substrate before forming the low dielectric constant layer (step 104), and forming the low dielectric constant layer (step 114) may be performed in a second semiconductor processing system.

[0089] According to an example of the present disclosure, the various steps of the exemplary method 100 may be performed in one or more reaction chambers, either as part of a single semiconductor processing system or as one or more reactions on multiple semiconductor processing systems. The following non-limiting examples describe an exemplary process flow for performing method 100 ( Figure 1 ) and the semiconductor processing system for performing the exemplary process flow.

[0090] Exemplary Process Flow #1

[0091] According to an example of the present disclosure, method 100 includes forming a plurality of trenches (step 102) in a conductive layer. The steps of preprocessing the substrate to remove any residues (step 104) and forming a passivation layer (step 106) are performed in a first semiconductor processing system. Method 100 may then optionally include inspecting the substrate (step 108) or optionally holding the substrate for a period of time before subsequent process steps. Method 100 may proceed with the steps of removing the passivation layer (step 112) and forming the low dielectric constant layer (step 114) in a second semiconductor processing system.

[0092] Exemplary Process Flow #2

[0093] In a further example according to the present disclosure, method 100 includes forming a plurality of trenches in a conductive layer (step 102). The step of forming a passivation layer (step 106) is performed in a first semiconductor processing system. Method 100 may then optionally include inspecting the substrate (step 108) or alternatively holding the substrate for a period of time prior to subsequent process steps. The method may continue with the steps of preprocessing the substrate (step 104), removing the passivation layer (step 112), and forming a low dielectric constant layer (step 114) in a second semiconductor processing system.

[0094] Exemplary Process Flow #3

[0095] In a further example according to the present disclosure, method 100 includes forming a plurality of trenches in a conductive layer (step 102), preprocessing the substrate (step 104), and forming a passivation layer in a first semiconductor processing system (step 106). Method 100 may then optionally include inspecting the substrate (step 108) or alternatively holding the substrate for a period of time prior to subsequent process steps. Method 100 may continue with the steps of removing the passivation layer (step 112) and forming a low dielectric constant layer (step 114) in a second semiconductor processing system.

[0096] Exemplary Process Flow #4

[0097] In yet another example according to the present disclosure, method 100 includes forming a plurality of trenches in a conductive layer (step 102) and forming a passivation layer (step 106) in a first semiconductor processing system. Method 100 may then optionally include inspecting the substrate (step 108) or alternatively holding the substrate for a period of time prior to subsequent process steps. Method 100 may continue with the steps of removing the passivation layer (step 112), preprocessing the substrate (step 104), and forming a low dielectric constant layer (step 114) in a second semiconductor processing system.

[0098] According to an example of the present disclosure, when two or more processing steps are performed in the same semiconductor processing system, the above exemplary process flow may include transferring one or more substrates between different reaction chambers (step 110). In some embodiments, when two or more processing steps of method 100 are performed in the same semiconductor processing system, the two or more processing steps of method 100 may be performed in the same reaction chamber of the semiconductor processing system. As a non-limiting example, the steps of removing a passivation layer (step 112) and forming a low dielectric constant layer (step 114) may be performed in the same reaction chamber of the semiconductor processing system. In such an example, method 100 includes removing a passivation layer (step 112) and subsequently forming a low dielectric constant layer (step 114), where steps 112 and 114 are performed in the same reaction chamber without an intermediate process, i.e., the low dielectric constant layer is formed directly after removing the passivation layer.

[0099] Method 100( Figure 1 ) may also include a step of planarizing the low dielectric constant layer (step 116).

[0100] Figure 7 The structure 700 after planarizing the low dielectric constant layer 602 is shown. According to an example of the present disclosure, a planarization process may be performed to remove a portion of the low dielectric constant layer 602 formed on the top surfaces of the plurality of conductive elements 304. The planarization process may be any suitable process, such as a chemical mechanical polishing (CMP) process, an etch-back process, or a combination of both. As a result of the planarization process, the top surface 404 of the low dielectric constant layer may be substantially coplanar with the top surfaces 406 of the plurality of conductive elements 304.

[0101] Various embodiments of the present disclosure also relate to a semiconductor processing system configured and arranged to perform the above-described method for forming an interconnect structure.

[0102] Figure 8An exemplary semiconductor processing system 800 is shown, including a first reaction chamber 802, a second reaction chamber 804, a third reaction chamber 806, and an optional metrology chamber 808. According to an example of the present disclosure, the semiconductor processing system 800 includes a transfer module 810 to transfer substrates between the first, second, and third reaction chambers and the optional metrology chamber under vacuum or an inert atmosphere. The semiconductor processing system 800 includes a controller 814 that is operably connected to the first reaction chamber 802, the second reaction chamber 804, the third reaction chamber 806, the metrology chamber 808, and the transfer module 810 via a link 816 (such as a physical or wireless link). As described above, the controller 814 is configured and arranged to cause the semiconductor processing system 800 to perform the steps of method 100. According to an example of the present disclosure, the first reaction chamber 802, the second reaction chamber 804, the third reaction chamber 806, and the metrology chamber 808 may be operably coupled to one or more precursor / reactant sources 818 via a gas channel 820.

[0103] According to an example of the present disclosure, the first reaction chamber 802 is configured and arranged to etch a passivation layer disposed on a non-planar surface of a substrate, the non-planar surface including a plurality of conductive elements and a plurality of trenches (as described in step 112 of reference method 100).

[0104] According to an example of the present disclosure, the second reaction chamber is configured and arranged to perform a pre-treatment process on the non-planar surface before depositing a low dielectric constant layer on the non-planar surface (as described in step 104 of reference method 100).

[0105] According to an example of the present disclosure, the third reaction chamber is configured and arranged to deposit a low dielectric constant layer on the non-planar surface (as described in step 114 of reference method 100).

[0106] According to an example of the present disclosure, the first reaction chamber 802 and the third reaction chamber 806 may include a single reaction chamber that is configured and arranged to etch the passivation layer and deposit the low dielectric constant layer. In such an example, when etching the passivation layer and depositing the low dielectric constant layer, the substrate does not need to be transferred between reaction chambers and / or between different semiconductor processing systems.

[0107] According to a further example of the present disclosure, the semiconductor processing system 800 may optionally include a metrology chamber 808 that is configured and arranged to inspect the substrate. In such an example, the substrate may be inspected after etching the passivation layer in the first reaction chamber, and / or after performing the pre-treatment process on the non-planar surface before depositing the low dielectric constant layer, and / or after depositing the low dielectric constant layer.

[0108] According to an example of the present disclosure, the transfer module 810 is configured and arranged to transfer substrates (as described in step 110 of reference method 100) between the first reaction chamber 802, the second reaction chamber 804, the third reaction chamber 806, and an optional metrology chamber 808 under vacuum or an inert atmosphere.

[0109] In some embodiments of the present disclosure, before etching the passivation layer (step 112), i.e., before transferring the substrate to Figure 8 the semiconductor processing system 800, an additional semiconductor processing system (not shown) may be employed to perform the steps of method 100.

[0110] According to an additional example of the present disclosure, an initial semiconductor processing system (not shown) is used to etch a plurality of trenches in a conductive layer. In such an example, the initial semiconductor processing system may optionally include a metrology chamber for inspecting the substrate after the trenches are formed to confirm the critical dimensions of the trenches in the conductive layer. In some embodiments, the substrate is transferred from the initial semiconductor processing system to an additional semiconductor processing system that includes a first reaction chamber configured and arranged to perform a pretreatment process on a plurality of conductive elements and a second reaction chamber configured and arranged to deposit a passivation layer. In some embodiments, the substrate is transferred from the initial semiconductor processing system to an additional semiconductor processing system that includes a first reaction chamber configured and arranged to deposit a passivation layer.

[0111] According to another example of the present disclosure, the additional processing system may include a first reaction chamber configured and arranged to etch a plurality of trenches in a conductive layer, a second reaction chamber configured and arranged to perform a pretreatment process on the plurality of trenches before forming the passivation layer, and a third reaction chamber configured and arranged to deposit the passivation layer.

[0112] According to an example of the present disclosure, the additional semiconductor processing system may include a first reaction chamber configured and arranged to etch a plurality of trenches in a conductive layer and a second reaction chamber configured and arranged to deposit a passivation layer.

[0113] To summarize the present invention and the advantages achieved relative to the prior art, certain objectives and advantages of the present invention have been described above. Of course, it should be understood that not all of these objectives or advantages may be achieved according to any particular embodiment of the present invention. Thus, for example, those skilled in the art will recognize that the present invention may be implemented or carried out in a manner that realizes or optimizes one advantage or a group of advantages taught or suggested herein, without necessarily realizing other objectives or advantages taught or suggested herein.

[0114] All of these embodiments are within the scope of the present invention disclosed herein. From the following detailed description of certain embodiments with reference to the accompanying drawings, these and other embodiments will become apparent to those skilled in the art, and the present invention is not limited to any particular embodiment disclosed.

Claims

1. A method for forming an interconnect structure on a substrate including a conductive layer, the method comprising: forming a plurality of trenches in the conductive layer, the trenches extending through the conductive layer to the substrate, thereby forming a plurality of conductive elements; forming a passivation layer on the plurality of conductive elements; transferring a substrate from a first semiconductor processing system to a second semiconductor processing system; Removing the passivation layer; as well as The plurality of trenches are filled with a low dielectric constant layer.

2. The method according to claim 1, wherein: The steps of forming the plurality of trenches in the conductive layer and forming the passivation layer are performed in the first semiconductor processing system.

3. The method according to claim 1, wherein: The step of forming the passivation layer is performed in the first semiconductor processing system. 4 . The method of claim 3 , further comprising performing a pretreatment process on the plurality of conductive elements before forming the passivation layer. The method of claim 3 , further comprising inspecting a substrate after forming the passivation layer.

6. The method according to claim 3, wherein: After forming the passivation layer, the substrate is transferred from the first semiconductor processing system to the second semiconductor processing system.

7. The method according to claim 6, wherein: The steps of removing the passivation layer and filling the plurality of trenches with the low dielectric constant layer are performed in the second semiconductor processing system.

8. The method according to claim 7, wherein: The steps of removing the passivation layer and filling the plurality of trenches with the low dielectric constant layer are performed in a single reaction chamber. 9 . The method of claim 8 , further comprising performing a pre-treatment process on the plurality of conductive elements after removing the passivation layer and before filling the plurality of trenches with the low dielectric constant layer.

10. The method according to claim 1, wherein: The passivation layer is hermetically deposited over the plurality of trenches and the plurality of conductive elements, thereby sealing the plurality of trenches and the plurality of conductive elements.

11. The method according to claim 1, wherein: The passivation layer is selected from an elemental metal, such as tungsten, molybdenum, ruthenium or tantalum, a nitride, such as silicon nitride, titanium nitride or tantalum nitride, an oxide, such as silicon oxide or aluminum oxide, or a carbide, such as silicon carbide.

12. A method for forming an interconnect structure on a substrate including a device region, the method comprising: depositing a conductive layer on a substrate; etching a plurality of trenches in the conductive layer, the trenches extending through the conductive layer to the substrate, thereby forming a non-planar surface including a plurality of conductive elements and a plurality of trenches; depositing a passivation layer on a non-planar surface; transferring a substrate from a first semiconductor processing system to a second semiconductor processing system; etching the passivation layer to remove the passivation layer and expose the non-planar surface; as well as A low dielectric constant layer is deposited directly on the non-planar surface to fill the plurality of trenches with the low dielectric constant layer.

13. The method according to claim 12, wherein: The step of depositing the passivation layer is performed in the first semiconductor processing system.

14. The method of claim 13, further comprising performing a pre-treatment process on the plurality of conductive elements prior to depositing the passivation layer.

15. The method according to claim 13, wherein: After forming the passivation layer, the substrate is transferred from the first semiconductor processing system to the second semiconductor processing system.

16. The method according to claim 15, wherein: The steps of etching the passivation layer and depositing the low dielectric constant layer are performed in the second semiconductor processing system.

17. The method according to claim 16, wherein: The steps of etching the passivation layer and depositing the low dielectric constant layer are performed in a single reaction chamber.

18. A semiconductor processing system comprising: a first reaction chamber constructed and arranged to etch a passivation layer disposed on a non-planar surface of a substrate, the non-planar surface comprising a plurality of conductive elements and a plurality of trenches; a second reaction chamber constructed and arranged to perform a pretreatment process on the non-planar surface prior to depositing the low dielectric constant layer on the non-planar surface; a third reaction chamber constructed and arranged to deposit a low dielectric constant layer on a non-planar surface; a transfer module constructed and arranged to move the substrate between the first reaction chamber, the second reaction chamber, and the third reaction chamber while maintaining the substrate in a vacuum or inert gas environment; one or more precursor / reactant sources operably coupled to each of the first reaction chamber, the second reaction chamber, and the third reaction chamber; as well as A controller is constructed and arranged to interconnect a semiconductor processing system.

19. The semiconductor processing system of claim 18, wherein: The first reaction chamber and the third reaction chamber include a single reaction chamber constructed and arranged for etching the passivation layer and depositing the low dielectric constant layer.

20. The semiconductor processing system of claim 18, further comprising a metrology chamber constructed and arranged to inspect a substrate after etching the passivation layer and / or after depositing the low dielectric constant layer.

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