Chip packaging structure

Abstract

The invention provides a chip packaging structure. The chip packaging structure comprises a bare chip, the bare chip comprises a first internal wire, a first access bonding pad and a plurality of functional bonding pads, the first access bonding pad and the functional bonding pads are located on the surface of the bare chip, the bare chip is provided with a first side edge and a second side edge which are adjacent, the first access bonding pad is arranged on the first side edge, and the functional bonding pads are arranged on the first side edge and the second side edge; the first access bonding pad is electrically connected with the functional bonding pad on the first side edge through a first internal wire; the first pin is located on one side of the bare chip, and the first pin is a power supply pin or a grounding pin; and the plurality of bonding wires comprise a first bonding wire and at least one second bonding wire crossing over the bare chip, the first bonding wire is electrically connected with the first pin and the first access bonding pad, and the second bonding wire is electrically connected with one functional bonding pad of the first side edge and one functional bonding pad of the second side edge. In this way, packaging of a single power pin or a single ground pin is achieved, and impedance of electrical conduction can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a chip packaging structure. Background Art

[0002] At present, chip packaging structures usually require multiple sets of power / ground pads to ensure the robustness of power supply. For packaging with only a single power pin and a single ground pin, because there is only one access point for external power / ground and internal power / ground of the bare chip, the external power / ground needs to be transmitted to various parts of the bare chip through the metal wire inside the bare chip connected to the access point. Since the resistance of the metal wire inside the bare chip is relatively large, it will have a relatively large impact on the voltage drop (IR drop), electrostatic discharge (ESD) and electromagnetic compatibility (EMC) of the bare chip. Summary of the invention

[0003] One of the purposes of the present invention is to provide a chip packaging structure that can realize the packaging form of a single power pin and / or a single ground pin, and can effectively reduce the impedance of bare chip electrical conduction, and improve the voltage drop performance, electrostatic release performance and electromagnetic compatibility performance of the bare chip.

[0004] In order to achieve the above-mentioned object, the present invention provides a chip packaging structure. The chip packaging structure includes: a bare chip, the bare chip includes a first internal wire located inside the bare chip and a plurality of pads located on the surface of the bare chip, the plurality of pads include a first access pad and a plurality of functional pads; the bare chip has a first side and a second side adjacent to each other, the first access pad is arranged on the first side, the first side and the second side are both provided with the functional pad, the first access pad and the functional pad of the first side are electrically connected through the first internal wire; a first pin, located on one side of the bare chip, the first pin is a power pin or a ground pin; and a plurality of bonding wires, including a first bonding wire and at least one second bonding wire crossing over the bare chip, the first bonding wire electrically connecting the first pin and the first access pad, the second bonding wire electrically connecting one of the functional pads on the first side and one of the functional pads on the second side, the two functional pads electrically connected by the second bonding wire are also electrically connected through the first internal wire, and the portion of the first internal wire between the two functional pads is connected in parallel with the second bonding wire.

[0005] Optionally, at least two of the functional pads are provided on each side of the bare chip, and the functional pads located on the same side are electrically connected through the first internal wire; for any two adjacent sides of the bare chip, a functional pad on one side corresponds to a functional pad on the other side, and the corresponding two functional pads are electrically connected through a second bonding wire.

[0006] Optionally, all of the functional pads are disposed above the first internal wire and electrically connected through the first internal wire.

[0007] Optionally, the first internal wire includes multiple electrically connected portions or multiple disconnected segments.

[0008] Optionally, the first internal wire is distributed in a metal layer within the die; alternatively, the first internal wire is distributed in multiple metal layers within the die, and the first internal wires in the multiple metal layers are connected in parallel through vias.

[0009] Optionally, the first pin is a power pin and the functional pad is a power pad.

[0010] Optionally, the chip package structure further includes a second pin located on one side of the die, and the second pin is a ground pin; the die further has a second internal wire located inside the die; the multiple pads further include a second access pad and multiple ground pads, and the multiple ground pads include a first ground pad and a second ground pad; the second access pad and the second pin are electrically connected through a third bonding wire, the second access pad and the first ground pad are disposed on the same side edge of the die and electrically connected through the second internal wire, the first ground pad and the second ground pad are respectively disposed on two adjacent side edges of the die, and are electrically connected through a fourth bonding wire spanning above the die.

[0011] Optionally, the first ground pad and the second ground pad are further electrically connected through a second internal wire, and the portion of the second internal wire between the first ground pad and the second ground pad is connected in parallel with the fourth bonding wire.

[0012] Optionally, all of the ground pads are disposed above the second internal wire and electrically connected through the second internal wire; at least two of the ground pads are disposed on each side edge of the die; for any two adjacent side edges of the die, one ground pad on one side edge corresponds to one ground pad on the other side edge, and the two corresponding ground pads are further electrically connected through a fourth bonding wire.

[0013] Optionally, the package structure includes a package frame, the package frame includes a base island and the first pin located on the side edge of the base island, and the die is mounted on the base island.

[0014] Optionally, the first pin and the second pin are disposed near different side edges of the die, or the first pin and the second pin are disposed near the same side edge of the die.

[0015] In the chip packaging structure provided by the present invention, the first pin is a power pin or a ground pin. A first access pad and a functional pad electrically connected by a first internal wire are provided on the first side of the die. The first pin is electrically connected to the first access pad through a first bonding wire. A functional pad is also provided on the second side of the die adjacent to the first side. A functional pad on the first side is electrically connected to a functional pad on the second side through a second bonding wire, that is, in the present invention, the functional pads on adjacent sides of the die are electrically connected by a bonding wire crossing above the die. Since the line width of the bonding wire is usually greater than that of the internal wire of the die, compared with the case where the functional pads on adjacent sides are only electrically connected by the metal wires inside the die, the electrical connection of the functional pads on adjacent sides of the die by the bonding wire in the present invention can reduce the impedance of electrical conduction, and thus can improve the voltage drop performance, electrostatic discharge performance and electromagnetic compatibility performance of the die; in addition, since the distance between the functional pads on adjacent sides is relatively small, the electrical connection of the functional pads on adjacent sides of the die by the bonding wire can also avoid the problem of bonding wire collapse, and thus can improve the reliability of the chip packaging structure, and the effect is particularly significant for large-area dies.

[0016] Further, the two functional pads electrically connected by the second bonding wire are also electrically connected by a first internal wire, and the part of the first internal wire between the two functional pads is in parallel with the second bonding wire, so that the impedance of electrical conduction can be further reduced. Description of the Drawings

[0017] Figure 1 It is a schematic plan view of a chip packaging structure provided by an embodiment of the present invention.

[0018] Figure 2 It is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the present invention.

[0019] Figure 3 It is a schematic cross-sectional view of a chip packaging structure provided by another embodiment of the present invention.

[0020] Figure 4 It is a schematic plan view of a chip packaging structure provided by another embodiment of the present invention.

[0021] Description of the reference numerals: 10-bare die; 11-first side; 12-second side; 13-third side; 14-fourth side; 15-first internal wire; 16-second internal wire; 17-through hole; 110-first access pad; 111-first power pad; 112-second power pad; 113-third power pad; 114-fourth power pad; 115-fifth power pad; 116-sixth power pad; 117-seventh power pad; 118-eighth power pad; 120-second access pad; 121-first ground pad; 122-second ground pad; 123- The third ground pad; 124-the fourth ground pad; 125-the fifth ground pad; 126-the sixth ground pad; 127-the seventh ground pad; 128-the eighth ground pad; 20-the package frame; 21-the first pin; 22-the second pin; 23-the base island; 301-the first bonding wire; 302-one of the second bonding wires; 303-the second bonding wire; 304-the second bonding wire; 305-the second bonding wire; 306-the third bonding wire; 307-one of the fourth bonding wires; 308-the fourth bonding wire; 309-the fourth bonding wire; 310-the fourth bonding wire. DETAILED DESCRIPTION

[0022] The chip packaging structure proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0023] The words "first", "second" and similar words used in the present specification do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, the words "a" or "an" and similar words do not indicate a quantity limitation, but indicate the existence of at least one. "Multiple" or "several" means two or more. Unless otherwise specified, the words "upper / upper layer" and / or "lower / lower layer" and similar words are only for convenience of description and are not limited to one position or one spatial orientation.

[0024] In order to realize the packaging form of a single power pin and / or a single ground pin, reduce the impedance of electrical conduction, and improve the voltage drop performance, electrostatic release performance and electromagnetic compatibility performance of the bare chip, the present invention provides a chip packaging structure.

[0025] Figure 1 A schematic plan view of a chip packaging structure provided by an embodiment of the present invention. Figure 2 A schematic cross-sectional view of a chip packaging structure provided by an embodiment of the present invention. Figure 1 and Figure 2As shown, the chip packaging structure provided in this embodiment includes a die 10, a first pin 21, and multiple bonding wires.

[0026] The die 10 includes a first internal wire 15 located inside the die 10 and multiple pads located on the surface of the die 10. The multiple pads include a first access pad 110 and multiple functional pads; the die 10 has adjacent first and second sides 11 and 12. The first access pad 110 is disposed on the first side 11, and functional pads are disposed on both the first side 11 and the second side 12. The first access pad 110 and the functional pads on the first side are electrically connected through the first internal wire 15.

[0027] The first pin 21 is located on one side of the die 10, and the first pin 21 is a power pin or a ground pin.

[0028] The multiple bonding wires include a first bonding wire 301 and at least one second bonding wire spanning over the die 10. The first bonding wire 301 electrically connects the first pin 21 and the first access pad 110, that is, one end of the first bonding wire 301 is soldered to the first pin 21 and the other end is soldered to the first access pad 110. The second bonding wire electrically connects a functional pad on the first side 11 and a functional pad on the second side 12.

[0029] Specifically, as Figure 2 shown, the chip packaging structure may include a packaging frame 20 (lead frame). The packaging frame 20 includes a die attached pad 23 and the first pin 21 located on the side of the die attached pad 23, and the die 10 is mounted on the die attached pad 23.

[0030] The material of the first pin 21 is metal. In a specific embodiment, the material of the first pin 21 may be one or several of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

[0031] The material of the die attached pad 23 may be the same as or different from that of the first pin 21. In some embodiments, the material of the die attached pad 23 is metal or an insulating material. The metal may be one or several of W, Al, Cu, Ti, Ag, Au, Pt, and Ni. The insulating material may be an inorganic insulating material or an organic insulating material. The inorganic insulating material may be one or several of silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, and carbonitride silicon. The organic insulating material may be epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin, or the organic insulating material may also be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, or polyvinyl alcohol.

[0032] In this embodiment, the die 10 is a chip particle obtained by cutting a wafer and has not undergone a packaging process. The die 10 has opposite front and back sides. The back side of the die 10 can be adhered to the base island 23 with an adhesive, but is not limited thereto. The front side of the die 10 has a plurality of pads. The material of the pads may include copper, nickel, stainless steel, or beryllium copper, but is not limited thereto.

[0033] In this embodiment, the chip packaging structure can be a QFN (Quad Flat No-leads Package) packaging structure, a QFP (quad flat package) packaging structure, or an LQFP (Low-profile Quad Flat Package) packaging structure.

[0034] Exemplarily, as Figure 1 shown, the die 10 can be rectangular and has a first side 11, a second side 12, a third side 13, and a fourth side 14 that enclose the rectangle.

[0035] The die 10 can have multiple metal layers inside, such as 4 layers or 8 layers, etc. The multiple metal layers inside the die 10 include a first internal wire 15. In some embodiments, as Figure 2 shown, the first internal wire 15 can be distributed in one metal layer inside the die 10. Figure 3 This is a cross-sectional schematic diagram of a chip packaging structure provided in another embodiment of the present invention. In some embodiments, as Figure 3 shown, the first internal wire 15 can be distributed in multiple metal layers inside the die 10, for example, distributed in two metal layers. The first internal wires 15 in the multiple metal layers can be connected through vias 17 and form a parallel relationship, which helps to reduce the resistance.

[0036] As Figure 1 and Figure 2 shown, the multiple pads on the front side of the die 10 include a first access pad 110 and multiple functional pads. The first side 11 and the second side 12 of the die are adjacent. The first access pad 110 is provided on the first side 11 of the die. Functional pads are provided on both the first side 11 and the second side 12. The first internal wire 15 is electrically connected to the first access pad 110 and the functional pads on the first side 11.

[0037] In this embodiment, the first pin 21 is a power pin and the functional pads are power pads. In other embodiments, the first pin 21 can be a ground pin and the functional pads can be ground pads. Hereinafter, an example in which the first pin 21 is a single power pin and the functional pads are power pads will be described.

[0038] As Figure 1 and Figure 2As shown, a first power pad 111 is further provided on the first side 11 of the die 10. The first access pad 110 is electrically connected to the first power pad 111 through a first internal wire 15. A second power pad 112 is provided on the second side 12 of the die 10.

[0039] In this embodiment, the bonding wires are, for example, gold wires, silver wires or copper wires, etc. The wire diameter (wire width) of the bonding wire can be greater than 10 μm, for example, 18 μm.

[0040] Continue to refer to Figure 1 and Figure 2 As shown, the multiple bonding wires include a first bonding wire 301 and at least one second bonding wire that traverses above the die 10. The first bonding wire 301 is electrically connected to the first pin 21 and the first access pad 110. One of the second bonding wires 302 is electrically connected to the first power pad 111 and the second power pad 112.

[0041] It should be noted that the wire width of the internal wires of the die is usually less than 1 μm or is in the nanometer range. The wire width of the internal wires of the die is much smaller than the wire width of the bonding wire. The resistance of the internal wires of the die with the same length is much greater than that of the bonding wire. In this embodiment, the first power pad 111 and the second power pad 112 on the adjacent sides are electrically connected through one of the second bonding wires 302, which can reduce the impedance of electrical conduction, and thus can improve the voltage drop performance, electrostatic discharge performance and electromagnetic compatibility performance of the die 10; in addition, since the distance between the power pads on the adjacent sides is relatively small, the power pads on the adjacent sides of the die are connected by bonding wires, which can avoid the problem of bonding wire collapse, and thus can improve the reliability of the chip packaging structure, and the effect is particularly significant for large-area dies.

[0042] Furthermore, although theoretically the wider the wire width of the bonding wire, the smaller its resistance and the more effective it is in reducing impedance, since the resistance of the bonding wire is much smaller than the resistance of the internal metal wires of the die, in actual applications, when the conduction resistance reaches the target value, the bonding wire with the minimum wire width can be selected to greatly reduce the resistance of electrical conduction and can reduce the packaging cost.

[0043] In some embodiments, the wire width of the bonding wire and the wire width of the internal wires can be determined respectively through the simulation of the bonding wire model and the internal metal wire model, so that the best combination of the bonding wire width and the internal wire width can be selected. Among them, the bonding wire model can be established through packaging data; the internal metal wire model can be established through layout data.

[0044] Continue to refer to Figure 1 and Figure 2, in this embodiment, the two functional pads (i.e., the first power pad 111 and the second power pad 112) electrically connected by one of the second bonding wires 302 are also electrically connected by a first internal wire 15. The portion of the first internal wire 15 between the first power pad 111 and the second power pad 112 is in parallel with one of the second bonding wires 302. Compared with the case where the first power pad and the second power pad are electrically connected only by bonding wires or only by internal wires of the die, the impedance of electrical conduction can be significantly reduced in this way.

[0045] In this embodiment, at least two power pads are provided on each side of the die 10, and the power pads located on the same side are electrically connected by a first internal wire, but it is not limited thereto. In other embodiments, power pads may be provided on some adjacent sides of the die 10.

[0046] In this embodiment, for any two adjacent sides of the die 10, one power pad on one side corresponds to one power pad on the other side, and the two corresponding power pads are electrically connected by a second bonding wire. In this way, the resistance can be significantly reduced. In other embodiments, only the power pads on the adjacent sides of only part of the die 10 are electrically connected by the second bonding wire.

[0047] In this embodiment, as Figure 2 shown, all power pads are provided above the first internal wire 15 and are electrically connected to the first internal wire 15 through via holes 17.

[0048] Exemplarily, as Figure 1 shown, the first side 11 of the die is provided with a first power pad 111 and an eighth power pad 118. The first power pad 111 and the eighth power pad 118 can be provided on both sides of the first access pad 110 and are both electrically connected to the first access pad 110 through the first internal wire 15; the second side 12 of the die is provided with a second power pad 112 and a third power pad 113, and the second power pad 112 and the third power pad 113 are electrically connected by the first internal wire 15; the third side 13 of the die is provided with a fourth power pad 114 and a fifth power pad 115, and the fourth power pad 114 and the fifth power pad 115 are electrically connected by the first internal wire 15; the fourth side 14 of the die is provided with a sixth power pad 116 and a seventh power pad 117, and the sixth power pad 116 and the seventh power pad 117 are electrically connected by the first internal wire 15.

[0049] In this embodiment, as Figure 1As shown, the first internal wire 15 can be multiple electrically connected parts. The first internal wire 15 electrically connects the first power pad 111 and the second power pad 112, electrically connects the third power pad 113 and the fourth power pad 114, electrically connects the fifth power pad 115 and the sixth power pad 116, and electrically connects the seventh power pad 117 and the eighth power pad 118. In other embodiments, the first internal wire 15 between the first power pad 111 and the second power pad 112, between the third power pad 113 and the fourth power pad 114, between the fifth power pad 115 and the sixth power pad 116, and between the seventh power pad 117 and the eighth power pad 118 can be disconnected, that is, the first internal wire 15 can include multiple disconnected segments.

[0050] In this embodiment, as Figure 1 shown, the multiple second bonding wires can further include the second bonding wire two 303, the second bonding wire three 304, and the second bonding wire four 305. The second bonding wire two 303 can electrically connect the third power pad 113 and the fourth power pad 114, and the part of the first internal wire 15 between the third power pad 113 and the fourth power pad 114 is in parallel with the second bonding wire two 303. The second bonding wire three 304 can electrically connect the fifth power pad 115 and the sixth power pad 116, and the part of the first internal wire 15 between the fifth power pad 115 and the sixth power pad 116 is in parallel with the second bonding wire three 304. The second bonding wire four 305 can electrically connect the seventh power pad 117 and the eighth power pad 118, and the part of the first internal wire 15 between the seventh power pad 117 and the eighth power pad 118 is in parallel with the second bonding wire four 305.

[0051] In another embodiment of the present application, the chip package structure can have a single power pin and a single ground pin at the same time. The chip package structure in the following situation will be described.

[0052] Figure 4 is a schematic plan view of the chip package structure provided by another embodiment of the present invention. As Figure 4 shown, the chip package structure includes a first pin 21 and a second pin 22 located on the side of the die 10. The first pin 21 can be a power pin, and the second pin 22 can be a ground pin. Among them, the electrical connection status of the first pin 21 with the first access pad 110 of the die 10 and with the multiple power pads on the surface of the die 10 is as described above and will not be elaborated here.

[0053] As Figure 4 shown, the die 10 can further have a second internal wire 16 located inside the die 10. The multiple pads on the surface of the die 10 can further include a second access pad 120 and multiple ground pads.

[0054] The plurality of ground pads includes a first ground pad 121 and a second ground pad 122. The second access pad 120 and the second pin 22 are electrically connected through a third bonding wire 306. The second access pad 120 and the first ground pad 121 are disposed on the same side edge of the die 10, for example, both are disposed on the third side edge 13 of the die, and are electrically connected through a second internal wire 16. The first ground pad 121 and the second ground pad 122 are respectively disposed on two adjacent side edges of the die 10, and are electrically connected through one of the fourth bonding wires 307 spanning above the die 10.

[0055] As Figure 4 shown, the first ground pad 121 and the second ground pad 122 are also electrically connected through the second internal wire 16. The portion of the second internal wire 16 between the first ground pad 121 and the second ground pad 122 is in parallel with one of the fourth bonding wires 307 connecting the first ground pad 121 and the second ground pad 122, so that the resistance can be further reduced.

[0056] In this embodiment, all the ground pads can be disposed above the second internal wire 16 and are electrically connected through the second internal wire 16.

[0057] In this embodiment, at least two ground pads can be disposed on each side edge of the die 10; for any two adjacent side edges of the die 10, one ground pad on one side edge corresponds to one ground pad on the other side edge, and the corresponding two ground pads are also electrically connected through a fourth bonding wire, but not limited thereto.

[0058] Exemplarily, as Figure 4 shown, the third side edge 13 of the die is provided with a first ground pad 121 and an eighth ground pad 128. The first ground pad 121 and the eighth ground pad 128 can be disposed on both sides of the second access pad 120 and are both electrically connected to the second access pad 120 through the second internal wire 16; the second side edge 12 of the die 10 is provided with a second ground pad 122 and a third ground pad 123, and the second ground pad 122 and the third ground pad 123 are electrically connected through the second internal wire 16; the first side edge 11 of the die is provided with a fourth ground pad 124 and a fifth ground pad 125, and the fourth ground pad 124 and the fifth ground pad 125 are electrically connected through the second internal wire 16; the fourth side edge 14 of the die is provided with a sixth ground pad 126 and a seventh ground pad 127, and the sixth ground pad 126 and the seventh ground pad 127 are electrically connected through the second internal wire 16.

[0059] As Figure 4As shown, the second internal wire 16 can be multiple electrically connected parts. The second internal wire 16 can also be electrically connected to the first ground pad 121 and the second ground pad 122, electrically connected to the third ground pad 123 and the fourth ground pad 124, electrically connected to the fifth ground pad 125 and the sixth ground pad 126, and electrically connected to the seventh ground pad 127 and the eighth ground pad 128. In other embodiments, the second internal wire 16 between the first ground pad 121 and the second ground pad 122, between the third ground pad 123 and the fourth ground pad 124, between the fifth ground pad 125 and the sixth ground pad 126, and between the seventh ground pad 127 and the eighth ground pad 128 can be disconnected, that is, the second internal wire 16 includes multiple disconnected segments.

[0060] As Figure 4 shown, the multiple fourth bonding wires can also include the second fourth bonding wire 308, the third fourth bonding wire 309, and the fourth fourth bonding wire 310. The second fourth bonding wire 308 can be electrically connected to the third ground pad 123 and the fourth ground pad 124, and the portion of the second internal wire 16 between the third ground pad 123 and the fourth ground pad 124 is in parallel with the second fourth bonding wire 308. The third fourth bonding wire 309 can be electrically connected to the fifth ground pad 125 and the sixth ground pad 126, and the portion of the second internal wire 16 between the fifth ground pad 125 and the sixth ground pad 126 is in parallel with the third fourth bonding wire 309. The fourth fourth bonding wire 310 can be electrically connected to the seventh ground pad 127 and the eighth ground pad 128, and the portion of the second internal wire 16 between the seventh ground pad 127 and the eighth ground pad 128 is in parallel with the fourth fourth bonding wire 310.

[0061] As Figure 4 shown, in this embodiment, the first pin 21 and the second pin 22 are arranged close to different sides of the die 10. In other embodiments, the first pin 21 and the second pin 22 can be arranged close to the same side of the die 10. The multiple ground pads are arranged on the periphery of the multiple power pads, or, the multiple power pads are arranged on the periphery of the multiple ground pads, but not limited thereto.

[0062] In the chip packaging structure provided by the present invention, the first pin 21 is a power pin or a ground pin. A first access pad 110 and a functional pad electrically connected through a first internal wire 15 are provided on the first side 11 of the die 10. The first pin 21 is electrically connected to the first access pad 110 through a first bonding wire 301. Functional pads are also provided on the second side 12 of the die 10 adjacent to the first side 11. A functional pad on the first side 11 is electrically connected to a functional pad on the second side 12 through a bonding wire spanning over the die 10. That is, in the present invention, the functional pads on the adjacent sides of the die 10 are electrically connected through a second bonding wire spanning over the die 10. Since the line width of the bonding wire is usually greater than that of the internal wire of the die, compared with the case where the functional pads on the adjacent sides are only electrically connected through the metal wires inside the die, the electrical connection of the functional pads on the adjacent sides of the die 10 through the second bonding wire in the present invention can reduce the impedance of electrical conduction, and thus can improve the voltage drop performance, electrostatic discharge performance and electromagnetic compatibility performance of the die 10. In addition, since the distance between the functional pads on the adjacent sides is relatively small, the electrical connection of the functional pads on the adjacent sides of the die 10 through the bonding wire can also avoid the problem of bonding wire sagging, and thus can improve the reliability of the chip packaging structure, and the effect is particularly significant for large-area dies.

[0063] Further, the two functional pads electrically connected by the second bonding wire are also electrically connected through the first internal wire 15, and the part of the first internal wire 15 between the two functional pads is in parallel with the second bonding wire, so that the impedance of electrical conduction can be further reduced.

[0064] It should be noted that this specification is described in a progressive manner. The parts described later mainly focus on the differences from the parts described earlier. For the same and similar parts between each part, reference can be made to each other.

[0065] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the rights of the present invention in any way. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention all belong to the protection scope of the technical solution of the present invention.

Claims

1. A chip packaging structure, characterized in that, The chip packaging structure includes: A die, the die includes a first internal wire located inside the die and a plurality of pads located on the surface of the die, and the plurality of pads include a first access pad and a plurality of functional pads; the die has adjacent first and second sides, the first access pad is disposed on the first side, and the functional pads are disposed on both the first side and the second side, and the first access pad and the functional pads on the first side are electrically connected through the first internal wire; A first pin, located on one side of the die, and the first pin is a power pin or a ground pin; and A plurality of bonding wires, including a first bonding wire and at least one second bonding wire spanning over the die, the first bonding wire electrically connects the first pin and the first access pad, the second bonding wire electrically connects a functional pad on the first side and a functional pad on the second side, and the two functional pads electrically connected by the second bonding wire are also electrically connected through the first internal wire, and the portion of the first internal wire between the two functional pads is in parallel with the second bonding wire.

2. The chip packaging structure according to claim 1, characterized in that, At least two functional pads are disposed on each side of the die, and the functional pads on the same side are electrically connected through the first internal wire; for any two adjacent sides of the die, a functional pad on one side corresponds to a functional pad on the other side, and the two corresponding functional pads are electrically connected through a second bonding wire.

3. The chip packaging structure according to claim 2, wherein All the functional pads are disposed above the first internal wire and are electrically connected through the first internal wire.

4. The chip packaging structure according to claim 1, wherein The first internal wire includes a plurality of connected parts or a plurality of disconnected segments.

5. The chip packaging structure according to claim 1, wherein, The first internal wire is distributed in a metal layer inside the die; or, the first internal wire is distributed in multiple metal layers inside the die, and the first internal wires in the multiple metal layers are in parallel through via holes.

6. The chip packaging structure according to claim 1, characterized in that The first pin is the power pin, and the functional pads are power pads.

7. The chip packaging structure according to claim 6, wherein The chip packaging structure further includes a second pin located on one side of the die, and the second pin is a ground pin; The die further has a second internal wire located inside the die; The plurality of pads further include a second access pad and a plurality of ground pads, and the plurality of ground pads include a first ground pad and a second ground pad; the second access pad and the second pin are electrically connected through a third bonding wire, the second access pad and the first ground pad are disposed on the same side of the die and are electrically connected through the second internal wire, and the first ground pad and the second ground pad are respectively disposed on two adjacent sides of the die and are electrically connected through a fourth bonding wire spanning over the die.

8. The chip packaging structure according to claim 7, characterized in that, The first ground pad and the second ground pad are also electrically connected through the second internal wire, and the portion of the second internal wire between the first ground pad and the second ground pad is in parallel with the fourth bonding wire.

9. The chip packaging structure according to claim 7, wherein, All the ground pads are disposed above the second internal wire and are electrically connected through the second internal wire; at least two ground pads are disposed on each side of the die; for any two adjacent sides of the die, one ground pad on one side corresponds to one ground pad on the other side, and the two corresponding ground pads are also electrically connected through a fourth bonding wire.

10. The chip packaging structure according to claim 1, characterized in that, The packaging structure includes a packaging frame, the packaging frame includes a base island and the first pins located on the sides of the base island, and the die is mounted on the base island.

11. The chip packaging structure according to claim 7, wherein, The first pins and the second pins are disposed close to different sides of the die, or the first pins and the second pins are disposed close to the same side of the die.

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