Vertical cavity surface emitting semiconductor laser and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductor lasers, in particular to a vertical-cavity surface-emitting semiconductor laser and a manufacturing method thereof.The vertical-cavity surface-emitting semiconductor laser comprises a substrate, an N-face electrode, an N-type DBR layer, an N-type limiting layer, an active region, a P-type limiting layer, a P-type DBR layer, a limiting layer, a medium filling layer, a surface passivation layer, a P-face electrode, a P-type metal contact and an ALD layer; the material of the limiting layer comprises BiSe, and the limiting hole is of a rotary asymmetric structure. The bandwidth and the relative intensity noise RIN of the laser are greatly improved, so that the laser prepared by the scheme of the invention can meet the requirements of high bandwidth and low noise required by a single-channel 100Gbps link; biSe is innovatively used for manufacturing the limiting layer of the VCSEL laser, the preparation process of a VCSEL product is simplified, and the product bandwidth and the process uniformity are improved; a limiting layer of a VCSEL laser is manufactured by innovatively using a rotational asymmetric morphology, and the relative intensity noise performance of a product is optimized.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor lasers, and particularly to a vertical cavity surface emitting semiconductor laser and a manufacturing method thereof. Background Art

[0002] Currently, for short-distance transmission links with a single-channel 100 Gbps, vertical cavity surface emitting lasers stand out among many semiconductor optical communication chips due to their advantages such as high speed, high reliability, easy coupling, low power consumption, low cost, and compatibility with existing multimode fiber cabling systems, becoming the preferred optical chip solution for data centers and short-distance optical communication. Along with the increasing market demand, higher requirements are also put forward for the transmission rate of VCSEL optical chips.

[0003] For traditional oxidation-confined vertical cavity surface emitting lasers, reducing the confinement aperture and thus reducing the mode volume is the main strategy to increase the bandwidth. However, it is quite challenging to achieve a confinement aperture smaller than 4 microns because of the strict requirements for high reliability and repeatability of devices in mass production. In addition, the oxide layer also imposes certain restrictions on the thermal diffusion of the device. Moreover, the design constraints brought by the process make it extremely difficult for oxide vertical cavity surface emitting lasers to achieve a bandwidth higher than 35 GHz.

[0004] It is very difficult to achieve the high bandwidth required for a single-channel 100 Gbps link through traditional oxidation-confined vertical cavity surface emitting laser technology. The limitations of the technology based on traditional oxidation-confined vertical cavity surface emitting laser (VCSEL) chips are becoming increasingly prominent. Summary of the Invention

[0005] To solve the above problems, this application provides a vertical cavity surface emitting semiconductor laser and a manufacturing method thereof.

[0006] One objective of this application is to provide a vertical cavity surface emitting semiconductor laser, adopting the following technical solution: A vertical cavity surface emitting semiconductor laser includes a substrate, an N-side electrode, an N-type DBR layer, an N-type confinement layer, an active region, a P-type confinement layer, a P-type DBR layer, a confinement layer, a dielectric filling layer, a surface passivation layer, a P-side electrode, a P-type metal contact, and an ALD layer. A confinement hole is formed in the confinement layer, and the material of the confinement layer includes Bi2Se3.

[0007] By adopting the above technical solution, the material of the confinement layer is grown through Bi2Se3. The current confinement of Bi2Se3 is determined by the intrinsic characteristics of the material, avoiding the pore diameter fluctuations caused by wet oxidation. The deviation of the traditional process is ±10%, while the process deviation of this application is <±2%. In addition, the confinement layer of Bi2Se3 has the effects of ultra-low resistance and efficient carrier injection. The surface state electron mobility of Bi2Se3 is as high as 10 4 ~10 5 cm² / (V·s), far exceeding that of GaAs bulk material (~8000 cm² / (V·s)), significantly reducing the series resistance and improving the AC performance of the laser. The confinement layer of Bi2Se3 also has high temperature stability and device reliability. The Bi2Se3 material remains stable below 300 °C, enabling the VCSEL to continuously operate in an environment of 150 °C. While the traditional oxide layer is prone to structural relaxation at >100 °C. The high thermal conductivity of the Bi2Se3 layer (the thermal conductivity of Bi2Se3 is ~2 W / m·K) improves the heat dissipation efficiency, and the device thermal resistance is reduced to 5 K / W (the traditional structure is 10 - 15 K / W). The Bi2Se3 layer also has the advantage of polarization controllable output. The spin-momentum locking property (Spin-Momentum Locking) of the Bi2Se3 surface state induces carrier spin polarization, making the output light have a specific polarization direction (extinction ratio >30 dB).

[0008] Preferably, the confinement hole is a rotationally asymmetric structure.

[0009] By adopting the above technical solution, relative intensity noise (RIN) is the core index to measure the output light intensity stability of the laser, which is defined as the ratio of the power spectral density of the light intensity fluctuation to the square of the average light intensity (RIN = ⟨ΔP²⟩ / ⟨P⟩²). In VCSELs, RIN mainly comes from the following mechanisms: 1) Carrier density fluctuations, relaxation oscillations caused by carrier-photon interactions (Relaxation Oscillation). 2) Mode competition noise: Energy competition between multiple transverse modes or polarization modes causes instantaneous power fluctuations. 3) Spatial hole burning effect: Local gain saturation caused by uneven carrier distribution. Due to symmetry limitations, traditional circular aperture VCSELs have a large RIN (poor performance). While the rotationally asymmetric aperture significantly suppresses RIN through the following physical mechanisms: 1) Carrier transport optimization: The asymmetric aperture restricts the diffusion of carriers in a specific direction, forming a directional carrier transport channel, reducing the spatial fluctuations of the carrier density. The carrier density non-uniformity is reduced from 5% of the circular aperture to 1% of the asymmetric structure, corresponding to the RIN spectral width being compressed to 2 GHz (5 GHz for the circular aperture). 2) The rotationally asymmetric aperture changes the optical field distribution in the cavity through geometric anisotropy. The optical field localization in the long axis direction is stronger, resulting in lower loss of the fundamental transverse mode (LP 01 ), than that of the higher-order mode (LP 11etc.) to suppress multimode oscillation. The asymmetric structure breaks the polarization degeneracy, forces the locking of a single polarization state, and eliminates polarization mode competition noise. 3) The rotating asymmetric aperture disperses carrier consumption through a non-uniform optical field distribution, avoiding carrier depletion in the central region (i.e., "spatial hole burning") caused by the symmetric optical field in a circular aperture. Improvement in gain uniformity: The standard deviation of the light intensity distribution decreases from 30% of the circular aperture to 10% of the asymmetric structure, reducing the non-linear gain coefficient (ε) from 1×10⁻²³ m³ to 3×10⁻² 4 m³, and the RIN is reduced by 4 dB in the region above the threshold. The rotating asymmetric aperture VCSEL reduces the RIN noise to below -148 dB / Hz through a triple mechanism of mode competition suppression, carrier localization, and thermo-optical coupling optimization, which is 5 - 7 dB / Hz higher than that of the circular structure.

[0010] Preferably, a buffer layer is inserted into the confinement layer, and the buffer layer material is AlAs.

[0011] Preferably, an intermediate layer is inserted into the buffer layer, and the material of the intermediate layer is hexagonal boron nitride.

[0012] By adopting the above technical solutions, the buffer layer alleviates the lattice mismatch (Bi2Se3 lattice constant 4.14 Å vs. GaAs 5.65 Å). Using hexagonal boron nitride as the intermediate layer, a low-defect interface is achieved through weak van der Waals force coupling, and the surface roughness is <0.5 nm. The defect density can be reduced to 10¹ 0 cm⁻² or less. The Dirac surface state electrons of Bi2Se3 have the property of spin-momentum locking, forming a conductive channel with a high mobility (>10 4 cm² / (V·s)), while the bulk phase remains insulating. In the VCSEL, the Bi2Se3 layer covers the mesa sidewall, and its bulk phase insulation property is used to laterally block the current, allowing the current to be injected into the quantum well active region only through the top surface state, realizing self-aligned current confinement.

[0013] Another object of the present application is to provide a manufacturing method of a vertical cavity surface emitting semiconductor laser, adopting the following technical solutions: A manufacturing method of a vertical cavity surface emitting semiconductor laser for manufacturing the above-mentioned vertical cavity surface emitting semiconductor laser, including, S1. Using molecular beam epitaxy technology to grow an N-type DBR layer, an N-type confinement layer, an active region, a λ / 2 cavity, and a P-type confinement layer on a substrate respectively; S2. Using molecular beam epitaxy to grow a confinement layer on the P-type confinement layer with Bi2Se3 as the material.

[0014] By adopting the above technical solution, using Bi2Se3 as the material to grow the confinement layer can simplify the process, eliminate the oxidation step (wet oxidation requires high-temperature steam treatment at 400 °C or above), reduce the process flow by 30%, and increase the yield to over 90%.

[0015] Preferably, in step S2, when growing the confinement layer, insert a 1.5 nm thick buffer layer of AlAs.

[0016] Preferably, in step S2, insert a buffer layer with hexagonal boron nitride as the intermediate layer.

[0017] Preferably, in step S2, use a step-and-repeat projection lithography machine to transfer the rotationally asymmetric conductive pattern onto the confinement layer, and then use a focused ion beam for irradiation treatment to destroy the Dirac surface state and induce insulation to form confinement holes.

[0018] By adopting the above technical solution, it is very difficult for the traditional wet oxidation process to achieve rotationally asymmetric confinement holes with a major axis of 3.6 μm, and it cannot be compared with the solution mentioned in this application in terms of production yield and process uniformity.

[0019] Preferably, in step S2, the growth temperature is controlled at 200 - 300 °C.

[0020] By adopting the above technical solution, the growth temperature is controlled at 200 - 300 °C to avoid damaging the VCSEL quantum well structure.

[0021] Preferably, it further includes S3. Use molecular beam epitaxy to perform secondary epitaxial growth on the confinement layer to complete the growth of the P-type DBR layer; S4. Use an evaporation process to fabricate a P-type electrode metal ring on the top of the device light-emitting area as the current injection area; S5. Grow a layer of SiNx through plasma-enhanced chemical vapor deposition process, and cover the device surface with a low-stress SiNx passivation protective film for passivation protection; S6. Isolate the device through ion implantation process and reduce the parasitic capacitance; S7. Use benzocyclobutene as the dielectric material to fill the positive and negative electrode areas of the chip to reduce the parasitic parameters of the chip itself; S8. Grow a layer of SiNx through plasma-enhanced chemical vapor deposition process as the optical dielectric film of the chip light-emitting hole; S9. Remove the dielectric film above the current injection area in S1 through dry etching process, and use the metal of the current injection area in S1 as the seed gold to grow the P-type electrode by electroplating process; S10. Use an evaporation process to fabricate and grow the front N-type electrode; S11. Use the ALD process to passivate the chip device area, protect the internal structure of the chip, and improve the reliability of the chip; S12. Grind and thin the chip; S13. Evaporate metal on the back side; S14. Perform RTA treatment; S15. Test and age; S16. Cut and sort.

[0022] In summary, this application includes at least one of the following beneficial technical effects: 1. Under the condition of meeting the reliability requirements of commercial laser applications, the AC performance of VCSEL laser products has been greatly improved. In particular, the bandwidth and relative intensity noise (RIN) of the laser have been significantly improved, enabling the lasers prepared by the preferred solution of this patent to meet the high-bandwidth and low-noise requirements of single-channel 100Gbps links; 2. Innovatively use Bi2Se3 to manufacture the confinement layer of VCSEL lasers, simplify the manufacturing process of VCSEL products, and improve the product bandwidth and process uniformity; 3. Innovatively use a rotationally asymmetric morphology to manufacture the confinement holes of VCSEL lasers, and optimize the relative intensity noise performance of the products. Description of the Drawings

[0023] Figure 1 is a schematic cross-sectional structure diagram of Example 1; Figure 2 is a schematic plan structure diagram of Example 1; Figure 3 is a test curve graph of the laser bandwidth in Example 1; Figure 4 is a test curve graph of the relative intensity noise of the laser in Example 1; Figure 5 is the eye diagram of the laser in Example 1; Figure 6 is the reliability verification diagram of the laser in Example 1; Figure 7 is the preparation process diagram of the confinement holes in S in Example 2.

[0024] Description of the Reference Numerals: 1. Substrate; 2. N-side electrode; 3. N-type DBR layer; 4. N-type confinement layer; 5. Active region; 6. P-type confinement layer; 7. P-type DBR layer; 8. Confinement layer; 9. Dielectric filling layer; 10. Surface passivation layer; 11. P-side electrode; 12. P-type metal contact; 13. ALD layer; 14. Back-side N-type electrode; 15. Confinement hole. Detailed Embodiments

[0025] The present application will be further described in detail below in conjunction with all the accompanying drawings.

[0026] Embodiment 1

[0027] The embodiment of the present application discloses a vertical cavity surface emitting semiconductor laser. Referring to Figures 1 to 2 , it includes a substrate 1, an N-side electrode 2, an N-type DBR layer 3, an N-type confinement layer 4, an active region 5, a P-type confinement layer 6, a P-type DBR layer 7, a confinement layer 8, a dielectric filling layer 9, a surface passivation layer 10, a P-side electrode 11, a P-type metal contact 12, and an ALD layer 13. A back N-type electrode 14 is provided at the bottom of the substrate 1.

[0028] Referring to Figures 1 to 2 , the material of the N-type substrate 1 is GaAs; the material of the N-side electrode 2 is Au / Ge / Ni / Au. The material of the N-type DBR layer 3 is GaAs / AlAs, and AlAs is used as a heat dissipation layer, providing relatively high reliability. The material of the N-type confinement layer 4 is AlGaAs; the active region 5 has a material of InGaAs / AlGaAs strained quantum well structure. The material of the P-type confinement layer 6 is AlGaAs; the material of the P-type DBR layer 7 is GaAs / AlGaAs.

[0029] Referring to Figures 1 to 2 , the material of the confinement layer 8 is Bi2Se3, and a confinement hole 15 with a rotationally asymmetric structure, such as a semicircle, is formed on the confinement layer 8. A buffer layer is inserted into the confinement layer 8, the material of the buffer layer is AlAs, and an intermediate layer is inserted into the buffer layer, and the material of the intermediate layer is hexagonal boron nitride.

[0030] Referring to Figures 1 to 2 , the material of the dielectric filling layer 9 is BCB (benzocyclobutene), reducing the external parasitic capacitance. The material of the surface passivation layer 10 is SiNx, providing a passivation protection effect. The material of the P-side electrode 11 is Ti / Pt / Au. The material of the optical dielectric film is SiNx, and the refractive index can be changed by controlling the film thickness to adjust the optical characteristics. The material of the ALD layer 13 is Al2O3, which is a passivation layer of the laser, protecting the inside of the laser from water vapor erosion and improving the reliability of the product. The material of the back N-type electrode 14 is Au / Ge / Ni / Au. Designing an N-type electrode on the back of the laser is beneficial for the laser to adapt to different packaging scenarios at the application end and improve the compatibility of the laser at the application end.

[0031] Referring to Figure 3 , for a vertical cavity surface emitting semiconductor laser in the present application, the room temperature -3dB bandwidth is as high as 35 GHz under the working current, and the high temperature -3dB bandwidth is as high as 30 GHz, with performance superior to traditional lasers.

[0032] Referring to Figure 4, at the operating current, the relative intensity noise at room temperature is lower than -148 dB / Hz, and the relative intensity noise at high temperature is lower than -145 dB / Hz, with performance superior to traditional lasers. It meets the IEEE802.3 (Institute of Electrical and Electronics Engineers) standard for the relative noise intensity of VCSEL products (<138 dB / Hz).

[0033] Refer to Figure 5 , at the operating current, the eye diagram TDECQ at room temperature is 1.32 dB, and the eye diagram TDECQ at high temperature is 2.61 dB, meeting the IEEE802.3 (Institute of Electrical and Electronics Engineers) standard for the eye diagram TDECQ of VCSEL products (<3 dB).

[0034] Refer to Figure 6 , it meets the reliability requirements of VCSELs for commercial data communication applications (at a current of 8 mA and a usage condition of 75 °C, the time to 1% device failure (TT1%F) is greater than 10 years.

[0035] Example Two

[0036] The embodiment of the present application discloses a manufacturing method of a vertical cavity surface emitting semiconductor laser, including, S1. Use molecular beam epitaxy (MBE) to form an epitaxial layer on one side surface of the substrate. The epitaxial layer includes an N-type DBR layer, an N-type confinement layer, an active region, a λ / 2 cavity, and a P-type confinement layer stacked in sequence.

[0037] S2. Use molecular beam epitaxy (MBE) to grow a confinement layer on the above epitaxial layer with Bi2Se3 as the material; a 1.5 nm AlAs buffer layer needs to be inserted during the growth process to relieve lattice mismatch (Bi2Se3 lattice constant 4.14 Å vs. GaAs 5.65 Å). Use hexagonal boron nitride (h-BN) as the intermediate layer to achieve a low-defect interface through weak van der Waals coupling, and the surface roughness is <0.5 nm. The defect density can be reduced to below 10¹ 0 cm⁻². The growth temperature is controlled at 200 - 300 °C to avoid damaging the VCSEL quantum well structure. Use a stepper to transfer the rotationally asymmetric conductive pattern onto the confinement layer, and then use a focused ion beam (Ga⁺ ions) for irradiation treatment to destroy the Dirac surface state and induce insulation to form a confinement hole (the diameter is controlled at 3.5 un + / - 0.1).

[0038] S3. Use molecular beam epitaxy (MBE) to perform secondary epitaxial growth on the confinement layer to complete the growth of the P-type DBR layer.

[0039] Among them, the principle of using Bi2Se3 with hexagonal boron nitride (h-BN) as an intermediate layer inserted into the buffer layer (AlAs) as the confinement layer of the patented VCSEL laser is as follows: The Dirac surface state electrons of Bi2Se3 have the spin-momentum locking property, forming a high-mobility (>10 4 cm² / (V·s)) conductive channel, while the bulk phase remains insulating. In a VCSEL, the Bi2Se3 layer covers the mesa sidewalls, and its bulk-phase insulating property is used to laterally block the current, allowing the current to be injected into the quantum well active region only through the top surface states, achieving self-aligned current confinement.

[0040] The advantages of using Bi2Se3 with hexagonal boron nitride (h-BN) as an intermediate layer inserted into the buffer layer (AlAs) as the confinement layer of the patented VCSEL laser are as follows: 1. Process simplification: The oxidation step is omitted (wet oxidation requires high-temperature steam treatment at above 400°C), the process flow is reduced by 30%, and the yield is increased to over 90%. 2. Aperture uniformity: The current confinement of Bi2Se3 is determined by the material's intrinsic properties, avoiding the aperture diameter fluctuations caused by wet oxidation (the deviation of the traditional process is ±10%, and the deviation of this patented process is <±2%). 3. Ultra-low resistance and efficient carrier injection: The electron mobility of the Bi2Se3 surface states is as high as 10 4 ~10 5 cm² / (V·s), far exceeding that of the GaAs bulk material (~8000 cm² / (V·s)), significantly reducing the series resistance and improving the AC performance of the laser. 4. High temperature stability and device reliability: The Bi2Se3 material remains stable below 300°C, enabling the VCSEL to continuously operate in an environment of 150°C (the traditional oxide layer is prone to structural relaxation at >100°C). The high thermal conductivity of Bi2Se3 (the thermal conductivity of Bi2Se3 is ~2 W / m·K) improves the heat dissipation efficiency, and the device thermal resistance is reduced to 5 K / W (the traditional structure is 10 - 15 K / W). 5. Polarization-controllable output: The spin-momentum locking property (Spin-Momentum Locking) of the Bi2Se3 surface states induces carrier spin polarization, making the output light have a specific polarization direction (extinction ratio >30 dB). 6. It is very difficult to achieve a rotationally asymmetric oxidation confinement layer (semicircular arc) with a major axis of 3.6 um by the traditional wet oxidation process, and it cannot be compared with the preferred solution mentioned in the patent in terms of production yield and process uniformity.

[0041] The advantages of using rotational asymmetry (arc-shaped) as the confinement layer of a patented VCSEL laser are as follows: Relative intensity noise (RIN) is a core indicator for measuring the stability of the output optical intensity of a laser, and it is defined as the ratio of the power spectral density of the optical intensity fluctuation to the square of the average optical intensity (RIN = ⟨ΔP²⟩ / ⟨P⟩²). In VCSELs, RIN mainly stems from the following mechanisms: 1. Carrier density fluctuations and relaxation oscillations caused by carrier-photon interactions. 2. Mode competition noise: Energy competition between multiple transverse modes or polarization modes leads to instantaneous power fluctuations. 3. Spatial hole burning effect: Local gain saturation caused by uneven carrier distribution. Due to symmetry limitations, traditional circular-aperture VCSELs have a relatively large RIN (poor performance).

[0042] The rotationally asymmetric aperture significantly suppresses RIN through the following physical mechanisms: 1. Optimized carrier transport: The asymmetric aperture restricts the diffusion of carriers in a specific direction, forming a directional carrier transport channel, reducing the spatial fluctuations of carrier density. The carrier density non-uniformity decreases from 5% in the circular aperture to 1% in the asymmetric structure, corresponding to the compression of the RIN spectral width to 2 GHz (5 GHz for the circular aperture). 2. The rotationally asymmetric aperture (such as an arc shape) changes the optical field distribution in the cavity through geometric anisotropy. The optical field localization in the long-axis direction is stronger, resulting in lower losses for the fundamental transverse mode (LP 01 ), compared to higher-order modes (LP 11 etc.), suppressing multimode oscillations. The asymmetric structure breaks the polarization degeneracy, forcibly locking a single polarization state and eliminating polarization mode competition noise. 3. The rotationally asymmetric aperture disperses carrier consumption through a non-uniform optical field distribution, avoiding carrier depletion in the central region (i.e., "spatial hole burning") caused by the symmetric optical field in the circular aperture. Improvement in gain uniformity: The standard deviation of the optical intensity distribution decreases from 30% in the circular aperture to 10% in the asymmetric structure, reducing the non-linear gain coefficient (ε) from 1×10⁻²³ m³ to 3×10⁻² 4 m³, and reducing RIN by 4 dB in the region above threshold. The rotationally asymmetric aperture VCSEL reduces the RIN noise to below -148 dB / Hz through a triple mechanism of mode competition suppression, carrier localization, and thermo-optical coupling optimization, representing a 5 - 7 dB / Hz improvement compared to the circular structure.

[0043] S4. Using an evaporation process, a P-type electrode metal ring is fabricated on top of the device's light-emitting area as the current injection region.

[0044] S5. Growing a layer of SiNx through plasma-enhanced chemical vapor deposition to cover the device surface with a low-stress SiNx passivation protective film for passivation protection.

[0045] S6. Isolating the device and reducing the parasitic capacitance through ion implantation.

[0046] S7. Fill the positive and negative electrode regions of the chip with benzocyclobutene as the dielectric material to reduce the parasitic parameters of the chip itself.

[0047] S8. Grow a layer of SiNx by plasma-enhanced chemical vapor deposition process as the optical dielectric film of the chip light-emitting hole.

[0048] S9. Remove the dielectric film above the current injection region in S1 by dry etching process, and use the metal in the current injection region in S1 as the seed gold to grow the P-type electrode by electroplating process.

[0049] S10. Use the evaporation process to fabricate and grow the front N-type electrode.

[0050] S11. Use the ALD process to passivate the chip device region, protect the internal structure of the chip, and improve the reliability of the chip.

[0051] S12. Grind and thin the chip.

[0052] S13. Evaporate metal on the back to form the back N-type electrode.

[0053] S14. Perform RTA treatment.

[0054] S15. Test and age.

[0055] S16. Cut and sort.

[0056] The above are all preferred embodiments of this application. The protection scope of this application is not limited thereby. Therefore, all equivalent changes made according to the structure, shape, and principle of this application shall be covered within the protection scope of this application.

Claims

1. A vertical cavity surface emitting semiconductor laser, characterized in that: It includes a substrate (1), an N-side electrode (2), an N-type DBR layer (3), an N-type confinement layer (4), an active region (5), a P-type confinement layer (6), a P-type DBR layer (7), a confinement layer (8), a dielectric filling layer (9), a surface passivation layer (10), a P-side electrode (11), a P-type metal contact (12), and an ALD layer (13). A confinement hole (15) for light output is formed in the confinement layer (8), and the material of the confinement layer (8) includes Bi2Se3.

2. The vertical cavity surface emitting semiconductor laser according to claim 1, characterized in that: The confinement hole (15) is a rotationally asymmetric structure.

3. The vertical cavity surface emitting semiconductor laser according to claim 1, characterized in that: A buffer layer is inserted into the confinement layer (8), and the material of the buffer layer is AlAs.

4. A vertical cavity surface emitting semiconductor laser according to claim 3, characterized in that: An intermediate layer is inserted into the buffer layer, and the material of the intermediate layer is hexagonal boron nitride.

5. A manufacturing method of a vertical cavity surface emitting semiconductor laser, characterized in that: A method for manufacturing a vertical cavity surface emitting semiconductor laser as described in any one of claims 1-4 includes: S1: Using molecular beam epitaxy to grow an N-type DBR layer, an N-type confinement layer, an active region, a λ / 2 cavity, and a P-type confinement layer on a substrate respectively. S2: Using molecular beam epitaxy to grow a confinement layer on the P-type confinement layer with Bi2Se3 as the material.

6. The manufacturing method of a vertical cavity surface emitting semiconductor laser according to claim 5, characterized in that: In step S2, when growing the confinement layer, insert a 1.5-nm-thick buffer layer of AlAs.

7. The manufacturing method of a vertical cavity surface emitting semiconductor laser according to claim 6, characterized in that: In step S2, insert hexagonal boron nitride as the intermediate layer into the buffer layer.

8. The manufacturing method of a vertical cavity surface emitting semiconductor laser according to claim 5, characterized in that: In step S2, use a step-and-repeat projection lithography machine to transfer a rotationally asymmetric conductive pattern onto the confinement layer, and then use a focused ion beam for irradiation treatment to destroy the Dirac surface state and induce insulation to form the confinement hole.

9. The manufacturing method of a vertical cavity surface emitting semiconductor laser according to claim 5, characterized in that: In step S2, control the growth temperature at 200-300 °C.

10. The manufacturing method of a vertical cavity surface emitting semiconductor laser according to claim 5, characterized in that: It further includes: S3: Using molecular beam epitaxy to perform secondary epitaxial growth on the confinement layer to complete the growth of the P-type DBR layer. S4: Using evaporation coating technology to fabricate a P-type electrode metal ring on the top of the device light-emitting area as the current injection area. S5: Grow a layer of SiNx through plasma enhanced chemical vapor deposition technology, and cover the device surface with a low-stress SiNx passivation protection film for passivation protection. S6: Isolate the device through ion implantation technology and reduce the parasitic capacitance. S7: Use benzocyclobutene as the dielectric material to fill the positive and negative electrode areas of the chip and reduce the parasitic parameters of the chip itself. S8: Grow a layer of SiNx through plasma enhanced chemical vapor deposition technology as the optical dielectric film of the chip light output hole. S9: Remove the dielectric film above the current injection area in S1 through dry etching technology, and use the metal of the current injection area in S1 as the seed metal to grow the P-type electrode by electroplating technology. S10: Use evaporation coating technology to fabricate and grow the front N-type electrode. S11: Use ALD technology to passivate the chip device area, protect the internal structure of the chip, and improve the reliability of the chip. S12: Grind and thin the chip. S13: Evaporate metal on the back. S14: Perform RTA treatment. S15: Test and age. S16: Cut and sort.

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