Method and equipment for determining optimal resistance value of fault current limiter when regional short-circuit current exceeds standard

Abstract

The invention discloses a method and equipment for determining the optimal resistance value of a fault current limiter with regional short-circuit current exceeding the standard, and the method comprises the steps: determining a regional short-circuit current exceeding point set, and adding the fault current limiter on a branch with the maximum short-circuit current branch coefficient for a bus with the most serious exceeding; the impedance value of the branch is gradually increased, and if the branch is no longer the maximum bus branch coefficient and the number of groups of fault current limiters does not exceed a set value, the fault current limiters are configured on the branch with the maximum branch coefficient until the short-circuit current of the bus does not exceed the limit any more; comparing the economical efficiency of each scheme, and updating a standard exceeding point set; and repeating the steps until the exceeding point set is an empty set, and outputting the optimal configuration result of the fault current limiter at the moment. According to the technical scheme, the fault current limiter is dynamically configured on the branch with the highest short-circuit current branch coefficient, configuration scheme economical efficiency comparison is carried out according to the ratio of the economic cost of the fault current limiter to the current limiting effect, and therefore the optimal resistance value of the fault current limiter under the regional short-circuit current standard exceeding scene is determined.

Description

Technical Field

[0001] The present invention belongs to the technical field of short-circuit current limiting, and particularly relates to a method and device for determining the optimal resistance value of a fault current limiter with excessive regional short-circuit current. Background Art

[0002] In recent years, with the continuous increase of grid load, the continuous acceleration of power source construction, and the continuous strengthening of the grid structure, the problem of excessive short-circuit current in the whole network, especially in the densely meshed areas of the eastern grid, has gradually become prominent. The over-limitation of short-circuit current and the insufficient switching breaking capacity have hindered the further development of regional power grids, and it is urgent to carry out short-circuit current suppression. Fault current limiters based on various principles are important means to limit short-circuit current and have been gradually applied in practice. However, the resistance value selection scheme of fault current limiters usually only considers the busbar of a single substation, lacking overall consideration of the region as a whole. At the same time, the configuration scheme usually directly selects the branch with the largest branch coefficient, resulting in generally larger single-set resistance value selection, without making full use of the high current limiting sensitivity at low resistance values. In practice, problems such as excessive land occupation of a single set and difficulty in arranging within the substation site may also be faced.

[0003] Therefore, how to overall plan the overall solution for excessive regional short-circuit current, quantitatively analyze the economic cost and regional short-circuit current limiting effect of multiple sets of fault current limiter configurations, optimize the overall configuration scheme of regional fault current limiters and determine the optimal resistance value of each set of fault current limiters, and then make full use of the high current limiting sensitivity of low-resistance fault current limiters is the key to determining the optimal resistance value scheme of fault current limiters. Summary of the Invention

[0004] In order to solve the problems of not making full use of the low-resistance sensitivity and ignoring the overall planning of regional short-circuit current in the process of determining the resistance value of traditional fault current limiters, the present invention proposes a method and device for determining the optimal resistance value of a fault current limiter with excessive regional short-circuit current, dynamically configures the fault current limiter on the branch with the highest short-circuit current branch coefficient, and conducts an economic comparison of the configuration scheme according to the ratio of the economic cost to the current limiting effect of the fault current limiter, so as to determine the optimal resistance value of the fault current limiter in the scenario of excessive regional short-circuit current.

[0005] To achieve the above object, the solution of the present invention is:

[0006] A method for determining the optimal resistance value of a fault current limiter with excessive regional short-circuit current, comprising the following steps:

[0007] Step 1, scan the short-circuit current of each busbar in the regional power grid to determine the set M of points with excessive regional short-circuit current;

[0008] Step 2, for the most serious busbar K in the set M of points with excessive regional short-circuit current, calculate the short-circuit current branch coefficient of this busbar, and initially select the branch L with the largest short-circuit current branch coefficient where the fault current limiter is to be installedi superior;

[0009] Step 3: gradually increase the impedance value X of the branch where the fault current limiter is located by increments of Δx. Li , re-carry out the short-circuit current scan of the regional power grid and calculate the busbar branching coefficient. If the short-circuit current no longer exceeds the standard, output the fault current limiter resistance value X FCLi , go to step 5, otherwise go to step 4;

[0010] Step 4: If branch L i It is no longer the branch with the largest busbar branching coefficient and the number of fault current limiter groups does not exceed the set value. The output branch L i Configured fault current limiter resistance X FCLi , and further configure the fault current limiter on the branch with the largest branch coefficient, i=i+1, and repeat steps 3-4 until the short-circuit current of bus K no longer exceeds the limit;

[0011] Step 5: Calculate the economic performance index COST of each solution i , carry out economic comparison of the schemes, and then update the short-circuit current exceeding point set M;

[0012] Step 6, repeat steps 2-5 until the excess point set M is an empty set, and output the optimal configuration result of the fault current limiter at this time.

[0013] In the above step 2, the short-circuit current branching coefficient is the ratio of the short-circuit current to the total current flowing through the faulty line segment when a short circuit occurs in adjacent line segments.

[0014] In the above step 2, branch L i It is the branch with the largest short-circuit current branching coefficient corresponding to bus K, where i is the number of fault current limiter groups, which shall not exceed 3 groups.

[0015] In step 3 above, the branch impedance value X Li The specific expression is as follows:

[0016] X Li =X0+X FCLi

[0017] Among them, X0 is branch L i Initial impedance value, X FCLi is the fault current limiter impedance value.

[0018] In step 3 above, the fault current limiter resistance is X FCLi The specific expression is as follows:

[0019] X FCLi =n*Δx

[0020] Among them, n is the number of times of the loop in step 3 when the number of groups of fault current limiters is fixed at i, and Δx is the increment of the resistance value of the fault current limiter each time entering the loop.

[0021] In the above step 5, the scheme economic index COST i has the following specific expression:

[0022]

[0023] Among them, i is the number of groups of fault current limiters, M0 is the basic cost of the fault current limiter, ρ is the resistance cost coefficient of the fault current limiter, corresponding to the cost increment per 1 ohm increase in the resistance value of the fault current limiter, and E is the current limiting effect function of the fault current limiter.

[0024] The above current limiting effect function E of the fault current limiter is defined as the algebraic sum of the suppression effects of the short-circuit currents of the over-standard nodes. The specific expression of E is as follows:

[0025] E = ∑ 超标节点 (C X - C0)

[0026] Among them, C X is the short-circuit current of the over-standard node after configuring the fault current limiter, and C0 is the short-circuit current of the over-standard node in the initial state.

[0027] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor; when the processor executes the computer program, it implements the steps of the method for determining the optimal resistance value of the fault current limiter for regional short-circuit current exceeding the standard as described above.

[0028] A computer-readable storage medium stores a computer program; when the computer program is executed by a processor, it implements the steps of the method for determining the optimal resistance value of the fault current limiter for regional short-circuit current exceeding the standard as described above.

[0029] After adopting the above scheme, the beneficial effects of the present invention are as follows:

[0030] (1) The present invention dynamically configures the fault current limiter on the branch with the highest short-circuit current branch coefficient, making full use of the high current limiting sensitivity of the fault current limiter at low resistance values;

[0031] (2) The present invention overall considers the problem of regional short-circuit current exceeding the standard, conducts scheme optimization according to the ratio of the economic cost and current limiting effect of the fault current limiter, and obtains the optimal fault current limiter configuration scheme for solving the problem of regional short-circuit current exceeding the standard;

[0032] (3) The method flow of the present invention is clear and the logic is clear, which is convenient for programming to automatically generate the optimal resistance value configuration scheme of the fault current limiter. Description of the Drawings

[0033] Figure 1 is the schematic diagram of the fault current limiter applied in the present invention;

[0034] Names of the reference numerals in the figure: 1. Fault current limiter; 2. Current-limiting reactance; 3. Variable impedance switching element; 4. Equivalent external power grid; 5. Busbar; 6. Line;

[0035] Figure 2 is the flowchart of the method of the present invention. Detailed Embodiment

[0036] The technical solutions and beneficial effects of the present invention will be described in detail below with reference to the drawings.

[0037] A fault current limiter is a type of device with variable impedance used to limit the short-circuit current in the power grid. When the power grid is normal, its impedance is zero or very small. When the power grid fails, its impedance value is very large, and it can return to the low-resistance state after the fault disappears. It includes power electronic switch type, mechanical switch type, resonant type, superconducting type, and electrodynamic type fault current limiters; Figure 1 The shown figure is the schematic diagram of the fault current limiter applied in the present invention. The fault current limiter 1 is connected to the busbar 5 of the equivalent external power grid 4 through the line 6. The fault current limiter 1 includes a current-limiting reactance 2 and a variable impedance switching element 3 connected in parallel. When the power grid is operating normally, the variable impedance switching element 3 is in the closed state. At this time, the external impedance of the fault current limiter 1 is zero or very small. When a fault occurs in the power grid, the variable impedance switching element 3 changes to the open state, and the current-limiting reactance 2 is put into operation to increase the impedance value, thereby limiting the current. Once the fault disappears, it will return to the zero-impedance or low-impedance state.

[0038] As Figure 2 shown, the present invention provides a method for determining the optimal resistance value of a fault current limiter for which the short-circuit current in a region exceeds the standard, including the following steps:

[0039] Step 1, scan the short-circuit currents of each busbar in the regional power grid to determine the set M of points where the regional short-circuit current exceeds the standard;

[0040] Step 2, for the most serious busbar K in the set M of points where the regional short-circuit current exceeds the standard, calculate the short-circuit current branch coefficient of this busbar, and initially select the branch L i on which the fault current limiter is to be installed;

[0041] Among them, the short-circuit current branch coefficient is the ratio of the short-circuit current to the full current flowing through the fault line segment when a short circuit occurs in the adjacent line segment. Therefore, the branch with the largest branch coefficient is also the branch where the effect of configuring the fault current limiter is the best;

[0042] Among them, branch L iis the branch with the largest branch coefficient of the short-circuit current corresponding to the busbar K, where i is the number of fault current limiter groups, and according to the actual project, it is usually set to no more than 3 groups;

[0043] Step 3: Gradually increase the impedance value X of the branch where the fault current limiter is located in increments of Δx Li , restart the short-circuit current scanning of the regional power grid, and calculate the busbar branch coefficient. If the short-circuit current no longer exceeds the standard, output the resistance value X of the fault current limiter FCLi , go to Step 5, otherwise go to Step 4;

[0044] Among them, the fault current limiter is connected in series in the branch, and the impedance value X Li of the branch has the following specific expression:

[0045] X Li = X0 + X FCLi

[0046] Among them, X0 is the initial impedance value of branch L i , and X FCLi is the impedance value of the fault current limiter;

[0047] Among them, the resistance value X FCLi of the fault current limiter has the following specific expression:

[0048] X FCLi = n * Δx

[0049] Among them, n is the number of cycles in Step 3 when the number of fault current limiter groups is fixed at i, Δx is the increment of the resistance value of the fault current limiter after each entry into the loop, and the selection of Δx needs to balance the calculation accuracy and the calculation scale;

[0050] Step 4: If branch L i is no longer the branch with the largest busbar branch coefficient and the number of fault current limiter groups does not exceed the set value, output the resistance value X of the fault current limiter configured for branch L i , and further configure the fault current limiter on the branch with the largest branch coefficient, i = i + 1, repeat Steps 3 - 4 until the short-circuit current of busbar K no longer exceeds the limit; FCLi In Step 4, since the current limiting sensitivity of the fault current limiter is inversely proportional to the resistance value of the fault current limiter, that is, the lower the resistance value of the fault current limiter, the better the short-circuit current suppression effect per unit resistance value. Therefore, the configuration principle of the fault current limiter in Step 4 is to be dynamically configured on the branch with the highest short-circuit current branch coefficient;

[0051] In Step 4, since the current limiting sensitivity of the fault current limiter is inversely proportional to the resistance value of the fault current limiter, that is, the lower the resistance value of the fault current limiter, the better the short-circuit current suppression effect per unit resistance value. Therefore, the configuration principle of the fault current limiter in Step 4 is to be dynamically configured on the branch with the highest short-circuit current branch coefficient;

[0052] Step 5: Calculate the economic index COST i of each scheme, conduct an economic comparison of the schemes, and then update the short-circuit current over-limit point set M;

[0053] Among them, the scheme economic index COST i is defined as the ratio of the economic cost of the fault current limiter to the current limiting effect, and is used to compare and optimize the economy of the schemes of configuring 1 group, 2 groups, ……, i groups of fault current limiters. Among them, the economic cost of the fault current limiter can be expressed as the sum of the basic cost and the linear resistance cost, or can be expressed as the linear cost of the resistance value, the exponential function cost of the resistance value, the power function cost of the resistance value, or any combination of the above forms; the current limiting effect of the fault current limiter can be defined as the algebraic sum of the short-circuit current suppression effects of the over-standard nodes, or can be defined as the algebraic sum, weighted algebraic sum or any combination of the above forms of the short-circuit current suppression effects of all nodes in the over-standard nodes or regions;

[0054] The scheme economic index COST i has the following specific expression:

[0055]

[0056] Among them, i is the number of groups of fault current limiters, M0 is the basic cost of the fault current limiter, that is, the cost of the fault current limiter when the resistance value is 0, which only includes inputs such as research and development, design, installation and construction, and does not include current limiting impedance, other additional equipment, etc. ρ is the resistance cost coefficient of the fault current limiter, corresponding to the cost increment per 1 ohm increase in the resistance value of the fault current limiter, and E is the current limiting effect function of the fault current limiter;

[0057] The current limiting effect function E of the fault current limiter is defined as the algebraic sum of the short-circuit current suppression effects of the over-standard nodes. The specific expression of E is as follows:

[0058] E = ∑ 超标节点 (C X - C0)

[0059] Among them, C X is the short-circuit current of the over-standard nodes after configuring the fault current limiter, and C0 is the short-circuit current of the over-standard nodes in the initial state;

[0060] Step 6, repeat steps 2-5 until the over-standard point set M is an empty set, and output the optimal configuration result of the fault current limiter at this time.

[0061] The embodiment of the present invention also provides another computer device, including a processor and a memory configured to store a computer program that can run on the processor; among them, when the processor is configured to run the computer program, it executes the method steps in the foregoing embodiment.

[0062] In practical applications, the above-mentioned processor includes a Field-Programmable Gate Array (FPGA). The processor can be a Central Processing Unit (CPU) or a Digital Signal Processor (DSP). It can be understood that for different devices, the electronic devices used to implement the functions of the above-mentioned processor can also be others, and the embodiments of the present invention do not make specific limitations.

[0063] The above-mentioned memory can be a volatile memory, such as a Random-Access Memory (RAM); or a non-volatile memory, such as a Read-Only Memory (ROM), a flash memory, a Hard Disk Drive (HDD), or a Solid-State Drive (SSD); or a combination of the above types of memories, and provides instructions and data to the processor.

[0064] In an exemplary embodiment, the embodiments of the present invention also provide a computer-readable storage medium for storing a computer program.

[0065] Optionally, the computer-readable storage medium can be applied to any one of the methods in the embodiments of the present invention, and the computer program causes the computer to execute the corresponding processes implemented by the processor in each of the methods of the embodiments of the present invention. For the sake of brevity, it will not be elaborated here.

[0066] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed with each other can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical, or other forms.

[0067] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The solutions in the embodiments of the present invention can be implemented in various computer languages. For example, object-oriented programming languages such as Java and interpreted scripting languages such as JavaScript, etc.

[0068] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0069] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing devices to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0070] These computer program instructions can also be loaded onto a computer or other programmable data processing devices, such that a series of operation steps are executed on the computer or other programmable devices to generate a computer-implemented process, so that the instructions executed on the computer or other programmable devices provide steps for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0071] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0072] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims

1. A method for determining the optimal resistance value of a fault current limiter with excessive regional short-circuit current, characterized in that, Including the following steps: Step 1, scan the short-circuit current of each bus in the regional power grid to determine the set M of regional short-circuit current over-limit points; Step 2: For the most severe bus K in the set M of regional short-circuit current over-standard points, calculate the short-circuit current branch coefficient of this bus, and preliminarily select the fault current limiter to be installed on the branch L with the largest short-circuit current branch coefficient i ; Step 3, gradually increase the impedance value X of the branch where the fault current limiter is located in increments of Δx Li , restart the short-circuit current scan of the regional power grid, and calculate the bus branch coefficient. If the short-circuit current no longer exceeds the standard, output the resistance value X of the fault current limiter FCLi , go to Step 5, otherwise go to Step 4; Step 4, if branch L i is no longer the branch with the largest bus branch coefficient and the number of fault current limiter groups does not exceed the set value, output the resistance value X i of the fault current limiter configured for branch L FCLi , and further configure the fault current limiter on the branch with the largest branch coefficient, i = i + 1, repeat steps 3 - 4 until the short-circuit current of bus K is no longer out of limit; Step 5, calculate the economic index COST of each scheme i , conduct an economic comparison of the schemes, and then update the set M of short-circuit current over-limit points; Step 6, repeat Steps 2 - 5 until the set M of regional short-circuit current over-limit points is an empty set, and output the optimal configuration result of the fault current limiter at this time.

2. The method according to claim 1, wherein: In the said Step 2, the short-circuit current branch coefficient is the ratio of the short-circuit current to the full current flowing through the fault line segment when a short circuit occurs in an adjacent line segment.

3. The method according to claim 1, wherein: In the said step 2, branch L i is the branch with the largest branch coefficient of the short-circuit current corresponding to bus K, where i is the number of fault current limiter groups, and the value is no more than 3 groups.

4. The method according to claim 1, characterized in that: In the said step 3, the branch impedance value X Li has the following specific expression: X Li = X0 + X FCLi Among them, X0 is the impedance value of branch L i at the initial stage, and X FCLi is the impedance value of the fault current limiter.

5. The method according to claim 1, characterized in that: In step 3, the resistance value X of the fault current limiter FCLi has the following specific expression: X FCLi = n * Δx Wherein, n is the number of times of the loop in Step 3 when the number of fault current limiter groups is fixed as i, and Δx is the increment of the resistance value of the fault current limiter after each entry into the loop.

6. The method according to claim 1, characterized in that: In step 5, the specific expression of the scheme economic index COST i is as follows: Wherein, i is the number of fault current limiter groups, M0 is the basic cost of the fault current limiter, ρ is the resistance value cost coefficient of the fault current limiter, corresponding to the cost increment increased for each 1-ohm increase in the resistance value of the fault current limiter, and E is the current-limiting effect function of the fault current limiter.

7. The method according to claim 6, wherein: The current-limiting effect function E of the said fault current limiter is defined as the algebraic sum of the short-circuit current suppression effects of the over-limit nodes, and the specific expression of E is as follows: E = ∑ 超标节点 (C X - C0) Among them, C X is the short-circuit current of the over-standard node after configuring the fault current limiter, and C0 is the short-circuit current of the over-standard node in the initial state.

8. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor; characterized in that: When the processor executes the said computer program, it implements the steps of the method for determining the optimal resistance value of the fault current limiter for regional short-circuit current over-limit as described in any one of Claims 1 to 7.

9. A computer-readable storage medium storing a computer program; characterized in that: When the said computer program is executed by the processor, it implements the steps of the method for determining the optimal resistance value of the fault current limiter for regional short-circuit current over-limit as described in any one of Claims 1 to 7.

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