Gate driver, load driving circuit and gate driving method

Abstract

The invention provides a gate driver, a load driving circuit and a gate driving method. The gate driver has: a power supply voltage terminal; a bootstrap terminal connected to the power supply voltage terminal; a driver having a power input terminal connected to the bootstrap terminal and an output connected to the gate control signal output terminal and configured to generate a gate drive signal at the gate control signal output terminal based on a voltage on the power input terminal; a clamp driver connected to the bootstrap terminal; a clamp transistor connected between the clamp signal input terminal and a reference voltage terminal and having a gate connected to the clamp driver; and an energy harvesting circuit connected between the clamp signal input terminal and the gate of the clamp transistor.

Description

Technical Field

[0001] The present disclosure generally relates to electronic circuits, and more particularly, to gate drivers that reduce feedthrough activation. Background Art

[0002] Power semiconductor devices include semiconductor structures configured to conduct a load current along a load current path between two load terminal structures of the device. The load current path can be controlled by a gate electrode of the power semiconductor device. Summary of the Invention

[0003] This Summary of the Invention is provided to introduce a series of concepts that are further described below in the Detailed Description in a simplified form. This Summary of the Invention is not intended to identify key factors or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0004] According to some embodiments, a gate driver includes: a power supply voltage terminal; a bootstrap terminal connected to the power supply voltage terminal; a driver having a power input terminal connected to the bootstrap terminal and an output connected to a gate control signal output terminal and configured to generate a gate drive signal at the gate control signal output terminal based on a voltage at the power input terminal; a clamp driver connected to the bootstrap terminal; a clamp transistor connected between a clamp signal input terminal and a reference voltage terminal and having a gate connected to the clamp driver; and an energy harvesting circuit connected between the clamp signal input terminal and the gate of the clamp transistor.

[0005] According to some embodiments, a circuit includes: a power supply voltage terminal, a bootstrap terminal connected to the power supply voltage terminal, a bootstrap capacitor connected to the bootstrap terminal, a high-side transistor, a low-side transistor, a high-side gate driver connected to the high-side transistor and having a power input terminal connected to the bootstrap terminal, a low-side gate driver connected to the low-side transistor, a controller configured to generate a startup pulse using the low-side gate driver to charge the bootstrap capacitor, a clamp driver, a clamp transistor connected between the gate of the high-side transistor and the reference voltage terminal and having a gate connected to the clamp driver, and an energy harvesting circuit connected between the gate of the high-side transistor and the gate of the clamp transistor and configured to collect energy from the gate of the high-side transistor in response to the startup pulse and use the collected energy to activate the clamp transistor.

[0006] According to some embodiments, a system includes: means for generating a startup pulse, means for collecting energy injected at a clamp signal input terminal in response to the startup pulse, and means for using the collected energy to activate a clamp transistor connected between the clamp signal input terminal and a reference voltage terminal to provide a low impedance path from the clamp signal input terminal to the reference voltage terminal.

[0007] According to some embodiments, a method includes: generating a startup pulse, collecting energy injected at a clamp signal input terminal in response to the startup pulse, and using the collected energy to activate a clamp transistor connected between the clamp signal input terminal and a reference voltage terminal to provide a low impedance path from the clamp signal input terminal to the reference voltage terminal.

[0008] To achieve the foregoing and related purposes, the following description and drawings set forth certain illustrative aspects and implementations. These illustrative aspects and implementations only indicate some of the various ways in which one or more aspects can be employed. When considered in conjunction with the drawings, other aspects, advantages, and novel features of the present disclosure will become apparent from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a circuit such as for driving a load according to some embodiments.

[0010] Figure 2 is a schematic diagram of a circuit such as for protection according to some embodiments.

[0011] Figure 3 is a signal diagram showing the operation of a protection circuit according to some embodiments.

[0012] Figure 4 shows a method of driving a gate of a transistor such as according to some embodiments. DETAILED DESCRIPTION

[0013] The claimed subject matter is now described with reference to the drawings, in which like reference numerals are always used to refer to like elements. In the following description, numerous specific details are set forth for purposes of illustration in order to provide a thorough understanding of the claimed subject matter. However, it is apparent that the claimed subject matter may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the claimed subject matter.

[0014] In the following description, equivalent or similar elements or elements having equivalent or similar functions are denoted by equivalent or similar reference numerals. Since elements that are identical or functionally equivalent in the drawings are given the same reference numerals, repeated descriptions of elements provided with the same reference numerals may be omitted. Accordingly, the descriptions provided for elements having the same or similar reference numerals may be interchanged with one another.

[0015] In this regard, directional terms such as "top", "bottom", "below", "above", "front", "rear", "back", "front portion", "tail portion", etc. may be used with reference to the directions of the described drawings. Since the components of the embodiments may be positioned in a plurality of different orientations, the directional terms are for illustrative purposes only and are in no way limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. Accordingly, the following detailed description should not be construed in a limiting sense.

[0016] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in the same manner (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", etc.).

[0017] In the embodiments described herein or shown in the drawings, any direct electrical connection or coupling - i.e., any connection or coupling without additional intervening elements - may also be achieved by an indirect connection or coupling - i.e., a connection or coupling having one or more additional intervening elements - and vice versa, so long as the general purpose of the connection or coupling is substantially maintained, such as transmitting a certain signal or transmitting a certain piece of information. Features from different embodiments may be combined to form additional embodiments. For example, unless stated to the contrary, variations or modifications described with respect to one of the embodiments may also apply to other embodiments.

[0018] The term "substantially" may be used herein to interpret small manufacturing tolerances (e.g., within 5%) that are considered acceptable in the industry without departing from the aspects of the embodiments described herein.

[0019] A gate driver is used to control a power semiconductor device so that a load current can be controlled. Example applications include motor control, inverters, power supplies, voltage converters, or some other applications. Low-threshold voltage power semiconductor devices (such as gallium nitride (GaN) devices) are prone to short through activation, where the voltage on the source of the power semiconductor device causes the power semiconductor device to activate, and this effect is called the Miller effect. A Miller clamping circuit can be provided to clamp the gate voltage of the power semiconductor device to a reference voltage corresponding to an off state (such as ground) to prevent parasitic activation. To enable the Miller clamping circuit, a supply voltage is required to enable the clamping transistor to clamp the gate voltage. However, during the startup cycle of the gate driver, a bootstrap technique can be used, where the voltage V CC supplied to the gate driver integrated circuit is used to charge a bootstrap capacitor to generate a supply voltage. During the startup cycle, the supply voltage is not sufficient to drive the Miller clamping circuit. For example, the power semiconductor device can include a high-side switch and a low-side switch. A drive signal can be used to activate the low-side switch to charge the bootstrap capacitor. Since the Miller clamping circuit cannot be activated, the activation of the low-side switch can generate a voltage on the gate of the high-side switch that is sufficient to cause parasitic activation of the high-side switch due to the Miller effect.

[0020] Referring Figure 1 , a schematic diagram of a load driving circuit 100 according to some embodiments is provided. The load driving circuit 100 includes a gate driver 102 and a load driver 104. In some embodiments, the gate driver 102 includes a high-side driver 106H, a protection circuit 110, and a bootstrap circuit 112. The high-side driver 106H has an output connected to a gate control signal output terminal 108 for providing a gate drive signal (HO). The bootstrap circuit 112 is configured to generate a bootstrap voltage (V CC ) at a bootstrap output terminal 114 according to a supply voltage (V B ) provided at a supply voltage terminal 116S. In some embodiments, the bootstrap circuit 112 includes a resistor 118 in series with a bootstrap diode 120 connected between the supply voltage terminal 116S and the bootstrap output terminal 114. The bootstrap output terminal 114 is connected to a power input terminal 106S of the high-side driver 106H. The high-side driver 106H generates a gate drive signal at the gate control signal output terminal 108 based on the voltage on the power input terminal 106S. A reference terminal 106R of the high-side driver 106H is connected to a reference voltage terminal 116R. In some embodiments, the voltage at the reference voltage terminal 116R is grounded. The protection circuit 110 is connected between the bootstrap output terminal 114 and a clamp signal input terminal 122 to protect the components of the load driver 104.

[0021] In some embodiments, the load driver 104 includes a high-side transistor 124H and a low-side transistor 124L connected at node 124N. The drain of the high-side transistor 124H is connected to the bus voltage (V BUS ), and the source of the low-side transistor 124L is connected to ground through resistor 124R. The high-side transistor 124H and the low-side transistor 124L control the power supplied to a load (such as a motor, a voltage bus, or some other load) connected to the load driver 104. The clamp signal input terminal 122 is connected to the gate of the high-side transistor 124H. The bootstrap capacitor 126 is connected between the bootstrap output terminal 114 and the reference voltage terminal 116R for storing the bootstrap voltage used to power the high-side driver 106H. Optional filter elements (such as resistor 128 and capacitor 130) may be provided between the gate control signal output terminal 108 and the gate of the high-side transistor 124H or between the gate and the drain of the high-side transistor 124H to affect the switching response of the high-side transistor 124H. Optional filter elements such as resistor 132 and capacitor 134 may be provided for the low-side transistor 124L. For ease of illustration, the drive circuitry for the low-side transistor 124L is represented by the low-side driver 106L. The low-side driver 106L may be provided in the gate driver 102 or a separate gate driver may be provided to drive the low-side transistor 124L. Other structures and / or configurations of the load driver 104 are within the scope of the present disclosure.

[0022] During the startup period, the low-side driver 106L provides a series of startup pulses to the low-side transistor 124L, thereby creating a path for charging the bootstrap capacitor 126 from the power supply voltage terminal 116S. Before the bootstrap capacitor 126 is fully charged, there is not enough voltage to activate the protection circuit 110 to shunt the Miller current in the high-side transistor 124H.

[0023] Figure 2FIG. is a diagram of a protection circuit 110 according to some embodiments. In some embodiments, the protection circuit 110 includes a clamping circuit 200, an energy harvesting circuit 202, an electrostatic discharge (ESD) circuit 204, and a startup circuit 206. The clamping circuit 200 shunts the Miller current injected at the clamping signal input terminal 122 to the reference voltage terminal 116R. During a startup period, the energy harvesting circuit 202 harvests the Miller current injected at the clamping signal input terminal 122 to enable the clamping circuit 200 until the bootstrap capacitor 126 is charged to enable normal operation of the clamping circuit 200. The ESD circuit 204 prevents an electrostatic voltage present at the clamping signal input terminal 122. The startup circuit 206 provides an additional DC coupling path from the bootstrap output terminal 114 to the clamping circuit 200 to allow the clamping circuit 200 to operate fully at the minimum power supply of a given technology node.

[0024] The clamping circuit 200 includes a clamping transistor 208 (e.g., n-type) and a clamping driver 210 connected between the clamping signal input terminal 122 and the reference voltage terminal 116R. In some embodiments, the clamping driver 210 includes a pull-up transistor 212 (e.g., p-type) connected to the bootstrap output terminal 114, a pull-down transistor 214 (e.g., n-type) connected to the reference voltage terminal 116R, and a decoupling diode 216 connected between the pull-up transistor 212 and the pull-down transistor 214. The decoupling diode 216 is connected to the gate of the clamping transistor 208. During normal operation, when there is a bootstrap voltage V B , the pull-up transistor 212 is activated by a voltage derived from V B to activate the clamping transistor 208. Other structures and / or configurations of the clamping circuit 200 are within the scope of the present disclosure.

[0025] The energy harvesting circuit 202 is connected between the clamping signal input terminal 122 and the gate of the clamping transistor 208. In some embodiments, the energy harvesting circuit 202 includes a transistor 218 (e.g., p-type), a resistor 220 connected between the drain and the gate of the transistor 218, a capacitor 222 connected between the gate and the source of the transistor 218, and a decoupling diode 224 connected to the gate of the transistor 218. The energy harvesting circuit 202 is an active AC clamping circuit that converts the AC Miller current generated at the clamping signal input terminal 122 by a startup pulse for charging the bootstrap capacitor 126 to activate the clamping transistor 208. The current at the clamping signal input terminal 122 charges the capacitor 222 to generate a DC signal for charging the gate of the clamping transistor 208. Other structures and / or configurations of the energy harvesting circuit 202 are within the scope of the present disclosure.

[0026] The ESD circuit 204 is connected between the clamp signal input terminal 122 and the reference voltage terminal 116R. In some embodiments, the ESD circuit 204 includes one or more Zener diodes 204Z. Other structures and / or configurations of the ESD circuit 204 are within the scope of the present disclosure.

[0027] The startup circuit 206 is connected between the bootstrap output terminal 114 and the gate of the clamp transistor 208. In some embodiments, the startup circuit 206 includes a resistor 226 connected to the bootstrap output terminal 114, a transistor 228 (e.g., n-type) connected between the resistor 226 and the reference voltage terminal 116R and having a gate connected to the under-voltage lockout (UVLO) terminal 230, a transistor 232 (p-type) having a drain connected to the bootstrap output terminal 114 and a gate connected to the resistor 226 and the transistor 228, and a decoupling diode 234 connected between the source of the transistor 232 and the gate of the clamp transistor 208. Other structures and / or configurations of the startup circuit 206 are within the scope of the present disclosure.

[0028] During the startup period, the low-side driver 106L provides a series of startup pulses, such as a pulse-width modulation (PWM) signal, to the low-side transistor 124L, thereby creating a path for charging the bootstrap capacitor 126 from the power supply voltage terminal 116S. Before the bootstrap capacitor 126 is fully charged, there is not enough voltage to activate the clamp circuit 200 to shunt the Miller current in the high-side transistor 124H using the clamp driver 210. The Miller current (i.e., drain-to-gate current) exists on the clamp signal input terminal 122. The energy harvesting circuit 202 converts the AC Miller current into a DC voltage and stores (i.e., aggregates) the DC voltage on the gate of the clamp transistor 208. The stored voltage activates the clamp transistor 208 and shunts any subsequent Miller current. The decoupling diodes 216, 224, 234 prevent the voltage stored on the gate of the clamp transistor 208 from decaying.

[0029] Figure 3 is a signal diagram 300 showing the operation of the protection circuit 110 according to some embodiments. Figure 3 includes a low-side transistor drive signal 302 (V LS ), a drain-to-gate current signal 304 (I G ) representing the Miller current in the high-side transistor 124H, a clamp current signal 306 (I 钳位 ) representing the current on the clamp signal input terminal 122, and a clamp voltage signal 308 (V 钳位)。The startup pulse 302P in the low-side transistor drive signal 302 provided by the low-side driver 106L activates the low-side transistor 124L to charge the bootstrap capacitor 126. Due to the Miller effect, the gate-to-source voltage across the high-side transistor 124H from the first startup pulse 302P in the low-side transistor drive signal 302 induces an AC gate current pulse 304P in the high-side transistor 124H, as shown in the gate current signal 304. A corresponding current pulse 306P is seen in the clamp current signal 306 at the clamp signal input terminal 122. The energy harvesting circuit 202 converts the current pulse 306P into a DC voltage 308D on the gate of the clamp transistor 208 to enable the clamp transistor 208 and shunt the Miller current from subsequent startup pulses 302P in the low-side transistor drive signal 302. In some embodiments, the protection circuit 110 activates the clamp transistor 208 after a startup pulse 302P and the corresponding Miller current pulse 304P in the low-side transistor drive signal 302.

[0030] Figure 4 A method 400 for driving a transistor gate is shown in accordance with some embodiments. At 402, a startup pulse is generated. In some embodiments, the startup pulse includes the pulse 302P provided by the low-side driver 106L in the low-side transistor drive signal 302 to enable the low-side transistor 124L to charge the bootstrap capacitor 126. At 404, energy injected at the clamp signal input terminal 122 in response to the startup pulse is collected, for example, by the energy harvesting circuit 202. At 406, the collected energy is used to activate a clamp transistor 208 connected between the clamp signal input terminal 122 and the reference voltage terminal 116R to provide a low impedance path from the clamp signal input terminal 122 to the reference voltage terminal 116R.

[0031] The protection circuit 110 addresses the startup effect on low-threshold voltage power transistor devices such as GaN devices. Here, the low threshold voltage is, for example, a threshold voltage of about 2.5V, about 2V, about 1.5V, or about 1V or lower. The threshold voltage of a power transistor device can be a function of temperature and decreases as the temperature increases, and the given example values can relate to one of the following: the typical operating temperature of the device in a particular application, the standard temperature for testing the device, the maximum rated operating temperature of the device, or the typical ambient temperature. Here, the relevant temperature range can be from about 0°C to about 200°C. Parasitic activation of the low-threshold voltage power transistor device can be suppressed by activating a clamp circuit system using energy collected from the Miller current induced during the startup period. Shoot-through in the half-bridge defined by the transistors 124H, 124L is also suppressed.

[0032] According to some embodiments, when the power transistor threshold voltage has a value lower than or on the order of the gate driver logic minimum operating voltage (e.g., the power transistor threshold voltage is within 50% of the gate driver logic minimum operating voltage) and / or when the power transistor threshold voltage has a value lower than or on the order of the activation voltage of the activation clamping transistor (e.g., the power transistor threshold voltage is within 50% of the activation voltage of the clamping transistor), the protection circuit can suppress the parasitic activation of the power transistor device. For example, the gate driver logic minimum operating voltage can be about 1.5V, and the power transistor threshold voltage can be lower than 1.5V, or can be in the range up to about 2.3V. As another example, the activation voltage of the clamping transistor can be about 1.2V, and the power transistor threshold voltage can be lower than 1.2V, or in the range up to about 2V. These voltages are only example values and should not be construed as restrictive.

[0033] According to some embodiments, a gate driver includes: a power supply voltage terminal; a bootstrap terminal connected to the power supply voltage terminal; a driver having a power input terminal connected to the bootstrap terminal and an output connected to a gate control signal output terminal and configured to generate a gate drive signal at the gate control signal output terminal based on a voltage on the power input terminal; a clamping driver connected to the bootstrap terminal; a clamping transistor connected between a clamping signal input terminal and a reference voltage terminal and having a gate connected to the clamping driver; and an energy harvesting circuit connected between the clamping signal input terminal and the gate of the clamping transistor.

[0034] According to some embodiments, the energy harvesting circuit includes an active AC clamper connected to the clamping signal input terminal and a decoupling diode connected between the active AC clamper and the gate of the clamping transistor.

[0035] According to some embodiments, the active AC clamper includes a second clamping transistor connected between the clamping signal input terminal and the decoupling diode, a resistor connected between the clamping signal input terminal and the gate of the second clamping transistor, and a capacitor connected between the gate of the second clamping transistor and the decoupling diode.

[0036] According to some embodiments, the clamping driver includes a decoupling diode, a pull-up transistor connected between the bootstrap terminal and the decoupling diode, and a pull-down transistor connected between the decoupling diode and the reference voltage terminal.

[0037] According to some embodiments, the gate driver includes a startup circuit that includes a decoupling diode connected to the gate of a clamping transistor, a startup transistor connected between a bootstrap terminal and the decoupling diode, a resistor connected between the bootstrap terminal and the gate of the startup transistor, and a latching transistor connected between the gate of the startup transistor and a reference voltage terminal.

[0038] According to some embodiments, the gate driver includes an electrostatic discharge protection device connected between a clamp signal input terminal and a reference voltage terminal.

[0039] According to some embodiments, the electrostatic discharge protection device includes a Zener diode.

[0040] According to some embodiments, a circuit includes: a power supply voltage terminal, a bootstrap terminal connected to the power supply voltage terminal, a bootstrap capacitor connected to the bootstrap terminal, a high-side transistor, a low-side transistor, a high-side gate driver connected to the high-side transistor and having a power input terminal connected to the bootstrap terminal, a low-side gate driver connected to the low-side transistor, a controller configured to use the low-side gate driver to generate a startup pulse to charge the bootstrap capacitor, a clamp driver, a clamping transistor connected between the gate of the high-side transistor and a reference voltage terminal and having a gate connected to the clamp driver, and an energy harvesting circuit connected between the gate of the high-side transistor and the gate of the clamping transistor and configured to harvest energy from the gate of the high-side transistor in response to the startup pulse and use the harvested energy to activate the clamping transistor.

[0041] According to some embodiments, the energy harvesting circuit includes an active AC clamp connected to the gate of the high-side transistor and a decoupling diode connected between the active AC clamp and the gate of the clamping transistor.

[0042] According to some embodiments, the active AC clamp includes a second clamping transistor connected between the gate of the high-side transistor and the decoupling diode, a resistor connected between the gate of the high-side transistor and the gate of the second clamping transistor, and a capacitor connected between the gate of the second clamping transistor and the decoupling diode.

[0043] According to some embodiments, the clamp driver includes a decoupling diode, a pull-up transistor connected between the bootstrap terminal and the decoupling diode, and a pull-down transistor connected between the decoupling diode and the reference voltage terminal.

[0044] According to some embodiments, the circuit includes a startup circuit that includes a decoupling diode connected to the gate of a clamping transistor, a startup transistor connected between a bootstrap terminal and the decoupling diode, a resistor connected between the bootstrap terminal and the gate of the startup transistor, and a latching transistor connected between the gate of the startup transistor and a reference voltage terminal.

[0045] According to some embodiments, the circuit includes an electrostatic discharge protection device connected between the gate of a high-side transistor and a reference voltage terminal.

[0046] According to some embodiments, the electrostatic discharge protection device includes a Zener diode.

[0047] According to some embodiments, a method includes: generating a startup pulse, collecting energy injected at a clamping signal input terminal in response to the startup pulse, and using the collected energy to activate a clamping transistor connected between the clamping signal input terminal and a reference voltage terminal to provide a low-impedance path from the clamping signal input terminal to the reference voltage terminal.

[0048] According to some embodiments, activating the clamping transistor includes connecting an active AC clamp to the clamping signal input terminal, connecting a decoupling diode between the active AC clamp and the gate of the clamping transistor, and using the decoupling diode to suppress discharge of the collected energy at the gate of the clamping transistor.

[0049] According to some embodiments, connecting the active AC clamp to the clamping signal input terminal includes connecting a second clamping transistor between the clamping signal input terminal and the decoupling diode, connecting a resistor between the clamping signal input terminal and the gate of the second clamping transistor, and connecting a capacitor between the gate of the second clamping transistor and the decoupling diode, and collecting the energy injected at the clamping signal input terminal includes storing the collected energy at the gate of the clamping transistor by charging the capacitor.

[0050] According to some embodiments, the method includes connecting a clamp driver to the gate of the clamping transistor, the clamp driver including a second decoupling diode, a pull-up transistor connected between a bootstrap terminal connected to a power supply voltage terminal and the second decoupling diode for activating the clamping transistor, and a pull-down transistor connected between the second decoupling diode and a reference voltage terminal for deactivating the clamping transistor, and using the second decoupling diode to suppress discharge of the collected energy at the gate of the clamping transistor.

[0051] According to some embodiments, the method includes connecting a startup circuit to a bootstrap voltage generated by a startup pulse by: connecting a decoupling diode to the gate of a clamping transistor, connecting a startup transistor between a bootstrap terminal and the decoupling diode, connecting a resistor between the bootstrap terminal and the gate of the startup transistor, and connecting a latching transistor between the gate of the startup transistor and a reference voltage terminal, wherein the method includes using the decoupling diode to suppress discharge of the collected energy on the gate of the clamping transistor.

[0052] According to some embodiments, the method includes connecting an electrostatic discharge protection device between a clamping signal input terminal and a reference voltage terminal.

[0053] Although the subject matter has been described in language specific to structural features or method acts, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the above specific features and acts are disclosed as example forms of implementing at least some of the claims.

[0054] Various operations of embodiments are provided herein. The order of description of some or all of the operations should not be construed as implying that these operations must be order-dependent. Benefiting from this description, alternative orderings can be understood. In addition, it should be understood that not all operations must be present in every embodiment provided herein. In addition, it should be understood that in some embodiments, not all operations are required.

[0055] Furthermore, terms such as "exemplary" are used herein to mean serving as an example, instance, illustration, etc., and are not necessarily advantageous. Instead, the use of terms such as "example" is intended to present a possible aspect and / or implementation that may be related to the technology presented herein. Such examples are not required or intended to be limiting for such technology. Various embodiments of such technology may include such examples alone or in combination with other features, and / or may vary and / or omit the examples shown.

[0056] As used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or". Additionally, the articles "a" and "an" as used in this application and the appended claims generally should be construed to mean "one or more" unless otherwise specified or clear from the context as being singular. Further, at least one of A and B, etc. generally means A or B or both A and B. Additionally, to the extent that the terms "includes", "having", "has", "with" or variations thereof are used, such terms are intended to be inclusive in a manner similar to the term "comprising". Additionally, unless otherwise stated, "first", "second", etc. are not intended to imply a temporal, spatial, ordering, etc. Instead, these terms are merely used as identifiers, names, etc. for features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B or two different or two identical elements or the same element.

[0057] In addition, although the present disclosure has been shown and described with respect to one or more implementations, equivalent changes and modifications will occur to others of ordinary skill in the art based on a reading and understanding of this specification and the drawings. The present disclosure includes all such modifications and changes and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-described components (e.g., elements, resources, etc.), unless otherwise indicated, the terms used to describe such components are intended to correspond to any component that performs the specified function of the described component (e.g., is functionally equivalent), even if it is not structurally equivalent to the disclosed structure. Additionally, although a particular feature of the present disclosure may be disclosed with respect to only one of several implementations, such a feature may be combined with one or more other features of other implementations as may be desired and advantageous for any given or particular application. Further, to the extent that the terms "includes", "having", "has", "with" or variations thereof are used in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term "comprising".

Claims

1. A gate driver, comprising: Supply voltage terminal; a bootstrap terminal connected to the supply voltage terminal; a driver having a power input terminal connected to the bootstrap terminal and an output connected to a gate control signal output terminal and configured to generate a gate drive signal at the gate control signal output terminal based on a voltage on the power input terminal; a clamp driver connected to the bootstrap terminal; a clamp transistor connected between a clamp signal input terminal and a reference voltage terminal and having a gate connected to the clamp driver; as well as An energy harvesting circuit is connected between the clamp signal input terminal and the gate of the clamp transistor.

2. The gate driver according to claim 1, wherein: The energy harvesting circuit comprises: an active AC clamp connected to the clamp signal input terminal; and A decoupling diode is connected between the active AC clamp and a gate of the clamp transistor.

3. The gate driver according to claim 2, wherein: The active AC clamp comprises: a second clamp transistor connected between the clamp signal input terminal and the decoupling diode; a resistor connected between the clamp signal input terminal and a gate of the second clamp transistor; and A capacitor is connected between the gate of the second clamp transistor and the decoupling diode.

4. The gate driver according to claim 1, wherein: The clamp driver comprises: Decoupling diodes; a pull-up transistor connected between the bootstrap terminal and the decoupling diode; and A pull-down transistor is connected between the decoupling diode and the reference voltage terminal.

5. The gate driver according to claim 1, comprising: Starting circuit, including: a decoupling diode connected to the gate of the clamp transistor; a startup transistor connected between the bootstrap terminal and the decoupling diode; a resistor connected between the bootstrap terminal and the gate of the start transistor; and A blocking transistor is connected between the gate of the enable transistor and the reference voltage terminal.

6. The gate driver according to claim 1, comprising: An electrostatic discharge protection device is connected between the clamp signal input terminal and the reference voltage terminal.

7. The gate driver according to claim 6, wherein: The electrostatic discharge protection device includes a Zener diode.

8. A load driving circuit, comprising: Supply voltage terminal; a bootstrap terminal connected to the supply voltage terminal; a bootstrap capacitor connected to the bootstrap terminal; High-side transistor; Low-side transistor; a high-side gate driver connected to the high-side transistor and having a power input terminal connected to the bootstrap terminal; a low-side gate driver connected to the low-side transistor; a controller configured to generate a start pulse using the low-side gate driver to charge the bootstrap capacitor; Clamp driver; a clamp transistor connected between the gate of the high-side transistor and a reference voltage terminal and having a gate connected to the clamp driver; as well as An energy harvesting circuit is connected between the gate of the high-side transistor and the gate of the clamp transistor and is configured to harvest energy from the gate of the high-side transistor in response to the start pulse and activate the clamp transistor using the harvested energy.

9. The load driving circuit according to claim 8, wherein: The energy harvesting circuit comprises: an active AC clamp connected to the gate of the high-side transistor; and A decoupling diode is connected between the active AC clamp and a gate of the clamp transistor.

10. The load driving circuit according to claim 9, wherein: The active AC clamp comprises: a second clamp transistor connected between the gate of the high-side transistor and the decoupling diode; a resistor connected between the gate of the high-side transistor and the gate of the second clamp transistor; and A capacitor is connected between the gate of the second clamp transistor and the decoupling diode.

11. The load driving circuit according to claim 8, wherein: The clamp driver comprises: Decoupling diodes; a pull-up transistor connected between the bootstrap terminal and the decoupling diode; and A pull-down transistor is connected between the decoupling diode and the reference voltage terminal.

12. The load driving circuit according to claim 8, comprising: Starting circuit, including: a decoupling diode connected to the gate of the clamp transistor; a startup transistor connected between the bootstrap terminal and the decoupling diode; a resistor connected between the bootstrap terminal and the gate of the start transistor; and A blocking transistor is connected between the gate of the enable transistor and the reference voltage terminal.

13. The load driving circuit according to claim 8, comprising: An electrostatic discharge protection device is connected between the gate of the high-side transistor and the reference voltage terminal.

14. The load driving circuit according to claim 13, wherein: The electrostatic discharge protection device includes a Zener diode.

15. A gate driving method, comprising: generating a start pulse; collecting energy injected at a clamp signal input terminal in response to the start pulse; as well as A clamp transistor connected between the clamp signal input terminal and a reference voltage terminal is activated using the harvested energy to provide a low impedance path from the clamp signal input terminal to the reference voltage terminal.

16. The gate driving method according to claim 15, wherein: Activating the clamp transistor includes: connecting an active AC clamp to the clamp signal input terminal; connecting a decoupling diode between the active AC clamp and the gate of the clamp transistor; and The decoupling diode is used to suppress discharge of the harvested energy on the gate of the clamp transistor.

17. The gate driving method according to claim 16, wherein: Connecting the active AC clamp to the clamp signal input terminal comprises: connecting a second clamp transistor between the clamp signal input terminal and the decoupling diode; connecting a resistor between the clamp signal input terminal and the gate of the second clamp transistor; and connecting a capacitor between the gate of the second clamp transistor and the decoupling diode; and The energy injected at the clamp signal input terminal is collected by: The harvested energy is stored on the gate of the clamp transistor by charging the capacitor.

18. The gate driving method according to claim 16, comprising: A clamp driver is connected to the gate of the clamp transistor, the clamp driver comprising: A second decoupling diode; a pull-up transistor connected between a bootstrap terminal connected to a power supply voltage terminal and the second decoupling diode for activating the clamp transistor; and a pull-down transistor connected between the second decoupling diode and the reference voltage terminal for deactivating the clamp transistor; and The second decoupling diode is used to suppress discharge of the harvested energy on the gate of the clamp transistor.

19. The gate driving method according to claim 15, comprising: Connect the startup circuit to the bootstrap voltage generated by the startup pulse by following these steps: connecting a decoupling diode to the gate of the clamping transistor; connecting a start-up transistor between the bootstrap terminal and the decoupling diode; connecting a resistor between the bootstrap terminal and the gate of the start transistor; as well as A blocking transistor is connected between the gate of the enabling transistor and the reference voltage terminal, wherein: The gate driving method further comprises: The decoupling diode is used to suppress discharge of the harvested energy on the gate of the clamp transistor.

20. The gate driving method according to claim 15, comprising: An electrostatic discharge protection device is connected between the clamp signal input terminal and the reference voltage terminal.

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