Converter PCB parasitic inductance parameter optimization method based on multi-target weighting

Abstract

The invention discloses a converter PCB parasitic inductance parameter optimization method based on multi-target weighting, which considers the influence of parasitic inductance parameters of a grid electrode, a drain electrode and a source electrode on switching characteristics, and comprehensively considers performance indexes of a grid-source voltage peak, a turn-off voltage peak and a turn-on current peak. Weighted calculation and standardization processing are carried out on different indexes, and an objective function capable of reflecting the overall switching performance of the SiC MOSFET device is established. And performing simulation solution to obtain a relation graph between the target function and parasitic inductance parameters, and finally combining simulation data and the 3D graph to obtain a parasitic inductance optimization interval which enables the overall performance and loss of the device to be optimal. According to the method, parasitic inductance parameters of a SiC MOSFET driving loop and a power loop are comprehensively considered, multiple performance indexes of the device serve as optimization targets, the multiple performance indexes are comprehensively considered to effectively suppress switching oscillation and overshoot of the device, the high-speed switching and low-loss advantages of the device are maximized, and PCB layout optimization design of the converter is guided.

Description

Technical Field

[0001] The present invention belongs to the fields of power electronics technology and electrical engineering technology, and particularly relates to a method for optimizing the parasitic inductance parameters of a converter PCB based on multi-objective weighting. Background Art

[0002] As a typical wide-bandgap semiconductor device, silicon carbide (SiC) devices have the advantages of lower on-resistance, smaller inter-pole capacitance, higher voltage rating, higher thermal conductivity, and high temperature resistance. They are gradually replacing traditional silicon (Si) based power semiconductor devices and are widely used in high-voltage, high-frequency, high-power aerospace DC converter systems. However, in high-frequency and high-speed application scenarios, there are large di / dt and dv / dt in the circuit, making SiC MOSFETs more sensitive to parasitic inductance parameters, resulting in serious voltage / current oscillations and overshoot problems during the switching transient. There will be gate-source voltage spikes and turn-on current spikes during the turn-on stage, and turn-off voltage spikes during the turn-off stage, threatening the safe and reliable operation of the device.

[0003] Since the switching oscillation and overshoot are generated by the resonance of the parasitic inductance and capacitance in the loop, the oscillation phenomenon can be fundamentally eliminated or weakened by optimizing the parasitic inductance parameters of the drive loop or the power loop, thereby reducing the voltage / current overshoot during the high-speed switching process. However, the current research on the optimization method of the parasitic inductance parameters of the PCB for SiC MOSFETs mainly focuses on a single drive loop or power loop, and the consideration of the device performance indicators is not comprehensive enough, making it difficult to effectively guide the PCB layout optimization of the converter. The parasitic inductance parameters of the drive loop and the power loop have significant effects on the performance indicators of SiC MOSFETs. The effects of different parasitic inductances on the same performance indicator are different, and the change trends are also different. Multiple performance indicators should be taken into account and the parasitic inductance in the loop should be comprehensively optimized to guide the PCB engineering design. This is of great significance for fundamentally eliminating or suppressing the switching oscillation and overshoot of the device and improving the reliability of power devices and converters. Summary of the Invention

[0004] The purpose of the present invention is to address the above-mentioned deficiencies of the prior art. The present invention provides a method for optimizing the parasitic inductance parameters of a converter PCB based on multi-objective weighting, comprehensively considering the parasitic inductance parameters of the SiC MOSFET drive and power loops, and taking into account multiple performance indicators of the SiC MOSFET to comprehensively optimize the parasitic inductance in the loop, giving full play to the high-frequency, high-speed, and low-loss advantages of SiC MOSFET devices.

[0005] The present invention adopts the following technical solutions to achieve the above object:

[0006] A method for optimizing the parasitic inductance parameters of a converter PCB based on multi-objective weighting, comprising the following steps:

[0007] Step S1: Determine the performance indicators of the evaluated device;

[0008] Step S2: Set the range of the performance indicators;

[0009] Step S3: Define and calculate the weighting coefficients of different performance indicators;

[0010] Step S4: Establish and solve the objective function, and finally determine the range of parasitic inductance values with the optimal overall performance and loss of the SiC MOSFET according to the relationship map between the objective function value and the parasitic inductance parameters.

[0011] Further, in the step S1, establish a double-pulse test equivalent circuit model of the SiC MOSFET considering parasitic inductance parameters, analyze the influence law of parasitic inductance parameters on the device switching oscillation and overshoot through switching mode analysis and simulation, and determine the indicators for evaluating the overall switching performance of the device.

[0012] Further, in the step S1, based on the switching mode analysis of the SiC MOSFET, select the gate-source voltage spike, turn-off voltage spike, and turn-on current spike as the indicators for evaluating the reliability of the device.

[0013] Further, in the step S2, according to the requirements under different application scenarios, operating conditions, and converter conditions, set the range of the performance indicators, and the range of the performance indicators is between the minimum value and the target value; the minimum value is the minimum value that this indicator of the SiC MOSFET can reach under the circuit parameter boundary conditions or ideal conditions; the target value is the indicator value expected to be achieved during engineering design.

[0014] Further, in the step S3, the weighting coefficient is defined as the change rate of the three performance indicators of the gate-source voltage spike, turn-off voltage spike, and turn-on current spike with respect to the parasitic inductance parameters; the parasitic inductance parameters include gate parasitic inductance parameters, drain parasitic inductance parameters, and source parasitic inductance parameters.

[0015] Further, in the step S3, the weighting coefficients of different performance indicators are obtained by theoretical calculation and experimental data fitting; through the double-pulse experimental platform, taking the parasitic inductance parameters of the drive and power circuits as variables, obtain the performance indicator values of the SiC MOSFET under different parasitic inductance parameters through experimental tests, use the method of linear fitting to obtain the trend lines of different performance indicators changing with the parasitic inductance parameters, obtain the corresponding change rates, and further calculate the weighting coefficient values of different indicators.

[0016] Further, in step S4, the objective function is constructed by the sum of the products of the standardized values of various performance indicators and the corresponding weighting coefficients, which can reflect the optimization degree of the performance indicators of the gate-source voltage spike, turn-off voltage spike, and turn-on current spike of the SiC MOSFET device. The smaller the objective function value, the better the overall performance optimization effect of the SiC MOSFET; the standardization of the performance indicators refers to converting indicators with different units and orders of magnitude into dimensionless values.

[0017] Further, in step S4, the solution of the objective function includes the following steps:

[0018] Step S4-1: Determine the value boundaries of different parasitic inductances according to the typical values of the parasitic inductances of the metal pins of the SiC MOSFET device and engineering design experience.

[0019] Step S4-2: Establish a double-pulse simulation model of the SiC MOSFET, and use the exhaustive method to perform simulation calculations on different combinations of parasitic inductances within the constraint range to obtain the gate-source voltage spike, turn-off voltage spike, turn-on current spike, and switching loss values of the device during the switching transient.

[0020] Step S4-3: Standardize the performance indicator values obtained by simulation, calculate the corresponding objective function values, and finally obtain a 3D map between the objective function and the parasitic inductance parameters.

[0021] Further, in step S4, the coordinate axes of the 3D map represent the gate parasitic inductance, drain parasitic inductance, and source parasitic inductance, and the color in the fourth dimension represents the magnitude of the objective function value. The darker the color, the larger the objective function value, that is, the worse the overall performance of the device; the minimum value of the objective function corresponds to the range of values of the parasitic inductance parameters with the optimal overall switching performance of the device.

[0022] Further, in step S4, within the range of values of the parasitic inductance parameters with the optimal overall switching performance, combined with the simulation data and images, based on the principle of optimal loss, obtain the optimized range of the parasitic inductance parameters with the optimal loss.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1. A method for optimizing the parasitic inductance parameters of a converter PCB based on multi-objective weighting proposed by the present invention comprehensively considers the parasitic inductance parameters of the SiC MOSFET drive and the power loop, takes multiple performance indicators of the device as the optimization objectives, and can maximize the reliability advantages of the device.

[0025] 2. A method for optimizing the parasitic inductance parameters of a converter PCB based on multi-objective weighting proposed by the present invention does not increase the switching loss of the device while ensuring the high-speed switching advantage of the device, and can effectively suppress switching oscillation and overshoot.

[0026] 3. The method for optimizing the parasitic inductance parameters of the converter PCB based on multi-objective weighting proposed by the present invention gives a clear parasitic inductance parameter optimization process, and can obtain the value range of the parasitic inductance that makes the overall performance of the SiC MOSFET optimal and the loss lowest, which has guiding significance for the PCB layout optimization of the converter. Description of the Drawings

[0027] Figure 1 is a schematic flow chart of a method for optimizing the parasitic inductance parameters of the converter PCB based on multi-objective weighting provided by an embodiment of the present invention.

[0028] Figure 2 is a schematic diagram of a 3D map between the objective function and the parasitic inductance parameters in an embodiment of the present invention.

[0029] Figure 3 is a distribution diagram of the switching performance indexes of the SiC MOSFET under different combinations of parasitic inductance parameters in an embodiment of the present invention. Detailed Embodiments

[0030] The following further describes the specific embodiments of the present invention in conjunction with the drawings. The technical solutions in the embodiments of the present invention are clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] Combined with Figure 1 , the method for optimizing the parasitic inductance parameters of the converter PCB based on multi-objective weighting provided by an embodiment of the present invention includes the following steps:

[0032] Step S1: Determine the performance indexes of the evaluated device;

[0033] Step S2: Set the range of the performance indexes;

[0034] Step S3: Define and calculate the weighting coefficients of different performance indexes;

[0035] Step S4: Establish and solve the objective function, and finally determine the value range of the parasitic inductance with the optimal overall performance and loss of the SiC MOSFET according to the relationship map between the objective function value and the parasitic inductance parameters.

[0036] Further, in the step S1, a double-pulse test equivalent circuit model of the SiC MOSFET considering the parasitic inductance parameters is established, and the influence law of the parasitic inductance parameters on the device switching oscillation and overshoot is analyzed through switching mode analysis and simulation, so as to determine the indexes for evaluating the overall switching performance of the device.

[0037] Further, in step S1, based on the switching mode analysis of the SiC MOSFET, the gate-source voltage spike, turn-off voltage spike, and turn-on current spike are selected as the indexes for evaluating the device reliability.

[0038] Further, in step S2, according to the requirements under different application scenarios, working conditions, and converter conditions, the range of performance indexes is set, and the range of performance indexes is between the minimum value and the target value; the minimum value is the minimum value that this index of the SiC MOSFET can reach under the circuit parameter boundary conditions or ideal conditions; the target value is the index value expected to be achieved during engineering design; the target value and minimum value of the gate-source voltage spike can be set according to the maximum gate-source voltage withstand and recommended drive voltage values in the SiC MOSFET data book; the range of the turn-off voltage spike is mainly determined by the working condition current, the minimum value can be determined according to the working condition voltage, and then the target value of the turn-off voltage spike can be determined according to the limit value of the equal-power consumption curve in the device operating safe area; the range of the turn-on current spike is mainly determined by the working condition voltage, the minimum value can be determined according to the load current, and then the target value can be determined by the drain current corresponding to the drain-source voltage on the equal-power consumption curve.

[0039] Further, in step S3, the weighting factor is defined as the change rate of the three performance indexes of the gate-source voltage spike, turn-off voltage spike, and turn-on current spike with respect to the parasitic inductance parameters; the parasitic inductance parameters include the gate parasitic inductance parameter, drain parasitic inductance parameter, and source parasitic inductance parameter; the weighting factor values of different performance indexes represent their importance to the overall performance of the SiC MOSFET. Based on the switching transient model considering the parasitic inductance parameters, mathematical models of voltage and current overshoots are established respectively. Among them, the peak value of the drain-source voltage is V GS(max) , then the degree of change of the turn-off voltage spike value of the SiC MOSFET with respect to the drain parasitic inductance variable, that is, the weighting factor k2 corresponding to the turn-off voltage spike is dV DS(max) / dL D ; the weighting factor k3 corresponding to the turn-on current spike value of the SiC MOSFET with respect to the parasitic inductance variable is dI D(max) / dL D ; the sum of the weighting factors of the gate-source voltage spike, turn-off voltage spike, and turn-on current spike indexes is 1, then the weighting factor corresponding to the gate-source voltage is defined as k1 = 1 - k2 - k3.

[0040] Further, in step S3, the weighting coefficients of different performance indicators are obtained by fitting theoretical calculations and experimental data; on the basis of theoretical analysis, the theoretical values are corrected through experimental test data. Under the same working conditions, the parasitic inductance parameters of the drive and power circuits are taken as variables by means of a double-pulse experimental platform, the variation trends of the performance indicators of SiC MOSFET under different parasitic inductance parameters are analyzed, the performance indicator values are standardized, and a trend line of the performance indicators varying with the parasitic inductance parameters is obtained by using the method of linear fitting, the corresponding change rates are obtained, and the weighting coefficient values are calculated.

[0041] Further, in step S4, the objective function is constructed by the sum of the products of the standardized values of each performance indicator and the corresponding weighting coefficients, which can reflect the optimization degree of the performance indicators of the gate-source voltage spike, turn-off voltage spike, and turn-on current spike of the SiC MOSFET device. The smaller the objective function value, the better the overall performance optimization effect of the SiC MOSFET; the standardization of the performance indicators refers to converting indicators with different units and orders of magnitude into dimensionless values.

[0042] The standardized values of the performance indicators of SiC MOSFET are calculated as follows:

[0043]

[0044] Further, in step S4, the solution of the objective function includes the following steps:

[0045] Step S4-1: Determine the value boundaries of different parasitic inductances according to the typical values of the parasitic inductances of the metal pins of the SiC MOSFET device and engineering design experience.

[0046] Step S4-2: Establish a double-pulse simulation model of SiC MOSFET, and use the exhaustive method to perform simulation calculations on different parasitic inductance combinations within the constraint conditions to obtain the gate-source voltage spike, turn-off voltage spike, turn-on current spike, and switching loss values of the device during the switching transient.

[0047] Step S4-3: Standardize the performance indicator values obtained by simulation, calculate the corresponding objective function values, and finally obtain the 3D map between the objective function and the parasitic inductance parameters.

[0048] Based on the calculated standardized values of different performance indicators and the weighting coefficients of the corresponding indicators, the objective function for the multi-objective optimization design of the device is established as:

[0049]

[0050] Among them, A1, A2, and A3 are the weighted coefficients of the evaluation indexes of the gate-source voltage spike, turn-off voltage spike, and turn-on current spike respectively, which represent the importance of this performance index of the SiC MOSFET to the objective function.

[0051] Considering the typical value of the parasitic inductance of the metal pins of the SiC MOSFET device in TO-247-3L package and engineering design experience, the value boundaries of different parasitic inductances are determined, and the constraint conditions of the objective function are set as:

[0052]

[0053] Among them, L G is the gate parasitic inductance, L D is the drain parasitic inductance, L S is the source parasitic inductance.

[0054] Establish a double-pulse simulation model of the SiC MOSFET in LTspice software. Within the range of parasitic inductance constraints, use the exhaustive method to simulate different combinations of parasitic inductances, measure the gate-source voltage spike, turn-off voltage spike, turn-on current spike, and switching loss of the device during the switching transient respectively. After standardization processing, calculate the value of its objective function, and finally obtain the 3D map between the objective function and the parasitic inductance parameters.

[0055] Furthermore, combined with Figure 2 , in the step S4, the relationship map between the objective function obtained by simulation calculation and the parasitic inductance parameters, Figure 2 in which the three coordinate axes are the gate parasitic inductance, the drain parasitic inductance, and the source parasitic inductance respectively, the simulation step size is set to 2nH, and the color of the fourth dimension represents the size of the objective function value. The darker the color, the larger the objective function value, that is, the worse the overall reliability of the device.

[0056] From Figure 2 the relationship map in, it can be seen that as the gate parasitic inductance, the drain parasitic inductance, and the source parasitic inductance increase, the value of the objective function increases, and the overall reliability of the SiC MOSFET gradually decreases. Among them, the drain parasitic inductance and the source parasitic inductance have the most significant impact on the overall performance of the device, and the impact of the gate parasitic inductance is relatively small. Combining the simulation data and images, the range of parasitic inductance parameters corresponding to the minimum value of the objective function is the range of optimal values for the overall performance of the device. Then the optimized interval of the parasitic inductance corresponding to the optimal overall reliability of the device can be expressed as:

[0057]

[0058] Within this interval, the gate-source voltage spike, turn-off voltage spike, and turn-on current spike of the device are all within the design requirements, ensuring the safe and reliable operation of the device.

[0059] Furthermore, in step S4, within the range of parasitic inductance parameter values where the overall switching performance is optimal, by combining simulation data and images and based on the principle of optimal loss, an optimized range of parasitic inductance parameters with optimal loss is obtained. To further maximize the low-loss advantage of the SiC MOSFET, based on the principle of optimal loss, the optimal loss combination is searched within the above range, and the loss-optimized range obtained by combining simulation data and images is:

[0060]

[0061] Combined with Figure 3 , multiple sets of parasitic inductance combinations are taken at the boundaries and within the optimized range of parasitic inductance corresponding to the optimal overall reliability of the device and the loss-optimized range. The switching characteristic parameters of the SiC MOSFET under different parasitic inductance parameter combinations are obtained through LTspice software simulation. From Figure 3 it can be seen that the inductance parameter groups within both optimized ranges have good switching characteristics, and the switching loss in the loss-optimized range decreases significantly; at the same time, within the proposed optimized range of parasitic inductance parameters, while the switching characteristics of the SiC MOSFET are optimized, the rise time and fall time of the device remain basically unchanged, ensuring the high-speed switching advantage of the SiC MOSFET.

[0062] The present invention proposes an optimization method for the parasitic inductance parameters of the PCB of a power electronic converter based on multi-objective weighting. This method comprehensively considers the restrictive relationship between the parasitic inductance parameters and the performance indicators of the SiC MOSFET, selects multiple performance indicators of the device for evaluation, coordinates and compromises different performance indicators, and then collaboratively optimizes the parasitic inductance parameters of the drive loop and the power loop. Finally, the range of parasitic inductance values that makes the overall performance of the SiC MOSFET optimal and the loss lowest is given to guide the optimized design of the PCB layout of the converter.

[0063] The above embodiments are only used to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any changes made on the basis of the technical solution according to the technical idea proposed by the present invention fall within the protection scope of the present invention.

Claims

1. A method for optimizing converter PCB parasitic inductance parameters based on multi-objective weighting, characterized in that: The following steps are involved: Step S1: Determine the performance index of the evaluation device; Step S2: setting the range of performance indicators; Step S3: define and calculate weighted coefficients of different performance indicators; Step S4: Establish and solve the objective function, and finally determine the parasitic inductance value range with the best overall performance and loss of SiC MOSFET based on the relationship diagram between the objective function value and the parasitic inductance parameter.

2. The method for optimizing converter PCB parasitic inductance parameters based on multi-objective weighting according to claim 1, characterized in that: In the step S1, a SiC MOSFET double pulse test equivalent circuit model considering parasitic inductance parameters is established, and the influence of parasitic inductance parameters on device switching oscillation and overshoot is analyzed through switching modal analysis and simulation to determine an index for evaluating the overall switching performance of the device.

3. The method for optimizing converter PCB parasitic inductance parameters based on multi-objective weighting according to claim 1, characterized in that: In the step S1, based on the switching mode analysis of SiC MOSFET, the gate-source voltage spike, the turn-off voltage spike and the turn-on current spike are selected as indicators for evaluating the reliability of the device.

4. The method for optimizing converter PCB parasitic inductance parameters based on multi-objective weighting according to claim 1, characterized in that: In step S2, a range of the performance indicator is set according to requirements under different application scenarios, working conditions and converter conditions, and the range of the performance indicator is between a minimum value and a target value; the minimum value is the minimum value that can be achieved by this indicator of the SiC MOSFET under circuit parameter boundary conditions or ideal conditions; and the target value is the indicator value expected to be achieved during engineering design.

5. The method for optimizing converter PCB parasitic inductance parameters based on multi-objective weighting according to claim 1, characterized in that: In step S3, the weighting coefficient is defined as the rate of change of three performance indicators, namely, gate-source voltage peak, turn-off voltage peak, and turn-on current peak, with parasitic inductance parameters; the parasitic inductance parameters include gate parasitic inductance parameters, drain parasitic inductance parameters, and source parasitic inductance parameters.

6. The method for optimizing converter PCB parasitic inductance parameters based on multi-objective weighting according to claim 1, characterized in that: In the step S3, the weighted coefficients of different performance indicators are obtained by fitting theoretical calculations and experimental data; through a dual-pulse experimental platform, the parasitic inductance parameters of the drive and power circuits are used as variables, and the performance indicator values ​​of SiC MOSFET under different parasitic inductance parameters are obtained through experimental tests. The trend lines of different performance indicators changing with the parasitic inductance parameters are obtained by a linear fitting method, and the corresponding change rates are obtained, and the weighted coefficient values ​​of different indicators are further calculated.

7. The method for optimizing converter PCB parasitic inductance parameters based on multi-objective weighting according to claim 1, characterized in that: In step S4, the objective function is constructed by the sum of the standardized values ​​of various performance indicators and the corresponding weighted coefficient products, which can reflect the optimization degree of the performance indicators of the gate-source voltage spike, the turn-off voltage spike and the turn-on current spike of the SiC MOSFET device. The smaller the objective function value, the better the overall performance optimization effect of the SiC MOSFET. The standardization of the performance indicators refers to converting indicators of different units and orders of magnitude into dimensionless values.

8. The method for optimizing converter PCB parasitic inductance parameters based on multi-objective weighting according to claim 1, characterized in that: In step S4, solving the objective function includes the following steps: Step S4-1, determining the value boundaries of different parasitic inductances according to the typical value of the metal pin parasitic inductance of the SiC MOSFET device and engineering design experience; Step S4-2, establishing a double-pulse simulation model of SiC MOSFET, and using an exhaustive method to simulate and calculate different parasitic inductance combinations within the constraints, to obtain the gate-source voltage spike, turn-off voltage spike, turn-on current spike and switching loss value of the device switching transient; Step S4-3: normalize the performance index values ​​obtained by simulation, and calculate the corresponding objective function values, and finally obtain a 3D graph between the objective function and the parasitic inductance parameters.

9. The method for optimizing converter PCB parasitic inductance parameters based on multi-objective weighting according to claim 1, characterized in that: In step S4, the coordinate axes of the 3D graph represent the gate parasitic inductance, the drain parasitic inductance and the source parasitic inductance, and the color of the fourth dimension represents the magnitude of the objective function value. The darker the color, the larger the objective function value, that is, the worse the overall performance of the device. The minimum value of the objective function corresponds to the parasitic inductance parameter value range for the optimal overall switching performance of the device.

10. The method for optimizing converter PCB parasitic inductance parameters based on multi-objective weighting according to claim 1, characterized in that: In the step S4, the simulation data and the image are combined within the parasitic inductance parameter value range with the best overall switch performance, and based on the loss optimization principle, the parasitic inductance parameter optimization range with the best loss is obtained.

Images