Efficient phase interleaving controller applied to biphase inductive current

Abstract

The invention discloses an efficient phase interleaving controller applied to a double-phase inductive current, and solves the problem of inductive current zero passage of a traditional double-phase inductive current circuit in a light load mode in the prior art. According to the circuit, current in a system is firstly detected for zero-cross detection, and circuit voltage is obtained; the light and heavy load mode selector is used for judging the mode of the circuit according to the circuit voltage; in a heavy load mode, a marking signal is delayed by half a period according to the periodic frequency-halving module and the 180-degree staggered phase generator for adaptive delay compensation; in a light load mode, the self-adaptive staggered phase generator generates a mark signal of self-adaptively adjusted time-delay inductive current discharge time according to the light load mode; the duty ratio replicator is used for replicating the signal to obtain an initial slave phase duty ratio signal; the maximum conduction time limiting module is used for limiting the initial slave phase duty ratio signal to obtain a final slave phase duty ratio signal; the circuit has the characteristics of high precision and self-adaptive adjustment.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular, to an efficient phase interleaved controller applied to a dual-phase inductor current. Background Art

[0002] With the development of the big data and Internet of Things industries, the IC market has an increasingly strong demand for high-voltage conversion ratio chips. Flying capacitors are commonly used in high step-down ratio converter structures. On the one hand, they are used to reduce the voltage stress of power transistors. On the other hand, the soft charging of the inductor current is achieved through the characteristic that the current flowing through the capacitor cannot change suddenly. In order to improve the load-carrying capacity and reduce the output voltage ripple at the same time, a dual-phase or even multi-phase structure is commonly applied to high step-down ratio converters. However, the interleaved phase generation circuit for a dual-phase inductor current system has become a very difficult problem.

[0003] For a dual-phase inductor current system, a 180° phase difference is usually adopted between the duty cycles of the two phases to minimize the output voltage ripple. In the light load mode, when the freewheeling diode of one-phase inductor current is turned off at the zero crossing, the charging of the other inductor current is carried out through the discharge of the flying capacitor. The discharge of the flying capacitor requires its lower plate to be grounded, which will force the lower transistor of the previously turned-off inductor current to conduct again, causing the inductor current to cross zero, which reduces the efficiency of the system in the light load mode. Summary of the Invention

[0004] The present invention provides an efficient phase interleaved controller applied to a dual-phase inductor current, which solves the problem of the inductor current crossing zero in the light load mode in the prior art traditional dual-phase inductor current circuit, and at the same time has the characteristics of high precision and adaptive adjustment.

[0005] The present invention provides an efficient phase interleaved controller applied to a dual-phase inductor current. The circuit includes: a zero-crossing detector, a light / heavy load mode selector, a period frequency divider by two, a 180° interleaved phase generator with adaptive delay compensation, a light load mode adaptive interleaved phase generator, a duty cycle duplicator, a maximum conduction time limit module, and a D flip-flop and an RC delay.

[0006] The zero-crossing detector is used to detect the zero crossing of the current in the system to obtain the circuit voltage ZCD_EN.

[0007] The light / heavy load mode selector is used to judge the mode in which the circuit is located according to the circuit voltage ZCD_EN. Among them, the mode includes: a light load mode and a heavy load mode.

[0008] In the overload mode, the period frequency divider module is configured to divide the system clock signal CLK by two to obtain the CLK1 signal and the CLK2 signal, and then pass the CLK1 signal and the CLK2 signal through the D flip-flop and the RC delay element to obtain a first duty cycle signal group with different conduction times;

[0009] In the overload mode, the 180° interleaved phase generator with adaptive delay compensation is configured to generate a flag signal with a delay of half a period according to the first duty cycle signal group;

[0010] In the light load mode, the light load mode adaptive interleaved phase generator is configured to record the discharge time of the current inductor, and pass the discharge time through the D flip-flop and the RC delay element to obtain a second duty cycle signal group; and then generate a flag signal for adaptively adjusting the discharge time of the inductor current according to the second duty cycle signal group;

[0011] The duty cycle duplicator is configured to determine the high-level start time of the slave phase duty cycle according to the input flag signal with a delay of half a period or the flag signal for delaying the inductor current discharge time and the D flip-flop and the RC delay element, and determine the low-level start time of the slave phase duty cycle according to the flip of the comparator CMP3 to obtain an initial slave phase duty cycle signal;

[0012] The maximum conduction time limiting module is configured to limit the maximum time when the high level of the initial slave phase duty cycle signal appears to obtain a final slave phase duty cycle signal.

[0013] One or more technical solutions provided in the present invention have at least the following technical effects or advantages:

[0014] Through a zero-crossing detector and a light / heavy load mode selector, the system can dynamically adjust its operating mode according to the load conditions. In the light load mode, the system can reduce power consumption, while in the heavy load mode, the system can ensure sufficient power output. This dynamic adjustment helps to improve the overall efficiency, especially in applications with large load variations. In the heavy load mode, the cycle frequency division module and the 180° interleaved phase generator with adaptive delay compensation can generate accurate duty cycle signals, ensuring that the conduction time of the power devices is optimized, thereby reducing energy losses and improving power conversion efficiency. In the light load mode, the light load mode adaptive interleaved phase generator further optimizes the power management during light load by recording the inductor discharge time and generating an adaptively adjusted signal, avoiding unnecessary energy waste. Through the duty cycle duplicator and the maximum conduction time limit module, the system can accurately control the high-level time of the slave phase duty cycle signal, avoiding overheating or damage caused by too long conduction time, thereby enhancing the stability and reliability of the system. The system has an adaptive ability and can automatically adjust the operating mode and control signals according to the load changes. This adaptability enables the system to remain efficient and stable under different operating conditions, reducing the need for manual intervention. Through the 180° interleaved phase generator and precise duty cycle control, the system can reduce the current and voltage mutations during the switching process, thereby reducing electromagnetic interference and improving the electromagnetic compatibility of the system. Through the maximum conduction time limit module, the system can prevent the power devices from being in a high conduction state for a long time, thereby reducing the thermal stress and electrical stress of the devices and extending their service life. Description of the Drawings

[0015] Figure 1 It is the circuit diagram of the adaptive interleaved phase adjustment of the two-phase inductor current provided by the embodiment of the present invention;

[0016] Figure 2 It is the working flow chart of the adaptive interleaved phase adjustment circuit of the two-phase inductor current provided by the embodiment of the present invention;

[0017] Figure 3a It is the waveform diagram of the logic signals generated by the frequency division module, D flip-flop and RC delay provided by the embodiment of the present invention;

[0018] Figure 3b It is the working waveform of the adaptive interleaved phase adjustment circuit in the heavy load mode provided by the embodiment of the present invention;

[0019] Figure 3c It is the working waveform of the adaptive interleaved phase adjustment circuit in the light load mode provided by the embodiment of the present invention;

[0020] Figure 3d It is the zero-crossing adjustment waveform of the slave phase inductor current provided by the embodiment of the present invention;

[0021] Figure 3eThe main-phase inductor current zero-crossing adjustment waveform provided by the embodiment of the present invention;

[0022] Figure 4a The working waveform in the light-load mode provided by the embodiment of the present invention;

[0023] Figure 4b The working waveform in the heavy-load mode provided by the embodiment of the present invention. Detailed implementation manners

[0024] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0025] The present invention provides an efficient phase interleaving controller applied to the current of a two-phase inductor. Refer to Figure 1 , the circuit includes: a zero-crossing detector, a light / heavy load mode selector, a period frequency divider by two, a 180° interleaved phase generator with adaptive delay compensation, a light-load mode adaptive interleaved phase generator, a duty cycle duplicator, a maximum conduction time limit module, and a D flip-flop and an RC delay.

[0026] The zero-crossing detector is used to detect the current in the system for zero-crossing detection to obtain the circuit voltage ZCD_EN.

[0027] Among them, the specific circuit structure of the zero-crossing detector is the same as that of the existing zero-crossing detector, and the present invention will not elaborate.

[0028] The light / heavy load mode selector is used to judge the mode in which the circuit is located according to the circuit voltage ZCD_EN; among them, the modes include: light-load mode and heavy-load mode.

[0029] Here, the light / heavy load mode selector judges the mode in which the circuit is located according to the circuit voltage ZCD_EN, including:

[0030] Judging the magnitude relationship between the circuit voltage ZCD_EN and 0;

[0031] If the circuit voltage ZCD_EN = 0, the circuit is in the light-load mode;

[0032] If the circuit voltage ZCD_EN > 0, the circuit is in the heavy-load mode.

[0033] Specifically, the heavy / light load mode selector includes a selector MUX1; the selection enable terminal of the selector MUX1 is connected to the output terminal of the zero-crossing detector; the signal input terminals of the selector MUX1 are connected to the output terminals of the 180° interleaved phase generator with adaptive delay compensation and the light load mode adaptive interleaved phase generator; the output terminal of the selector MUX1 is connected to the duty cycle duplicator.

[0034] In the heavy load mode, the period divide-by-two module is used to divide the system period signal CLK by two to obtain the CLK1 signal and the CLK2 signal, and then the CLK1 signal and the CLK2 signal pass through D flip-flops and RC delay elements to obtain a first group of duty cycle signals with different conduction times, and the waveform is as Figure 3a shown.

[0035] In the heavy load mode, the 180° interleaved phase generator with adaptive delay compensation is used to generate a flag signal (CLK_TSW / 2Delay signal) with a delay of half a period according to the first group of duty cycle signals.

[0036] Here, the time delay of the flag signal with a delay of half a period is half of the period of the system period signal CLK.

[0037] Specifically, the 180° interleaved phase generator with adaptive delay compensation includes:

[0038] MOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, capacitors C1, C2, C3, C4, and comparator CMP1;

[0039] The gate terminal of the MOS transistor MN1 is connected to the duty cycle signal S1; the source terminal of the MOS transistor MN1 is connected to the drain terminal of the MOS transistor MN2, the drain terminal of the MOS transistor MN3, and the upper plate of the capacitor C1; the drain terminal of the MOS transistor MN1 is connected to the current bias.

[0040] The gate terminal of the MOS transistor MN2 is connected to the duty cycle signal S2; the source terminal of the MOS transistor MN2 is connected to the upper plate of the capacitor C3, the source terminal of the MOS transistor MN5, and the negative terminal of the comparator CMP1;

[0041] The gate terminal of the MOS transistor MN3 is connected to the duty cycle signal S3; the source terminal of the MOS transistor MN3 is connected to the lower plate of the capacitor C1 and grounded;

[0042] The gate terminal of the MOS transistor MN4 is connected to the duty cycle signal S4; the source terminal of the MOS transistor MN4 is connected to the drain terminal of the MOS transistor MN5, the drain terminal of the MOS transistor MN6, and the upper plate of the capacitor C2; the drain terminal of the MOS transistor MN4 is connected to the current bias.

[0043] The gate terminal of MOS transistor MN5 is connected to the duty cycle signal S5;

[0044] The gate terminal of MOS transistor MN6 is connected to the duty cycle signal S6; the source terminal of MOS transistor MN6 is connected to the lower plate of capacitor C2, the lower plate of capacitor C3, the lower plate of capacitor C4, and the source terminal of MOS transistor MN8 and is grounded;

[0045] The gate terminal of MOS transistor MN7 is connected to the duty cycle signal S7; the source terminal of MOS transistor MN7 is connected to the drain terminal of MOS transistor MN8, the upper plate of capacitor C4, and the positive terminal of comparator CMP1; the drain terminal of MOS transistor MN7 is connected to the current bias;

[0046] The gate terminal of MOS transistor MN8 is connected to the duty cycle signal S8;

[0047] The output terminal of comparator CMP1 is connected to the 0 terminal of the light load mode adaptive interleaved phase generator. The first duty cycle signal group includes: duty cycle signals S1 to S8.

[0048] The first duty cycle signal group of the 180° interleaved phase generator with adaptive delay compensation is sequentially input from the gate terminals of MOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, and MN8 into the 180° interleaved phase generator with adaptive delay compensation, and a flag signal (CLK_TSW / 2Delay signal) with a half-cycle delay is output at the output terminal of comparator CMP1.

[0049] In the light load mode, the light load mode adaptive interleaved phase generator is used to record the discharge time of the current inductor, and the discharge time passes through a D flip-flop and an RC delay to obtain a second duty cycle signal group; and then an adaptively adjusted CLK_TSW / 2Delay signal is generated according to the second duty cycle signal group.

[0050] Here, the time delay of the CLK_TSW / 2Delay signal is the discharge time of the current inductor.

[0051] Specifically, the light load mode adaptive interleaved phase generator includes: MOS transistors MN9, MN10, MN11, MN12, MN13, capacitor C5, capacitor C6, capacitor C7, comparator CMP2;

[0052] The source terminal of MOS transistor MN9 is connected to the drain terminal of MOS transistor MN10, the drain terminal of MOS transistor MN11, and the upper plate of capacitor C5; the drain terminal of MOS transistor MN9 is connected to the current bias; the gate terminal of MOS transistor MN9 is connected to the duty cycle signal S9;

[0053] The source terminal of MOS transistor MN10 is connected to the upper plate of capacitor C6 and the negative terminal of comparator CMP2; the gate terminal of MOS transistor MN10 is connected to the duty cycle signal S10;

[0054] The source terminal of MOS transistor MN11 is connected to the lower plate of capacitor C5, the lower plate of capacitor C6, the lower plate of capacitor C7, and the source terminal of MOS transistor MN13 and is connected to GND; the gate terminal of MOS transistor MN11 is connected to the duty cycle signal S11;

[0055] The source terminal of MOS transistor MN12 is connected to the drain terminal of MOS transistor MN13, the upper plate of capacitor C7, and the positive terminal of comparator CMP2; the drain terminal of MOS transistor MN12 is connected to the current bias; the gate terminal of MOS transistor MN12 is connected to the duty cycle signal S12;

[0056] The gate terminal of MOS transistor MN13 is connected to the duty cycle signal S13;

[0057] The output terminal of comparator CMP2 is connected to terminal 1 of the light load mode adaptive interleaved phase generator; the second duty cycle signal group includes: duty cycle signals S9 to S13.

[0058] When the inductor current is charging, its freewheeling diode is turned off and the gate control signal is at a low level; when the inductor current is discharging, the freewheeling diode is turned on and the gate control signal is at a high level; when the inductor current passes through zero during the discharging process, the freewheeling diode is turned off and the gate control signal is at a low level. Therefore, when the gate control signal of the freewheeling diode is at a high level, it indicates that the inductor is in the discharging state and has not passed through zero. The duration of this high level is represented by DIL, that is, the DIL high level records the inductor current discharging time. The DIL signal is input to the D flip-flop and the RC delay module to obtain the interleaved conduction signals S9, S10, and S11 with the same principle as S1, S2, and S3. The light load mode adaptive interleaved phase delay generator starts to work. The high level of the duty cycle signal S9 controls MOS transistor MN9 to conduct. At this time, both MOS transistors MN10 and MN11 are turned off. The conduction time is recorded as T4. Then the current source ID charges capacitor C5 through MOS transistor MN9, and the voltage VC5 reached by the capacitor charging is VC5 = ID × T4 / C5.

[0059] After the conduction time T4 ends, the duty cycle signal S10 is at a high level, controlling MOS transistor MN10 to conduct. At this time, both MOS transistors MN9 and MN11 are turned off. Capacitor C5 shares charges with capacitor C6 through MOS transistor MN10. The capacitance values of capacitor C5 and capacitor C6 are equal;

[0060] Next, the duty cycle signal S11 is at a high level, controlling MOS transistor MN11 to conduct, and discharging the charges on capacitor C5 to GND through MOS transistor MN11.

[0061] After multiple cycles, the voltage value on capacitor C6 is nearly equal to the peak voltage of the voltage VC5 of capacitor C5. When the rising edge of the system clock signal CLK arrives, the duty cycle signal S12 conducts, and the conduction time is denoted as T5. The current bias ID charges capacitor C7 through MOS transistor MN12. The voltage VC7 on capacitor C7 = ID × T5 / C7. Since C7 = C6 and VC6 = VC5 = ID × T4 / C5, after T4 = DIL time, VC7 on capacitor C7 is higher than VC6. At this time, the comparator CMP2 outputs a high level, generating a high-level pulse CLK_TSW / 2Delay.

[0062] A duty cycle duplicator is used to determine the high-level turn-on time of the slave-phase duty cycle according to the input CLK_TSW / 2Delay signal or CLK_DIL_Delay signal, as well as the D flip-flop and the delay generator, and determine the low-level start time of the slave-phase duty cycle according to the flip of the comparator CMP3 to obtain the initial slave-phase duty cycle signal.

[0063] Specifically, the duty cycle duplicator includes:

[0064] MOS transistors MN14, MN15, MN16, MN17, MN18, MN19, comparator CMP3, capacitors C8, C9, and C10;

[0065] The gate terminal of MOS transistor MN14 is connected to the duty cycle signal S14; the source terminal of MOS transistor MN14 is connected to the drain terminals of MOS transistors MN15 and MN18 and the upper plate of capacitor C10; the drain terminal of MOS transistor MN14 is connected to the current bias.

[0066] The gate terminal of MOS transistor MN15 is connected to the duty cycle signal S15; the source terminal of MOS transistor MN15 is connected to the lower plate of capacitor C10, the lower plates of capacitors C9 and C8, and the source terminal of MOS transistor MN19 and is connected to GND.

[0067] The gate terminal of MOS transistor MN16 is connected to the output terminal of the light / heavy load mode selector; the source terminal of MOS transistor MN16 is connected to the drain terminal of MOS transistor MN17; the drain terminal of MOS transistor MN16 is connected to the current bias; among them, the output terminal of the light / heavy load mode selector outputs the CLK_TSW / 2Delay signal or the CLK_DIL_Delay signal.

[0068] The gate terminal of MOS transistor MN17 is connected to the duty cycle signal S17; the source terminal of MOS transistor MN17 is connected to the upper plate of capacitor C8, the drain terminal of MOS transistor MN19, and the negative terminal of comparator CMP3.

[0069] The gate terminal of MOS transistor MN18 is connected to the duty cycle signal S18; the source terminal of MOS transistor MN18 is connected to the upper plate of capacitor C9 and the positive terminal of comparator CMP3;

[0070] The gate terminal of MOS transistor MN19 is connected to the duty cycle signal S19;

[0071] The output terminal of comparator CMP3 is connected to the maximum conduction time limit module, where the output terminal of comparator CMP3 is the initial slave phase duty cycle signal.

[0072] The maximum conduction time limit module is used to limit the maximum time when the high level of the initial slave phase duty cycle signal appears to obtain the final slave phase duty cycle signal.

[0073] Combined with the specific circuit structure of the above duty cycle duplicator, the output signal of the heavy and light load mode selector is the CLK_TSW / 2Delay signal in the heavy load mode and the CLK_DIL_Delay signal in the light load mode; when working in the heavy load mode, at the moment when the rising edge of the CLK_TSW / 2Delay signal arrives, it represents that half a cycle of time has been delayed. At this time, the rising edge of the CLK_TSW / 2Delay signal triggers the D flip-flop to output a high level, making S16 and S17 high levels, capacitor C8 starts to charge, and the duty cycle duplicator starts to work. At this time, the slave phase duty cycle changes from low to high.

[0074] The main item duty cycle signal PA passes through a D flip-flop and an RC delay element to generate interleaved conduction duty cycle signals S14, S15, S18. The generation principle is the same as that of S1, S2, S3, and the waveform of the duty cycle signal S14 is the same as that of the main item duty cycle signal PA. The duty cycle signal S14 is first high level to control MOS transistor MN14 to conduct first. At this time, both MOS transistor MN15 and MOS transistor MN18 are turned off, and the conduction time is recorded as TA. Then the current source ID charges capacitor C10 through MOS transistor MN14, and the voltage VC10 reached by capacitor C10 charging is VC10 = ID×TA / C10.

[0075] After the conduction time TA ends, the duty cycle signal S18 is at a high level, controlling the MOS transistor MN18 to conduct. At this time, both the MOS transistors MN14 and MN15 are turned off. The capacitor C10 shares charge with the capacitor C9 through the MOS transistor MN18. The capacitance values of the capacitors C10 and C9 are equal. Then, the duty cycle signal S15 is at a high level, controlling the MOS transistor MN15 to conduct, and discharging the charge on the capacitor C10 to GND through the MOS transistor MN15. After multiple cycles, the voltage value on the capacitor C9 is nearly equal to the peak voltage of the capacitor C10. The rising edge of the output selection signal of the light / heavy load mode selector causes the MOS transistors MN16 and MN17 to conduct. At this time, the MOS transistor MN19 is in the off state. The current bias ID charges the capacitor C8 through the MOS transistors MN16 and MN17. Since C8 = C9 = C10 and the charging currents of C8 and C10 are both ID, after TA, the voltage VC8 of the capacitor C8 reaches the peak voltage of VC10. At this time, the comparator CMP3 outputs a low-level pulse, controlling the MOS transistors MN16 and MN17 to turn off. At the same time, the duty cycle signal S19 is at a high level to control the MOS transistor MN19 to conduct, clearing the charge on the capacitor C9, and the system enters the next cycle.

[0076] After the above steps, the slave phase duty cycle that changes from low to high when the CLK_TSW / 2Delay signal arrives is obtained. When CMP3 flips, the slave phase duty cycle changes from high to low. Since the flip duration of CMP3 is related to the voltage on C9, and the voltage on C9 is equal to the voltage VC10 = ID×TA / C10 reached by C10 charging, and the high-level time of the slave phase duty cycle is equal to TA, the replication of the duty cycle is completed.

[0077] In a specific embodiment provided by the present invention, refer to Figure 2 , when the system starts to work, the light / heavy load mode selector generates an output signal ZCD_EN. If ZCD_EN is at a high level of 5V, it indicates that the system is working in the heavy load mode at this time; similarly, when ZCD_EN is at a low level of 0V, it indicates that the system is working in the light load mode at this time.

[0078] When the system is working in the heavy load mode, ZCD_EN is at a low level of 0V. The system cycle signal CLK is divided into CLK1 and CLK2 signals by the cycle frequency divider module. The CLK1 signal generates duty cycle signals S1, S2, and S3 with a certain staggered time through the D flip-flop and the RC delay. And the waveform of the duty cycle signal S1 is the same as that of CLK1. For the specific waveform, refer to Figure 3a .

[0079] The 180° interleaved phase generator with adaptive delay compensation starts to work. The high level of the duty cycle signal S1 controls the MOS transistor MN1 to conduct. The high-level conduction time of the duty cycle signal S1 is denoted as T1. At this time, both the MOS transistors MN3 and MN2 are turned off. Then, the current bias ID charges the capacitor C1 through the MOS transistor MN1. The voltage VC1 reached by the capacitor C1 during charging is VC1 = ID × T1 / C1.

[0080] After the high-level conduction time T1 of the duty cycle signal S1 ends, the duty cycle signal S2 becomes high level, controlling the MOS transistor MN2 to conduct. At this time, both the MOS transistors MN1 and MN3 are turned off. The capacitor C1 shares charges with the capacitor C3 through the MOS transistor MN2. Since the capacitance values of the capacitor C1 and the capacitor C3 are equal, the charges on the capacitor C1 are equally divided with the capacitor C3.

[0081] Next, the duty cycle signal S3 becomes high level, controlling the MOS transistor MN3 to conduct, and discharges the charges on the capacitor C1 to GND through the MOS transistor MN3.

[0082] Finally, when the next cycle of the system clock signal CLK arrives, the capacitor C1 starts to charge again to the peak voltage of VC1. After multiple cycles, the voltage value on the capacitor C3 is nearly equal to the peak voltage of the capacitor C1.

[0083] When the CLK1 signal is at low level, the MOS transistors MN1, MN2, and MN3 are all turned off. At this time, the CLK2 signal is at high level. The CLK2 passes through a D flip-flop and an RC delay circuit to generate duty cycle signals S4, S5, and S6 with a certain interleaved time. And the waveform of the duty cycle signal S4 is the same as that of the CLK2. For the specific waveform, refer to Figure 3a 。

[0084] The high level of the duty cycle signal S4 controls the MOS transistor MN4 to conduct. The high-level conduction time of the duty cycle signal S4 is denoted as T2, and T2 = T1. At this time, both the MOS transistors MN5 and MN6 are turned off. The current bias IID charges the capacitor C2 through the MOS transistor MN4. C2 = C1 = C3, and the voltage VC2 of the capacitor during charging is VC2 = ID × T2 / C2.

[0085] After the high-level conduction time T2 of the duty cycle signal S4 ends, the duty cycle signal S5 becomes high level, controlling the MOS transistor MN5 to conduct. At this time, both the MOS transistors MN4 and MN6 are turned off. The capacitor C2 shares charges with the capacitor C3 through the MOS transistor MN5. The capacitance values of the capacitor C2 and the capacitor C3 are equal;

[0086] Next, the duty cycle signal S6 is at a high level. The setting of the conduction time of S6 only needs to ensure that S6 is at a high level when S4 and S5 are at a low level. The duration of the high level only needs to ensure that the electricity of the capacitor C2 is discharged to 0. S6 controls the MOS transistor MN6 to conduct, and discharges the charge on the capacitor C2 to GND through the MOS transistor MN6.

[0087] CLK1 and CLK2 alternate to a high level within one cycle of CLK, that is, VC1 and VC2 alternately correct the voltage of the capacitor C3, so that when the frequency of the system cycle signal CLK is fixed, the voltage value VC3 on the capacitor C3 is a fixed value, that is, VC3 is approximately equal to the peak voltages of VC1 and VC2.

[0088] The duty cycle signal S7 is a square wave signal with the same period as CLK. The high level time is denoted as T7. After a period of time when S7 is at a low level, S8 becomes high level, with a duration of T8, and then becomes low level. The conduction time of the MOS transistor MN7 is T7. When the duty cycle signal S7 is at a high level, the MOS transistor MN7 conducts, and at this time, the MOS transistor MN8 is turned off. The MOS transistor MN7 conducts, and the current flowing through the MOS transistor MN7 is 2ID, with a conduction time of T7, charging the capacitor C4. Then, the time required for the capacitor C4 to charge to the voltage VC3 is half of the high level conduction time T1 of the duty cycle signal S1, that is, the charging time of the capacitor C3 is T7 = T1 / 2. When the capacitor voltage VC4 of the capacitor C4 is higher than VC3, the comparator CMP1 outputs a high level pulse.

[0089] Since CLK1 is a divide-by-two of CLK and the duty cycle of CLK1 is 50%, the high level time of CLK1 is the period of the system cycle signal CLK, that is, the comparator CMP1 generates a high level pulse every half of the system cycle. At this time, the high level pulse is the CLK_TSW / 2Delay signal.

[0090] When the system operates in the light load mode, the discharge time DIL of the inductor current generates duty cycle signals S9, S10, S11 with a certain interleaving time through a D flip-flop and an RC delay, and the waveform of the duty cycle signal S9 is the same as the discharge time DIL of the inductor current. The generation principle of the waveforms of S9, S10, S11 is the same as that of S1, S2, S3.

[0091] The light load mode adaptive interleaved phase delay generator starts to work. The high level of the duty cycle signal S9 controls the MOS transistor MN9 to conduct. At this time, both the MOS transistor MN10 and the MOS transistor MN11 are turned off. The conduction time is denoted as T4. Then, the current source ID charges the capacitor C5 through the MOS transistor MN9, and the voltage VC5 reached by the capacitor charging is VC5 = ID × T4 / C5.

[0092] After the conduction time T4 ends, the duty cycle signal S10 is at a high level, controlling the MOS transistor MN10 to conduct. At this time, both the MOS transistors MN9 and MN11 are turned off, and the capacitor C5 shares charge with the capacitor C6 through the MOS transistor MN10. The capacitance values of the capacitors C5 and C6 are equal.

[0093] Next, the duty cycle signal S11 is at a high level, controlling the MOS transistor MN11 to conduct, and discharging the charge on the capacitor C5 to GND through the MOS transistor MN11.

[0094] After multiple cycles, the voltage value on the capacitor C6 is nearly equal to the peak voltage of the voltage VC5 of the capacitor C5. When the rising edge of the system clock signal CLK arrives, the duty cycle signal S12 conducts, and the conduction time is denoted as T5. The current bias ID charges the capacitor C7 through the MOS transistor MN12. The voltage VC7 on the capacitor C7 = ID×T5 / C7. Since C7 = C6 and VC6 = VC5 = ID×T4 / C5, the voltage VC7 on the capacitor C7 is higher than VC6 after T4 = DIL time. At this time, the comparator CMP2 outputs a high level, generating a high-level pulse CLK_DIL_Delay.

[0095] The CLK_DIL_Delay signal and the CLK_TSW / 2Delay signal are selected by the light / heavy load mode selector. When the output signal ZCD_EN of the light / heavy load mode selector is at a high level of 5V, the selector outputs CLK_TSW / 2Delay, indicating that the system is working in the heavy load mode at this time; similarly, when ZCD_EN is at a low level of 0V, the selector outputs CLK_DIL_Delay, indicating that the system is working in the light load mode at this time.

[0096] The rising edge of the output signal of the light / heavy load mode selector (the CLK_DIL_Delay signal or the CLK_TSW / 2Delay signal) makes the MOS transistor MN16 conduct, triggering the duty cycle duplicator to work. The main duty cycle signal PA passes through a D flip-flop and an RC delay to generate staggered conduction duty cycle signals S14, S15, and S18. The generation principle is the same as that of S1, S2, and S3, and the waveform of the duty cycle signal S14 is the same as that of the main duty cycle signal PA. The duty cycle signal S14 is first at a high level to control the MOS transistor MN14 to conduct first. At this time, both the MOS transistors MN15 and MN18 are turned off, and the conduction time is denoted as TA. Then the current source ID charges the capacitor C10 through the MOS transistor MN14. The voltage VC10 reached by the capacitor C10 charging = ID×TA / C10.

[0097] After the conduction time TA ends, the duty cycle signal S18 is at a high level, controlling the MOS transistor MN18 to conduct. At this time, both the MOS transistors MN14 and MN15 are turned off. The capacitor C10 shares charge with the capacitor C9 through the MOS transistor MN18. The capacitance values of the capacitor C10 and the capacitor C9 are equal. Then the duty cycle signal S15 is at a high level, controlling the MOS transistor MN15 to conduct, and discharging the charge on the capacitor C10 to GND through the MOS transistor MN15. After multiple cycles, the voltage value on the capacitor C9 is nearly equal to the peak voltage of the capacitor C10. The rising edge of the selection signal output by the light / heavy load mode selector causes the MOS transistors MN16 and MN17 to conduct. At this time, the MOS transistor MN19 is in the off state. The current bias ID charges the capacitor C8 through the MOS transistors MN16 and MN17. Since C8 = C9 = C10 and the charging currents of C8 and C10 are both ID, after TA, the voltage VC8 of the capacitor C8 reaches the peak voltage of VC10. At this time, the comparator CMP3 outputs a low-level pulse, controlling the MOS transistors MN16 and MN17 to turn off. At the same time, the duty cycle signal S19 is at a high level to control the MOS transistor MN19 to conduct, clearing the charge on the capacitor C9, and the system enters the next cycle.

[0098] Through the above steps, the duty cycle output by the comparator CMP3 is the same as that of PA, that is, the duty cycle replication is completed. Repeating the above steps generates two-phase duty cycle signals with a phase difference of 180° during heavy load and two-phase duty cycle signals with an adaptive phase difference during light load.

[0099] Please refer to Figures 3b to 3e , Figures 3b to 3e which is the working waveform diagram of the adaptive interleaved phase adjustment circuit for the dual-phase inductor current system provided by the embodiment of the present invention;

[0100] The working waveform of the adaptive interleaved phase generator when the system operates in heavy load is as Figure 3bAs shown, first, the period of PA is divided by two to generate duty cycle signals S1 and S4. The signals pass current ID to alternately charge capacitor C1 and capacitor C2. After the charging time ends, the peak voltages of capacitor C1 and capacitor C2 are sampled on capacitor C3. When the rising edge of PA in the next period arrives, capacitor C4 starts to charge with a current of 2×ID. After half a period, the voltage of capacitor C4 reaches the voltage stored on capacitor C3. Considering the switching delay of the comparator and the circuit, the delay is compensated, that is, the voltage of VC4 is increased by Voffset = Ioffset×Roffset. This voltage can compensate for the circuit delay so that the comparator generates the CLK_TSW_Delay signal after half a period. At this time, the duty cycle duplicator starts to work and charges capacitor C8 with the high-level time of PA. Its peak voltage is recorded on capacitor C9. When the rising edge of the CLK_TSW / Delay signal comes, capacitor C10 starts to be charged. When the voltage of capacitor C10 reaches the voltage of capacitor C9, the charging time is the same as the high-level time of PA. At this time, comparator CMP3 flips and the charging is turned off. By repeating the above steps, a two-phase duty cycle signal with a phase difference of 180° is achieved.

[0101] When the system operates in the light load mode, the working waveform of the adaptive interleaved phase generator is as Figure 3c shown. First, the discharge time DIL of the inductor current generates a duty cycle signal S9 through a logic gate. The duty cycle signal S9 charges capacitor C5. After the charging time ends, the peak voltage of capacitor C5 is sampled on capacitor C6. When the rising edge of PA in the next period arrives, capacitor C7 starts to charge with the same current. After time DIL, the voltage of capacitor C7 reaches the voltage stored on capacitor C6. At this time, the comparator generates a pulse signal CLK_DIL_Delay. At the same time, the duty cycle duplicator starts to work and charges capacitor C8 with the high-level time of PA. Its peak voltage is recorded on capacitor C9. When the rising edge of CLK_DIL_Delay comes, capacitor C10 starts to be charged. When the voltage of capacitor C10 reaches capacitor C9, its charging time is the same as the high-level time of PA. At this time, the comparator flips and the charging is turned off. By repeating the above steps, a two-phase duty cycle signal with an adaptive phase difference is achieved according to different DILs.

[0102] Figure 3d and Figure 3e respectively correspond to two different types of inductor current zero-crossing situations, namely, phase A zero-crossing and phase B non-zero-crossing; phase B zero-crossing and phase A non-zero-crossing. For Figure 3c , when the interleaved phase control method of this patent is not adopted, the charging of phase A will cause the current of phase B to cross zero. By using the method of this patent to adjust the interleaved phases of the two phases, it is possible to achieve that the currents of both phases do not cross zero. For Figure 3d, when the interleaved phase control method of this patent is not adopted, the charging of phase B will cause the current of phase A to cross zero. By using the method of this patent to adjust the interleaved phases of the two phases, it is possible to ensure that the currents of both phases do not cross zero.

[0103] Please refer to Figures 4a to 4b , Figures 4a to 4b is the simulation schematic diagram of the adaptive interleaved phase adjustment circuit for the dual-phase inductor current system provided by the embodiment of the present invention;

[0104] Figure 4a is the working waveform in the light load mode. By using the adaptive interleaved phase generator in the light load mode to generate the phase difference between the two phases, it is ensured that the currents of both phases do not cross zero. Figure 4b is the working waveform in the heavy load mode. The phase difference between the two phases generated by the 180° interleaved phase generator with adaptive delay compensation is 180°, achieving the minimum ripple of the output voltage and a higher load-carrying capacity.

[0105] The present invention relates to an adaptive interleaved phase adjustment circuit applied to a dual-phase inductor current system, including: a zero-crossing detector, a light / heavy load mode selector, a period frequency divider by two, an 180° interleaved phase generator with adaptive delay compensation, an adaptive interleaved phase generator in the light load mode, a duty cycle duplicator, a maximum conduction time limit module, and logic gates. For a dual-phase inductor current system, the phase difference affects the ripple of the output voltage. Usually, a 180° phase difference is adopted to minimize the output voltage ripple. However, in the light load mode, due to the characteristics of the dual-phase current, when the inductor current of one phase turns off at zero crossing, the charging of the inductor current of the other phase will force the inductor current that has turned off in the previous phase to conduct again, causing the inductor current to cross zero, thereby reducing the light load efficiency. The adaptive interleaved phase adjustment circuit of the present invention can adaptively generate a phase difference according to the working state of the system, maintain a 180° phase difference in the heavy load mode to achieve the minimum output ripple, and adaptively adjust the phase difference according to the discharge time of the inductor current in the light load mode to ensure that the currents of both phases do not cross zero, improving the light load efficiency. This method can be widely applied to dual-phase inductor current systems.

[0106] The various embodiments in this specification are described in a progressive manner. For the same or similar parts between the various embodiments, reference can be made to each other. The key points of each embodiment are the differences from other embodiments. All or part of the present invention can be used in many general or special computer system environments or configurations.

[0107] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting the present invention; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A high-efficiency phase interleaving controller for dual-phase inductive current, characterized in that: include: Zero-crossing detector, light and heavy load mode selector, cycle two-division module, 180° staggered phase generator with adaptive delay compensation, light load mode adaptive staggered phase generator, duty cycle replicator, maximum on-time limit module, D flip-flop and RC delay; The zero-crossing detector is used to perform zero-crossing detection on the current in the system to obtain the circuit voltage ZCD_EN; The light-load and heavy-load mode selector is used to determine the mode of the circuit according to the circuit voltage ZCD_EN; wherein the modes include: light-load mode and heavy-load mode; In the overload mode, the periodic frequency division module is used to divide the system periodic signal CLK by two to obtain a CLK1 signal and a CLK2 signal, and then pass the CLK1 signal and the CLK2 signal through the D trigger and the RC delay to obtain a first duty cycle signal group with different conduction times; In the heavy load mode, the adaptive delay-compensated 180° staggered phase generator is used to generate a half-cycle delayed flag signal according to the first duty cycle signal group; In the light load mode, the light load mode adaptive staggered phase generator is used to record the discharge time of the current inductor, and pass the discharge time through the D trigger and the RC delay device to obtain a second duty cycle signal group; and then generate a flag signal of the adaptively adjusted delayed inductor current discharge time according to the second duty cycle signal group; The duty cycle replicator is used to determine the high level start time of the slave phase duty cycle according to the input delayed half cycle flag signal or the delayed inductor current discharge time flag signal and the D flip-flop and the RC delay device, and determine the low level start time of the slave phase duty cycle according to the flip of the comparator CMP3 to obtain the initial slave phase duty cycle signal; The maximum on-time limiting module is used to limit the maximum time during which the high level of the initial slave phase duty cycle signal appears, so as to obtain the final slave phase duty cycle signal.

2. The high-efficiency phase interleaving controller for dual-phase inductive current according to claim 1, characterized in that: The light-load or heavy-load mode selector determines the mode of the circuit according to the circuit voltage ZCD_EN, including: Determine the magnitude relationship between the circuit voltage ZCD_EN and 0; If the circuit voltage ZCD_EN=0, the circuit is in light load mode; If the circuit voltage ZCD_EN>0, the circuit is in heavy load mode.

3. The high-efficiency phase interleaving controller for dual-phase inductive current according to claim 1, characterized in that: The delay of the half-cycle delayed flag signal is half of the cycle of the system cycle signal CLK.

4. The high-efficiency phase interleaving controller for dual-phase inductive current according to claim 1, characterized in that: The time delay of the sign signal of the delayed inductor current discharge time is the discharge time of the current inductor.

5. The high-efficiency phase interleaving controller for dual-phase inductive current according to claim 1, characterized in that: The 180° staggered phase generator with adaptive delay compensation comprises: MOS transistor MN1, MOS transistor MN2, MOS transistor MN3, MOS transistor MN4, MOS transistor MN5, MOS transistor MN6, MOS transistor MN7, MOS transistor MN8, capacitor C1, capacitor C2, capacitor C3, capacitor C4 and comparator CMP1; The gate terminal of the MOS transistor MN1 is connected to the duty cycle signal S1; the source terminal of the MOS transistor MN1 is connected to the drain terminal of the MOS transistor MN2, the drain terminal of the MOS transistor MN3 and the upper plate of the capacitor C1; the drain terminal of the MOS transistor MN1 is connected to the current bias; The gate terminal of the MOS transistor MN2 is connected to the duty cycle signal S2; the source terminal of the MOS transistor MN2 is connected to the upper plate of the capacitor C3, the source terminal of the MOS transistor MN5 and the negative terminal of the comparator CMP1; The gate terminal of the MOS tube MN3 is connected to the duty cycle signal S3; the source terminal of the MOS tube MN3 is connected to the lower plate of the capacitor C1 and connected to GND; The gate terminal of the MOS transistor MN4 is connected to the duty cycle signal S4; the source terminal of the MOS transistor MN4 is connected to the drain terminal of the MOS transistor MN5, the drain terminal of the MOS transistor MN6 and the upper plate of the capacitor C2; the drain terminal of the MOS transistor MN4 is connected to the current bias; The gate terminal of the MOS tube MN5 is connected to the duty cycle signal S5; The gate terminal of the MOS tube MN6 is connected to the duty cycle signal S6; the source terminal of the MOS tube MN6 is connected to the lower plate of the capacitor C2, the lower plate of the capacitor C3, the lower plate of the capacitor C4 and the source terminal of the MOS tube MN8 and connected to GND; The gate terminal of the MOS tube MN7 is connected to the duty cycle signal S7; the source terminal of the MOS tube MN7 is connected to the drain terminal of the MOS tube MN8, the upper plate of the capacitor C4 and the positive terminal of the comparator CMP1; the drain terminal of the MOS tube MN7 is connected to the current bias; The gate terminal of the MOS tube MN8 is connected to the duty cycle signal S8; The output terminal of the comparator CMP1 is connected to the 0 terminal of the light load mode adaptive staggered phase generator; The first duty cycle signal group includes: the duty cycle signal S1 to the duty cycle signal S8.

6. The high-efficiency phase interleaving controller for dual-phase inductive current according to claim 1, characterized in that: The light load mode adaptive staggered phase generator includes: MOS transistor MN9, MOS transistor MN10, MOS transistor MN11, MOS transistor MN12, MOS transistor MN13, capacitor C5, capacitor C6, capacitor C7, and comparator CMP2; The source end of the MOS tube MN9 is connected to the drain end of the MOS tube MN10, the drain end of the MOS tube MN11 and the upper plate of the capacitor C5; the drain end of the MOS tube MN9 is connected to the current bias; the gate end of the MOS tube MN9 is connected to the duty cycle signal S9; The source terminal of the MOS tube MN10 is connected to the upper plate of the capacitor C6 and the negative terminal of the comparator CMP2; the gate terminal of the MOS tube MN10 is connected to the duty cycle signal S10; The source end of the MOS tube MN11 is connected to the lower plate of the capacitor C5, the lower plate of the capacitor C6, the lower plate of the capacitor C7 and the source end of the MOS tube MN13 and connected to GND; the gate end of the MOS tube MN11 is connected to the duty cycle signal S11; The source end of the MOS tube MN12 is connected to the drain end of the MOS tube MN13, the upper plate of the capacitor C7 and the positive end of the comparator CMP2; the drain end of the MOS tube MN12 is connected to the current bias; the gate end of the MOS tube MN12 is connected to the duty cycle signal S12; The gate terminal of the MOS tube MN13 is connected to the duty cycle signal S13; The output end of the comparator CMP2 is connected to the terminal 1 of the light load mode adaptive staggered phase generator; The second duty cycle signal group includes: the duty cycle signal S9 to the duty cycle signal S13.

7. The high-efficiency phase interleaving controller for dual-phase inductive current according to claim 1, characterized in that: The duty cycle replicator includes: MOS tube MN14, MOS tube MN15, MOS tube MN16, MOS tube MN17, MOS tube MN18, MOS tube MN19, comparator CMP3, capacitor C8, capacitor C9 and capacitor C10; The gate terminal of the MOS tube MN14 is connected to the duty cycle signal S14; the source terminal of the MOS tube MN14 is connected to the drain terminal of the MOS tube MN15, the drain terminal of the MOS tube MN18, and the upper plate of the capacitor C10; the drain terminal of the MOS tube MN14 is connected to the current bias; The gate terminal of the MOS tube MN15 is connected to the duty cycle signal S15; the source terminal of the MOS tube MN15 is connected to the lower plate of the capacitor C10, the lower plate of the capacitor C9, the lower plate of the capacitor C8 and the source terminal of the MOS tube MN19 and connected to GND; The gate end of the MOS tube MN16 is connected to the output end of the light or heavy load mode selector; the source end of the MOS tube MN16 is connected to the drain end of the MOS tube MN17; the drain end of the MOS tube MN16 is connected to the current bias; wherein the output end of the light or heavy load mode selector outputs a mark signal of a delay of half a cycle or a mark signal of a delay inductor current discharge time; The gate terminal of the MOS tube MN17 is connected to the duty cycle signal S17; the source terminal of the MOS tube MN17 is connected to the upper plate of the capacitor C8, the drain terminal of the MOS tube MN19 and the negative terminal of the comparator CMP3; The gate terminal of the MOS tube MN18 is connected to the duty cycle signal S18; the source terminal of the MOS tube MN18 is connected to the upper plate of the capacitor C9 and the positive terminal of the comparator CMP3; The gate terminal of the MOS tube MN19 is connected to the duty cycle signal S19; The output end of the comparator CMP3 is connected to the maximum on-time limiting module, wherein the output end of the comparator CMP3 is an initial slave phase duty cycle signal.

8. The high-efficiency phase interleaving controller for dual-phase inductive current according to claim 1, characterized in that: The light and heavy load mode selector comprises a selector MUX1; The selection enable terminal of the selector MUX1 is connected to the output terminal of the zero-crossing detector; The signal input end of the selector MUX1 is connected to the output end of the adaptive delay compensation 180° staggered phase generator and the light load mode adaptive staggered phase generator; The output end of the selector MUX1 is connected to the duty cycle copier.

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