High-linearity distributed amplifier structure based on multi-grid voltage bias
By using a multi-gate bias array in the CMOS distributed amplifier to offset the third-order nonlinear term, the substrate loss and insufficient linearity of the CMOS distributed amplifier in the ultra-high frequency millimeter band are solved, and higher linearity and input point performance are achieved.
Patent Information
- Application Number
- CN202510379635.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-01
AI Technical Summary
CMOS distributed amplifiers have problems of substrate loss and insufficient linearity in the ultra-high frequency millimeter band, which affects its practical application.
By providing incompletely consistent gate bias voltage to each gain unit, a multi-gate bias array is formed, and the cancellation effect of third-order nonlinear terms is achieved, improving the third-order distortion problem of distributed amplifiers.
The amplitude of the third-order transconductance is effectively reduced, the third-order nonlinear distortion is suppressed, the input third-order intercept point and the input 1dB compression point are improved, and the linearity of the distributed amplifier is improved.
Smart Images

Figure CN120238074A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of radio frequency integrated circuits, relates to a distributed amplifier, and specifically provides a high-linearity distributed amplifier structure based on multi-gate voltage biasing. Background Art
[0002] The evolution of 6G communication technology has promoted the breakthrough development of the ultra-high frequency millimeter wave / terahertz band (0.1 - 10 THz) and ultra-high speed data transmission (Tbps level). The ultra-wideband architecture based on the distributed amplifier (DA) provides a signal amplification solution for large-scale MIMO systems with its cross-band phase consistency. Considering cost and compatibility with digital logic modules, the distributed amplifier structure based on bulk silicon CMOS process becomes the preferred solution. However, the inherent defects such as substrate loss and insufficient linearity in this process restrict the practical application of CMOS distributed amplifiers in the ultra-high frequency millimeter wave band. Therefore, how to improve the distortion of CMOS distributed amplifiers to enhance their linearity is a major problem to be solved. Summary of the Invention
[0003] The purpose of the present invention is to provide a high-linearity distributed amplifier structure based on multi-gate voltage biasing for the problems existing in the above-mentioned prior art. This technology realizes the cancellation effect of the third-order nonlinear term within a certain input voltage range by providing inconsistent gate bias voltages to each gain unit of the distributed amplifier, thereby improving the third-order distortion problem of the distributed amplifier.
[0004] To achieve the above purpose, the technical solution adopted by the present invention is as follows:
[0005] A high-linearity distributed amplifier structure based on multi-gate voltage biasing, characterized by comprising: a gate transmission line inductor, a drain transmission line, a gain unit, a gate terminal resistor, a drain terminal resistor, a signal input terminal, a signal output terminal, and a bias network; wherein, the multi-gate voltage biasing array of the gain unit is V Bi , The gate transmission line is composed of N gate inductors L gi and 1 terminal inductor L gt The drain transmission line is composed of 1 terminal inductor L dt and N drain inductors L di wherein, N is the number of gain units, which can be selected from positive integers greater than 1, i is an integer from 1 to N ; thei One gate inductor is connected to the input terminal of the i +1-th gate inductor and the i input terminal of the gain cell; the i -1-th drain inductor is connected to the i drain inductor and the i output terminal of the gain cell; the gate terminal inductor and the drain terminal inductor are respectively connected to the terminal resistors of their respective transmission lines.
[0006] Furthermore, the gain cell adopts a transconductance cell with the same structural size, and the multi-gate voltage biasing array of the gain cell V Bi needs to make the third-order non-linear term of the output current of the distributed amplifier i out,3 approach 0. Further, make the integral term of the third-order transconductance g m3 approach 0, satisfying the following relationship:
[0007]
[0008]
[0009] where V m and K m respectively represent a certain bias voltage point and the amplitude of the third-order transconductance impulse function at this bias voltage point.
[0010] The beneficial effects of the present invention are as follows:
[0011] The present invention provides a high-linearity distributed amplifier structure based on multi-gate voltage biasing. By reasonably setting the values of the multi-gate voltage biasing array, the g m3 amplitude of the impulse function K m is reduced, and by creating multiple zero-crossing points, the g m3 positive and negative alternation of the impulse quantity amplitude is realized, and then the g m3 cancellation effect is achieved. Finally, the third-order non-linearity cancellation of the distributed amplifier is completed, the third-order intermodulation distortion IMD3 is improved, and the input third-order intercept point IIP3 and the input 1dB compression point IP1dB are further improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 is a schematic diagram of the high-linearity distributed amplifier structure based on multi-gate voltage biasing in the present invention.
[0013] Figure 2The comparison diagram of the curves of the high-linearity distributed amplifier structure based on multi-gate voltage biasing at 100 GHz in the present invention and the traditional structure g m3 with respect to the change with bias voltage
[0014] Figure 3 The comparison diagram of the normalized third-order nonlinear distortion ( I out,3 / ) I out,1 ) 2 between the high-linearity distributed amplifier structure based on multi-gate voltage biasing at 100 GHz in the present invention and the traditional structure
[0015] Figure 4 The comparison diagram of the normalized third-order intermodulation distortion IMD3 between the high-linearity distributed amplifier structure based on multi-gate voltage biasing at 100 GHz in the present invention and the traditional structure
[0016] Figure 5 The comparison diagram of the in-band input 1 dB compression point IP1dB and in-band input third-order intercept point IIP3 indexes between the high-linearity distributed amplifier structure based on multi-gate voltage biasing in the present invention and the traditional structure Specific embodiments
[0017] To make the invention purpose, technical solutions and technical effects of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments
[0018] This embodiment provides a high-linearity distributed amplifier structure based on multi-gate voltage biasing, and its structure is as Figure 1 shown, including two-stage amplifier circuits. Among them, each stage of the circuit includes: gate transmission line inductor, drain transmission line, eight gain units, gate terminal resistor, drain terminal resistor, signal input terminal, signal output terminal, and bias network
[0019] The two-stage circuits of this embodiment are only different in the gate bias network. The gate bias network of the input stage is set as a uniform gate bias voltage array, and the gate bias network of the output stage is set as a multi-gate voltage biasing array; among them, the multi-gate voltage biasing array of the gain units in the output stage is V Bi , where i is from 1 to 8, the gate transmission line is composed of seven gate inductors L g and two terminal inductors L g / 2, and the drain transmission line is composed of seven drain inductors L d and two terminal inductors L d / 2 configuration; the gate terminal inductance and the drain terminal inductance are respectively connected to the terminal resistances of their respective transmission lines.
[0020] In terms of the working principle: a distributed amplifier is a transconductance amplifier in which multiple transconductance units convert their respective input voltage signals into current signals and then superimpose and output them. The third-order intermodulation distortion term of the output current is:
[0021] {i}_{out,IM3}=\frac {1} {8}{g}_{m3}{A}^{3}\cos {[(2{ω}_{in1}-{ω}_{in2})t]}
[0022] Wherein, ω in1 and ω in2 are the input dual-tone signals, A is the amplitude of the dual-tone signal, g m3 is the third-order transconductance term; thus, it can be seen that the output third-order intermodulation distortion term is strongly correlated with the third-order transconductance term. Given that the third-order transconductance term is strongly correlated with the DC bias, therefore, the linearity of the distributed amplifier can be improved by reducing the third-order transconductance term g m3 .
[0023] The third-order transconductance g m3 of the traditional distributed amplifier has only one zero-crossing point in the curve of its variation with the gate bias voltage, and the coordinate origin is not included therein; the present invention proposes a distributed amplifier structure with a non-uniform multi-gate voltage bias array, which increases the number of zero-crossing points of the curve of the third-order transconductance g m3 varying with the gate bias voltage; more specifically: at 100 GHz, the third-order transconductance g m3 generates three zero-crossing points (Z1, Z2, Z3) as the gate bias voltage changes, and compared with the traditional structure, the amplitude of g m3 under class A or AB bias is greatly reduced, as shown in Figure 2 .
[0024] In this embodiment, all gain units adopt a cascode structure with peaking inductance, the transistors all adopt NMOSFETs with a width-to-length ratio of 2×12 μm / 30 nm, the power supply voltage is 1.8 V, and the multi-gate voltage bias array of the output stage V Biis [0.58V, 0.58 V, 0.58 V, 0.58 V, 0.28 V, 0.33 V, 0.33 V, 0.13V]; the port impedances of the input and output and the terminal load resistance are all set to 50 Ω; in order to demonstrate the optimized linearity effect obtained by the present invention, the third-order nonlinear distortion (normalized value), the third-order intermodulation distortion IMD3 (normalized value), and the input 1dB compression point IP1dB and the input third-order intercept point IIP3 indexes of the present invention and the traditional structure are compared.
[0025] Finally, this embodiment achieves an optimized linearity effect. At 100 GHz, compared with the traditional structure, the third-order nonlinear distortion of the present invention is suppressed. When the input is -16 dBV, the third-order nonlinear distortion is reduced by 12.39 dB, effectively suppressing the third-order nonlinear distortion, as Figure 3 shown; the third-order intermodulation distortion IMD3 of the present invention is also suppressed. When the input power is -8dBm, IMD3 is reduced by 3.7 dB, as Figure 4 shown; this embodiment achieves a 3-dB bandwidth range of 51-136 GHz. The in-band input 1dB compression point IP1dB can be increased by up to 3 dB, and at the same time, the in-band input third-order intercept point IIP3 is increased by up to 2.1 dB, as Figure 5 shown.
[0026] As described above, the above is only a specific embodiment of the present invention. Any feature disclosed in this specification, unless specifically described, can be replaced by other equivalent or similar-purpose alternative features; all the features disclosed, or all the steps in any method or process, except for mutually exclusive features and / or steps, can be combined in any way.
Claims
1. A high linearity distributed amplifier structure based on multi-gate bias, characterized in that: include: A gate transmission line inductor, a drain transmission line, a gain unit, a gate terminal resistor, a drain terminal resistor, a signal input terminal, a signal output terminal and a bias network; wherein the multi-gate bias array of the gain unit is V Bi , The gate transmission line is composed of N Gate Inductance L gi and 1 terminal inductor L gt The drain transmission line consists of a terminal inductor L dt and N Drain inductance L di Composition, among which, N is the number of gain units, which can be selected from positive integers greater than 1. i 1 to N The integer of i The gate inductance and i +1 gate inductance between and i The input terminals of the first gain unit are connected; i -1 drain inductor and the i The leakage inductance between i The output ends of the gain units are connected; the gate terminal inductor and the drain terminal inductor are respectively connected to the terminal resistance of their own transmission lines.
2. The high linearity distributed amplifier structure based on multi-gate biasing according to claim 1, characterized in that: The gate biases provided to the different gain units are non-uniform values.
3. The high linearity distributed amplifier structure based on multi-gate biasing according to claim 1, characterized in that: Third-order transconductance g m3 The curve of the change with the gate bias voltage has at least two zero-crossing points, which does not include the origin of the coordinate.