Carrier generator, switching power supply and envelope tracking modulator

Abstract

The invention provides a carrier generator, a switching power supply and an envelope tracking modulator, and relates to the technical field of electronics, and the carrier generator comprises a plurality of carrier generation circuits which are used for generating a plurality of triangular carrier signals with the same amplitude and phase; the plurality of carrier wave generating circuits comprise a first carrier wave generating circuit and a second carrier wave generating circuit, and a synchronous capacitor is connected between the output end of the first carrier wave generating circuit and the output end of the second carrier wave generating circuit. According to the technical scheme provided by the invention, the waveform distortion condition of the carrier signal can be reduced, so that the synchronization degree and the waveform matching degree of the output carrier signal are improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technologies, and in particular, to a carrier generator, a switching power supply, and an envelope tracking modulator. Background Art

[0002] A power amplifier (PA) is used to amplify a radio frequency (RF) signal and is an important component in a wireless communication system. As one of the main power consumption sources of the battery power in a wireless communication device, reducing its power consumption is of great significance for extending the battery life of the wireless communication device.

[0003] Different from the traditional fixed power supply technology, envelope tracking (ET) technology can dynamically adjust the power supply voltage provided to the PA, effectively reducing the power consumption of the PA and improving the efficiency of the PA. Currently, it has become the most widely used power supply technology for power amplifiers in wireless communication systems. Among them, the ETPA system includes a PA and an envelope tracking modulator (ETM) for providing a modulated power supply voltage to the PA. In the ETM, a linear power supply and a switching power supply jointly generate a power output to supply power to the PA.

[0004] The switching power supply can generate a switching signal. Compared with a two-level switching power supply, a multi-level switching power supply that can provide more levels can well improve the efficiency of the envelope modulator. The multi-level switching power supply mainly includes a PWM modulator for generating a pulse width modulation (PWM) signal and a switching converter for outputting multiple levels according to the PWM signal. Taking a three-level switching signal as an example, in the PWM modulator, a carrier generator can generate two synchronous carrier signals and provide them to two comparators. The two comparators generate a PWM signal according to the carrier signals and a feedback signal detected from the output end of the linear power supply.

[0005] Among them, the carrier signals output by the carrier generator need to have a high degree of synchronization and waveform matching. However, the current carrier generators are prone to waveform distortion due to circuit mismatch, thereby affecting the synchronization and waveform matching of the carrier signals. Summary of the Invention

[0006] In view of this, the present application provides a carrier generator, a switching power supply, and an envelope tracking modulator, which are used to reduce the waveform distortion of carrier signals, thereby improving the synchronization and waveform matching of the output carrier signals.

[0007] To achieve the above object, in a first aspect, an embodiment of the present application provides a carrier generator, including: a plurality of carrier generation circuits for generating a plurality of triangular carrier signals with the same amplitude and phase; the plurality of carrier generation circuits include a first carrier generation circuit and a second carrier generation circuit, and a synchronization capacitor is connected between the output end of the first carrier generation circuit and the output end of the second carrier generation circuit.

[0008] In the carrier generator provided by the embodiment of the present application, the synchronization capacitor is connected between the output ends of the respective carrier generation circuits, which can automatically promote the synchronization of the carrier signals output by the respective carrier circuits; and a feedback path can be established between the respective carrier generation circuits to interconnect the error signals between the respective carrier generation circuits and balance this error signal to each carrier generation circuit, so that even if there is a circuit mismatch in each carrier generation circuit, the output carrier signals can still maintain a good waveform matching degree. It can be seen that the carrier generator provided by the embodiment of the present application can improve the synchronization degree and waveform matching degree of the carrier signals.

[0009] In a possible implementation manner of the first aspect, there are a plurality of second carrier generation circuits, a synchronization capacitor is connected between the output end of the first carrier generation circuit and the output ends of at least one second carrier generation circuit, and a synchronization capacitor is connected between the output end of each second carrier generation circuit and the output ends of at least one other second carrier generation circuit.

[0010] Through the above implementation manner, the carrier generator can output more carrier signals.

[0011] In a possible implementation manner of the first aspect, a synchronization capacitor is connected between the output end of the first carrier generation circuit and the output end of each second carrier generation circuit. This can improve the synchronization degree and waveform matching degree of the carrier signals output by the carrier generator.

[0012] In a possible implementation manner of the first aspect, a synchronization capacitor is connected between the output end of the first carrier generation circuit and the output end of one of the second carrier generation circuits;

[0013] According to the first connection sequence, synchronization capacitors are connected between the output ends of adjacent second carrier generation circuits.

[0014] Through the above implementation manner, the synchronization degree and waveform matching degree of the carrier signals output by the carrier generator can be improved.

[0015] In a possible implementation manner of the first aspect, all the synchronization capacitors are the same. This can improve the synchronization effect and simplify the circuit design.

[0016] In a possible implementation of the first aspect, the carrier generation circuit includes: a square wave generation circuit and a charge and discharge circuit. The charge and discharge circuit is connected to the output end of the square wave generation circuit and is used to generate a triangular carrier signal. In this implementation, the structure of the carrier generation circuit is simple and easy to implement.

[0017] In a possible implementation of the first aspect, the square wave generation circuit includes: a first comparator, a second comparator, and a latch;

[0018] The first input end of the first comparator is used to input a first voltage, and the second input end of the second comparator is used to input a second voltage; the output end of the charge and discharge circuit is respectively connected to the second input end of the first comparator and the first input end of the second comparator;

[0019] The output end of the first comparator is connected to the first input end of the latch, and the output end of the second comparator is connected to the second input end of the latch; the output end of the latch is connected to the control end of the charge and discharge circuit and is used to control the charge and discharge of the charge and discharge circuit.

[0020] Through the above implementation, the output accuracy of the square wave generation circuit can be better controlled.

[0021] In a possible implementation of the first aspect, the square wave generation circuit includes: a hysteresis comparator. The inverting input end of the hysteresis comparator is used to input a voltage signal, the non-inverting input end of the hysteresis comparator is connected to the output end of the charge and discharge circuit, and the output end of the hysteresis comparator is connected to the control end of the charge and discharge circuit and is used to control the charge and discharge of the charge and discharge circuit.

[0022] Through the above implementation, the structural complexity of the square wave generation circuit can be reduced.

[0023] In a possible implementation of the first aspect, the charge and discharge circuit includes: a first current source, a second current source, and a charge and discharge capacitor;

[0024] The first current source is connected to the first end of the charge and discharge capacitor through a first switch and is used to charge the charge and discharge capacitor;

[0025] The second current source is connected to the first end of the charge and discharge capacitor through a second switch and is used to discharge the charge and discharge capacitor;

[0026] The second end of the charge and discharge capacitor is grounded;

[0027] The output end of the square wave generation circuit is respectively connected to the control ends of the first switch and the second switch. The square wave generation circuit is used to control the first switch to conduct and the second switch to turn off when the charge and discharge capacitor is charging; and control the first switch to turn off and the second switch to conduct when the charge and discharge capacitor is discharging.

[0028] Through the above embodiments, the output accuracy of the charge and discharge circuit can be better controlled.

[0029] In a possible embodiment of the first aspect, the charge and discharge circuit is an integrating circuit. This can reduce the structural complexity of the charge and discharge circuit.

[0030] In a possible embodiment of the first aspect, the synchronous capacitor and the charge and discharge capacitors of the charge and discharge circuits in each carrier generation circuit are the same. This can simplify the circuit design.

[0031] In a second aspect, an embodiment of the present application provides a switching power supply, including: a PWM modulator and a power conversion circuit. The power conversion circuit is connected to the output end of the PWM modulator and is configured to output more than three switching signals according to the PWM signal output by the PWM modulator. Among them, the PWM modulator includes the carrier generator described in the first aspect or any embodiment of the first aspect.

[0032] In a third aspect, an embodiment of the present application provides an envelope tracking modulator, including: a linear power supply and the switching power supply described in the second aspect.

[0033] It can be understood that the beneficial effects of the second aspect and the third aspect can refer to the relevant descriptions in the first aspect, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic structural diagram of an ETPA system provided by an embodiment of the present application;

[0035] Figure 2 It is a schematic diagram of the relationship between the carrier signal, the feedback signal, and the switching signal provided by an embodiment of the present application;

[0036] Figure 3 It is a schematic structural diagram of a carrier generator in the related art;

[0037] Figure 4 is Figure 3 a schematic waveform diagram of the carrier signal output by the carrier generator in different situations in;

[0038] Figure 5 It is a schematic structural diagram of a carrier generator provided by an embodiment of the present application;

[0039] Figure 6 is this Figure 5 a working timing diagram of the carrier generation circuit in;

[0040] Figure 7 is Figure 5 a schematic waveform diagram of the carrier signal output by the carrier generator in different situations in;

[0041] Figure 8 Schematic diagram of the simulation result of the carrier generator provided by the embodiment of the present application during power-on;

[0042] Figure 9 Schematic diagram for comparing the simulation results of the carrier generator before and after adding circuit mismatch provided by the embodiment of the present application;

[0043] Figure 10 Schematic diagram of the simulation result of the ETM provided by the embodiment of the present application;

[0044] Figure 11 Another structural schematic diagram of the carrier generator provided by the embodiment of the present application;

[0045] Figure 12 is Figure 11 Schematic diagram of the waveform of the carrier signal output by the carrier generator in

[0046] Figures 13 - 16 Some other structural schematic diagrams of the carrier generator provided by the embodiment of the present application. Detailed implementation manners

[0047] The embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. The terms used in the implementation manner part of the embodiments of the present application are only used to explain the specific embodiments of the present application, rather than to limit the present application. These several specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0048] The carrier generator provided by the embodiment of the present application can be applied to class D amplifiers, buck-boost converters, continuous current boost converters, switching power supplies with switching signals of more than three levels, average power tracking (APT) modulators, ETMs, etc. For the convenience of description, the technical solution of the present application will be exemplarily described mainly by taking the carrier generator applied to the ETM in the embodiments of the present application as an example.

[0049] The ETPA system related to the embodiment of the present application will be described below first.

[0050] Figure 1 Schematic diagram of the ETPA system provided by the embodiment of the present application. As Figure 1 shown, the ETPA system may include: an ETM and a PA. Among them, the ETM includes a linear power supply 10 and a switching power supply 20.

[0051] The linear power supply 10 can amplify the input envelope signal En and output a linear voltage V LA, providing high-frequency components for the PA; the switching power supply 20 can detect and amplify the voltage output by the linear power supply 10, and output a DC voltage Vsw to provide low-frequency components for the PA; the linear voltage V output by the linear power supply 10 LA and the DC voltage Vsw output by the switching power supply 20 together constitute the power supply voltage V of the PA PA , where the DC voltage Vsw can be output to the PA through the inductor L. The PA can amplify the input radio frequency signal RF according to the power supply voltage V provided by the ETM PA and output a radio frequency signal RF with the desired power in . out .

[0052] Among them, the linear power supply 10 can be implemented by a linear amplifier (LA) and related modulation circuits; the switching power supply 20 can be implemented by a power conversion circuit and related modulation circuits.

[0053] Exemplarily, the power conversion circuit can be a multilevel switching converter, and the corresponding modulation circuit can be a PWM modulator. Taking the three-level as an example, the carrier generator in the PWM modulator can generate two synchronous carrier signals Vc1 and Vc2, which are respectively provided to two comparators Cmp1 and Cmp2. The two comparators generate PWM signals according to the carrier signals and the feedback signal VFB detected from the output end of the linear power supply 10; the multilevel switching converter outputs a switching signal with multiple levels according to the PWM signal (i.e., the DC voltage Vsw output by the switching power supply 20). Among them, the feedback signal VFB can also be determined based on the signal detected from the output end of the linear power supply 10 and the signal detected from the output end of the switching power supply 20.

[0054] It can be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the ETPA system. In other embodiments of the present application, the ETPA system may include more or fewer devices than those shown, or combine certain devices, or split certain devices, or arrange different devices. The illustrated devices can be implemented in hardware, software, or a combination of software and hardware. For example, in some embodiments, the above ETPA system can be a hybrid architecture including an ETM and an APT modulator.

[0055] Figure 2 shows a schematic diagram of the relationship between the carrier signal, the feedback signal, and the switching signal, as Figure 2As shown, the upper and lower limit voltages of the carrier signal Vc1 are V1a and V1b respectively, and the upper and lower limit voltages of the carrier signal Vc2 are V2a and V2b respectively. When VFB is between V1a and V2a, the switching signal Vsw switches between Vbat and 2Vbat; when VFB is between V2a and V1b, the switching signal Vsw switches between the ground level GND, Vbat and 2Vbat; when VFB is between V1b and V2b, the switching signal Vsw switches between GND and Vbat.

[0056] To ensure precise control of the outputs of the linear power supply and the switching power supply, the carrier signals Vc1 and Vc2 should have a high degree of synchronization, that is, the phases of the carrier signals Vc1 and Vc2 are the same; and a high degree of waveform matching is required, that is, the amplitudes and waveforms of the carrier signals Vc1 and Vc2 match. Otherwise, it may lead to inaccurate output power voltage, resulting in increased power consumption and reduced power efficiency, and even circuit failures in some cases.

[0057] Among them, the carrier generator generally adopts a master-slave architecture to implement, as Figure 3 shown, the master carrier generator can be implemented by two comparators, a latch, two current sources and a capacitor. Among them, the two comparators and the latch L1 are used to ensure that the carrier signal Vc1 remains between V1a and V1b. The two current sources are connected in series between the power supply Vdd and the ground Gnd through two switches. The latch L1 controls the on-off of the path between the two current sources and the capacitor C1 by controlling the two switches, thereby controlling the charging and discharging of the capacitor C1; the structure of the slave carrier generator is similar. The latch L2 controls the charging and discharging process of the capacitor C2 according to the clock signal generated by the master carrier generator and the outputs of the two comparators, outputs the carrier signal, so as to synchronize with the carrier signal output by the master carrier generator, and limits the carrier signal Vc2 between V2a and V2b.

[0058] In the ideal case of perfect matching of the master-slave carrier generators, the carrier signals Vc1 and Vc2 are well synchronized and have a low distortion degree, and the waveforms are as shown in (a) of Figure 4 . However, in actual design, circuit mismatches are likely to occur. For example, comparator delay, mismatches of current sources and capacitors, etc. These mismatches may cause distortion of Vc2.

[0059] As Figure 3 shown, the currents generated by the four current sources are i p1 , i p2 , i n1 and i n2 . Exemplarily, as shown in (b) of Figure 4 , when i p2 < i p1 and i n2 < in1 When this occurs, the capacitor C2 charges / discharges at a slower rate, resulting in the overall amplitude of Vc2 being less than expected (as shown by the dashed line). This will cause an error in the output voltage of the switching power supply. For the ETM, it will lead to degradation in the performance of the linear power supply and the ETM, including reduced bandwidth, limited signal swing, etc. In addition, if the amplitude of Vc2 decreases to the extent that it does not overlap with Vc1, it may cause incorrect switching in the switching converter, which may lead to circuit failures.

[0060] When i p2 >i p1 and i n2 >i n1 then waveforms as shown in (c) or (d) of Figure 4 may occur. These will all cause an error in the output voltage of the switching power supply and lead to a decline in the performance of the linear power supply and the ETM. In addition, Figure 4 the carrier signal shown in (d) of

[0061] may cause glitches during switching, resulting in increased power consumption and reduced power amplifier efficiency. In some cases, it may even lead to circuit failures.

[0062] In view of this, an embodiment of the present application provides a carrier generator. By connecting a synchronization capacitor between the output terminals of multiple carrier generation circuits, automatic synchronization of the carrier signals is achieved, and the distortion caused by circuit mismatch is reduced, thereby improving the synchronization degree and waveform matching degree of the carrier signals.

[0063] Figure 5 FIG. Figure 5 shows a schematic structural diagram of the carrier generator provided by an embodiment of the present application. As shown in

[0064] the carrier generator provided by an embodiment of the present application includes two carrier generation circuits: carrier generation circuit Carr1 and carrier generation circuit Carr2, which are used to generate two synchronous (i.e., in-phase) and equal-amplitude triangular carrier signals Vc1 and Vc2. A synchronization capacitor Cs is connected between the output terminal of carrier generation circuit Carr1 and the output terminal of carrier generation circuit Carr2.

[0065] Each carrier generation circuit can be implemented by a mutually connected square wave generation circuit and a charge and discharge circuit. Among them, the charge and discharge circuit is connected to the output terminal of the square wave generation circuit and is used to generate a triangular carrier signal. Here, by way of example, the square wave generation circuit is implemented by a comparator and a latch, and the charge and discharge circuit is implemented by a current source and a charge and discharge capacitor.

[0066] Specifically, as Figure 5 shown, the carrier generation circuit Carr1 includes: a comparator Cm1a, a comparator Cm1b, a latch L1, a current source Ip1, a current source In1, and a capacitor C1. The first input terminal of the comparator Cm1a inputs a first voltage (i.e., the upper limit voltage V1a of the carrier signal Vc1), and the second input terminal of the comparator Cm1b inputs a second voltage (i.e., the lower limit voltage V1b of the carrier signal Vc1); the first terminal of the capacitor C1 (i.e., the output terminal of the charge and discharge circuit) is respectively connected to the second input terminal of the comparator Cm1a and the first input terminal of the comparator Cm1b. Here, by way of example, the first input terminal of the comparator is the inverting input terminal, and the second input terminal is the non-inverting input terminal.

[0067] The output terminal of the comparator Cm1a is connected to the first input terminal (here, by way of example, the S terminal) of the latch L1, and the output terminal of the comparator Cm1b is connected to the second input terminal (here, by way of example, the R terminal) of the latch L1.

[0068] One end of the current source Ip1 is connected to the power supply Vdd, and the other end is connected to the first terminal of the capacitor C1 through a switch Sp1; one end of the current source In1 is connected to the first terminal of the capacitor C1 through a switch Sn1, and the other end is grounded to Gnd; the second terminal of the capacitor C1 is grounded.

[0069] The first output terminal (here, by way of example, the Q terminal) of the latch L1 is connected to the control terminal of the switch Sp1, and the second output terminal (here, by way of example, the Q terminal) is connected to the control terminal of the switch Sn1.

[0070] Figure 6 is the working timing diagram of the carrier generation circuit Carr1. As Figure 6 shown, when the carrier signal Vc1 rises to the upper limit voltage V1a, the comparator Cm1a outputs a high-level pulse signal, and the comparator Cm1b outputs a low-level signal; the states of the two input terminals of the latch L1 are S = 1 and R = 0. Correspondingly, the states of the two output terminals of the latch L1 are Q = 1 and Q = 0; at this time, the switch Sp1 connected to the Q terminal is turned off, and the switch Sn1 connected to the Q terminal is turned on, and the capacitor C1 discharges, and the voltage of the carrier signal Vc1 output from the output terminal (i.e., the first terminal of the capacitor C1) of the carrier generation circuit Carr1 decreases.

[0071] When the carrier signal Vc1 is lower than the upper limit voltage V1a, the comparator Cm1a outputs a low-level signal, and the comparator Cm1b outputs a low-level signal; the states of the two input terminals of the latch L1 are S = 0 and R = 0. Correspondingly, the states of the two output terminals of the latch L1 remain unchanged, that is, Q = 1 and Q = 0. The capacitor C1 continues to discharge, and the voltage of the carrier signal Vc1 continues to decrease.

[0072] When the carrier signal Vc1 drops to the lower limit voltage V1b, the comparator Cm1a outputs a low-level signal, and the comparator Cm1b outputs a high-level pulse signal; the states of the two input terminals of the latch L1 are S = 0 and R = 1. Correspondingly, the states of the two output terminals of the latch L1 are Q = 0 and Q = 1; at this time, the switch Sp1 connected to the Q terminal conducts, and the switch Sn1 connected to the Q terminal turns off. The capacitor C1 is charged, and the voltage of the carrier signal Vc1 output from the output terminal of the carrier generation circuit Carr1 (i.e., the first terminal of the capacitor C1) rises.

[0073] When the carrier signal Vc1 is higher than the lower limit voltage V1b, the comparator Cm1a outputs a low-level signal, and the comparator Cm1b outputs a low-level signal; the states of the two input terminals of the latch L1 are S = 0 and R = 0. Correspondingly, the states of the two output terminals of the latch L1 remain unchanged, that is, Q = 0 and Q = 1. The capacitor C1 continues to be charged, and the voltage of the carrier signal Vc1 continues to rise.

[0074] In this way, a triangular carrier signal Vc1 is output by the carrier generation circuit Carr1, and the voltage of the triangular carrier signal Vc1 is limited between the upper limit voltage V1a and the lower limit voltage V1b.

[0075] The carrier generation circuit Carr2 includes: a comparator Cm2a, a comparator Cm2b, a latch L2, a current source Ip2, a current source In2, a capacitor C2, as well as a switch Sp2 and a switch Sn2. The connection relationship and working principle of each device in the carrier generation circuit Carr2 are similar to those of the carrier generation circuit Carr1, and will not be elaborated here.

[0076] It can be understood that Figure 5 The circuit connection relationship shown in

[0077] In addition, it can be understood that the carrier generation circuits shown in the embodiments of the present application are only illustrative and do not constitute specific limitations on the carrier generation circuits. In other embodiments of the present application, the carrier generation circuit may include more or fewer devices than those shown, or combine certain devices, or split certain devices, or arrange different devices. The illustrated devices may be implemented in hardware, software, or a combination of software and hardware. For example, in some embodiments, various resistors and / or capacitor devices may be provided in the carrier generation circuit to improve the performance of the circuit.

[0078] Among them, the frequencies of the carrier signals Vc1 and Vc2 can be determined according to the current of the current source and the charge and discharge parameters of the charge and discharge capacitors, and the capacitance value of the synchronization capacitor Cs can be determined according to the frequencies of the carrier signals Vc1 and Vc2. In some embodiments, the synchronization capacitor Cs may adopt the same capacitor as the capacitor C1 and the capacitor C2 to simplify the circuit design.

[0079] In this embodiment, the synchronization capacitor Cs is connected between the output end of the carrier generation circuit Carr1 and the output end of the carrier generation circuit Carr2, which can automatically promote the synchronization of the two carrier signals Vc1 and Vc2; and a feedback path can be established between the carrier generation circuit Carr1 and the carrier generation circuit Carr2 to interconnect the error signals between the two carrier generation circuits and balance this error signal to the two carrier generation circuits, so that even if there is a circuit mismatch between the two carrier generation circuits, the two carrier signals output can maintain a good waveform matching degree.

[0080] When the carrier generation circuit Carr1 and the carrier generation circuit Carr2 are well matched, as shown in (a) of Figure 7 , under the action of the synchronization capacitor Cs, the carrier signals Vc1 and Vc2 can have good synchronization and waveform matching degrees, and the frequency of each carrier signal matches the frequency of the corresponding carrier generation circuit.

[0081] When there is a circuit mismatch between the two carrier generation circuits, for example, when one or more current sources (Ip1, Ip2, In1, and In2) deviate from the design values and do not match, as shown in (b) and (c) of Figure 7 , under the action of the synchronization capacitor Cs, the carrier signals Vc1 and Vc2 can maintain good synchronization and waveform matching degrees, and the waveform distortion degree is low. Among them, when one or more current sources are higher than the design value, as shown in (b) of Figure 7 , under the action of the synchronization capacitor Cs, the carrier signals Vc1 and Vc2 are synchronized at a frequency higher than the design value; when one or more current sources are lower than the design value, as shown in (c) of Figure 7 , under the action of the synchronization capacitor Cs, the carrier signals Vc1 and Vc2 are synchronized at a frequency lower than the design value.

[0082] It can be understood that when there are both current sources higher than the design value and current sources lower than the design value simultaneously, at different degrees of deviation, the carrier signals Vc1 and Vc2 may exhibit synchronization at a frequency higher than, lower than, or equal to the design value. Other types of circuit mismatch conditions (such as comparator delay, capacitance mismatch) can be analyzed similarly and will not be elaborated here.

[0083] To verify the effectiveness of the synchronization capacitor, Figure 8 A schematic diagram of the simulation results of the above carrier generator during power-on is shown. The simulation results show a schematic diagram of the voltage of the carrier signals Vc1 and Vc2 changing with time, as Figure 8 shown. During the period from 0 to 10 μs, the power supply voltage of the carrier generator gradually rises from 0 V to 3.7 V (nominal power supply voltage), and then remains constant at 3.7 V. In the initial stage of power-on, due to the power-on sequence and insufficient power supply voltage, the carrier signals Vc1 and Vc2 are not synchronized; as the power supply voltage continues to increase, under the action of the synchronization capacitor, the carrier signals Vc1 and Vc2 begin to gradually synchronize and gradually synchronize and match with low distortion after several cycles; after the power supply voltage stabilizes, the carrier signals Vc1 and Vc2 maintain a stable synchronization and matching effect.

[0084] The above simulation is based on a real transistor-level simulation. The two carrier generation circuits are quite matched, that is, no additional circuit mismatch is artificially introduced; however, since the two carrier signals Vc1 and Vc2 are at different DC levels, there are small differences between the two carrier generation circuits, for example, the comparator delay and slight changes in the current source. Under the action of the synchronization capacitor, this difference can be balanced, so that the carrier signals Vc1 and Vc2 maintain good synchronization and waveform matching.

[0085] When additional circuit mismatch is deliberately introduced, such as a 20% mismatch in the charging current, similar simulation results can be obtained. Figure 9 A schematic diagram comparing the simulation results of the carrier generator before and after increasing the circuit mismatch is shown, where Figure 9 (a) in is a schematic diagram of the simulation results of the carrier generator before increasing the circuit mismatch, and (b) in 9 is a schematic diagram of the simulation results of the carrier generator after increasing the circuit mismatch. Specifically, the current i of Ip2 p2 is 20% higher than the current i of Ip1 p1 , i p1 = 8 μA, i p2 = 10 μA. For simplicity, the simulation results during power-on are omitted, Figure 9 and the simulation results of the carrier generator at steady state are shown in.

[0086] From Figure 9As can be seen, regardless of the matching accuracy of the carrier generation circuit, the carrier signals Vc1 and Vc2 can maintain good synchronization and waveform matching, and the distortion is very low. Among them, when i p1 = i p2 = 8 μA, as expected, the charging current Ic1 of capacitor C1 and the charging current Ic2 of capacitor C2 are equal, both 8 μA, and the current Ic3 in the synchronous capacitor Cs is almost zero. When the circuit mismatch is increased, i p1 = 8 μA, i p2 = 10 μA. At this time, the charging currents flowing into capacitor C1 and capacitor C2 are balanced by the synchronous capacitor Cs, and a current Ic3 of -1 μA is generated in the synchronous capacitor Cs. The charging currents of capacitor C1 and capacitor C2 almost remain the same (Ic1 = Ic2 = 9 μA), which highlights the role of the synchronous capacitor Cs as a feedback component, making the charging currents flowing into capacitor C1 and capacitor C2 balanced.

[0087] As more carrier signals are generated (as shown in Figure 12 ), the degree of mismatch will increase. According to the simulation results, the proposed design can tolerate a mismatch of more than 100% in the charging current, which is sufficiently effective for carrier generators with two outputs and more outputs.

[0088] Figure 10 Fig. shows a schematic diagram of the simulation results of the ETM using the above carrier generator. Among them, the ETM is in the form of a chip. Since the carrier signal is an internal signal and cannot be directly measured, only the test waveform schematic diagrams of the ETM input signal (i.e., the envelope signal En input by the linear power supply), the ETM output signal (i.e., the power supply voltage V PA ) provided to the PA, and the switch signal Vsw are shown. As can be seen from Figure 10 , the ETM output signal is very similar to the ETM input signal with a DC voltage offset, thus confirming the function of the ETM chip and further verifying the function of the proposed carrier generator. In addition, the switch signal Vsw shows intermediate consistency between the boost operation (the switch signal Vsw switches between Vbat and 2Vbat) and the buck operation (the switch signal Vsw switches between GND and Vbat), that is, the switch signal Vsw during the boost period and the buck period are well connected, which further confirms the effectiveness of the carrier generator proposed in the embodiments of the present application.

[0089] The above is described by taking the carrier generator including two carrier generation circuits as an example. In some embodiments, the carrier generator may also include more carrier generation circuits. Figure 11 Another structural schematic diagram of the carrier generator provided by the embodiment of the present application Figure 12 is Figure 11Schematic diagram of the waveform of the carrier signal output by the intermediate carrier generator, as shown in Figure 11 and Figure 12 shown, the carrier generator provided by the embodiment of the present application includes N carrier generation circuits: carrier generation circuit Carr1 to carrier generation circuit CarrN, which are used to generate N carrier signals Vc1 to VcN with the same amplitude and phase, where N > 2; the upper and lower limit voltages of the carrier signal Vc1 are V1a and V1b respectively, the upper and lower limit voltages of the carrier signal Vc2 are V2a and V2b respectively... the upper and lower limit voltages of the carrier signal VcN are VNa and VNb respectively. For the sake of simplicity, the specific structures of the respective carrier generation circuits are not shown here, and reference can be made to the above embodiments, which will not be elaborated here.

[0090] Among them, a synchronous capacitor Cs is connected between the output terminals of at least some of the carrier generation circuits; in some embodiments, each carrier generation circuit is connected to at least one other carrier generation circuit with a synchronous capacitor Cs to improve the synchronization degree and waveform matching degree of the carrier signals output by the carrier generator.

[0091] Each synchronous capacitor Cs can be the same to improve the synchronization effect and simplify the circuit design. Of course, in some embodiments, each synchronous capacitor Cs can also be different, and each synchronous capacitor Cs can be selected according to needs.

[0092] It can be understood that any one of the carrier generation circuits can be selected as the first carrier generation circuit, and the other carrier generation circuits can all be used as the second carrier generation circuits. A synchronous capacitor Cs can be connected between the output terminals of the first carrier generation circuit and at least one second carrier generation circuit; for each second carrier generation circuit, a synchronous capacitor Cs can also be connected between the output terminals of the second carrier generation circuit and at least one other second carrier generation circuit.

[0093] Exemplarily, as shown in Figure 11 shown, a synchronous capacitor Cs is connected between the output terminal of the carrier generation circuit Carr1 and the output terminals of each other carrier generation circuit. That is, a synchronous capacitor Cs is connected between the output terminal of the first carrier generation circuit and the output terminals of each second carrier generation circuit.

[0094] In some embodiments, as shown in Figure 13 shown, synchronous capacitors Cs can be connected between adjacent carrier generation circuits. That is, a synchronous capacitor Cs is connected between the output terminal of the first carrier generation circuit and the output terminal of one of the second carrier generation circuits; synchronous capacitors Cs are connected between the output terminals of adjacent second carrier generation circuits.

[0095] The adjacent ones here may refer to two carrier generation circuits connected in sequence when connecting the carrier generation circuits according to a certain connection sequence (hereinafter referred to as the first connection sequence); in some embodiments, the adjacent carrier generation circuits connected according to this first connection sequence may also be two carrier generation circuits adjacent in spatial position, which can shorten the connection lines and reduce the connection complexity.

[0096] Exemplarily, the carrier generation circuits Carr1 to CarrN are arranged in sequence, and synchronous capacitors Cs are connected between the carrier generation circuit Carr1 and the carrier generation circuit Carr2, between the carrier generation circuit Carr2 and the carrier generation circuit Carr3... between the carrier generation circuit CarrN-1 and the carrier generation circuit CarrN.

[0097] In some embodiments, the carrier generation circuits can also be divided into several groups, each group includes multiple carrier generation circuits, and the carrier generation circuits in each group can adopt the above Figure 11 or Figure 13 shown method to connect the synchronous capacitors to achieve the synchronization and matching of the carrier signals within the group; then, synchronous capacitors can be connected between adjacent groups to achieve the synchronization and matching of the carrier signals between groups. Of course, other connection methods can also be adopted to achieve the synchronization and matching of the carrier signals among the carrier generation circuits.

[0098] In some embodiments of the present application, the square wave generation circuit and the charge and discharge circuit in the above carrier generation circuit can also be implemented by other circuit structures. Hereinafter, several possible implementation methods will be exemplarily described. Among them, for the convenience of description, the following mainly takes the carrier generator including two carrier generation circuits as an example for exemplary description. It can be understood that the following solutions can also be applied to the carrier generator including more carrier generation circuits. For the sake of brevity, it will not be elaborated any further.

[0099] Figure 14 Shows another possible implementation method of the carrier generation circuit, Figure 14 In the shown carrier generator, the main difference between the carrier generation circuit and the carrier generation circuit in the foregoing Figure 5 shown embodiment is that the charge and discharge circuit in the carrier generation circuit is implemented by an integrator, where the integrator can mainly be composed of an operational amplifier, a resistor, and a capacitor.

[0100] Exemplarily, in the carrier generation circuit Carr1, the integrator includes an operational amplifier A1, a resistor R1, and a capacitor C1. The resistor R1 is connected between the Q terminal of the latch L1 and the inverting input terminal of the operational amplifier A1. The capacitor C1 is connected between the inverting input terminal and the output terminal of the operational amplifier A1. The non-inverting input terminal of the operational amplifier A1 is grounded. In the carrier generation circuit Carr2, the integrator includes an operational amplifier A2, a resistor R2, and a capacitor C2, and their connection relationship is similar to that of the carrier generation circuit Carr1. The synchronization capacitor Cs is connected between the output terminals of the operational amplifier A1 and the operational amplifier A2. The structure of the square wave generation circuit in the carrier generation circuit is similar to that in the foregoing embodiment, and will not be described herein again.

[0101] Taking the carrier generation circuit Carr1 as an example, the input terminal of the integrator (i.e., the end where the resistor R1 is connected to the latch L1, which can also be called the control terminal of the integrator) can periodically charge and discharge the capacitor C1 according to the square wave signal output from the Q terminal of the latch L1, so that the output terminal of the operational amplifier A1 outputs a triangular carrier signal. The working principle of the carrier generation circuit Carr2 is similar. The synchronization capacitor Cs can automatically promote the synchronization of the carrier signals Vc1 and Vc2 and keep the two carrier signals with good waveform matching.

[0102] It can be understood that, similar to Figure 5 the above circuit connection relationship is only an example, and the connection relationship of each device can be adjusted adaptively; the above carrier generation circuit is also a simplified structure, and the circuit may include more or fewer devices than shown in the figure, or combine some devices, or split some devices, or perform different device arrangements, and the embodiments of the present application do not make special limitations on this.

[0103] Figure 15 Another possible implementation manner of the carrier generation circuit is shown. Figure 15 In the shown carrier generator, the main difference between the carrier generation circuit and the carrier generation circuit in the foregoing Figure 5 shown embodiment is that the square wave generation circuit in the carrier generation circuit is implemented by a hysteresis comparator.

[0104] Exemplarily, in the carrier generation circuit Carr1, the square wave generation circuit mainly includes a hysteresis comparator Cm1. The inverting input terminal of the hysteresis comparator Cm1 inputs a voltage signal V1. The non-inverting input terminal of the hysteresis comparator Cm1 is connected to the first terminal of the capacitor C1 (i.e., the output terminal of the charge and discharge circuit). The output terminal of the hysteresis comparator Cm1 is connected to the control terminal of the charge and discharge circuit (including the inverting control terminal of the switch Sp1 and the non-inverting control terminal of the switch Sn1). In the carrier generation circuit Carr2, the square wave generation circuit mainly includes a hysteresis comparator Cm2, and its connection relationship is similar to that of the carrier generation circuit Carr1. The structure of the charge and discharge circuit in the carrier generation circuit is the same as that ofFigure 5 Similar to the illustrated embodiment, it will not be elaborated here. The synchronous capacitor Cs is connected between the first ends of the capacitors C1 and C2.

[0105] Taking the carrier generation circuit Carr1 as an example, the hysteresis comparator Cm1 can output a square wave signal. When the square wave signal is at a low level, the switch Sp1 in the charge and discharge circuit is turned on and the switch Sn1 is turned off, and the current source Ip1 can charge the capacitor C1. When the square wave signal is at a high level, the switch Sp1 in the charge and discharge circuit is turned off and the switch Sn1 is turned on, and the current source In1 can discharge the capacitor C1. Circulating in this way, a triangular carrier signal is output at the output end of the charge and discharge circuit. The working principle of the carrier generation circuit Carr2 is similar. The synchronous capacitor Cs can automatically promote the synchronization of the carrier signals Vc1 and Vc2 and keep a good waveform matching degree between the two carrier signals.

[0106] Among them, the voltage signals V1 and V2 can be set as needed, for example, they can be low-level signals. The frequency and upper and lower limit voltages of the carrier signal can be determined according to the threshold voltage of the hysteresis comparator, the current of the current source, the charge and discharge parameters of the charge and discharge capacitor, and other related peripheral circuit parameters, and can be selected as needed in specific implementations.

[0107] It can be understood that, similar to Figure 5 the above circuit connection relationship is only an example, and the connection relationship of each device can be adjusted adaptively; the above carrier generation circuit is also only a simplified structure, and the circuit may include more or fewer devices than those shown in the figure, or combine some devices, or split some devices, or arrange different devices. For example, the hysteresis comparator can be provided with relevant peripheral circuits (such as resistors and voltage regulators, etc.) to improve the circuit performance. The specific structure of the carrier generation circuit in the embodiments of the present application is not particularly limited.

[0108] Figure 16 shows another possible implementation manner of the carrier generation circuit, Figure 16 In the illustrated carrier generator, the main difference between the carrier generation circuit and the carrier generation circuit in the foregoing Figure 5 illustrated embodiment is that in the carrier generation circuit, the square wave generation circuit is implemented by a hysteresis comparator, and the charge and discharge circuit is implemented by an integrator.

[0109] Exemplarily here, in the carrier generation circuit Carr1, the square wave generation circuit mainly includes a hysteresis comparator Cm1. The integrator includes an operational amplifier A1, a resistor R1, and a capacitor C1. The inverted input terminal of the hysteresis comparator Cm1 inputs a voltage signal V1. The non-inverted input terminal of the hysteresis comparator Cm1 is connected to the output terminal of the operational amplifier A1 (i.e., the output terminal of the charge and discharge circuit). The resistor R1 is connected between the output terminal of the hysteresis comparator Cm1 and the inverted input terminal of the operational amplifier A1. The capacitor C1 is connected between the inverted input terminal and the output terminal of the operational amplifier A1. The non-inverted input terminal of the operational amplifier A1 is grounded. In the carrier generation circuit Carr2, the square wave generation circuit mainly includes a hysteresis comparator Cm2. The integrator includes an operational amplifier A2, a resistor R2, and a capacitor C2. Its connection relationship is similar to that of the carrier generation circuit Carr1. The synchronization capacitor Cs is connected between the output terminals of the operational amplifier A1 and the operational amplifier A2.

[0110] Taking the carrier generation circuit Carr1 as an example, the input terminal of the integrator (i.e., the end where the resistor R1 is connected to the hysteresis comparator Cm1, which can also be called the control terminal of the integrator) can periodically charge and discharge the capacitor C1 according to the square wave signal output by the hysteresis comparator Cm1, so that the output terminal of the operational amplifier A1 outputs a triangular carrier signal. The working principle of the carrier generation circuit Carr2 is similar. The synchronization capacitor Cs can automatically promote the synchronization of the carrier signals Vc1 and Vc2 and keep the two carrier signals with a good waveform matching degree.

[0111] It can be understood that, similar to the above embodiments, the above circuit connection relationship is only an example, and the connection relationship of each device can be adjusted adaptively; the above carrier generation circuit is also only a simplified structure, and the circuit may include more or fewer devices than shown in the figure, or combine some devices, or split some devices, or arrange different devices. The embodiments of the present application do not particularly limit the specific structure of the carrier generation circuit.

[0112] In addition, it can be understood that the specific implementation manner of the carrier generation circuit is not limited to the above examples. In some embodiments, other circuit structures can also be used. The embodiments of the present application do not particularly limit the specific structure of the carrier generation circuit.

[0113] The carrier generator provided by the embodiment of the present application has a synchronous capacitor connected between the output ends of each carrier generation circuit, which can automatically promote the synchronization of the carrier signals output by each carrier circuit; and a feedback path can be established between each carrier generation circuit to interconnect the error signals between each carrier generation circuit and balance this error signal to each carrier generation circuit, so that even if there is a circuit mismatch in each carrier generation circuit, the output carrier signals can still maintain a good waveform matching degree. It can be seen that the carrier generator provided by the embodiment of the present application can improve the synchronization degree and waveform matching degree of the carrier signals.

[0114] Based on the same concept, the embodiment of the present application further provides a switching power supply, including: a PWM modulator and a power conversion circuit. The power conversion circuit is connected to the output end of the PWM modulator and is configured to output more than three switching signals according to the PWM signal output by the PWM modulator; wherein, the PWM modulator includes the carrier generator described in any of the above embodiments.

[0115] For the specific descriptions of the carrier generator, the PWM modulator, and the power conversion circuit, reference can be made to the relevant descriptions in the foregoing embodiments, and details are not described herein again.

[0116] The embodiment of the present application further provides an envelope tracking modulator, including: a linear power supply and the above-mentioned switching power supply. For the specific description of the envelope tracking modulator, reference can be made to the relevant descriptions in the foregoing embodiments, and details are not described herein again.

[0117] It should be understood that in the description of the specification and the appended claims of the present application, the terms "include", "comprise", "have" and any variations thereof are intended to cover non-exclusive inclusion, all meaning "including but not limited to", unless otherwise specifically emphasized in another way. For example, a process, method, system, product or device that includes a series of steps or modules does not necessarily have to be limited to those steps or modules clearly listed, but may include other steps or modules not clearly listed or inherent to these processes, methods, products or devices.

[0118] In the description of the present application, unless otherwise specified, " / " indicates that the objects associated before and after are in an "or" relationship. For example, A / B may represent A or B; the "and / or" in the present application is used to describe the association relationship of the associated objects and indicates that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. Here, A and B may be singular or plural.

[0119] Also, in the description of the present application, unless otherwise specified, "a plurality of" means two or more than two. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c may represent: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, c may be single or plural.

[0120] In addition, in the present application, unless otherwise clearly defined and limited, the terms "installed", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. Unless otherwise clearly limited, for those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0121] Furthermore, in the description of the specification and the appended claims of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments described here can be implemented in an order other than that illustrated or described here; the features defined with "first", "second" may explicitly or implicitly include at least one such feature.

[0122] In the embodiments of the present application, words such as "exemplarily" or "for example" are used to give examples, illustrations, or explanations. Any embodiment or design solution described as "exemplarily" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplarily" or "for example" is intended to present relevant concepts in a specific manner.

[0123] Reference to "one embodiment" or "some embodiments" etc. described in the specification of this application means that a specific feature, structure or characteristic described in connection with that embodiment is included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in some other embodiments", "in still some other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all of the embodiments", unless otherwise specifically emphasized in other ways. Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A carrier generator, characterized in that, Including: A plurality of carrier generation circuits for generating a plurality of triangular carrier signals with the same amplitude and phase; the plurality of carrier generation circuits include a first carrier generation circuit and a second carrier generation circuit, and a synchronization capacitor is connected between the output terminal of the first carrier generation circuit and the output terminal of the second carrier generation circuit.

2. The carrier generator according to claim 1, wherein There are a plurality of the second carrier generation circuits, a synchronization capacitor is connected between the output terminal of the first carrier generation circuit and the output terminals of at least one second carrier generation circuit, and a synchronization capacitor is connected between the output terminal of each second carrier generation circuit and the output terminals of at least one other second carrier generation circuit.

3. The carrier generator according to claim 2, wherein A synchronization capacitor is connected between the output terminal of the first carrier generation circuit and the output terminal of each second carrier generation circuit.

4. The carrier generator according to claim 2, wherein A synchronization capacitor is connected between the output terminal of the first carrier generation circuit and the output terminal of one of the second carrier generation circuits. According to the first connection sequence, synchronization capacitors are connected between the output terminals of adjacent second carrier generation circuits.

5. The carrier generator according to any one of claims 2-4, characterized in that, Each of the synchronization capacitors is the same.

6. The carrier generator according to any one of claims 1-5, characterized in that, The carrier generation circuit includes: a square wave generation circuit and a charge and discharge circuit, and the charge and discharge circuit is connected to the output terminal of the square wave generation circuit for generating a triangular carrier signal.

7. The carrier generator according to claim 6, wherein The square wave generation circuit includes: a first comparator, a second comparator and a latch. The first input terminal of the first comparator is used for inputting a first voltage, and the second input terminal of the second comparator is used for inputting a second voltage; the output terminal of the charge and discharge circuit is respectively connected to the second input terminal of the first comparator and the first input terminal of the second comparator. The output terminal of the first comparator is connected to the first input terminal of the latch, and the output terminal of the second comparator is connected to the second input terminal of the latch; the output terminal of the latch is connected to the control terminal of the charge and discharge circuit for controlling the charge or discharge of the charge and discharge circuit.

8. The carrier generator according to claim 6, characterized in that, The square wave generation circuit includes: a hysteresis comparator, the inverting input terminal of the hysteresis comparator is used for inputting a voltage signal, the non-inverting input terminal of the hysteresis comparator is connected to the output terminal of the charge and discharge circuit, and the output terminal of the hysteresis comparator is connected to the control terminal of the charge and discharge circuit for controlling the charge or discharge of the charge and discharge circuit.

9. The carrier generator according to any one of claims 6-8, characterized in that, The charge and discharge circuit includes: a first current source, a second current source and a charge and discharge capacitor. The first current source is connected to the first end of the charge and discharge capacitor through a first switch for charging the charge and discharge capacitor. The second current source is connected to the first end of the charge and discharge capacitor through a second switch for discharging the charge and discharge capacitor. The second end of the charge and discharge capacitor is grounded. The output terminal of the square wave generation circuit is respectively connected to the control terminals of the first switch and the second switch, and the square wave generation circuit is used for controlling the first switch to conduct and the second switch to turn off when the charge and discharge capacitor is charging; and controlling the first switch to turn off and the second switch to conduct when the charge and discharge capacitor is discharging.

10. The carrier generator according to any one of claims 6-8, characterized in that, The charge and discharge circuit is an integrating circuit.

11. The carrier generator according to any one of claims 6-10, characterized in that, The synchronization capacitor is the same as the charge and discharge capacitor of the charge and discharge circuit in each of the carrier generation circuits.

12. A switching power supply, characterized in that, Comprising: a PWM modulator and a power conversion circuit, the power conversion circuit being connected to the output end of the PWM modulator and configured to output more than three kinds of switching signals according to the PWM signal output by the PWM modulator; wherein, the PWM modulator comprises a carrier generator as described in any one of claims 1-11.

13. An envelope tracking modulator, characterized in that, Comprising: a linear power supply and a switching power supply as described in claim 12.

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