Digital-to-analog converter, chip and computing device

Abstract

The invention provides a digital-to-analog converter, a chip and computing equipment, and the digital-to-analog converter comprises a data generation module which is used for generating a shadow signal and an effective signal according to an input original digital signal, and the shadow signal maintains the current data when the effective signal is overturned, and is overturned when the effective signal is maintained; the first operation logic module is used for carrying out operation on the effective signal; the second arithmetic logic module is used for carrying out operation on the shadow signal, and the second arithmetic logic module and the first arithmetic logic module share a power supply; and the digital-to-analog conversion module is used for carrying out digital-to-analog conversion on the operated effective signal so as to output an analog signal. The invention provides a scheme capable of eliminating harmonic distortion caused by data-related power supply noise.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a digital-to-analog converter, a chip and a computing device. Background Art

[0002] With the development of wireless communication needs, the digital to analog converter (DAC) used in wireless communication technology requires higher and higher accuracy and speed. DAC will convert the original digital signal into the corresponding voltage and current analog quantity through various processing operations. Figure 1 , the original digital signal will pass through various digital logics, and each digital logic usually has its own corresponding digital power supply.

[0003] However, how to eliminate the harmonic distortion caused by data-related power supply noise is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present application provides a solution capable of eliminating harmonic distortion caused by data-related power supply noise.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] In a first aspect, a digital-to-analog converter is provided, which includes: a data generation module, which is used to generate a shadow signal and a valid signal according to an input original digital signal, wherein the shadow signal maintains current data when the valid signal is flipped, and flips when the valid signal is maintained; a first operation logic module, which is used to operate on the valid signal; a second operation logic module, which is used to operate on the shadow signal, and the second operation logic module and the first operation logic module share a power supply; and a digital-to-analog conversion module, which is used to perform digital-to-analog conversion on the valid signal after operation to output an analog signal.

[0007] Optionally, a signal flips in each cycle of the clock signal, and the signal is the shadow signal or the valid signal.

[0008] Optionally, the data generation module includes: a judgment unit, used to judge whether the original digital signal within two adjacent clock signal cycles is flipped, and output the judgment result; and a flipping unit, used to determine whether to flip the shadow signal within the current clock signal cycle based on the judgment result.

[0009] Optionally, the judgment unit includes: a first delay subunit, an input end of the first delay unit being connected to the original digital signal, and an output end of the first delay unit outputting the first digital signal delayed by one clock signal cycle; a second delay subunit, an input end of the second delay unit being coupled to the output end of the first delay unit, and an output end of the second delay unit outputting the second digital signal delayed by two clock signal cycles; an XOR logic gate, an input end of the XOR logic gate being coupled to the output end of the first delay unit and the output end of the second delay unit, and the XOR logic gate being used to perform an XOR operation on the first digital signal and the second digital signal to output a selection signal, wherein the selection signal represents the judgment result.

[0010] Optionally, the flip unit includes: a flip subunit, a first input end of the flip subunit is connected to the shadow signal, a second input end of the flip subunit is connected to the flipped shadow signal, and the flip subunit selects to output the shadow signal or the flipped shadow signal according to the judgment result; and a third delay subunit, an input end of the third delay unit is coupled to the output end of the flip subunit.

[0011] Optionally, the second delay subunit outputs the valid signal, and the third delay unit outputs the shadow signal.

[0012] Optionally, the judgment unit also includes: a fourth delay sub-unit, the input end of the fourth delay sub-unit is coupled to the output end of the second delay unit, and the output end of the fourth delay sub-unit outputs the valid signal; the flip unit also includes: a fifth delay sub-unit, the input end of the fifth delay sub-unit is coupled to the output end of the third delay unit, and the output end of the fifth delay sub-unit outputs the shadow signal.

[0013] Optionally, there are multiple first operation logic modules and multiple second operation logic modules, the multiple first operation logic modules have a corresponding relationship with the multiple second operation logic modules, and the first operation logic modules and second operation logic modules with the corresponding relationship share the same power supply.

[0014] In a second aspect, the present application further provides a computing device, which includes the digital-to-analog converter of the first aspect.

[0015] In a third aspect, the present application further provides a chip, comprising the digital-to-analog converter of the first aspect.

[0016] In a fourth aspect, an embodiment of the present application further provides a system chip for use in a terminal, wherein the chip system includes at least one processor, an interface circuit, and the digital-to-analog converter of the first aspect.

[0017] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0018] In the technical solution of the present application, the digital-to-analog converter includes a data generation module, which is used to generate a shadow signal and a valid signal according to the input original digital signal, the shadow signal maintains the current data when the valid signal flips, and flips when the valid signal is maintained; a first operation logic module, which is used to operate on the valid signal; a second operation logic module, which is used to operate on the shadow signal, and the second operation logic module and the first operation logic module share a power supply; a digital-to-analog conversion module, which is used to perform digital-to-analog conversion on the effective signal after the operation to output an analog signal. The technical solution of the present application generates a shadow signal by setting a data generation module, and setting a second logic module to operate the shadow signal. The shadow signal and the valid signal have data flipping in each beat (that is, in each clock signal cycle), so that the power supply network generates power supply noise (that is, burrs) in each beat, and the establishment delay of each beat of data is equal, and the waveform distortion caused by the establishment error is no longer related to the data, thereby eliminating the data-related harmonic distortion.

[0019] Furthermore, the data generation module includes a judgment unit for judging whether the original digital signal in two adjacent clock signal cycles is flipped and outputting the judgment result; a flip unit for determining whether to flip the shadow signal in the current clock signal cycle according to the judgment result. The technical solution of the present application can judge whether the original digital signal is flipped in two adjacent clock signal cycles, that is, whether the signal value changes, through the judgment unit; the flip unit is used to determine whether the shadow signal is flipped according to whether the original digital signal is flipped, thereby ensuring that one of the valid signal and the shadow signal is flipped in each clock signal cycle, thereby eliminating data-related power supply noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural schematic diagram of an analog-to-digital converter in the prior art;

[0021] Figure 2 It is a schematic diagram of a DAC structure with N-bit binary weight in the prior art;

[0022] Figure 3 It is a signal timing diagram in the prior art;

[0023] Figure 4 It is a schematic diagram of a simulation quantity establishment step in the prior art;

[0024] Figure 5 It is a data spectrum schematic diagram in the prior art;

[0025] Figure 6is a structural schematic diagram of an analog-to-digital converter provided in an embodiment of the present application;

[0026] Figure 7 is a signal timing diagram provided by an embodiment of the present application;

[0027] Figure 8 It is a specific structural diagram of a data generation module provided in an embodiment of the present application;

[0028] Figure 9 is a specific structural diagram of another data generation module provided in an embodiment of the present application;

[0029] Figure 10 is another signal timing diagram provided in an embodiment of the present application;

[0030] Figure 11 It is a schematic diagram of the structure of another analog-to-digital converter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] As described in the background art, if a terminal device communicates with the above-mentioned network device that only supports the receiving function, there is currently no specific solution for how the terminal device performs uplink transmission with the network device.

[0032] Specifically, a basic N-bit binary weighted DAC structure is as follows: Figure 2 , each bit of the original digital signal D[N-1:0] controls the switch of the corresponding weight and determines the superposition of the corresponding analog quantity. In high-speed and high-precision DAC, in order to reduce the sensitivity of the high-weight bit of the binary-weighted DAC structure to circuit mismatch and reduce differential nonlinearity (DNL), a thermometer decoding method is usually introduced into the original digital signal path, and the number of "1" in the decoding is used to represent the size of the original code. In this way, the length of the N-bit binary code after decoding is 2 N -1. Thermometer decoding can be applied to the entire code element or only to the high-bit codeword to form segmented decoding. For example, a 14-bit DAC uses 6+8 segmented decoding, the upper 6 bits are translated into 63-bit thermometer code, and the lower 8 bits remain binary code, so that the 14-bit data becomes 71 bits, greatly increasing the scale of the logic in the original digital signal path to about 5 times the original. Larger-scale digital logic means greater instantaneous power consumption and a larger area of ​​the power supply network, both of which make the impedance of the power supply network more prominent, and the power supply network cannot be regarded as an ideal network with zero resistance.

[0033] When data is switched, the power supply needs to charge and discharge the logic node capacitor. The instantaneous charging current passing through the non-ideal power network will produce a larger power line voltage drop (IR Drop), which can also be called resistance voltage drop. Figure 3As shown in the figure, when the differential positive data Datap and the reverse data Datan are switched, a glitch will be generated on the power supply Power, that is, an instantaneous power line voltage drop. The fluctuation on the power supply will directly affect the delay of data establishment. Generally speaking, the greater the power supply voltage drop, the smaller the driving ability of the transistor, and thus the greater the establishment delay. Since the data controls the switch on and off, the delay on the data will be directly reflected in the output analog quantity, such as Figure 4 The ideal simulation step is as follows Figure 4 As shown in waveform 1, the actual setup process is an exponential curve of capacitor charging and discharging. Waveform 2 is the case of low delay, and waveform 3 is the case of high delay. At the same time t, the setup errors of different delay conditions relative to the ideal condition are different. The setup error 1 of the low delay step is usually smaller than the setup error 2 of the high delay step.

[0034] The waveform distortion caused by the above-mentioned setup error is data-dependent and appears as harmonic distortion on the spectrum. Figure 5 As shown in the figure, the original data is a sinusoidal signal. The larger the difference between adjacent data, the more data bits are flipped, and the corresponding power supply voltage drop is larger. The end of the establishment is the moment when the next data jump is about to begin. The larger the difference between adjacent data, the larger the establishment error. The difference between adjacent data is the derivative of the original data, so it is a sinusoidal signal with the same frequency as the original data. Since the relationship between the difference between adjacent data, the power line voltage drop and the establishment error is not completely linear, the establishment error will contain multiple frequency components related to the original data, causing harmonic distortion.

[0035] In traditional designs, the solution to power network fluctuations is to use wider and denser metal wires to reduce resistance, so that the instantaneous power line voltage drop is smaller under the same instantaneous current; or to increase the decoupling capacitor on the power network and use the charge stored in the capacitor to compensate for the transient current during logic switching.

[0036] However, the method of increasing line width and density can only suppress but not eliminate the data-related harmonics on the power supply. Design rules limit the metal line width and density, and there will always be weak points in the power supply network in high-speed and large-scale digital logic, and the suppression effect is limited. With the development of process technology, the density of transistors on the chip continues to increase, the chip area is getting smaller and smaller, the density and current density of devices are getting larger and larger, and the improvement of capacitance value is less affected by process improvement. Limited by the area cost of on-chip capacitors, there is limited room for increasing decoupling capacitors.

[0037] The technical solution of the present application generates a shadow signal by setting a data generation module, and sets a second logic module to operate on the shadow signal. The shadow signal and the valid signal are flipped in each beat (that is, in each clock signal cycle), so that the power supply network generates power supply noise (that is, burrs) in each beat. The establishment delay of each beat of data is equal, and the waveform distortion caused by the establishment error is no longer related to the data, thereby eliminating the data-related harmonic distortion.

[0038] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0039] See also Figure 6 The digital-to-analog converter provided in the present application specifically includes a data generation module 601 , a first operation logic module 602 , a second operation logic module 603 and a digital-to-analog conversion module 604 .

[0040] The data generating module 601 is used to generate a shadow signal and a valid signal according to the input original digital signal.

[0041] The first operation logic module 602 inputs a valid signal to the input terminal, and the first operation logic module 602 operates on the valid signal. Correspondingly, the second operation logic module 603 inputs a shadow signal to the input terminal, and the first operation logic module 602 operates on the shadow signal. The first operation logic module 602 and the second operation logic module 603 share a power supply VDD1.

[0042] The digital-to-analog conversion module 604 is used to perform digital-to-analog conversion on the effective signal after operation to output an analog signal.

[0043] In a specific implementation, a signal flipping indicates that the value of the signal changes. For example, for a digital signal, a signal value changing from 1 to 0, or from 0 to 1, both indicate that the signal flips. Accordingly, a flipping of an effective signal may specifically mean that the value of the effective signal changes from 1 to 0, or from 0 to 1; a flipping of a shadow signal may specifically mean that the value of the effective signal changes from 1 to 0, or from 0 to 1.

[0044] Compared with the prior art which has only one data path, the present embodiment includes a data path for the effective signal and a data path for the shadow signal. Since the shadow signal maintains the current data when the effective signal flips, and flips when the effective signal is maintained, a signal flips in each cycle of the clock signal.

[0045] Furthermore, since the power supply VDD1 needs to charge and discharge the capacitor of the logic module when the signal flips, the instantaneous charging current will generate a larger power line voltage drop through the non-ideal power network, which appears as a burr on the power supply.

[0046] Refer to Figure 7 , the effective signal is a differential signal, specifically including differential positive data Datap and negative data Datan. Correspondingly, the shadow signal is also a differential signal, specifically including differential positive data Shadowp and negative data Shadown. Figure 7 Each two vertical dashed lines represent a clock signal cycle.

[0047] from Figure 7 It can be seen that the shadow signal holds the current data when the valid signal flips, and flips when the valid signal is maintained. In each cycle of the clock signal, the valid signal or the shadow signal flips. Then, it can be seen from the signal timing of the power supply Power that the signal of the power supply Power has glitches in each clock signal cycle. In other words, the glitches of each beat on the power supply network are almost equal, and the establishment delay of each beat of data is also equal. The waveform distortion caused by the establishment error is no longer related to the data, thereby eliminating the data-related harmonic distortion.

[0048] Furthermore, the shadow signal generation logic of the embodiment of the present application is relatively independent from the data path of the effective signal, has little impact on the logic of the entire digital signal processing system, and is faster in design verification.

[0049] Furthermore, the implementation scheme of the embodiment of the present application is flexible, and the data generation module 601 can be deployed at various nodes of the data path, and the balancing effect can be achieved as long as it is set before the logic node driving the DAC switch.

[0050] Furthermore, compared with the prior art of adding decoupling capacitors, the embodiment of the present application uses digital logic to eliminate data-related harmonic distortion, which can take into account the area of ​​the chip where the digital-to-analog converter is located. That is, data-related harmonic distortion can be eliminated in a smaller chip area.

[0051] In addition, the analog-to-digital converter of the embodiment of the present application has low correlation with the process and higher portability.

[0052] In a non-limiting embodiment, the signal generating module 601 may include a determination unit and a flipping unit.

[0053] In this embodiment, the judging unit is used to judge whether the original digital signal in two adjacent clock signal cycles is flipped and output the judgment result. The flipping unit is used to determine whether to flip the shadow signal in the current clock signal cycle according to the judgment result.

[0054] Specifically, the determination result can indicate whether the original digital signal flips within two adjacent clock signal cycles. If so, the flipping unit flips the shadow signal in the current clock signal cycle; otherwise, the flipping unit maintains the shadow signal in the current clock signal cycle and outputs it.

[0055] Please refer to Figure 8 , Figure 8 which shows a specific structure of the signal generation module 601.

[0056] Specifically, the determination unit includes a first delay sub-unit DFF1, a second delay sub-unit DFF2, and an exclusive-OR logic gate XOR.

[0057] The flipping unit includes a flip sub-unit and a third delay sub-unit DFF3.

[0058] In this embodiment, the first delay sub-unit DFF1 can delay the original digital signal Data by one clock signal cycle to obtain a first digital signal DataFF1. The second delay sub-unit DFF2 delays the first digital signal DataFF1 by one clock signal cycle to obtain a second digital signal DataFF2. Among them, the second digital signal DataFF2 is output as a valid signal.

[0059] Furthermore, the first digital signal DataFF1 and the second digital signal DataFF2 are two inputs of the exclusive-OR logic gate XOR. When the first digital signal DataFF1 and the second digital signal DataFF2 are the same, the selection signal SEL output by the exclusive-OR logic gate XOR is 0; when the first digital signal DataFF1 and the second digital signal DataFF2 are different, the selection signal SEL output by the exclusive-OR logic gate XOR is 1. The selection signal SEL can represent the determination result of whether the original digital signal flips within two adjacent clock signal cycles.

[0060] Specifically, the flip sub-unit can include a selector and an inverter. The input terminal of the inverter is connected to the shadow signal shadow, and the output terminal of the inverter is coupled to one input terminal of the selector for outputting the flipped shadow signal; the other input terminal of the selector is connected to the shadow signal shadow, and the output terminal of the selector outputs a signal ShadPre. When the selection signal SEL is 1, the selector selects to output the shadow signal shadow; when the selection signal is 0, the selector selects to output the flipped shadow signal.

[0061] Since the determination unit determines whether the original digital signal of the next clock signal cycle flips, after the flip sub-unit flips the shadow signal of the current clock signal cycle, it needs to be delayed by one clock signal cycle (i.e., through the third delay sub-unit DFF3) for output.

[0062] Specifically, the first delay sub-unit DFF1, the second delay sub-unit DFF2, and the third delay sub-unit DFF3 can be D flip-flops or any other implementable delay devices, and the present application does not limit this.

[0063] Please refer to Figure 9 , Figure 9 which shows another specific structure of the signal generation module 601.

[0064] Different from the structure of the signal generation module 601 shown in Figure 8 the signal generation module 601 in the embodiment of the present application further includes a fourth delay sub-unit DFF4 and a fifth delay sub-unit DFF5.

[0065] Among them, the input end of the fourth delay sub-unit DFF4 is coupled to the output end of the second delay unit DFF2, and the output end of the fourth delay sub-unit DFF4 outputs a valid signal MainData. That is to say, the fourth delay sub-unit DFF4 is used to delay the second digital signal DataFF2 by one clock signal period.

[0066] Correspondingly, for the fifth delay sub-unit DFF5, the input end of the fifth delay sub-unit DFF5 is coupled to the output end of the third delay unit DFF3, and the output end of the fifth delay sub-unit DFF5 outputs a shadow signal Shadow.

[0067] Taking Figure 9 the structure of the signal generation module 601 shown as an example, Figure 10 it shows the timing of each signal in the digital-to-analog converter under this structure.

[0068] Among them, CLK represents the clock signal, Next Shad represents whether to flip the shadow signal Shadow, SB represents no flip, and S represents flip.

[0069] From Figure 10 it can be seen that in each beat, only one of the shadow signal Shadow and the second digital signal DataFF2 is in a flipped state.

[0070] In the above embodiment, the functions of the first arithmetic logic module 602 and the second arithmetic logic module 603 are the same, and their structures can also be the same. The difference is their input signals (that is, the valid signal and the shadow signal).

[0071] Further, the number of the first operation logic modules and the second operation logic modules can be multiple, and there is a corresponding relationship between the multiple first operation logic modules and the multiple second operation logic modules. The first operation logic module and the second operation logic module with the corresponding relationship share the same power supply. The first operation logic module and the second operation logic module with the corresponding relationship have the same function and can also have the same structure. The multiple first operation logic modules are connected in series with each other, and the multiple second operation logic modules are connected in series with each other.

[0072] For details, please refer to Figure 11 , the digital-to-analog converter includes n logic modules, that is, n first operation logic modules and n second operation logic modules, where n is a positive integer greater than or equal to 1.

[0073] Specifically, the first operation logic module 6021 and the second operation logic module 6031 have the same function and result, and both share the power supply VDD1. Correspondingly, the first operation logic module 602n and the second operation logic module 603n have the same function and result, and both share the power supply VDDn.

[0074] The output end of the first operation logic module 602n is coupled to the input end of the digital-to-analog conversion module 604.

[0075] It should be noted that the first operation logic module 602 and the second operation logic module 603 can be any implementable functional modules, such as modulation modules, filtering modules, amplitude detection modules, amplification modules, reduction modules, etc., and can be adaptively adjusted according to the actual application scenario. The present application does not limit this.

[0076] It should be noted that the output end of the data generation module 601 can be coupled to any one of the n operation logic modules. For example, the two output ends of the data generation module can be respectively coupled to the first operation logic module 602n and the second operation logic module 603n. The present application does not limit this.

[0077] For more specific implementation manners of the embodiments of the present application, please refer to the foregoing embodiments, and details are not described herein again.

[0078] In a non-limiting embodiment, the above digital-to-analog converter can be used in any suitable hardware device, such as a chip, such as an SOC, a baseband chip, etc., a chip module or a computing device.

[0079] Other related descriptions of the above hardware device can be referred to the prior art, and details are not described herein again.

[0080] Regarding each device and product described in the above embodiments, each module / unit included therein can be a software module / unit, a hardware module / unit, or can be partially a software module / unit and partially a hardware module / unit. For example, for each device and product applied to or integrated into a chip, each module / unit included therein can be implemented in the form of hardware such as circuits, or at least some of the modules / units can be implemented in the form of a software program that runs on a processor integrated inside the chip, and the remaining (if any) part of the modules / units can be implemented in the form of hardware such as circuits; for each device and product applied to or integrated into a chip module, each module / unit included therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (such as a chip, a circuit module, etc.) or different components of the chip module, or at least some of the modules / units can be implemented in the form of a software program that runs on a processor integrated inside the chip module, and the remaining (if any) part of the modules / units can be implemented in the form of hardware such as circuits; for each device and product applied to or integrated into a terminal device, each module / unit included therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (such as a chip, a circuit module, etc.) or different components inside the terminal device, or at least some of the modules / units can be implemented in the form of a software program that runs on a processor integrated inside the terminal device, and the remaining (if any) part of the modules / units can be implemented in the form of hardware such as circuits.

[0081] It should be understood that the term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article indicates that the objects before and after are in an "or" relationship.

[0082] The term "a plurality of" that appears in the embodiments of this application refers to two or more.

[0083] The descriptions such as first and second that appear in the embodiments of this application are only for schematic and differentiating the described objects, without an order, nor do they represent a special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation to the embodiments of this application.

[0084] The term "connection" that appears in the embodiments of this application refers to various connection methods such as direct connection or indirect connection to achieve communication between devices, and this application does not make any limitation thereto.

[0085] The above embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired or wireless manner.

[0086] It should be understood that in various embodiments of the present application, the sequence numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0087] In several embodiments provided in the present application, it should be understood that the disclosed methods, devices, and systems can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings, direct couplings, or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0088] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0089] In addition, in each embodiment of the present application, the functional units can be integrated into one processing unit, or each unit can be physically included separately, or two or more units can be integrated into one unit. The above integrated units can be implemented in the form of hardware or in the form of a combination of hardware and software functional units.

[0090] The integrated unit implemented in the form of software functional units can be stored in a computer-readable storage medium. The above-mentioned software functional units are stored in a storage medium and include several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute some steps of the methods described in various embodiments of the present application.

[0091] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A digital-to-analog converter, characterized in that, Comprising: A data generation module, configured to generate a shadow signal and a valid signal according to an input original digital signal, where the shadow signal maintains the current data when the valid signal flips and flips when the valid signal remains unchanged; A first arithmetic logic module, configured to perform arithmetic operations on the valid signal; A second arithmetic logic module, configured to perform arithmetic operations on the shadow signal, and the second arithmetic logic module and the first arithmetic logic module share a power supply; A digital-to-analog conversion module, configured to perform digital-to-analog conversion on the arithmetic operation result of the valid signal to output an analog signal.

2. The digital-to-analog converter according to claim 1, wherein In each cycle of the clock signal, a signal flips, and the signal is the shadow signal or the valid signal.

3. The digital-to-analog converter according to claim 1, characterized in that The data generation module includes: a judgment unit, configured to judge whether the original digital signal flips in two adjacent clock signal cycles and output a judgment result; A flip unit, configured to determine whether to flip the shadow signal in the current clock signal cycle according to the judgment result.

4. The digital-to-analog converter according to claim 3, characterized in that, The judgment unit includes: A first delay sub-unit, where the input end of the first delay unit is connected to the original digital signal, and the output end of the first delay unit outputs a first digital signal delayed by one clock signal cycle; A second delay sub-unit, where the input end of the second delay unit is coupled to the output end of the first delay unit, and the output end of the second delay unit outputs a second digital signal delayed by two clock signal cycles; An exclusive-OR logic gate, where the input ends of the exclusive-OR logic gate are coupled to the output end of the first delay unit and the output end of the second delay unit, and the exclusive-OR logic gate is configured to perform an exclusive-OR operation on the first digital signal and the second digital signal to output a selection signal, and the selection signal represents the judgment result.

5. The digital-to-analog converter according to claim 4, wherein The flip unit includes: A flip sub-unit, where the first input end of the flip sub-unit is connected to the shadow signal, the second input end of the flip sub-unit is connected to the flipped shadow signal, and the flip sub-unit selects to output the shadow signal or the flipped shadow signal according to the judgment result; A third delay sub-unit, where the input end of the third delay unit is coupled to the output end of the flip sub-unit.

6. The digital-to-analog converter according to claim 5, characterized in that The second delay sub-unit outputs the valid signal, and the third delay unit outputs the shadow signal.

7. The digital-to-analog converter according to claim 5, wherein The judgment unit further includes: A fourth delay sub-unit, where the input end of the fourth delay sub-unit is coupled to the output end of the second delay unit, and the output end of the fourth delay sub-unit outputs the valid signal; The flip unit further includes: A fifth delay sub-unit, where the input end of the fifth delay sub-unit is coupled to the output end of the third delay unit, and the output end of the fifth delay sub-unit outputs the shadow signal.

8. The digital-to-analog converter according to claim 1, wherein The number of the first arithmetic logic modules and the second arithmetic logic modules is multiple, and multiple first arithmetic logic modules and multiple second arithmetic logic modules have a corresponding relationship, and the first arithmetic logic module and the second arithmetic logic module with a corresponding relationship share the same power supply.

9. A computing device, characterized in that, Comprising the digital-to-analog converter according to any one of claims 1 to 8.

10. A chip, characterized in that, Comprising the digital-to-analog converter according to any one of claims 1 to 8.

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