High-bit-rate QC-LDPC check matrix construction method and device for NAND, medium and product

Abstract

The invention discloses a high-code-rate QC-LDPC check matrix construction method and device for NAND, a medium and a product, and relates to the technical field of channel coding, and the method comprises the steps: firstly, generating an initial check matrix which is uniform in row weight distribution and is free of a four-ring structure; secondly, traversing a preset shift value range for each non-zero item of the initial check matrix, and selecting a shift value which enables the number of six rings to be minimum to generate an intermediate check matrix; and finally, based on the number of the six rings in which each non-zero item participates in the intermediate check matrix, sequentially eliminating the non-zero items participating in the most six rings to obtain a target check matrix. According to the method, the four-ring, six-ring and global balance is progressively optimized, so that the error correction performance of the check matrix is remarkably improved, the decoding time delay is reduced, and the reliability requirement of a high-bit-rate NAND flash memory is met.

Description

Technical Field

[0001] This application relates to the technical field of channel coding, and particularly to a method, device, medium and product for constructing a high code rate QC-LDPC parity-check matrix for NAND. Background Art

[0002] With the improvement of the storage density of NAND flash memory, high code rate QC-LDPC codes have become the core error correction solution due to their error correction ability and hardware friendliness. However, in the prior art, the construction of high code rate QC-LDPC parity-check matrices faces two major challenges: First, in high code rate scenarios, the parity-check matrix is prone to short cycle structures such as four-cycles and six-cycles, forming "trap sets", which hinder decoding convergence and reduce error correction performance; Second, uneven row weight distribution leads to a decrease in the stability of the normalized min-sum decoding algorithm, affecting decoding efficiency. In addition, existing methods lack systematicness in optimizing short cycles and it is difficult to balance the requirements of high code rate and low complexity.

[0003] Therefore, there is an urgent need for a method for constructing a high code rate QC-LDPC parity-check matrix suitable for NAND flash memory, which can effectively eliminate four-cycle structures, minimize the number of six-cycles and achieve uniform row weight distribution. Summary of the Invention

[0004] This application provides a method, device, medium and product for constructing a high code rate QC-LDPC parity-check matrix for NAND, so as to solve the problem that the existing solutions cannot systematically eliminate short cycles and destroy the uniform row weight in high code rate scenarios.

[0005] This application provides a method for constructing a high code rate QC-LDPC parity-check matrix for NAND, and the method includes: Generating an initial parity-check matrix; the row weights of the initial parity-check matrix are uniformly distributed and there are no four-cycle structures; For each non-zero term of the initial parity-check matrix, traversing a preset range of shift values, selecting the shift value that minimizes the number of six-cycles to generate an intermediate parity-check matrix; Based on the number of six-cycles participated by each non-zero term in the intermediate parity-check matrix, sequentially eliminating the non-zero terms with the largest number of six-cycles participated to obtain a target parity-check matrix.

[0006] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above methods for constructing a high code rate QC-LDPC parity-check matrix for NAND when executing the computer program.

[0007] This application also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above methods for constructing a high code rate QC-LDPC parity-check matrix for NAND are implemented.

[0008] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned high code rate QC-LDPC check matrix construction methods for NAND when executed by a processor.

[0009] Through the present application, based on the progressive three-step construction method, the performance and hardware adaptability of the high code rate QC-LDPC check matrix are systematically optimized. First, an initial check matrix with a uniform row weight distribution and no four-cycle structure is generated. By equalizing the number of non-zero terms in each row, the parameter adaptation instability of the decoding algorithm is avoided, and at the same time, the four-cycle closed paths are eliminated to block the information transfer conflict, improving the decoding convergence speed and error correction reliability. Secondly, the non-zero term shift values of the initial check matrix are traversed and the configuration with the fewest six-cycles is selected to generate an intermediate check matrix, which significantly reduces the six-cycle density in a column-by-column local optimization manner, avoiding the high complexity of global search, and at the same time maintaining the uniform row weight of the initial matrix. Finally, based on the priority of the number of non-zero terms participating in six-cycles in the intermediate check matrix, the high-frequency six-cycle terms are sequentially eliminated to generate the target check matrix, which directionally breaks the remaining trap sets and disperses the elimination operation positions, reducing the global short-cycle number while maintaining the row weight balance. Finally, the collaborative optimization of the check matrix among error correction performance, decoding stability and hardware complexity is realized, meeting the core requirements of NAND flash memory for high reliability, low latency and low power consumption in high code rate scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 It is a schematic flowchart of a method for constructing a high code rate QC-LDPC check matrix for NAND provided by an embodiment of the present application; Figure 2 It is a schematic flowchart of a method for constructing a high code rate QC-LDPC code check matrix applicable to NAND flash memory provided by an embodiment of the present application; Figure 3 It is a schematic flowchart of a method for eliminating non-zero term elements of an intermediate check matrix provided by an embodiment of the present application; Figure 4 It is a schematic diagram of the total number of six-cycles of three check matrices provided by an embodiment of the present application; Figure 5 It is a schematic diagram of the decoding result of the bit error rate of three check matrices provided by an embodiment of the present application; Figure 6Schematic diagram of the frame error rate decoding results of three parity check matrices provided by the embodiments of the present application; Figure 7 Schematic diagram of the structure of a high code rate QC-LDPC parity check matrix construction device for NAND provided by the embodiments of the present application; Figure 8 Schematic diagram of the structure of a computer device provided by the embodiments of the present application. Detailed implementation manners

[0012] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0013] It should be noted that in the description of the present application, the terms "including", "comprising" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0014] In order to enable those skilled in the art of the present technology to better understand the solutions of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0015] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the high code rate QC-LDPC parity check matrix construction method for NAND depends, the specific application environment architecture or specific hardware architecture will be described herein.

[0016] With the rapid increase in the storage density of NAND flash memory, especially the widespread application of 3D stacking technology (such as TLC and QLC), the reduction in the size of storage cells and the increase in the number of stacking layers have led to a significant increase in internal noise, and the bit error rate has increased accordingly. Quasi-cyclic low-density parity check (QC-LDPC) code has become the core solution for NAND flash error correction coding due to its good error correction performance and hardware friendliness. However, in the high code rate (>0.8) scenario, the construction of the check matrix of the existing QC-LDPC code faces severe challenges: on the one hand, the high code rate requires a significant increase in the proportion of information bits in the check matrix, resulting in a sparse matrix structure. Short loops such as four-loops and six-loops are very likely to form "trap sets", which hinder the information transmission between variable nodes and check nodes during the decoding process, extend the number of iterations and reduce the error correction capability; on the other hand, traditional construction methods (such as random generation and heuristic optimization) are difficult to take into account both short loop elimination and row weight uniformity. Uneven row weight distribution will cause an adaptation imbalance of the normalization factor in the decoding algorithm, further exacerbating the fluctuation of decoding performance.

[0017] In the prior art, although the progressive edge growth (PEG) method can construct a basis matrix without short cycles, it lacks systematic optimization of cyclic shift values ​​and cannot effectively solve the problem of hidden short cycles generated by cyclic shifts in QC-LDPC codes. In addition, the number of non-zero items in the check matrix in high-code rate scenarios needs to be strictly controlled to reduce hardware complexity, but the existing methods often destroy the row weight distribution or introduce new short cycles when eliminating non-zero items, making it difficult to achieve both performance and efficiency. For example, some schemes reduce short cycles by randomly eliminating non-zero items, but this increases the standard deviation of row weights and affects decoding stability; other schemes use global search to optimize shift values, which can reduce the density of short cycles, but the computational complexity is extremely high and it is difficult to adapt to the real-time requirements of NAND flash memory.

[0018] Therefore, there is an urgent need for a high-rate QC-LDPC check matrix construction method for NAND flash memory, which can systematically eliminate short ring structures such as four-ring and six-ring structures, strictly maintain uniform distribution of row weights, and achieve an optimal balance between the number of non-zero items and hardware complexity, thereby meeting the stringent requirements of 3D TLC / QLC NAND flash memory for high reliability, low latency and low power consumption.

[0019] Therefore, an embodiment of the present application provides a method for constructing a high-rate QC-LDPC check matrix for NAND, and describes the method in detail in conjunction with the execution flow of the method for constructing a high-rate QC-LDPC check matrix for NAND.

[0020] First, the terms involved in this application are introduced.

[0021] NAND: NAND flash, a non-volatile storage medium; LDPC (Low Density Parity Check Code): Low Density Parity Check Code; QC-LDPC (Quasi-cyclic LDPC): Quasi-cyclic Low Density Parity Check Code; PEG (Progressive Edge-Growth): Progressive Edge Growth; AWGN (Additive White Gaussian Noise): Additive White Gaussian Noise; LLR value (Log Likelihood Ratio): Log Likelihood Ratio; RLMS (Row Layered Normalized Min-Sum): Row Layered Normalized Min-Sum.

[0022] Embodiments of the present application provide a method for constructing a high code rate QC-LDPC parity check matrix for NAND. The specific process of this method is as Figure 1 shown and specifically includes the following steps.

[0023] S101. Generate an initial parity check matrix.

[0024] Specifically, in step S101, the initial parity check matrix is the starting matrix of the construction process and the starting point of the entire construction process. Its structure needs to meet two core conditions: uniform distribution of row weights and no four-cycle structure. As the basis for subsequent optimization, the balance and short-cycle-free characteristics of the initial matrix provide a reliable starting point for improving the performance of the intermediate and target matrices. If the initial matrix has uneven row weights or a four-cycle structure, it may be difficult to achieve global optimality in subsequent optimization due to basic defects.

[0025] The row weight refers to the number of non-zero terms in a row of the parity check matrix. For example, if a row contains 5 non-zero terms, its row weight is 5. The realization of uniform distribution is to make the number of non-zero terms in each row as close as possible when constructing the initial matrix. For example, the row weights of all rows are controlled between 4 and 6 (the specific values are determined by the code rate requirements), rather than some rows having only 2 non-zero terms and other rows having up to 10 non-zero terms.

[0026] The row weight has a great impact on decoding. Decoding algorithms (such as the min-sum algorithm) need to process parity check equations row by row. Uniform row weights can avoid some rows becoming computational bottlenecks due to too many non-zero terms and improve the hardware parallel efficiency. Moreover, decoding parameters such as the normalization factor are usually related to the row weight. Excessive differences in row weights will lead to difficulties in parameter adaptation and affect the convergence stability.

[0027] A four-cycle is a closed loop formed by four non-zero terms, and its path is as follows: starting from a certain variable node, after passing through two check nodes and two variable nodes, it returns to the starting point, forming a rectangular closed path. During the iterative decoding process, four-cycles will cause repeated conflicts of information between variable nodes and check nodes, hindering the transmission of reliable information. The existence of four-cycles will increase the number of decoding iterations and even lead to decoding failure.

[0028] In the initial matrix construction stage, by dynamically detecting four-cycles and adjusting the positions of non-zero terms or the cyclic shift values of sub-matrices, all four-cycles can be actively destroyed.

[0029] S102. For each non-zero term of the initial check matrix, traverse the preset range of shift values, select the shift value that minimizes the number of six-cycles, and generate an intermediate check matrix.

[0030] Specifically, in the above step S102, in QC-LDPC codes, non-zero terms correspond to sub-matrix blocks, usually the identity matrix or its cyclic shift version. For example, if the sub-matrix dimension is 64, each non-zero term represents a 64×64 cyclic shift identity matrix block. The cyclic shift value determines the number of bits that the identity matrix block is shifted to the right. For example, when the shift value is 3, each row of the identity matrix is cyclically shifted 3 bits to the right. By adjusting the shift value, the positions of sub-matrix blocks are changed, thereby affecting the distribution of non-zero terms in the check matrix and indirectly controlling the generation of short cycles.

[0031] The shift value range of the preset shift value range usually covers all possible values of the sub-matrix dimension. For example, when the sub-matrix dimension is 128, the shift value range is from 0 to 127.

[0032] For each sub-matrix corresponding to a non-zero term, traverse all possible shift values to generate multiple candidate matrices. For each candidate matrix, count the total number of its six-cycles, and select the candidate value with the fewest six-cycles as the final shift value. Traversing the shift values column by column (instead of globally adjusting simultaneously) reduces the computational complexity, and at the same time significantly reduces the six-cycle density through local optimization.

[0033] The generated intermediate check matrix retains the row weight uniformity and the number of six-cycles decreases in a staged manner. Specifically, during the shift value adjustment process, by constraining the row weight distribution, it is ensured that the number of non-zero terms in each row of the intermediate matrix is the same as that of the initial matrix, maintaining the decoding stability. The total number of six-cycles in the intermediate matrix is significantly reduced compared to the initial matrix, providing a transition structure for the final global optimization.

[0034] S103. Based on the number of six-cycles that each non-zero term in the intermediate check matrix participates in, sequentially eliminate the non-zero terms with the largest number of six-cycles participated in to obtain the target check matrix.

[0035] Specifically, in the above step S103, all hexagonal closed paths of the intermediate parity-check matrix are traversed, and the total number of six-cycles participated by each non-zero term is recorded. Sort them in descending order according to the number of six-cycles participated by non-zero terms to generate an elimination priority queue. High-frequency six-cycle terms (i.e., non-zero terms that participate in the most six-cycles) are regarded as elements that have the greatest impact on the global performance and are eliminated first.

[0036] Starting from the head of the priority queue, the sub-matrices corresponding to high-frequency six-cycle terms are sequentially replaced with all-zero matrices to gradually reduce the global number of six-cycles.

[0037] During the elimination process, it is necessary to maintain the uniformity of row weight. The standard deviation of row weight can be calculated in real time. If the number of non-zero terms in a certain row deviates from the preset range, the subsequent elimination operations of this row are skipped. Ensure that the number of non-zero terms in each column does not decrease excessively to avoid excessive column weight differences affecting the code rate stability.

[0038] The final characteristic of the generated target parity-check matrix is the global minimization of the number of short cycles and the maintenance of row weight uniformity. By directionally eliminating high-frequency six-cycle terms, the number of six-cycles in the target matrix is further reduced, completely breaking the decoding trap set. The elimination operations are scattered in different rows and columns to avoid local over-sparsity, and the standard deviation of row weight is maintained within the preset threshold.

[0039] The method for constructing a high code rate QC-LDPC parity-check matrix for NAND provided by the embodiments of the present application is based on a progressive three-step construction method, which systematically optimizes the performance and hardware adaptability of the high code rate QC-LDPC parity-check matrix. First, an initial parity-check matrix with a uniform row weight distribution and no four-cycle structure is generated. By balancing the number of non-zero terms in each row, the parameter adaptation instability of the decoding algorithm is avoided. At the same time, the four-cycle closed paths are eliminated to block the information transfer conflict, improving the decoding convergence speed and error correction reliability. Secondly, the shift values of non-zero terms of the initial parity-check matrix are traversed and the configuration with the fewest six-cycles is selected to generate an intermediate parity-check matrix, which significantly reduces the six-cycle density in a column-by-column local optimization manner, avoiding the high complexity of global search, and at the same time maintaining the row weight uniformity of the initial matrix. Finally, based on the priority of the number of six-cycles participated by non-zero terms in the intermediate parity-check matrix, high-frequency six-cycle terms are sequentially eliminated to generate a target parity-check matrix, directionally breaking the remaining trap sets and dispersing the positions of elimination operations, while reducing the global number of short cycles and maintaining row weight balance, ultimately achieving the collaborative optimization among the error correction performance, decoding stability and hardware complexity of the parity-check matrix, and meeting the core requirements of NAND flash for high reliability, low latency and low power consumption in high code rate scenarios.

[0040] In an alternative embodiment, generating an initial parity-check matrix includes: constructing a base matrix based on the progressive edge-growth (PEG) method; the column weight of the base matrix is a first preset column weight, and the number of non-zero terms in each column is equal; connecting each variable node in the base matrix to a parity-check node that can maximize the current shortest path length in sequence; if there are multiple candidate parity-check nodes that can maximize the shortest path length, select the parity-check node with the fewest number of short cycles formed for connection; during each connection, detect the four-cycle structure through a four-cycle detection formula and monitor the uniformity of the row weight; if a four-cycle structure is detected, reselect the parity-check node and adjust the cyclic shift value of the submatrix in the base matrix until the four-cycle is eliminated; generate an initial parity-check matrix with a uniform row weight distribution and no four-cycle structure.

[0041] The progressive edge-growth (PEG) method constructs the connections between variable nodes and parity-check nodes step by step. It preferentially selects the parity-check node that "maximizes the current shortest path length", avoiding local overload caused by random connection, thereby reducing the probability of short cycle generation. When there are multiple candidate parity-check nodes, it selects the node with the fewest number of short cycles formed to further suppress short cycle structures other than four-cycles and improve the quality of the initial matrix. During each connection, it verifies in real time through a four-cycle detection formula to ensure that four-cycles are immediately detected and eliminated during the construction process, avoiding the high cost of backtracking and correction in the subsequent optimization stage. Combining with the adjustment of the cyclic shift value directly destroys the closed path of the four-cycle, laying a foundation for the subsequent six-cycle optimization. During the connection process, it synchronously monitors the standard deviation of the row weight, dynamically corrects the distribution of non-zero terms, prevents the problem of decoding parameter mismatch caused by excessive local row weight, and ensures the stability of the decoding algorithm.

[0042] In an alternative embodiment, monitoring the uniformity of the row weight includes: during each connection, calculating the standard deviation of the current row weight; if the standard deviation of the row weight exceeds a preset threshold, reallocate the positions of the non-zero terms to make the row weight distribution uniform.

[0043] The standard deviation is used to quantify the discreteness of the row weight distribution, providing an objective evaluation index for uniformity and avoiding the error of subjective experience judgment. When the standard deviation exceeds the threshold, reallocate the positions of the non-zero terms, preferentially filling the rows with lower row weight to achieve load balance among rows and prevent some rows from becoming performance bottlenecks due to overload during the decoding process. During the construction of the base matrix, the row weight deviation is corrected in real time, avoiding global adjustment after construction is completed, reducing computational redundancy, and improving construction efficiency.

[0044] In an optional implementation, an intermediate check matrix is ​​generated, including: based on a preset shift value range, traversing the cyclic shift value for each column submatrix of the initial check matrix; for each candidate shift value, generating a temporary check matrix and counting the total number of six rings; selecting the candidate shift value with the least total number of six rings as the target shift value; using the target shift value to replace the shift value of the corresponding submatrix in the initial check matrix; when the shift values ​​of all column submatrices in the initial check matrix are replaced, an intermediate check matrix is ​​obtained; and the rows of the intermediate check matrix are evenly distributed.

[0045] For each column of submatrices, all possible shift values ​​are traversed independently, and local optimization is performed in units of columns to ensure that the number of six-rings in each column reaches the optimal solution; the shift value with the least total number of six-rings is selected to replace the original value, directly reducing the global six-ring density of the intermediate matrix and reducing the set of decoding traps. In the process of replacing the shift value, the uniformity of row redistribution is constrained to prevent the balance of the initial matrix from being destroyed when optimizing the six-rings, ensuring that the decoding stability of the intermediate matrix is ​​consistent with the initial matrix.

[0046] In an optional implementation, the shift value ranges from 0 to an integer between the dimension of the submatrix in the initial check matrix minus 1; and counting the total number of six rings is achieved by traversing the hexagonal closed path algorithm.

[0047] The shift value range is limited to all possible values ​​of the submatrix dimension (0 to L-1) to avoid missing potential optimal solutions and ensure the comprehensiveness of the six-ring optimization; integer range traversal simplifies the calculation logic and reduces the complexity of hardware implementation. The hexagonal closed path algorithm accurately locates all six-ring closed paths by identifying the shift value relationship between adjacent submatrices to prevent missed or misjudgment; the algorithm traverses all possible paths to ensure the absolute accuracy of the six-ring quantity statistics and provide reliable data support for subsequent optimization.

[0048] In an optional implementation, the method further includes: in the process of generating the intermediate check matrix, after each shift value adjustment, re-detecting the four-ring structure using the four-ring detection formula to ensure that no new four-ring structure is added.

[0049] During the six-ring optimization process, the shift value adjustment may accidentally introduce a new four-ring structure. By detecting and eliminating the four-rings in real time, the four-ring-free characteristics of the intermediate matrix are maintained to prevent the regression of error correction performance. Combined with the four-ring elimination mechanism of the initial matrix, double protection is formed to ensure the controllability of short rings in the entire construction process.

[0050] In an alternative embodiment, obtaining the target parity-check matrix includes: for each non-zero entry of the intermediate parity-check matrix, counting the number of six-cycles each non-zero entry participates in to generate a six-cycle distribution matrix; according to the six-cycle distribution matrix, sorting the non-zero entries in descending order of the number of six-cycles to generate an elimination priority queue; following the elimination priority queue, selecting non-zero entries from the queue head for elimination round by round, and updating the six-cycle distribution matrix and the elimination priority queue after each round of elimination; when the number of eliminated non-zero entries reaches a preset target, terminating the elimination process to generate the target parity-check matrix.

[0051] Quantify the short-cycle influence of each non-zero entry through the six-cycle distribution matrix, identify high-frequency six-cycle entries as the priority elimination targets to maximize the reduction of the global short-cycle number; eliminate in rounds according to the priority queue to directionally break the remaining trap sets and avoid performance fluctuations caused by blind elimination. Update the six-cycle distribution matrix and the queue after each round of elimination to reflect the change of the matrix structure in real time, ensure that subsequent elimination decisions are based on the latest state, and improve the optimization efficiency.

[0052] In an alternative embodiment, generating the six-cycle distribution matrix includes: traversing all hexagonal closed paths of the intermediate parity-check matrix through a depth-first search algorithm and marking the number of six-cycles each non-zero entry participates in; the generation of the paths is determined by the cyclic shift value relationship of adjacent sub-matrices in the intermediate parity-check matrix; based on the determined number of six-cycles each non-zero entry participates in, generating the six-cycle distribution matrix.

[0053] The depth-first search algorithm traverses all potential hexagonal paths recursively, avoiding repeated calculations and significantly reducing the time complexity; the algorithm only focuses on the shift value relationship of adjacent sub-matrices, filters out invalid search paths, and improves the statistical efficiency. Every time a six-cycle path is found, immediately update the participation times of the corresponding non-zero entry to ensure the real-time and accuracy of the six-cycle distribution matrix and provide a reliable input for generating the priority queue.

[0054] In an alternative embodiment, selecting non-zero entries from the queue head for elimination round by round includes: setting flag bits for each row and each column of the six-cycle distribution matrix, and if a non-zero entry was eliminated from a certain row or column in the previous round, then operating on that row or column is prohibited in the current round.

[0055] Restrict the operation of the same row / column in consecutive rounds through the flag bits to prevent local over-sparsification and maintain the row weight uniformity of the matrix; the balanced elimination strategy avoids the aggregation of remaining short cycles in specific regions and improves the global optimization effect. Force the scattered elimination operation to prompt the short cycles to be gradually broken down in different regions and prevent the influence of residual local dense short cycles on the decoding convergence.

[0056] In an alternative embodiment, the row and column positions of the six-cycle distribution matrix correspond one-to-one with the non-zero entries of the intermediate parity-check matrix, and the matrix element value is the total number of six-cycles that the corresponding non-zero entry participates in.

[0057] The matrix row and column positions strictly correspond to non-zero terms, eliminating data redundancy and simplifying the priority sorting logic; the element values directly reflect the six-ring participation degrees of non-zero terms, intuitively guiding the elimination decision-making and reducing the algorithm implementation complexity. The matrix structure facilitates subsequent expansion (such as weighted statistics, multi-ring joint optimization), providing underlying data support for advanced optimization algorithms.

[0058] In addition, after generating the target check matrix, further dynamically fine-tune and optimize the cyclic shift values of the remaining non-zero terms, including: generating a fine-tuning priority sequence according to the number of six-rings participated by the remaining non-zero terms in the six-ring distribution matrix, and preferentially adjusting the non-zero terms with the largest number of participated six-rings; making forward and backward adjustments to the cyclic shift value of each target non-zero term within a preset fine-tuning range, respectively counting the changes in the number of six-rings after adjustment, and selecting the adjustment direction that reduces the number of six-rings the most as the final shift value; if the number of six-rings does not decrease after consecutive multiple adjustments, terminate the fine-tuning process of the current non-zero term to avoid wasting invalid computing resources.

[0059] Specifically, the fine-tuning optimization includes: generating a fine-tuning priority sequence according to the number of six-rings participated by the remaining non-zero terms in the six-ring distribution matrix, and sorting them from high to low according to the number of six-rings; for each non-zero term in the priority sequence, making forward and backward adjustments within the preset fine-tuning range of its cyclic shift value; respectively counting the number of six-rings in the forward adjustment, backward adjustment, and unadjusted cases, and selecting the adjustment direction that reduces the number of six-rings the most as the final shift value of the current non-zero term; if the number of six-rings does not decrease after consecutive preset times of adjustment, terminate the fine-tuning process of the current non-zero term; generate the final check matrix after traversing all the remaining non-zero terms.

[0060] In an optional implementation manner, the column weight of the initial check matrix is a first preset column weight; the first preset column weight is determined by the target code rate and the channel condition; and during the construction process of the initial check matrix, the column weight of each column is equal to the first preset column weight; the column weight of the intermediate check matrix is a mixed structure of the first preset column weight and a second preset column weight; the second preset column weight is obtained by reducing the non-zero terms of the target column in the initial check matrix; the column weight of the target check matrix is a mixed structure of the first preset column weight, the second preset column weight, and a third preset column weight; the third preset column weight is obtained by gradually reducing the non-zero terms of the intermediate check matrix column by column; the distribution ratio of the mixed structure is determined based on the target code rate and the channel noise condition.

[0061] The initial matrix adopts a single column weight (such as 5), the middle matrix introduces a second column weight (such as 4), and the target matrix further mixes a third column weight (such as 3) to balance the code rate and error correction performance through gradual adjustment; the column weight distribution is dynamically set according to the target code rate and channel noise to adapt to the diverse requirements of TLC / QLC flash memory. The high column weight area retains strong error correction ability, and the low column weight area reduces non-zero terms to reduce complexity, achieving the optimal balance between decoding performance and hardware resource occupancy.

[0062] In an alternative embodiment, the four-ring detection formula is: ; where i k , j k , i k+1 and j k+1 are all the row and column positions in the matrix where the non-zero terms are located, and L is the dimension of the sub-matrix; The six-ring detection formula is: ; where i k , j k , i k+1 , j k+1 , i k+2 and j k+2 are all the row and column positions in the matrix where the non-zero terms are located, L is the dimension of the sub-matrix, and P is the shift value of other sub-matrices except the all-zero sub-matrix.

[0063] In summary, the high code rate QC-LDPC parity-check matrix construction method for NAND provided by the embodiments of the present application systematically solves the problems of short-loop interference, uneven row weight, and hardware adaptability of high code rate QC-LDPC codes in NAND flash through a progressive construction process and a multi-level optimization strategy: First, based on the Progressive Edge Growth (PEG) method, an initial parity-check matrix is dynamically constructed. By preferentially connecting check nodes that "maximize the shortest path length", the generation of short loops is suppressed. Combining the four-cycle detection formula, the four-cycle structure is eliminated in real time, and the non-zero term distribution is dynamically adjusted by monitoring the standard deviation of the row weight, generating an initial matrix with uniform row weight and no four-cycles, laying a foundation for balance and stability for subsequent optimization; Second, the sub-matrix shift values are traversed column by column in the initial matrix. The number of six-cycles is accurately counted through the hexagonal closed-path algorithm, and the locally optimal shift value is selected to generate an intermediate matrix. At the same time, the four-cycle structure is re-detected to prevent performance degradation, and the six-cycle density is significantly reduced while maintaining the row weight uniformity; Finally, a priority queue is constructed based on the six-cycle distribution matrix, and the high-frequency six-cycle terms are marked by combining the depth-first search algorithm. Through row and column flag control, targeted elimination is performed round by round, the remaining trap sets are scattered and broken, and the code rate and channel conditions are dynamically adapted in the mixed column weight structure, ultimately minimizing the global number of short loops, controlling the standard deviation of the row weight distribution, and streamlining the non-zero terms. The above technical features are closely linked. Through the synergistic effect of "four-cycle elimination → six-cycle local optimization → global balance elimination", the error correction performance, decoding convergence speed, and hardware efficiency are significantly improved, fully meeting the stringent requirements of 3D TLC / QLC NAND flash for high reliability, low complexity, and real-time performance.

[0064] Based on the high code rate QC-LDPC parity-check matrix construction method for NAND provided by the above embodiments, a specific example will be used to illustrate it in detail below.

[0065] The rapid development of emerging fields such as 5G, artificial intelligence, cloud computing, and the Internet of Things has brought about an explosive growth of data. Due to its advantages such as large storage capacity, high read / write performance, and low operating power consumption, NAND flash has become a core component of current data centers. With the development of NAND flash manufacturing technology represented by 3D stacking technology, the storage capacity of NAND flash has been further increased, and the storage cost per bit of data has gradually decreased. However, the high stacking layers also bring greater noise inside NAND flash, increasing the bit error rate of the stored data in NAND flash.

[0066] Low-density parity-check (LDPC) codes have been widely used in deep space exploration, satellite communication, and digital watermarking due to their excellent error correction performance, and have also become the preferred ECC scheme in current NAND flash memories. LDPC codes essentially belong to linear block codes and can be determined by a parity-check matrix with a dimension of n rows and m columns. The number of rows of the parity-check matrix represents the number of parity-check equations, and the number of columns represents the length of the encoded information in each codeword. In NAND flash memories, QC-LDPC codes are usually used, and their parity-check matrices are composed of a series of sub-matrices with the same dimension. The sub-matrices are all-zero matrices, identity matrices, or shift matrices obtained by circularly shifting the identity matrix to the right. This special structure can reduce the complexity in the encoding and decoding process and is easy to implement in hardware.

[0067] The decoding process in NAND flash memories is usually an iterative decoding scheme. The encoded information is in error due to the change in the threshold voltage distribution. When the data is read, the encoded information will go through the decoding process by the H matrix. When the information c after iteration satisfies c·HT = 0, it indicates that it is a valid codeword, and at this time, the decoding is successful, and the final c is output. Otherwise, a new round of iteration starts until the final decoding result satisfies the parity-check relationship that the product of c and the transpose of the parity-check matrix H is 0 or reaches the set maximum number of iterations.

[0068] Different from applications in other fields, the characteristics of NAND flash memories require that the parity-check matrices of their corresponding QC-LDPC codes have good error correction performance while having a high code rate (usually above 0.8). Especially with the development of 3D TLC and 3D QLC, there are increasingly high requirements for the quality of LDPC parity-check matrices.

[0069] Therefore, based on the method for constructing a high-code-rate QC-LDPC parity-check matrix for NAND in the above embodiment, this embodiment also provides a method for constructing a high-code-rate QC-LDPC code parity-check matrix applicable to NAND flash memories.

[0070] The main process includes determining the dimension of the base matrix, code rate, sub-matrix dimension, and column weight of the initial QC-LDPC parity-check matrix; obtaining the initial parity-check matrix H1 without four cycles (for a variable node, a closed loop formed by alternately passing through several steps from the variable node to the parity-check node and then back to the starting variable node is called a "cycle" in LDPC codes), with the same column weight (5) and uniform row weight using the construction method based on the PEG method; modifying the shift values of the sub-matrices in H1 matrix column by column and row by row until the minimum number of six cycles is reached to obtain the parity-check matrix H2; constructing a frequency matrix of the non-zero terms corresponding to H2 that appear in the six cycles, setting row and column flags, and eliminating the shift value with the largest number of six cycles in the selected range each time to obtain the final parity-check matrix H3.

[0071] The method proposed in this embodiment can construct QC-LDPC codes with various code rates applicable to 3D TLC and QLC NAND flash memory media, and the constructed matrix has excellent error correction performance. In addition, since this method reduces the number of non-zero terms during the construction of matrix H3, the latency can be reduced in the hardware implementation of the serial decoding method.

[0072] The sub-matrix of the QC-LDPC code parity-check matrix is an all-zero matrix, an identity matrix, or a shift matrix formed by cyclically shifting the identity matrix to the right by a fixed value. Generally, the base matrix can be represented by the shift factor corresponding to the sub-matrix. Generally, when the sub-matrix is all-zero, it is represented by "-1", when the matrix is an identity matrix, it is represented by "0", and other numbers represent the corresponding shift value size. Among them, the size of the number is 0~q. q is the dimension of the sub-matrix.

[0073] The construction method of the high code rate QC-LDPC code parity-check matrix applicable to NAND flash memory in this embodiment uses a three-step construction method to construct the final parity-check matrix. The specific construction method is as Figure 2 shown.

[0074] For the construction of the initial parity-check matrix H1, the construction method based on the PEG method is adopted, which specifically includes the following steps: First, set the dimension m and n of the base matrix of the initial parity-check matrix, the column weight column_weight of the parity-check matrix, the girth g, and the dimension p of the sub-matrix. The dimension of the parity-check matrix is mp×np. According to the PEG method, for each variable node, calculate the shortest path length from the variable node to the unconnected parity-check node, select the parity-check node with the largest shortest path length. When there are multiple parity-check nodes with the largest shortest path length, select the position with the least number of short cycles, and connect the variable node to the parity-check node to ensure that each variable node is only connected to 5 parity-check nodes. This method can ensure that the non-zero terms appearing in each row of the constructed matrix are evenly distributed.

[0075] Each connected edge corresponds to a corresponding non - zero term in the parity - check matrix, which is either an identity matrix or a matrix with a shift value. Initialize the positions with non - zero terms to the identity matrix, i.e., the number 0, and then randomly add shift factors to these non - zero term positions column - by - column. First, randomly add shift values to the 5 non - zero terms in the first column. The selected shift value range is from 0 to the sub - matrix dimension p - 1.

[0076] When starting to add the shift value of the second column, for each added shift value, perform a four - cycle detection with the columns that have already had shift values added before. When the four - cycle detection formula of the above - mentioned embodiment is satisfied, it indicates that there is a four - cycle. At this time, randomly change the shift value. Repeat the addition of the shift value until all non - zero term shift factors are added, and a parity - check matrix H1 without any four - cycles, with a column weight of 5 and evenly distributed in rows can be obtained.

[0077] Although there are no four - cycles in the initial parity - check matrix H1 obtained through the above steps, since there is no six - cycle constraint when adding shift factors to the matrix, there will be a large number of six - cycles in the generated parity - check matrix H1. Since the number of short cycles is an important factor affecting the performance of the parity - check matrix, the number of six - cycles in the H1 matrix is optimized according to the following method to obtain an intermediate parity - check matrix H2 with the minimum number of six - cycles. The specific steps are as follows: Starting from the first row of the first column, if the corresponding position in this row and this column is not a non - zero term, use the six - cycle detection formula of the above - mentioned embodiment to count the number of six - cycles in the current parity - check matrix H1, record the current total number of six - cycles girth6_1 and initialize the flag of this non - zero term to 0.

[0078] Record the magnitude m of the shift value of the non - zero term at this row - column position. Starting from k = 1, successively select integers where k ≤ q (q is the sub - matrix dimension, and k increases by 1 each time). Set the shift value of this column to (m + k)%q to obtain a transition matrix H1' of the H1 matrix. Perform a four - cycle detection on the H1' matrix according to the four - cycle detection formula. If there are no four - cycles in the matrix, use the above - mentioned six - cycle detection formula to count the total number of six - cycles in the H1' matrix and record the total number of six - cycles girth6_2 at this time. At the same time, compare the magnitudes of girth6_1 and girth6_2. If girth6_2 is less than girth6_1, set the flag of this non - zero term position to 1, record the value of k at this time, and replace girth6_1 with girth6_2. The shift change value at this position traverses the integers from k = 1 to k ≤ q. Each time the k value is changed, repeat step 3. After the traversal is completed, if the flag of this position is 1 at this time, replace the latest (m + k)%q with the shift value at this position.

[0079] Select the next non-zero item in this column. After updating the shift values of all non-zero items, start a new round of updates from the first column. Stop until the number of six-cycles does not change in the latest complete round of updates. At this time, it means that the number of six-cycles in the matrix H2 has reached the minimum, and changing the shift value will not reduce the six-cycles in the matrix.

[0080] The intermediate check matrix H2 can be obtained through the above steps.

[0081] Currently, 3D TLC and QLC NAND flash media have high requirements for the bit error rate. The decoding methods of the widely used QC-LDPC codes are mostly based on the normalized min-sum decoding algorithm. The normalization factor is usually between 0.6 and 0.9. For different rows in the matrix, the row weight size has relatively high requirements for the normalization factor. This is because when the row weight number increases by 1, according to the most primitive check node update formula, the check node information will be multiplied by an additional tanh(Lq / 2). Since the value range of the tanh function is (-1, 1), when approximated to the normalized min-sum, the more uniform the row weight, the less the selected normalization factor affects the update of the check node information in each row of the matrix.

[0082] In addition, due to the high code rate requirements of QC-LDPC in NAND flash, there are often many six-cycles in the check matrix of the constructed NAND flash. In fact, in the check matrix of high code rate QC-LDPC codes, each non-zero item will generate a six-cycle with non-zero items in other positions. To further reduce the impact of cycles on the matrix performance, while reducing the average number of decoding iterations and the latency consumed during the decoding process, and accelerating the convergence process of the codeword.

[0083] Therefore, it is necessary to eliminate some non-zero item elements of the generated H2 matrix to obtain the final QL-LDPC check matrix H3 with uniform row weight suitable for 3D NAND flash. The specific process is as Figure 3 shown, including the following steps: According to the dimension of the check matrix H2, construct the six-cycle distribution matrix H2' corresponding to the H2 matrix, and the flag for each row and each column of the H2' matrix. The H2' matrix and its flag for each row and each column are initialized to 0. Determine the number of non-zero items to be eliminated and the range of the non-zero items to be eliminated in the matrix.

[0084] Starting from the first non-zero term to be eliminated, use the above six-cycle detection formula to count the number of six-cycles corresponding to each non-zero term in the H2 matrix, and initialize the maximum number of six-cycles to 0. Starting from each row of the matrix H2', if the flag of this row is 0, within the range of the selected non-zero terms to be eliminated, among all the columns where the column flag is 0, compare the number of six-cycles corresponding to each non-zero term with the initial maximum number of six-cycles point by point, and select the point with the largest number of six-cycles within the elimination range. If the number of six-cycles of this point is not 0, set the row and column flag corresponding to this point to 1, set the shift value corresponding to this point in the H2 matrix to "-1", and start the elimination of the next non-zero term. When the number of non-zero terms to be eliminated reaches an integer multiple of the number of rows of the parity-check matrix H2, reset the flag of all rows to 0, and repeat this process until the number of non-zero terms to be eliminated reaches the target number of non-zero terms to be eliminated, to obtain the final parity-check matrix H3.

[0085] Exemplarily, a specific matrix example is used for illustration.

[0086] According to the method in this embodiment, a 29×287 matrix applicable to 3D TLC NAND flash memory is constructed.

[0087] First, determine that the dimension of the sub-matrix is 128. Use the PEG-based method to construct a parity-check matrix H1 with a column weight of all 5 and a uniform row weight, and select the target range of the matrix. Further optimize it according to the method in this embodiment to obtain H2, and at the same time perform further short-cycle optimization on H2 to obtain H3. Among them, the number of short cycles in H1, H2, and H3 is as Figure 4 shown. It can be seen that compared with the initial H1 matrix, the number of six-cycles in the H3 matrix is only one-sixtieth of the initial matrix. The reduction in the number of short cycles will further break the trap sets composed of these short cycles and accelerate the information transfer between variable nodes and check nodes during the decoding process.

[0088] Furthermore, a hard-decision performance simulation is carried out on the matrix constructed by the construction method of the present invention. Under the same test conditions, the decoding performance of the initially constructed H1 and the finally optimized H3 is tested. The decoding results of BER (bit error rate) are as Figure 5 shown, and the decoding results of FER (frame error rate) are as Figure 6 shown. It can be seen that the construction method of the parity-check matrix constructed by the method of the present invention can improve the performance of the parity-check matrix. The finally constructed matrix has a decoding performance one order of magnitude higher than that of the initial matrix. When the initial number of error bits is 270, the FER of the final H3 matrix can reach the order of 1E-4, which can meet the requirements of current 3D QLC NAND flash memory, and has a good performance degradation advantage in the waterfall region.

[0089] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0090] An embodiment of the present application also provides a high code rate QC-LDPC parity check matrix construction device for NAND. The structure of the device is as Figure 7 shown, including: An initial generation module 701 for generating an initial parity check matrix; the row weights of the initial parity check matrix are evenly distributed and there is no four-cycle structure; An intermediate generation module 702 for traversing a preset shift value range for each non-zero term of the initial parity check matrix and selecting the shift value that minimizes the number of six-cycles to generate an intermediate parity check matrix; A target generation module 703 for sequentially eliminating the non-zero terms with the largest number of six-cycles participated in based on the number of six-cycles participated in by each non-zero term in the intermediate parity check matrix to obtain a target parity check matrix.

[0091] For the description of the features in the corresponding embodiment of the high code rate QC-LDPC parity check matrix construction device for NAND, reference can be made to the relevant description in the corresponding embodiment of the high code rate QC-LDPC parity check matrix construction method for NAND, which will not be elaborated here one by one.

[0092] An embodiment of the present application also provides an electronic device, such as Figure 8 shown, including a memory 14 and a processor 20. A computer program is stored in the memory 10, and the processor 20 is configured to run the computer program to execute the steps in any of the above embodiments of the high code rate QC-LDPC parity check matrix construction method for NAND.

[0093] An embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above embodiments of the high code rate QC-LDPC parity check matrix construction method when running.

[0094] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs and other various media that can store computer programs.

[0095] An embodiment of the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the method for constructing a high code rate QC-LDPC check matrix for NAND.

[0096] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the method for constructing a high code rate QC-LDPC check matrix for NAND.

[0097] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0098] The above has introduced in detail a method, device, equipment, storage medium, and program product for constructing a high code rate QC-LDPC check matrix for NAND provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for constructing a high code rate QC-LDPC parity check matrix for NAND, characterized in that, The method includes: Generating an initial parity-check matrix; the row weights of the initial parity-check matrix are evenly distributed and there is no four-cycle structure; For each non-zero entry of the initial parity-check matrix, traversing a preset range of shift values, selecting the shift value that minimizes the number of six-cycles, and generating an intermediate parity-check matrix; Based on the number of six-cycles that each non-zero entry in the intermediate parity-check matrix participates in, sequentially eliminating the non-zero entries with the largest number of six-cycles participated in to obtain a target parity-check matrix.

2. The method according to claim 1, wherein The generating of the initial parity-check matrix includes: Constructing a base matrix based on the progressive edge growth method; the column weight of the base matrix is a first preset column weight, and the number of non-zero entries in each column is equal; Connecting each variable node in the base matrix to the parity-check node that can maximize the current shortest path length in turn; if there are multiple candidate parity-check nodes that can maximize the shortest path length, select the parity-check node that forms the fewest short cycles for connection; At each connection, detecting the four-cycle structure through the four-cycle detection formula and monitoring the uniformity of the row weights; If a four-cycle structure is detected, reselecting the parity-check node and adjusting the cyclic shift value of the sub-matrix in the base matrix until the four-cycle is eliminated; Generating an initial parity-check matrix with evenly distributed row weights and no four-cycle structure.

3. The method according to claim 2, wherein The monitoring of the uniformity of the row weights includes: At each connection, calculating the standard deviation of the current row weights; If the standard deviation of the row weights exceeds a preset threshold, reallocating the positions of the non-zero entries to make the row weight distribution uniform.

4. The method according to claim 3, wherein The generating of the intermediate parity-check matrix includes: Based on a preset range of shift values, traversing the cyclic shift values for each column sub-matrix of the initial parity-check matrix; For each candidate shift value, generating a temporary parity-check matrix and counting the total number of six-cycles; Selecting the candidate shift value with the fewest total number of six-cycles as the target shift value; Using the target shift value to replace the shift value of the corresponding sub-matrix in the initial parity-check matrix; When the shift values of all column sub-matrices in the initial parity-check matrix are replaced, obtaining an intermediate parity-check matrix; the row weights of the intermediate parity-check matrix are evenly distributed.

5. The method according to claim 4, characterized in that, The range of the shift values is an integer between 0 and the dimension of the sub-matrix in the initial parity-check matrix minus 1; the counting of the total number of six-cycles is implemented by traversing the hexagonal closed path algorithm.

6. The method according to claim 5, characterized in that, The method further includes: During the process of generating the intermediate parity-check matrix, after each shift value adjustment, re-detecting the four-cycle structure through the four-cycle detection formula to ensure that no new four-cycle structures are added.

7. The method according to claim 6, wherein The obtaining of the target parity-check matrix includes: For each non-zero entry of the intermediate parity-check matrix, counting the number of six-cycles that each non-zero entry participates in to generate a six-cycle distribution matrix; According to the six-cycle distribution matrix, sorting the non-zero entries in descending order of the number of six-cycles to generate an elimination priority queue; According to the elimination priority queue, sequentially selecting non-zero entries from the head of the queue for elimination, and updating the six-cycle distribution matrix and the elimination priority queue after each round of elimination; When the number of eliminated non-zero entries reaches a preset target, terminating the elimination process to generate a target parity-check matrix.

8. The method according to claim 7, characterized in that, The generating of the six-cycle distribution matrix includes: Traversing all hexagonal closed paths of the intermediate parity-check matrix through the depth-first search algorithm, and marking the number of six-cycles that each non-zero entry participates in; the generation of the paths is determined by the cyclic shift value relationship of adjacent sub-matrices in the intermediate parity-check matrix; Generate a six-ring distribution matrix based on the number of six-rings each non-zero term participates in that is determined.

9. The method according to claim 8, characterized in that, The step of eliminating non-zero terms by selecting from the head of the queue round by round includes: Set flag bits for each row and each column of the six-ring distribution matrix. If a row or a column has had non-zero terms eliminated in the previous round, operations on that row or column are prohibited in the current round.

10. The method according to claim 9, characterized in that, The row and column positions of the six-ring distribution matrix correspond one-to-one with the non-zero terms of the intermediate parity-check matrix, and the matrix element value is the total number of six-rings that the corresponding non-zero term participates in.

11. The method according to claim 10, characterized in that, The column weight of the initial parity-check matrix is a first preset column weight; the first preset column weight is determined by the target code rate and the channel condition; and during the construction process of the initial parity-check matrix, the column weight of each column is equal to the first preset column weight; The column weight of the intermediate parity-check matrix is a mixed structure of a first preset column weight and a second preset column weight; The second preset column weight is obtained by reducing the non-zero terms of the target column in the initial parity-check matrix; The column weight of the target parity-check matrix is a mixed structure of a first preset column weight, a second preset column weight, and a third preset column weight; The third preset column weight is obtained by reducing the non-zero terms of the intermediate parity-check matrix column by column; The distribution ratio of the mixed structure is determined based on the target code rate and the channel noise condition.

12. The method according to any one of claims 1 to 11, characterized in that, The four-ring detection formula is: ； where i k , j k , i k+1 and j k+1 are the row and column positions in the matrix where the non-zero terms are located, and L is the dimension of the sub-matrix; The six-ring detection formula is: ； where i k , j k , i k+1 , j k+1 , i k+2 and j k+2 are the row and column positions in the matrix where the non-zero terms are located, L is the dimension of the sub-matrix, and P is the shift value of the other sub-matrices outside the all-zero sub-matrix.

13. An electronic device, characterized in that, including: A memory for storing a computer program; A processor, when executing the computer program, implements the steps of the method for constructing a high code rate QC-LDPC parity-check matrix for NAND as described in any one of claims 1 to 12.

14. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein when the computer program is executed by the processor, it implements the steps of the method for constructing a high code rate QC-LDPC parity-check matrix for NAND as described in any one of claims 1 to 12.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for constructing a high code rate QC-LDPC parity-check matrix for NAND as described in any one of claims 1 to 12.

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