Bus number distribution method, device, system and equipment of switch chip and medium

Abstract

The invention discloses a bus number distribution method, device, system and equipment for a switching chip and a medium, and relates to the technical field of chip design. The method comprises the following steps: determining each downlink bridge device and each host to which an endpoint device corresponding to each downlink bridge device belongs, and distributing bus numbers to the downlink bridge devices belonging to each host and the endpoint device corresponding to each downlink bridge device within the bus number range of each host according to the bus number range of each host. In this way, the bus numbers of the downlink bridge devices belonging to the same host and the bus numbers of the endpoint devices corresponding to the downlink bridge devices are not repeated. Therefore, under the scene of interconnection of the switching chips, the bus number does not need to be converted, and the bus number does not need to be reserved, so that the problem that the number of the current equipment in the switching chips does not exceed the limit of the total number of the bus numbers, but the host still cannot correctly allocate the bus number for each piece of equipment can be solved.

Description

Technical Field

[0001] This application relates to the technical field of chip design, and particularly to a method, apparatus, system, device and medium for allocating bus numbers of a switching chip. Background Art

[0002] For a domain-isolated switching chip, usually the CPU (Central Processing Unit, hereinafter referred to as CPU) inside the switching chip manages the switching chip connected to the host and the endpoint devices connected under the switching chip. As an actual RC device (Root Complex, hereinafter referred to as RC), this CPU enumerates and allocates bus numbers for the downstream bridge devices inside the switching chip and the endpoint devices connected to the downstream bridge devices.

[0003] In the scenario of interconnection between switching chips, since the bus numbers (Bus Numbers) between multiple switching chips may be duplicated, bus number conversion is required when devices between switching chips access each other. Since each switching chip needs to reserve bus numbers for possible accesses initiated by other switching chips, and the bus number range is restricted by the communication protocol, this may lead to a situation where the number of current devices does not exceed the limit of the total number of bus numbers, but the host still cannot correctly allocate bus numbers to each device. Summary of the Invention

[0004] This application provides a method, apparatus, system, device and medium for allocating bus numbers of a switching chip, so as to at least solve the problem that the host still cannot correctly allocate bus numbers to each device although the number of current devices in the switching chip does not exceed the limit of the total number of bus numbers.

[0005] This application provides a method for allocating bus numbers of a switching chip. The switching chip includes multiple downstream bridge devices, and each downstream bridge device is connected with a corresponding endpoint device. The method includes: obtaining each downstream bridge device and its corresponding endpoint device; determining each host to which each downstream bridge device and its corresponding endpoint device belong; obtaining the bus number range corresponding to each host; and allocating bus numbers to each downstream bridge device and its corresponding endpoint device by using each bus number range.

[0006] The present application also provides a bus number allocation device for a switching chip. The switching chip includes a plurality of downstream bridge devices, and each downstream bridge device is connected to a corresponding endpoint device. The device includes: a device acquisition module, configured to acquire each downstream bridge device and its corresponding endpoint device; a host determination module, configured to determine each host to which each downstream bridge device and its corresponding endpoint device belong; a bus number acquisition module, configured to acquire the bus number ranges corresponding to each host; and a bus number allocation module, configured to use each bus number range to allocate bus numbers to each downstream bridge device and its corresponding endpoint device.

[0007] The present application also provides a communication system, which includes a plurality of hosts, a plurality of switching chips, and a plurality of endpoint devices. Among them, one host is connected to one switching chip, one switching chip is connected to a plurality of endpoint devices, and the switching chip is configured to implement the steps of any one of the above bus number allocation methods for the switching chip.

[0008] The present application also provides an electronic device, including: a memory, configured to store a computer program; and a processor, configured to implement the steps of any one of the above bus number allocation methods for the switching chip when executing the computer program.

[0009] The present application also provides a computer-readable storage medium, in which a computer program is stored. Wherein, when the computer program is executed by a processor, the steps of any one of the above bus number allocation methods for the switching chip are implemented.

[0010] The present application also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of any one of the above bus number allocation methods for the switching chip are implemented.

[0011] Through the present application, each downstream bridge device in the switching chip and the endpoint device corresponding to each downstream bridge device respectively correspond to different hosts. In the process of the switching chip allocating bus numbers to each downstream bridge device and the endpoint device corresponding to each downstream bridge device, first determine each host to which each downstream bridge device and the endpoint device corresponding to each downstream bridge device belong, and then according to the bus number ranges of each host, within the bus number ranges of each host, allocate bus numbers to the downstream bridge devices belonging to each host and the endpoint devices corresponding to each downstream bridge device. In this way, the bus numbers of the downstream bridge devices belonging to the same host and the endpoint devices corresponding to each downstream bridge device are not repeated, and the downstream bridge devices belonging to the same host and the endpoint devices corresponding to each downstream bridge device are not located in the same switching chip. Thus, in the scenario of switching chip interconnection, there is no need to convert bus numbers, and there is no need to reserve bus numbers, thereby solving the problem that although the number of current devices in the switching chip does not exceed the limit of the total number of bus numbers, the host still cannot correctly allocate bus numbers to each device. Brief Description of the Drawings

[0012] To more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0013] Figure 1 It is a domain isolation switching chip; Figure 2 It is a domain isolation switching chip from the host perspective; Figure 3 It is a domain isolation switching chip from the real perspective; Figure 4 It is a schematic diagram of the interconnection between switching chip A and switching chip B; Figure 5 It is a schematic diagram of the interconnection between switching chip A and switching chip B provided by the embodiment of the present application; Figure 6 It is a schematic flow chart of a method for allocating bus numbers of a switching chip provided by the embodiment of the present application; Figure 7 It is a schematic diagram of a routing ambiguity situation of switching chip A provided by the embodiment of the present application; Figure 8 It is a schematic flow chart of a method for allocating bus numbers of a switching chip provided by the embodiment of the present application; Figure 9 It is a schematic diagram of routing through a target routing table provided by the embodiment of the present application; Figure 10 It is a schematic diagram of routing through a target communication bus provided by the embodiment of the present application; Figure 11 It is a schematic structural diagram of a device for allocating bus numbers of a switching chip provided by the embodiment of the present application; Figure 12 It is a schematic structural diagram of an electronic device provided by the embodiment of the present application. Detailed Description of the Embodiments

[0014] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

[0015] It should be noted that in the description of this application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] For traditional switching chips, an RC device located in the host manages the switching chips connected to the host and the endpoint devices under the switching chips. The management process includes device enumeration and bus number allocation for the devices, etc. As Figure 1 shown in the domain-isolated switching chip, usually a CPU (Central Processing Unit, abbreviated as CPU) inside the switching chip manages the switching chip connected to the host and the endpoint devices under the switching chip. As the actual RC device (Root Complex, abbreviated as RC), the CPU enumerates and allocates bus numbers for the downstream bridge devices (the bridge devices connected to the downstream ports are called downstream bridge devices) inside the switching chip and the corresponding endpoint devices connected to the downstream bridge devices. Among them, the PCIe domain (peripheral component interconnect express, abbreviated as PCIe) managed by the CPU as the RC is called the real domain, and the PCIe domain managed by the RC device of the host is called the host domain.

[0017] For the domain-isolated switching chip, after the CPU enumerates the devices, it will respond to the enumeration process of the host and perform spoofed responses, making the host "think" that the downstream bridge devices inside the switching chip and the endpoint devices connected to the downstream bridge devices are still managed by itself. As Figure 2 shown, from the perspective of the host, there is no internal CPU inside the switching chip, and all downstream bridge devices and endpoint devices are directly managed by the host, and the host allocates bus numbers for all downstream bridge devices and endpoint devices. As Figure 3 shown, from the real perspective, except for the upstream bridge device (the bridge device connected to the upstream port is called the upstream bridge device) connected to the host, other bridge devices are managed by the CPU, and the bus numbers actually used by the downstream bridge devices and endpoint devices (i.e., used on the PCIe link) are allocated by the internal CPU, and its value is generally different from the bus number allocated by the host. For example, Figure 2 and Figure 3The bus numbers corresponding to the shown downstream bridge devices and their corresponding endpoint devices are different. Due to the difference between the bus numbers assigned by the host and the actual bus numbers, bus number conversion is required when the host accesses the devices.

[0018] As Figure 4 shown, considering the scenario of two switching chips interconnected, since the CPUs independently manage their respective PCIe domains, each switching chip can start allocating bus numbers from 0, and the device enumeration process does not need to interact with other CPUs, and the process is relatively simple. However, this method also has the following defects: 1. Since the device BDF (BDF is used to represent the bus number, device number, and function number, namely Bus Number, Device Number, and Function Number respectively) of each switching chip will be repeated, BDF conversion is required for device mutual access between switching chips. When multiple switching chips are networked, a set of conversion rules is required for every two chips.

[0019] 2. Since each switching chip needs to reserve BDF for possible accesses initiated by other switching chips (devices belonging to the same host can access each other), and the bus number range is restricted by the communication protocol (0~255). Due to the existence of reserved bus numbers, from the perspective of the host, when the current number of devices does not exceed the bus number limit, there will still be a situation where bus numbers cannot be correctly allocated to each device.

[0020] In view of this, the present application proposes a bus number allocation method, device, system, device, and medium for a switching chip. The switching chip includes multiple downstream bridge devices, and each downstream bridge device is connected to a corresponding endpoint device. The method includes: obtaining each downstream bridge device and its corresponding endpoint device; determining each host to which each downstream bridge device and its corresponding endpoint device belong; obtaining the bus number range corresponding to each host; and using each bus number range to allocate bus numbers to each downstream bridge device and its corresponding endpoint device.

[0021] In the method for allocating bus numbers of the switching chip of the present application, each downstream bridge device in the switching chip and each endpoint device corresponding to each downstream bridge device correspond to different hosts. In the process of allocating bus numbers for each downstream bridge device and each endpoint device corresponding to each downstream bridge device in the switching chip, first determine the hosts to which each downstream bridge device and each endpoint device corresponding to each downstream bridge device belong, and then, according to the bus number ranges of each host, within the bus number ranges of each host, allocate bus numbers to the downstream bridge devices and the endpoint devices corresponding to each downstream bridge device that belong to each host. In this way, the bus numbers of the downstream bridge devices and the endpoint devices corresponding to each downstream bridge device that belong to the same host are not repeated, and the downstream bridge devices and the endpoint devices corresponding to each downstream bridge device that belong to the same host are not located in the same switching chip. Thus, in the scenario of switching chip interconnection, there is no need to convert bus numbers, and there is no need to reserve bus numbers, thereby solving the problem that although the number of current devices in the switching chip does not exceed the limit of the total number of bus numbers, the host still cannot correctly allocate bus numbers to each device.

[0022] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] First, in combination with the specific application environment architecture or specific hardware architecture on which the execution of the method for allocating bus numbers of the switching chip depends, the specific application environment architecture or specific hardware architecture will be described herein.

[0024] The present application provides a communication system, which includes multiple hosts, multiple switching chips, and multiple endpoint devices. Among them, one host is connected to one switching chip, and one switching chip is connected to multiple endpoint devices.

[0025] As Figure 5 shown, in the interconnected network composed of switching chip A and switching chip B, host 0 is connected to switching chip A, and there are four downstream bridge devices inside switching chip A, and each of the four downstream bridge devices is connected to four endpoint devices; host 1 is connected to switching chip B, and there are four downstream bridge devices inside switching chip B, and each of the four downstream bridge devices is also connected to four endpoint devices. In switching chip A, downstream bridge device A and endpoint device A corresponding to downstream bridge device A belong to host 0, and downstream bridge device B and endpoint device B corresponding to downstream bridge device B belong to host 1; in switching chip B, downstream bridge device A and endpoint device A corresponding to downstream bridge device A belong to host 0, and downstream bridge device B and endpoint device B corresponding to downstream bridge device B belong to host 1. That is, in the same switching chip, each downstream bridge device and each endpoint device corresponding to each downstream bridge device belong to different hosts.

[0026] Second, the bus number allocation method of the switching chip of the present application will be further described in detail in combination with the above application environment, accompanying drawings and specific embodiments.

[0027] According to an embodiment of the present application, an embodiment of a bus number allocation method for a switching chip is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0028] In this embodiment, a bus number allocation method for a switching chip is provided, which can be used in the above-mentioned switching chip, specifically in the CPU of the switching chip. The switching chip includes a plurality of downstream bridge devices, and each downstream bridge device is connected to a corresponding endpoint device. Figure 6 It is a flowchart of the bus number allocation method for the switching chip according to the embodiment of the present application, as Figure 6 shown, the process includes the following steps: Step S602, obtain each downstream bridge device and its corresponding endpoint device.

[0029] A bridge device is a functional module used to connect different buses or interfaces to implement data transmission and protocol conversion. As Figure 5 shown, the downstream bridge device is the bridge device connected to the downstream port. An endpoint device refers to a terminal device connected to a network or a switching system.

[0030] Obtaining each downstream bridge device and its corresponding endpoint device means that for the CPU of the switching chip, it is necessary to know in advance which downstream bridge devices and endpoint devices are in the switching chip. There can be various ways to obtain each downstream bridge device and its corresponding endpoint device. For example, the configuration information stored in the non-volatile storage unit can be used to obtain each downstream bridge device and its corresponding endpoint device configured in the switching chip; for another example, the CPU can communicate with each downstream bridge device and its corresponding endpoint device to obtain each downstream bridge device and its corresponding endpoint device configured in the switching chip.

[0031] Step S604, determine each host to which each downstream bridge device and its corresponding endpoint device belong.

[0032] As described above, in a switching chip, each downstream bridge device and its corresponding endpoint device belong to different hosts. To facilitate the allocation of bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to each host within the bus number range corresponding to each host, it is necessary to determine the hosts to which each downstream bridge and its corresponding endpoint device belong before allocating the bus numbers. In the actual application process, the hosts to which each downstream bridge device and its corresponding endpoint device belong can be determined according to the topology relationship of the switching chip stored in the non-volatile storage unit.

[0033] Step S606, obtain the bus number ranges corresponding to each host.

[0034] In a switching chip, the bus number is used to identify the numbers of different devices or device groups on the PCIe bus. Under the PCIe communication protocol, the bus number range of each host is 0 to 255. In actual applications, the bus number ranges corresponding to each host can be obtained by reading the non-volatile storage unit; or the bus number ranges corresponding to each host can be obtained by communicating with the host.

[0035] Optionally, for each host, its bus number range can be the same, that is, all are 0 to 255. For a switching chip, since other switching chips will allocate bus numbers to their own downstream bridge devices and endpoint devices, the bus number ranges of each host obtained by the switching chip can also be different.

[0036] Step S608, use each bus number range to allocate bus numbers to each downstream bridge device and its corresponding endpoint device.

[0037] In the PCIe topology structure, a superior bus can branch out multiple subordinate bridge devices, and they share the bus number allocated by the superior bus. As Figure 5 shown, for the downstream bridge device A belonging to host 0, their bus numbers are all 1. The endpoint device A connected to switching chip A and the endpoint device A connected to switching chip B both belong to host 0, and their bus numbers are different, that is, {2,0,0}, {3,0,0}, {4,0,0}, {5,0,0} respectively. The endpoint device B connected to switching chip A and the endpoint device B connected to switching chip B both belong to host 1, and their bus numbers are also non-repeating, that is, {2,0,0}, {3,0,0}, {4,0,0}, {5,0,0} respectively. Since the endpoint device A and the endpoint device B connected to switching chip A belong to different hosts, the bus numbers of the endpoint device A and the endpoint device B can be repeated, that is, the bus numbers of the downstream bridge device and the endpoint device belonging to the same host are non-repeating, and the bus numbers of the downstream bridge device and the endpoint device belonging to different hosts can be repeated.

[0038] It should be noted that for Figure 5 the {2,0,0}, {3,0,0}, {4,0,0}, and {5,0,0} in it are all BDF encodings. Among them, B is the bus number, that is, Bus number; D is the device number, that is, Device number; F is the function number, that is, Function number.

[0039] In the bus number allocation method of the switching chip provided in this embodiment, each downstream bridge device in the switching chip and each endpoint device corresponding to each downstream bridge device correspond to different hosts. In the process of the switching chip allocating bus numbers to each downstream bridge device and each endpoint device corresponding to each downstream bridge device, first determine each host to which each downstream bridge device and each endpoint device corresponding to each downstream bridge device belong, and then according to the bus number ranges of each host, within the bus number ranges of each host, allocate bus numbers to the downstream bridge devices belonging to each host and each endpoint device corresponding to each downstream bridge device. In this way, the bus numbers of the downstream bridge devices belonging to the same host and each endpoint device corresponding to each downstream bridge device are not repeated, and the downstream bridge devices belonging to the same host and each endpoint device corresponding to each downstream bridge device are not located in the same switching chip. In this way, in the scenario of switching chip interconnection, there is no need to convert the bus number, and there is no need to reserve the bus number, so as to solve the problem that although the number of current devices in the switching chip does not exceed the limit of the total number of bus numbers, the host still cannot correctly allocate bus numbers to each device.

[0040] As Figure 5 shown, the bus numbers in switching chip A and the bus numbers in switching chip B are not repeated. In this way, in the scenario of interconnection between switching chip A and switching chip B, there is no need to perform BDF conversion, nor is there a need to reserve BDF. In this way, the problem that although the number of current devices in the switching chip does not exceed the limit of the total number of bus numbers, the host still cannot correctly allocate bus numbers to each device can be solved.

[0041] In an optional implementation manner, determining each host to which each downstream bridge device and its corresponding endpoint device belong includes: obtaining the host information corresponding to each downstream bridge device; if the host information is used to represent that the downstream bridge device corresponds to the first target host, then determine that the host to which the downstream bridge device and its corresponding endpoint device belong is the first target host; if the host information is used to represent that the downstream bridge device corresponds to the second target host, then determine that the host to which the downstream bridge device and its corresponding endpoint device belong is the second target host, where the first target host is the host corresponding to the switching chip itself, and the second target host is the host not corresponding to the switching chip.

[0042] The host information is used to characterize the host corresponding to the downstream bridge device, which can be pre-stored in a non-volatile storage unit. For a switching chip, it can read the non-volatile storage unit to directly obtain the host information. Based on the host information, it can clearly and quickly know which host each downstream bridge device and the endpoint device corresponding to each downstream bridge device in the switching chip belong to.

[0043] For example, as Figure 5 shown, taking switching chip A as an example, it can read the non-volatile storage unit in switching chip A to obtain the host information. The host information can be expressed as but not limited to downstream bridge device A belonging to host 0 and downstream bridge device B belonging to host 1, so that it can be determined that downstream bridge device A and its corresponding endpoint device A belong to host 0, and downstream bridge device B and its corresponding endpoint device B belong to host 1.

[0044] The first target host is the host corresponding to the switching chip itself, and the second target host is the host not corresponding to the switching chip itself. In this way, there can be one or more second target hosts. For example, as Figure 5 shown, switching chip A includes downstream bridge device A and downstream bridge device B. Downstream bridge device A corresponds to host 0, which is the first target host; downstream bridge device B corresponds to host 1, which is the second target host.

[0045] Through the host information corresponding to each downstream bridge device, it can quickly and efficiently determine which host each downstream bridge device and the endpoint device corresponding to each downstream bridge device belong to.

[0046] In order to avoid the bus numbers of the downstream bridge devices and the endpoint devices corresponding to the downstream bridge devices belonging to the same host from being repeated, in an optional implementation, using each bus number range, bus numbers are allocated to each downstream bridge device and its corresponding endpoint device, including: obtaining the first bus number range corresponding to the first target host; using the first bus number range to allocate bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to the first target host; obtaining the second bus number range corresponding to the second target host; using the second bus number range to allocate bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to the second target host.

[0047] The first bus number range corresponding to the first target host and the second bus number range corresponding to the second target host can both be pre-stored in the non-volatile storage unit of the switching chip. It should be understood that in the case where there are multiple second target hosts, there are also multiple second bus number ranges corresponding to the second target hosts.

[0048] Within the bus number range of the same host, bus numbers are allocated to the downstream bridge devices belonging to the same host and the endpoint devices corresponding to the downstream bridge devices, which can avoid the problem of duplicate bus numbers for the downstream bridge devices belonging to the same host and the endpoint devices corresponding to the downstream bridge devices.

[0049] In an optional implementation, using the first bus number range, bus numbers are allocated to the downstream bridge devices belonging to the first target host and their corresponding endpoint devices, including: using the first bus number range to determine the first bus number of the downstream bridge devices and the second bus numbers of each endpoint device; allocating the first bus number to all downstream bridge devices; and allocating each second bus number to each endpoint device, with the second bus numbers of each endpoint device being different.

[0050] In a PCIe topology, a superior bus can branch out multiple downstream bridge devices, which share the bus number allocated by the superior bus. That is to say, multiple downstream bridge devices can share the same bus number. Therefore, the first bus number corresponding to the downstream bridge devices can be determined within the first bus number range, and the first bus number is allocated to multiple downstream bridge devices belonging to the first target host. Multiple second bus numbers are determined within the first bus number range, and one second bus number is allocated to one endpoint device, which can avoid duplicate bus numbers for the endpoint devices belonging to the same host and can also avoid the situation where the endpoint devices cannot be accurately located due to duplicate bus numbers.

[0051] For example, as Figure 5 shown, for switch chip A, two downstream bridge devices A and two endpoint devices A belong to host 0. Then switch chip A can determine one first bus number and two second bus numbers within the first bus number range corresponding to host 0, allocate the first bus number to the two downstream bridge devices A, and allocate the two second bus numbers to the two endpoint devices A.

[0052] As Figure 5 shown, for switch chip A, since two downstream bridge devices B and two endpoint devices B belong to host 1, it is also necessary to allocate bus signals to the two downstream bridge devices B and the two endpoint devices B. Then how can switch chip A allocate them to avoid duplicate bus numbers with the two downstream bridge devices B and the two endpoint devices B corresponding to switch chip B? For this problem, in an optional implementation, using the second bus number range, bus numbers are allocated to the downstream bridge devices belonging to the second target host and their corresponding endpoint devices, including: obtaining the central processing unit corresponding to the second target host, where the central processing unit is the processor in the switch chip corresponding to the second target host; and communicating with the central processing unit to allocate bus numbers to the downstream bridge devices belonging to the second target host and their corresponding endpoint devices using the second bus number range.

[0053] The central processing unit corresponding to the second target host is the central processing unit (CPU) in the switching chip to which the second target host is connected. As Figure 5 shown, the central processing unit corresponding to the second target host can be the CPU in switching chip B corresponding to host 1.

[0054] The central processing unit corresponding to the first target host communicates and negotiates with the central processing unit corresponding to the second target host, so that non-repetitive bus numbers can be quickly and efficiently allocated to the downstream bridge devices belonging to the second target host and the endpoint devices corresponding to the downstream bridge devices.

[0055] As described above, the second bus number range corresponding to the second target host can also be divided into multiple bus number sub-ranges, and the bus number sub-ranges are pre-stored in the non-volatile storage units of different switching chips. In this way, after the central processing unit corresponding to the first target host obtains the bus number sub-ranges from the non-volatile storage unit, it can allocate bus numbers to the downstream bridge devices belonging to the second target host and the endpoint devices corresponding to the downstream bridge devices within the bus number sub-ranges, which can omit the process of mutual negotiation between the central processing units of different switching chips.

[0056] Optionally, by communicating with the central processing unit to allocate bus numbers to the downstream bridge devices belonging to the second target host and their corresponding endpoint devices by using the second bus number range, it includes: communicating with the central processing unit to obtain the bus number sub-ranges sent by the central processing unit, where the bus number sub-ranges are included in the second bus number range; using the bus number sub-ranges to allocate bus numbers to the downstream bridge devices belonging to the second target host and their corresponding endpoint devices.

[0057] The central processing unit of the first target host receives the bus number sub-ranges sent by the central processing unit of the second target host, and then determines the bus numbers corresponding to the downstream bridge devices and their corresponding endpoint devices from the bus number sub-ranges, so as to allocate the bus numbers to the downstream bridge devices and their corresponding endpoint devices. In this way, for the central processing unit of the second target host, it is used to globally control the bus numbers corresponding to the downstream bridge devices belonging to the second target host and their corresponding endpoint devices, so as to avoid the problem of duplicate bus numbers corresponding to the downstream bridge devices belonging to the same host and their corresponding endpoint devices.

[0058] Optionally, by communicating with the central processing unit to allocate bus numbers to the downstream bridge devices belonging to the second target host and their corresponding endpoint devices by using the second bus number range, it includes: using the second bus number range to determine the bus number sub-ranges, where the bus number sub-ranges are included in the second bus number range; using the bus number sub-ranges to allocate bus numbers to the downstream bridge devices belonging to the second target host and their corresponding endpoint devices; communicating with the central processing unit to send the bus number sub-ranges to the central processing unit.

[0059] The central processing unit corresponding to the first target host can independently determine a bus number sub-range from within the second bus number range, and then determine the bus numbers corresponding to the downstream bridge device and its corresponding endpoint devices from within the bus number sub-range, so as to allocate the bus numbers to the downstream bridge device and its corresponding endpoint devices. To avoid the problem of duplicate bus numbers corresponding to the downstream bridge device and its corresponding endpoint devices belonging to the same host, the central processing unit corresponding to the first target host also needs to send the bus number sub-range to the central processing unit corresponding to the second target host. In this way, the central processing unit corresponding to the second target host can know that the bus numbers within the bus number sub-range may already be occupied and will no longer allow other hosts to use the bus number sub-range to allocate bus numbers.

[0060] After determining the bus number sub-range from within the second total signal range, the process of specifically allocating bus numbers to the downstream bridge device and its corresponding endpoint devices belonging to the second target host is the same as the process of allocating bus numbers to the downstream bridge device and its corresponding endpoint devices belonging to the first target host, and will not be elaborated here one by one.

[0061] As Figure 5 shown, after using the above bus number allocation method for the switching chip, when the endpoint device with BDF {4,0,0} in switching chip B accesses the device with BDF {3,0,0} in switching chip A, there will be no need for BDF conversion, and there will be no need to reserve BDF in switching chip A for the endpoint devices of switching chip B.

[0062] As Figure 5 and Figure 7 shown, there are two endpoint devices with BDF {3,0,0} inside switching chip A, which belong to host 0 and host 1 respectively. In this way, when using BDF to route communication data packets, it will lead to path ambiguity. For example, as Figure 7 shown, when host 0 sends a communication data packet routed by BDF to the endpoint device A {3,0,0} belonging to host 0, it may be misrouted to the endpoint device B {3,0,0} belonging to host 1. Similarly, when host 1 accesses the endpoint device B with BDF {3,0,0} belonging to host 1, it may also be misrouted to the endpoint device A belonging to host 0. In addition, when the endpoint device B {2,0,0} belonging to host 1 accesses the endpoint device B {3,0,0} belonging to host 1, it may also be misrouted to the endpoint device A {3,0,0} belonging to host 0.

[0063] To solve the problem of routing ambiguity, in this embodiment, a method for allocating bus numbers of a switching chip is provided, which can be used in the above-mentioned switching chip and specifically in the CPU of the switching chip. The switching chip includes a plurality of downstream bridge devices, and each downstream bridge device is connected to a corresponding endpoint device. Figure 8 is a flowchart of a method for allocating bus numbers of a switching chip according to an embodiment of the present application, as Figure 8 shown. The process includes the following steps: Step S802, obtain each downstream bridge device and its corresponding endpoint device. For details, please refer to Figure 6 step S602 of the embodiment shown, which will not be elaborated here.

[0064] Step S804, determine each host to which each downstream bridge device and its corresponding endpoint device belong. For details, please refer to Figure 6 step S604 of the embodiment shown, which will not be elaborated here.

[0065] Step S806, obtain the bus number range corresponding to each host. For details, please refer to Figure 6 step S606 of the embodiment shown, which will not be elaborated here.

[0066] Step S808, use each bus number range to allocate bus numbers to each downstream bridge device and its corresponding endpoint device. For details, please refer to Figure 6 step S608 of the embodiment shown, which will not be elaborated here.

[0067] Step S810, obtain the identification information of each host.

[0068] The identification information of the host is used to represent the identity information of the host. The identification information of the host can be the MAC (Media Access Control Address) address, UUID (Universally Unique Identifier), IP (Internet Protocol Address) of the host. Of course, the identification information of the host can also be encoded according to a predetermined encoding method.

[0069] Step S812, use the identification information of each host to update the total line routing table corresponding to each downstream bridge device.

[0070] The master route table is used to represent the PCIe bus topology and routing information, that is, to represent the correspondence between the BDF of the downstream bridge device and the physical port number. In the same switching chip, each downstream bridge device corresponds to a master route table, and the master route tables of each downstream bridge device can be the same.

[0071] Using the identification information of each host to update the master route table corresponding to each downstream bridge device means that the identification information of the host corresponding to each downstream bridge device can be added to the master route table.

[0072] The bus number allocation method of the switching chip provided in this embodiment uses the obtained identification information of each host to update the master route table corresponding to each downstream bridge device, so that two endpoint devices with duplicate bus numbers are stored separately in the master route table. In this way, when the downstream bridge device queries the master route table, it can use its corresponding host identifier and the bus number in the communication data packet to form {host identifier, bus number}, and then query the master route table according to {host identifier, bus number}, thus solving the problem of routing ambiguity.

[0073] There are various implementation methods for obtaining the identification information of each host.

[0074] Optionally, obtaining the identification information of each host includes: obtaining the total number of hosts corresponding to the switching chip; determining the identification information of each host according to a predetermined coding method and the total number.

[0075] The predetermined coding method can be a pre-set coding method, which can be encoded by digital coding or other methods. In this application, the actual method of the predetermined coding method is not limited.

[0076] For the switching chip, after obtaining the total number of hosts corresponding to the switching chip, the identification information of each host can be determined according to the predetermined coding method and the total number, so that the identification information of each host can be determined more flexibly.

[0077] For example, as Figure 5 shown, for switching chip A, the number of hosts corresponding to it is 2, namely host 0 and host 1. Switching chip A can use the predetermined coding method and the total number to determine the identification information of host 0 as 00 and the identification information of host 1 as 01. For switching chip B, it may determine the identification information of host 0 as 11 and the identification information of host 1 as 10 in the same way. From a global perspective, although host 0 and host 1 both correspond to two different host identifiers, in the PCIe protocol, endpoint devices under different hosts do not communicate directly with each other. Even if the same host corresponds to different host identifiers, it will not affect each other.

[0078] For another example, when there are N hosts in a switching chip, the identification information (HostID) of each host can be encoded as 0 to N-1 respectively.

[0079] Optionally, obtaining the identification information of each host includes: obtaining the host information corresponding to each downstream bridge device; determining the host to which each downstream bridge device belongs according to the host information, so as to obtain the identification information of each host.

[0080] Since the host information is used to represent the host corresponding to the downstream bridge device, the host corresponding to each downstream bridge device can be obtained according to the host information table. After knowing the host corresponding to the downstream bridge device, the host can be accessed to obtain the identification information corresponding to the host. Through this solution, the identification information of the hosts in the entire interconnected network can be made unique.

[0081] Optionally, global encoding can also be performed in an interconnected network composed of multiple switching chips. For example, in an interconnected network composed of 2 switching chips, one switching chip corresponds to N1 hosts, and the other switching chip corresponds to N2 hosts. In this way, each host can be encoded as 0 to N1+N2-1 respectively.

[0082] After determining the identification information of each host, the switching chip can also send the identification information of each host to the downstream bridge device belonging to each host, so that when the downstream bridge device performs a routing query later, it can form {host identification, bus number} according to its corresponding host identification and the bus number in the communication data packet, and then query the total line routing table according to {host identification, bus number}.

[0083] The total line routing table is used to record the correspondence between the bus number of each downstream bridge device and the physical port number ( Figure 9 Port# in it). The total line routing table generally has 256 entries, and the corresponding range is 0 to 255.

[0084] As described above, there is a problem of duplicate bus numbers in the same switching chip. Therefore, when using the total line routing table to store the relationship between the bus number of the downstream bridge device and the physical port number, there is a problem that one bus number corresponds to multiple physical port numbers. For this problem, the total line routing table needs to be updated. In an optional implementation manner, using the identification information of each host to update the total line routing table corresponding to each downstream bridge device includes: obtaining the total number of hosts corresponding to the switching chip; using the total number of hosts to expand the entries of the total line routing table to obtain a target routing table; using the identification information of each host to update the target routing table; and sending the updated target routing table to each downstream bridge device.

[0085] Since there are multiple hosts corresponding to the same switching chip, the total line routing table before the update cannot accommodate the routing information of all downstream bridge devices. Therefore, it is necessary to expand the entries of the total line routing table, and use the identification information of each host to update the obtained target routing table.

[0086] In an alternative embodiment, the target routing table is updated by using the identification information of each host, including: for each downstream bridge device, constructing target routing information by using the identification information of the host corresponding to the downstream bridge device, the bus number and its corresponding physical port number, to obtain a plurality of target routing information; and filling the plurality of target routing information into the target routing table to update the target routing table.

[0087] The correspondence between the bus number and the physical port number of the downstream bridge device in the total line routing table is updated to the identification information of the host of the downstream bridge device, the bus number and the corresponding physical port number, that is, in the target routing table, the identification information of the host is added, so that the downstream bridge devices with the same bus number in the same switching chip are stored separately in the target routing table, as specifically Figure 9 shown, further solving the routing ambiguity problem caused by the repeated bus numbers in the same switching chip.

[0088] For example, as Figure 9 shown, the process of updating the total line routing table includes: first, expanding the entries of the total line routing table, and the expansion method is: expanding the number of entries of the total line routing table to 256*N, where N is the maximum number of hosts supported by each switching chip. Secondly, using the Host ID as the high bit of the look-up table address, that is, constructing target routing information by using {Host ID, Bus, Port#}, and filling the target routing information into the target routing table to update the target routing table. Subsequently, when using the target routing table for look-up, {Host ID, Bus} can be used for look-up. For example, the physical port number of Host ID = 1 and Bus = 2 is located in the 258th entry (hexadecimal number 0x102 is equal to decimal number 258).

[0089] Since the internal CPU of the domain isolation switching chip is an RC device in the real domain, this means that it violates the PCIe protocol for this RC device to manage two identical bus numbers on the PCIe tree, and it will also cause the routing ambiguity problem of the CPU accessing the endpoint device. To solve this problem, in an alternative embodiment, each downstream bridge device in the switching chip is connected to the target communication bus, and each downstream bridge device corresponds to a communication identifier on the target communication bus; the target communication bus is constructed by using a predetermined communication protocol, and the communication data packet is routed by using the communication identifier.

[0090] Connect each downstream bridge device to the target communication bus. In this way, when the CPU accesses the internal downstream bridge device, it no longer uses the standard PCIe interconnection, but uses the predetermined communication protocol followed by the target communication bus for interconnection, solving the problem of violating the PCIe protocol caused by having two identical bus numbers on the PCIe tree, and solving the problem of ambiguous routing when the CPU accesses the endpoint device.

[0091] The predetermined communication protocol is a communication protocol that does not use BDF for routing, and it can be a communication protocol that uses a communication identifier for routing. The communication identifier includes but is not limited to an address and a port number.

[0092] In an alternative embodiment, the method further includes: obtaining a communication data packet to be transmitted to the target downstream bridge device; performing protocol conversion on the communication data packet through the predetermined communication protocol corresponding to the target communication bus, and sending the communication data packet after protocol conversion to the target downstream bridge device, so that the target downstream bridge device can recognize a communication data packet that conforms to the PCIe protocol.

[0093] For example, as Figure 10 shown, the target communication bus is used within the switching chip, and each downstream bridge device is connected to the target communication bus. The target communication bus can use the most common address routing method, that is, each downstream bridge device has a separate physical port on the target communication bus, and this physical port occupies a pre-allocated communication address. When the CPU needs to access a certain downstream bridge device, the CPU sends a communication data packet to the target communication bus where the downstream bridge device is located, and the communication data packet is a packet encapsulated by the predetermined communication protocol. After that, the communication data packet will be routed by the target communication bus to the corresponding physical port through the communication address. Before the communication data packet enters the downstream bridge device, the predetermined communication protocol is used to perform protocol conversion on the communication data packet to restore the communication data packet to a communication data packet that conforms to the PCIe protocol and can be recognized by the downstream bridge device. That is to say, the core of this method is not to use the routing method defined by the standard PCIe protocol to avoid routing ambiguity, and to use protocol conversion to complete the conversion between the predetermined communication protocol followed by the target communication bus and the PCIe protocol.

[0094] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0095] The embodiment of the present application also provides a bus number allocation device for a switching chip. The switching chip includes a plurality of downstream bridge devices, and each downstream bridge device is connected with a corresponding endpoint device. As Figure 11As shown in the figure, the device includes a device acquisition module, a host determination module, a bus number acquisition module, and a bus number allocation module. Among them, The device acquisition module 1110 is used to acquire each downstream bridge device and its corresponding endpoint device; The host determination module 1120 is used to determine each host to which each downstream bridge device and its corresponding endpoint device belong; The bus number acquisition module 1130 is used to acquire the bus number range corresponding to each host; The bus number allocation module 1140 is used to use each bus number range to allocate bus numbers to each downstream bridge device and its corresponding endpoint device.

[0096] In an alternative embodiment, the host determination module is used to acquire the host information corresponding to each downstream bridge device; if the host information is used to represent that the downstream bridge device corresponds to a first target host, then determine that the host to which the downstream bridge device and its corresponding endpoint device belong is the first target host; if the host information is used to represent that the downstream bridge device corresponds to a second target host, then determine that the host to which the downstream bridge device and its corresponding endpoint device belong is the second target host, where the first target host is the host corresponding to the switching chip itself, and the second target host is the host not corresponding to the switching chip itself.

[0097] In an alternative embodiment, the bus number allocation module is used to acquire the first bus number range corresponding to the first target host; use the first bus number range to allocate bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to the first target host; acquire the second bus number range corresponding to the second target host; use the second bus number range to allocate bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to the second target host.

[0098] In an alternative embodiment, the bus number allocation module is further used to use the first bus number range to determine the first bus number of the downstream bridge device and the second bus number of each endpoint device; allocate the first bus number to all downstream bridge devices; allocate each second bus number to each endpoint device, and the second bus numbers of each endpoint device are different.

[0099] In an alternative embodiment, the bus number allocation module is further used to acquire the central processing unit corresponding to the second target host, where the central processing unit is the processor in the switching chip corresponding to the second target host; communicate with the central processing unit to use the second bus number range to allocate bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to the second target host.

[0100] In an alternative embodiment, the bus number allocation module is further configured to communicate with a central processing unit to obtain a sub-range of bus numbers sent by the central processing unit, the sub-range of bus numbers being included in a second bus number range; and use the sub-range of bus numbers to allocate bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to a second target host.

[0101] In an alternative embodiment, the bus number allocation module is further configured to determine a sub-range of bus numbers by using the second bus number range, the sub-range of bus numbers being included in the second bus number range; use the sub-range of bus numbers to allocate bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to a second target host; and communicate with the central processing unit to send the sub-range of bus numbers to the central processing unit.

[0102] In an alternative embodiment, the apparatus further includes a host identifier acquisition module and a routing information update module. The host identifier acquisition module is configured to acquire the identifier information of each host, and the routing information update module is configured to update the general routing table corresponding to each downstream bridge device by using the identifier information of each host.

[0103] In an alternative embodiment, the host identifier acquisition module is configured to acquire the total number of hosts corresponding to a switching chip; and determine the identifier information of each host according to a predetermined coding method and the total number.

[0104] In an alternative embodiment, the host identifier acquisition module is configured to acquire the host information corresponding to each downstream bridge device; and determine the host to which each downstream bridge device belongs according to the host information of each downstream bridge device, so as to acquire the identifier information of each host.

[0105] In an alternative embodiment, the routing information update module is configured to acquire the total number of hosts corresponding to a switching chip; use the total number of hosts to expand the entries of the general routing table to obtain a target routing table; update the target routing table by using the identifier information of each host; and send the updated target routing table to each downstream bridge device.

[0106] In an alternative embodiment, the routing information update module is configured to, for each downstream bridge device, construct target routing information by using the identifier information of the host corresponding to the downstream bridge device, the bus number, and its corresponding physical port number to obtain a plurality of pieces of target routing information; and fill the plurality of pieces of target routing information into the target routing table to update the target routing table.

[0107] In an alternative embodiment, each downstream bridge device in a switching chip is connected to a target communication bus, and each downstream bridge device corresponds to a communication identifier on the target communication bus; the target communication bus is constructed by using a predetermined communication protocol, and communication data packets are routed by using the communication identifier.

[0108] In an alternative embodiment, the device further includes a data packet acquisition module and a protocol conversion module. The data packet acquisition module is configured to acquire communication data packets to be transmitted to a target downstream bridge device; the protocol conversion module is configured to perform protocol conversion on the communication data packets through a predetermined communication protocol corresponding to the target communication bus, and send the communication data packets after protocol conversion to the target downstream bridge device.

[0109] In the bus number allocation device of the switching chip of the present application, each downstream bridge device in the switching chip and each endpoint device corresponding to each downstream bridge device respectively correspond to different hosts. In the process of the switching chip allocating bus numbers to each downstream bridge device and each endpoint device corresponding to each downstream bridge device, first determine the hosts to which each downstream bridge device and each endpoint device corresponding to each downstream bridge device belong, and then according to the bus number ranges of each host, within the bus number ranges of each host, allocate bus numbers to the downstream bridge devices belonging to each host and each endpoint device corresponding to each downstream bridge device. In this way, the bus numbers of the downstream bridge devices belonging to the same host and each endpoint device corresponding to each downstream bridge device are not repeated, and the downstream bridge devices belonging to the same host and each endpoint device corresponding to each downstream bridge device are not located in the same switching chip. Thus, in the scenario of switching chip interconnection, there is no need to convert bus numbers, and there is no need to reserve bus numbers, thereby solving the problem that although the number of current devices in the switching chip does not exceed the limit of the total number of bus numbers, the host still cannot correctly allocate bus numbers to each device.

[0110] For the description of the features in the corresponding embodiment of the bus number allocation device of the switching chip, reference can be made to the relevant description of the corresponding embodiment of the bus number allocation method of the switching chip, which will not be elaborated here one by one.

[0111] An embodiment of the present application further provides a communication system, which includes a plurality of hosts, a plurality of switching chips, and a plurality of endpoint devices. One of the hosts is connected to one of the switching chips, and one of the switching chips is connected to a plurality of the endpoint devices. The switching chip is configured to implement the steps of any one of the above bus number allocation methods of the switching chip.

[0112] The communication system of the present application includes multiple hosts, multiple switching chips, and multiple endpoint devices. Among them, the multiple switching chips can execute the bus number allocation method of the above-mentioned switching chips. In this method, first, determine each downstream bridge device and each host to which the endpoint devices corresponding to each downstream bridge device belong, and then, according to the bus number ranges of each host, within the bus number ranges of each host, allocate bus numbers to the downstream bridge devices belonging to each host and the endpoint devices corresponding to each downstream bridge device. In this way, the bus numbers of the downstream bridge devices belonging to the same host and the endpoint devices corresponding to each downstream bridge device are not repeated, and the downstream bridge devices belonging to the same host and the endpoint devices corresponding to each downstream bridge device are not located in the same switching chip. Thus, in the scenario of switching chip interconnection, there is no need to convert bus numbers and no need to reserve bus numbers, thereby solving the problem that although the number of current devices in the switching chip does not exceed the limit of the total number of bus numbers, the host still cannot correctly allocate bus numbers to each device.

[0113] In an alternative embodiment, the switching chip includes a central processing unit, an upstream bridge device, at least one cascaded bridge device, and multiple downstream bridge devices. Among them, the central processing unit is configured to allocate bus numbers to each downstream bridge device in the switching chip and each endpoint device connected to each downstream bridge device; the upstream bridge device is configured to forward communication data packets sent by a first target host or each downstream bridge device, and the first target host is the host corresponding to the switching chip itself; at least one cascaded bridge device is configured to forward the communication data packets sent by the central processing unit or each downstream bridge device; and the multiple downstream bridge devices are configured to connect to multiple endpoint devices.

[0114] An embodiment of the present application further provides an electronic device, as Figure 12 shown, including a memory 1210 and a processor 1220. A computer program is stored in the memory 1210, and the processor 1220 is configured to run the computer program to execute the steps in any of the above embodiments of the bus number allocation method for the switching chip.

[0115] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above embodiments of the bus number allocation method for the switching chip when running.

[0116] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memory (ROM), random access memory (RAM), mobile hard disks, magnetic disks, or optical discs that can store computer programs.

[0117] The embodiments of the present application also provide a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the bus number allocation method for the switching chip.

[0118] The embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the bus number allocation method for the switching chip.

[0119] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0120] The above has introduced in detail a bus number allocation method, device, system, equipment, and medium for a switching chip provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for allocating bus numbers of a switching chip, characterized in that, The switching chip includes multiple downstream bridge devices, and each of the downstream bridge devices is connected to a corresponding endpoint device. The method includes: Obtain each of the downstream bridge devices and its corresponding endpoint device; Determine each host to which each of the downstream bridge devices and its corresponding endpoint device belongs; Obtain the bus number range corresponding to each host; Use each bus number range to allocate bus numbers to each of the downstream bridge devices and its corresponding endpoint device.

2. The method according to claim 1, wherein Determining each host to which each of the downstream bridge devices and its corresponding endpoint device belongs includes: Obtain the host information corresponding to each of the downstream bridge devices; If the host information is used to represent that the downstream bridge device corresponds to a first target host, determine that the host to which the downstream bridge device and its corresponding endpoint device belong is the first target host; If the host information is used to represent that the downstream bridge device corresponds to a second target host, determine that the host to which the downstream bridge device and its corresponding endpoint device belong is the second target host, where the first target host is the host corresponding to the switching chip itself, and the second target host is the host that does not correspond to the switching chip itself.

3. The method according to claim 2, characterized in that, Using each bus number range to allocate bus numbers to each of the downstream bridge devices and its corresponding endpoint device includes: Obtain the first bus number range corresponding to the first target host; Use the first bus number range to allocate the bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to the first target host; Obtain the second bus number range corresponding to the second target host; Use the second bus number range to allocate the bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to the second target host.

4. The method according to claim 3, wherein Using the first bus number range to allocate the bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to the first target host includes: Use the first bus number range to determine the first bus number of the downstream bridge device and the second bus number of each endpoint device; Allocate the first bus number to all the downstream bridge devices; Allocate each of the second bus numbers to each of the endpoint devices, and the second bus numbers of each endpoint device are different.

5. The method according to claim 3, wherein Using the second bus number range to allocate the bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to the second target host includes: Obtain the central processing unit corresponding to the second target host, where the central processing unit is the processor in the switching chip corresponding to the second target host; Communicate with the central processing unit to use the second bus number range to allocate the bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to the second target host.

6. The method according to claim 5, characterized in that, Communicating with the central processing unit to use the second bus number range to allocate the bus numbers to the downstream bridge devices and their corresponding endpoint devices belonging to the second target host includes: Communicate with the central processing unit to obtain a bus number sub-range sent by the central processing unit, where the bus number sub-range is included in the second bus number range; Use the bus number sub-range to allocate the bus numbers to the downstream bridge device belonging to the second target host and its corresponding endpoint devices.

7. The method according to claim 5, wherein By communicating with the central processing unit to allocate the bus numbers to the downstream bridge device belonging to the second target host and its corresponding endpoint devices by using the second bus number range, it includes: Use the second bus number range to determine a bus number sub-range, where the bus number sub-range is included in the second bus number range; Use the bus number sub-range to allocate the bus numbers to the downstream bridge device belonging to the second target host and its corresponding endpoint devices; Communicate with the central processing unit to send the bus number sub-range to the central processing unit.

8. The method according to claim 1, characterized in that The method further includes: Obtain the identification information of each host; Use the identification information of each host to update the general line routing table corresponding to each downstream bridge device.

9. The method according to claim 8, characterized in that, Obtaining the identification information of each host includes: Obtain the total number of hosts corresponding to the switching chip; Determine the identification information of each host according to a predetermined coding method and the total number.

10. The method according to claim 8, wherein Obtaining the identification information of each host includes: Obtain the host information corresponding to each downstream bridge device; According to the host information of each, determine the host to which each downstream bridge device belongs, so as to obtain the identification information of each host.

11. The method according to claim 8, wherein Using the identification information of each host to update the general line routing table corresponding to each downstream bridge device includes: Obtain the total number of hosts corresponding to the switching chip; Use the total number of hosts to expand the entries of the general line routing table to obtain a target routing table; Use the identification information of each host to update the target routing table; Send the updated target routing table to each downstream bridge device.

12. The method according to claim 11, wherein Using the identification information of each host to update the target routing table includes: For each downstream bridge device, construct target routing information by using the identification information of the host corresponding to the downstream bridge device, the bus number and its corresponding physical port number, to obtain a plurality of pieces of target routing information; Fill the plurality of pieces of target routing information into the target routing table to update the target routing table.

13. The method according to any one of claims 1 to 12, characterized in that Each downstream bridge device in the switching chip is connected to a target communication bus, and each downstream bridge device corresponds to a communication identifier on the target communication bus; The target communication bus is constructed by using a predetermined communication protocol, and the communication identifier is used to route communication data packets.

14. The method according to claim 13, wherein The method further includes: Obtain the communication data packet to be transmitted to the target downstream bridge device; Perform protocol conversion on the communication data packet through the predetermined communication protocol corresponding to the target communication bus, and send the communication data packet after the protocol conversion to the target downstream bridge device.

15. A bus number allocation device for a switching chip, characterized in that, The switching chip includes a plurality of downstream bridge devices, and each of the downstream bridge devices is connected to a corresponding endpoint device. The apparatus includes: A device acquisition module, configured to acquire each of the downstream bridge devices and its corresponding endpoint device; A host determination module, configured to determine each host to which each of the downstream bridge devices and its corresponding endpoint device belongs; A bus number acquisition module, configured to acquire the bus number range corresponding to each of the hosts; A bus number allocation module, configured to allocate bus numbers to each of the downstream bridge devices and its corresponding endpoint device by using each of the bus number ranges.

16. A communication system, characterized in that, The communication system includes a plurality of hosts, a plurality of switching chips, and a plurality of endpoint devices. Among them, one host is connected to one switching chip, and one switching chip is connected to a plurality of endpoint devices. The switching chip is configured to implement the steps of the bus number allocation method of the switching chip according to any one of claims 1 to 14.

17. The system according to claim 16, wherein The switching chip includes: A central processing unit, configured to allocate bus numbers to each of the downstream bridge devices in the switching chip and each endpoint device connected to each of the downstream bridge devices; An upstream bridge device, configured to forward communication data packets sent by a first target host or each of the downstream bridge devices, where the first target host is the host corresponding to the switching chip itself; At least one cascaded bridge device, configured to forward the communication data packets sent by the central processing unit or each of the downstream bridge devices; A plurality of the downstream bridge devices, configured to connect a plurality of endpoint devices.

18. An electronic device, characterized in that, Including: A memory, configured to store a computer program; A processor, configured to implement the steps of the bus number allocation method of the switching chip according to any one of claims 1 to 14 when executing the computer program.

19. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, where the computer program, when executed by a processor, implements the steps of the bus number allocation method of the switching chip according to any one of claims 1 to 14.

20. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the bus number allocation method of the switching chip according to any one of claims 1 to 14.

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